Datasheet, Version 2.3, September 2009 ISOFACE TM ISO1H801G Coreless Transformer Isolated Digital Output 8 Channel 0.625A High-Side Switch Power Management & Drives N e v e r s t o p t h i n k i n g . ISO1H801G Revision History: 2009-09-16 Previous Version: V2.2 V2.0 Final Datasheet V2.1 Final Datasheet V2.2 Page 15 creepage, clearance distance and VISO adapted, V2.3 Diagnostic output discontinued Version 2.3 Edition 2009-09-16 Published by Infineon Technologies AG, Am Campeon 1-12, 85579 Neubiberg, Germany © Infineon Technologies AG 2009. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. ISOFACETM ISO1H801G Coreless Transformer Isolated Digital Output 8 Channel 0.625A High-Side Switch Product Highlights • • • • Coreless transformer isolated data interface Galvanic isolation 8 High-side output switches 0.625A µC compatible 8-bit parallel peripheral Features • • • • • • • • • • • • • • • • • • • Interface 5V CMOS operation compatible Parallel interface Direct control mode High common mode transient immunity Short circuit protection Maximum current internally limited Overload protection Overvoltage protection (including load dump) Undervoltage shutdown with autorestart and hysteresis Switching inductive loads Common output disable pin Thermal shutdown with restart Thermal independence of separate channels ESD protection Loss of GNDbb and loss of Vbb protection Reverse Output Voltage protection • Isolated switch for industrial applications (PLC) All types of resistive, inductive and capacitive loads µC compatible power switch for 24V DC applications Driver for solenoid, relays and resistive loads Description The ISO1H801G is a galvanically isolated 8 bit data interface in PG-DSO-36 package that provides 8 fully protected high-side power switches that are able to handle currents up to 625 mA. An 8 bit parallel µC compatible interface allows to connect the IC directly to a µC system. The input interface supports also a direct control mode and is designed to operate with 5V CMOS compatible levels. The data transfer from input to output side is realized by the integrated Coreless Transformer Technology. Typical Application Typical Application VCC VCC VCCP1.x DIS AD0 CS WR WR P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 µC (i.e C166) D0 D1 D2 D3 D4 D5 D6 D7 Vbb Vbb CT Control Unit OUT0 Control & Protectio n Unit OUT1 Parallel Interface reserved OUT7 GND ISO1H801G GNDCC GNDbb Type On-state Resistance Package ISO1H801G 200mΩ PG-DSO-36 Datasheet 3 Version 2.3, 2009-09-16 ISOFACE™ ISO1H801G Pin Configuration and Functionality 1 Pin Configuration and Functionality 1.1 Pin Configuration Pin Symbol 1 N.C. Not connected 2 VCC Positive 5V logic supply 3 DIS Output disable 4 Chip select 5 CS WR 6 D0 Data input bit0 7 D1 Data input bit1 8 D2 Data input bit2 9 D3 Data input bit3 10 D4 Data input bit4 11 D5 Data input bit5 12 D6 Data input bit6 13 D7 Data input bit7 Function reserved - 15 GNDCC 16 N.C. Not connected 17 N.C. Not connected 18 N.C. Not connected 19 GNDbb 20 N.C 21 OUT7 High-side output of channel 7 22 OUT7 High-side output of channel 7 23 OUT6 High-side output of channel 6 24 OUT6 High-side output of channel 6 25 OUT5 High-side output of channel 5 26 OUT5 High-side output of channel 5 27 OUT4 High-side output of channel 4 28 OUT4 High-side output of channel 4 29 OUT3 High-side output of channel 3 30 OUT3 High-side output of channel 3 31 OUT2 High-side output of channel 2 32 OUT2 High-side output of channel 2 33 OUT1 High-side output of channel 1 34 OUT1 High-side output of channel 1 35 OUT0 High-side output of channel 0 36 OUT0 High-side output of channel 0 TAB Vbb Datasheet N.C. VCC DIS CS WR D0 D1 D2 D3 D4 D5 D6 D7 reserved GNDCC N.C. N.C. N.C. Parallel write 14 Figure 1 Vbb Input logic ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 TAB TAB 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 OUT0 OUT0 OUT1 OUT1 OUT2 OUT2 OUT3 OUT3 OUT4 OUT4 OUT5 OUT5 OUT6 OUT6 OUT7 OUT7 N.C. GNDbb Vbb . Output driver ground Not connected Positive driver power supply voltage Power SO-36 (430mil) 4 Version 2.3, 2009-09-16 ISOFACE™ ISO1H801G Pin Configuration and Functionality 1.2 Pin Functionality VCC (Positive 5V logic supply) The VCC supplies the input interface that is galvanically isolated from the output driver stage. The input interface can be supplied with 5V. DIS (Output disable) The high-side outputs OUT0...OUT7 can be immediately switched off by means of the low active pin DIS that is an asynchronous signal. The input registers are also reset by the DIS signal. The Output remains switched off after low-high transition of DIS signal, till new information is written into the input register. Current Sink to GNDCC. CS (Chip select) The system microcontroller selects the ISO1H801G by means of the low active pin CS to activate the parallel interface. By connecting the CS pin and WR pin to ground the parallel direct control is activated. Current Source to VCC. WR (Parallel write) In parallel mode data at the input pins (D0 ... D7) are latched by means of the rising edge of the low active signal WR (write). Current Source to VCC. D0 ... D7 (Data input bit0 ... bit7) The present data can be latched on the rising edge of the write signal WR. D0 ... D7 control the corresponding output channels OUT0 ...OUT7. By connecting CS and WR to ground, the signals at D0 ... D7 directly control the outputs. Current Sink to GNDCC. GNDCC (Ground for VCC domain) This pin acts as the ground reference for the input interface that is supplied by VCC. GNDbb (Output driver ground domain) This pin acts as the ground reference for the output driver that is supplied by Vbb. OUT0 ... OUT7 (High side output channel 0 ... 7) The output high side channels are internally connected to Vbb and controlled by the corresponding data input pins D0 ... D7 in parallel mode. TAB (Vbb, Positive supply for output driver) The heatslug is connected to the positive supply port of the output interface. Datasheet 5 Version 2.3, 2009-09-16 Datasheet 6 reserved D0 D1 D2 D3 D4 D5 D6 D7 WR CS ISO1H801G < D0 - D7 > Parallel Input Interface High-side Channel 7 Logic Charge Pump Level shifter Rectifier Charge Pump Level Shifter Rectifier Overvoltage Protection Temperature Sensor Overload Protection Current Limitation Limitation of Unclamped Inductive Load Gate Protection Channel 1 ... 6 Temperature Sensor Overload Protection Current Limitation Limitation of Unclamped Inductive Load Gate Protection Voltage Source from Temperatur e Sensor Channel 1 6 Undervoltage Shutdown with Restart Common Diagnostic Output High-side Channel 0 Logic to Logic Channel 1 6 to Logic Channel 1 6 Serial to Parallel Vbb OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 GNDbb Blockdiagram Direct Mode Control Parallel to Serial CT Figure 2 DIS Logic Blockdiagram GNDCC Undervoltage Shutdown with Restart Vbb 2 Galvanic Isolation VCC ISOFACE™ ISO1H801G Blockdiagram Version 2.3, 2009-09-16 ISOFACE™ ISO1H801G Functional Description 3 Functional Description 3.1 Introduction when solenoid loads are switched off. VON is then clamped to 47V (min.). The ISOFACE ISO1H801G includes 8 high-side power switches that are controlled by means of the integrated parallel interface. The interface is 8bit µC compatible. Furthermore a direct control mode can be selected that allows the direct control of the outputs OUT0...OUT7 by means of the inputs D0...D7 without any additional logic signal. The IC can replace 8 optocouplers and the 8 high-side switches in conventional I/O-Applications as a galvanic isolation is implemented by means of the integrated coreless transformer technology. The µC compatible interfaces allow a direct connection to the ports of a microcontroller without the need for other components. Each of the 8 high-side power switches is protected against short to Vbb, overload, overtemperature and against overvoltage by an active zener clamp. Vbb Vz VON OUTx GNDbb Figure 3 Inductive and overvoltage output clamp (each channel) Energy is stored in the load inductance during an inductive load switch-off. The diagnostic logic on the power chip recognizes the overtemperature information of each power transistor. 3.2 Vbb EL = 1 ⁄ 2 × L × IL 2 Power Supply Ebb The IC contains 2 galvanic isolated voltage domains that are independent from each other. The input interface is supplied at VCC and the output stage is supplied at Vbb. The different voltage domains can be switched on at different time. The output stage is only enabled once the input stage enters a stable state. EAS ELoad Vbb Dx OUTx L Vbb GNDbb EL ZL 3.3 Output Stage RL Each channel contains a high-side vertical power FET that is protected by embedded protection functions. Figure 4 The continous current for each channel is 625mA (all channels ON). 3.3.1 Output Stage Control E AS = E bb + E L – E R = V ON ( CL ) × i L ( t )dt with an approximate solution for RL > 0Ω: IL × L IL × RL E AS = ---------------- × ( V bb + V ON ( CL ) ) × ln 1 + -----------------------2 × RL V ON ( CL ) 3.3.3 Power Transistor Overcurrent Protection The outputs are provided with a current limitation that enters a repetitive switched mode after an initial peak current has been exceeded. The initial peak short circuit current limit is set to IL(SCp). During the repetitive mode short circuit current the limit is set to IL(SCr). If this operation leads to an overtemperature condition, a second protection level (Tj > 135°C) will change the Power Transistor Overvoltage Protection Each of the eight output stages has it own zener clamp that causes a voltage limitation at the power transistor Datasheet Inductive load switch-off energy dissipation (each channel) While demagnetizing the load inductance, the energy dissipation in the DMOS is Each output is independently controlled by an output latch and a common reset line via the pin DIS that disables all eight outputs and reset the latches. The parallel input data is transferred to the input latches with a high-to-low transition of the signal WR (write) while the CS is logic low. A low-to-high transition of CS transfers then the data of the input latches to the output buffer. 3.3.2 ER 7 Version 2.3, 2009-09-16 ISOFACE™ ISO1H801G Functional Description 3.4 output into a low duty cycle PWM (selective thermal shutdown with restart) to prevent critical chip temperatures. Reserved IN VOUT t TJ t t Figure 5 Overtemperature detection The following figures show the timing for a turn on into short circuit and a short circuit in on-state. Heating up of the chip may require several milliseconds, depending on external conditions. IN t VOUT Output short to GND IL IL(SCp) t IL(SCr) t Figure 6 Turn on into short circuit, shut down by overtemperature, restart by cooling IN t VOUT Normal operation IL Output short to GND IL(SCp) t IL(SCr) t Figure 7 Datasheet Short circuit in on-state, shut down down by overtemperature, restart by cooling 8 Version 2.3, 2009-09-16 ISOFACE™ ISO1H801G Functional Description Parallel Interface 3.5.2 uC Control Mode The ISO1H801G contains a parallel interface that can be directly controlled by the microcontroller output ports. The parallel interface can also be switched over to a direct control that allows direct changes of the outputs OUT0 ... OUT7 by means of the corresponding inputs D0 ... D7 without additional logic signals. To activate the parallel direct control mode pin CS and pin WR have to be connected both to GNDCC. 3.5.1 VCC VCC AD0 WR CS WR P0 P1 P2 P3 P4 P5 P6 P7 Parallel Interface Signal Description CS - Chip select. The system microcontroller selects the ISO1H801G by means of the CS pin. Whenever the pin is in a logic low state, data can be transferred from the µC. GND µC (i.e C166) Parallel input data can be written in from then on CS Low to high transition: • The data in the input latches is transferred to the output buffer Figure 8 Parallel bus configuration 3.5.3 Direct Control Mode VCC VCC Parallel input data at the pins D0 - D7 is written into the input latches VCC CS WR WR Logic high level: The parallel input data is latched in the input latches. Any changes at the pins D0 - D7 after the low-to-high transition of WR do not affect the input latches. D0 ... D7 - Parallel input. Parallel data bits are fed into the pins D0 ... D7. The data is written into the input latches when WR is logic low. P0 P1 P2 P3 P4 P5 P6 P7 D0 D1 D2 D3 D4 D5 D6 D7 reserved GND GNDCC Controller Figure 9 Datasheet IC1 . WR Logic low level: • GNDCC Beside the use of the parallel µC compatible interface a parallel direct control mode can be choosen. In this mode the output OUT0...OUT7 can be directly controlled via the inputs D0...D7 without the need for additional logic signals. To activate this mode pin CS and WR need to be connected to GNDCC. WR - Write. The system controller enables the write procedure in the ISO1H801G by means of the signal WR. A logic low state signal at pin WR writes the input data into the input latches when the CS pin is in a logic low state. • Output lines reserved CS High to low transition: • D0 D1 D2 D3 D4 D5 D6 D7 Parallel Interface VCC 9 Parallel Interface 3.5 Output lines IC1 Parallel Direct Control Version 2.3, 2009-09-16 ISOFACE™ ISO1H801G Functional Description 3.6 Parallel Interface Timing CS WR tCSWR t WHCS t CSD tWRPW t DS DATA tDH D0 - D7 ton/off OUTPUT OUT0 - OUT7 Figure 10 Parallel input - output timing diagram 3.7 Transmission Failure Detection There is a failure detection unit integrated to ensure also a stable functionality during the integrated coreless transformer transmission. This unit decides wether the transmitted data is valid or not. If four times serial data coming in from the internal registers is not accepted, the output stages are switched off until the next valid data is received. Datasheet 10 Version 2.3, 2009-09-16 ISOFACE™ ISO1H801G Electrical Characteristics 4 Electrical Characteristics Note: All voltages at pins 2 to 14 are measured with respect to ground GNDCC (pin 15). All voltages at pin 20 to pin 36 and TAB are measured with respect to ground GNDbb (pin 19). The voltage levels are valid if other ratings are not violated. The two voltage domains VCC and Vbb are internally galvanic isolated. 4.1 Absolute Maximum Ratings Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 2 (VCC) and TAB (Vbb) is discharged before assembling the application circuit. Supply voltages higher than Vbb(AZ) require an external current limit for the GNDbb pin, e.g. with a 15Ω resistor in GNDbb connection. Operating at absolute maximum ratings can lead to a reduced lifetime. Parameter at Tj = -40 ... 135°C, unless otherwise specified Symbol Supply voltage input interface (VCC) VCC Limit Values Unit min. max. -0.5 6.5 1) 45 Supply voltage output interface (Vbb) Vbb -1 Continuous voltage at data inputs (D0 ... D7) VDx -0.5 6.5 Continuous voltage at pin CS VCS -0.5 6.5 Continuous voltage at pin WR VWR -0.5 6.5 Continuous voltage at pin DIS VDIS -0.5 6.5 Continuous voltage at reserved pin VReserved -0.5 6.5 Load current (short-circuit current) IL self limited Reverse current through GNDbb1) IGNDbb -1.6 Operating Temperature Tj -25 Storage Temperature Tstg -50 150 3.3 Power Dissipation 2) Ptot 3) Inductive load switch-off energy dissipation single pulse, Tj = 125°C, IL = 0.625A one channel active all channel simultaneously active (each channel) Load dump protection3) VloadDump4)=VA + VS VIN = low or high td = 400ms, RI = 2Ω, RL = 27Ω, VA = 13.5V td = 350ms, RI = 2Ω, RL = 57Ω, VA = 27V V A internal limited °C EAS W J 10 1 VLoaddump V 90 117 Electrostatic discharge voltage (Human Body Model) according to JESD22-A114-B VESD Electrostatic discharge voltage (Charge Device Model) according to ESD STM5.3.1 - 1999 VESD Continuous reverse drain current1)3), each channel IS kV 2 kV 1 4 A 1) defined by Ptot 2) Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70µm thick) copper area for drain connection. PCB is vertical without blown air. 3) not subject to production test, specified by design 4) VLoaddump is setup without the DUT connected to the generator per ISO7637-1 and DIN40839 Datasheet 11 Version 2.3, 2009-09-16 ISOFACE™ ISO1H801G Electrical Characteristics 4.2 Thermal Characteristics Parameter at Tj = -25 ... 125°C, Vbb=15...30V, VCC=4.5...5.5V, unless otherwise specified Symbol Thermal resistance junction - case RthJC Thermal resistance @ min. footprint Rth(JA) Thermal resistance @ 6cm² cooling area1) Rth(JA) Limit Values Unit Test Condition min. typ. max. 1.5 K/W 50 38 1) Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70µm thick) copper area for drain connection. PCB is vertical without blown air. 4.3 Load Switching Capabilities and Characteristics Parameter at Tj = -25 ... 125°C, Vbb=15...30V, VCC=4.5...5.5V, unless otherwise specified On-state resistance, IL = 0.5A Tj = 25°C Tj = 125°C Symbol RON Limit Values Unit min. typ. max. 150 270 200 320 64 120 Test Condition mΩ Turn-on time to 90% VOUT1) RL = 47Ω, VDx = 0 to 5V ton Turn-off time to 10% VOUT1) RL = 47Ω, VDx = 5 to 0V toff 89 170 Slew rate on 10 to 30% VOUT RL = 47Ω, Vbb = 15V dV/dton 1 2 Slew rate off 70 to 40% VOUT RL = 47Ω, Vbb = 15V -dV/dtoff 1 2 µs V/µs 1) The turn-on and turn-off time includes the switching time of the high-side switch and the transmission time via the coreless transformer in normal operating mode. During a failure on the coreless transformer transmission turn-on or turn-off time can increase by up to 50µs. 4.4 Operating Parameters Parameter at Tj = -25 ... 125°C, Vbb=15...30V, VCC=4.5...5.5V, unless otherwise specified Symbol Common mode transient immunity1) Magnetic field immunity Voltage domain Vbb (Output interface) Datasheet 1) Limit Values Unit min. typ. max. ∆VISO/dt -25 - 25 HIM 100 Test Condition kV/µs ∆VISO = 200V A/m IEC61000-4-8 Undervoltage shutdown Vbb(under) 7 10.5 Undervoltage restart Vbb(u_rst) 11 Undervoltage hysteresis ∆Vbb(under) 0.5 Undervoltage current Ibb(uvlo) 1 2.5 mA Vbb < 7V Operating current IGNDL 10 14 mA All Channels ON - no load Leakage output current (included in Ibb(off)) VDx = low, each channel IL(off) 5 30 µA 12 V Version 2.3, 2009-09-16 ISOFACE™ ISO1H801G Electrical Characteristics Voltage domain VCC Operating voltage (Input interface) Undervoltage shutdown VCC 4.5 VCC(under) 2.5 Undervoltage restart VCC(u_rst) Undervoltage hysteresis ∆VCC(under) Undervoltage current ICC(uvlo) Operating current ICC(on) 5.5 0.1 1 2 mA 4.5 6 mA V 2.9 3 Vcc < 2.5V 1) not subject to production test 4.5 Output Protection Functions Parameter1) at Tj = -25 ... 125°C, Vbb=15...30V, VCC=4.5...5.5V, unless otherwise specified Symbol Initial peak short circuit current limit, Vbb = 30V, tm = 700µs Tj = -25°C Tj = 25°C Tj = 125°C IL(SCp) Repetitive short circuit current limit3) Tj = Tjt (see timing diagrams) Limit Values min. typ. Unit Test Condition max. A 1.9 0.7 IL(SCr) 1.1 Output clamp (inductive load switch off) at VOUT = Vbb - VON(CL) VON(CL) 47 53 60 V Overvoltage protection Vbb(AZ) 47 Tjt 135 °C 10 2)3) Thermal overload trip temperature 3) Thermal hysteresis ∆Tjt 1.4 K 1) Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continous repetitive operation. 2) Higher operating temperature at normal function for each channel available 3) not subject to production test, specified by design 4.6 Datasheet Reserved 13 Version 2.3, 2009-09-16 ISOFACE™ ISO1H801G Electrical Characteristics 4.7 Input Interface Parameter at Tj = -25 ... 125°C, Vbb=15...30V, VCC=4.5...5.5V, unless otherwise specified Symbol Limit Values Unit Test Condition min. typ. max. 0.3 x VCC Input low state voltage (D0 ... D7, DIS, CS, WR) VIL -0.3 Input high state voltage (D0 ... D7, DIS, CS, WR) VIH 0.7 x VCC Input voltage hysteresis (D0 ... D7, DIS, CS, WR) VIHys 100 mV Input pull down current (D0 ... D7, DIS) IIdown 100 µA Input pull up current (CS, WR) -IIup 100 Output disable time (transition DIS to logic low)1)2) Normal operation Turn-off time to 10% VOUT RL = 47Ω tDIS --- 85 170 Output disable time (transition DIS to logic low)1)2)3) Disturbed operation Turn-off time to 10% VOUT RL = 47Ω tDIS --- --- 230 V VCC+ 0.3 µs 1) The time includes the turn-on/off time of the high-side switch and the transmission time via the coreless transformer. 2) If Pin DIS is set to low the outputs are set to low; after DIS set to high a new write cycle is necessary to set the output again. 3) The parameter is not subject to production test - verified by design/characterization 4.8 Parallel Interface Input Timing Parameter at Tj = -25 ... 125°C, Vbb=15...30V, VCC=4.5...5.5V, unless otherwise specified Symbol Limit Values Unit Test Condition min. typ. max. tWRPW 20 Data setup time before WR tDS 20 Data hold time after WR tDH 10 Chip select valid to WR tCSWR 0 WR logic high to CS logic high tWHCS 10 tCSD 10 WR pulse width Delay to next CS cycle Datasheet 14 ns Version 2.3, 2009-09-16 ISOFACE™ ISO1H801G Electrical Characteristics 4.9 Reverse Voltage Parameter at Tj = -25 ... 125°C, Vbb=15...30V, VCC=4.5...5.5V, unless otherwise specified Symbol Reverse voltage1)2) RGND = 0 Ω RGND = 150 Ω -Vbb Diode forward on voltage IF = 1.25A, VDx = low, each channel -VON Limit Values Unit Test Condition min. typ. max. 1 45 1.2 V 1) defined by Ptot 2) not subject to production test, specified by design 4.10 Isolation and Safety-Related Specification Parameter Measured from input terminals to output terminals, unless otherwise specified Value Unit Conditions Rated dielectric isolation voltage VISO 500 VAC 1 minute duration 1) Minimum external air gap (clearance) 2.6 mm shortest distance through air. Minimum external tracking (creepage) 2.6 mm shortest distance path along body. Minimum Internal Gap 0.01 mm Insulation distance through insulation 1) The parameter is not subject to production test, verified by characterization; Production Test with 1100V, 100ms duration Note: For Qualification Report contact your local Infineon Technologies office! Datasheet 15 Version 2.3, 2009-09-16 ISOFACE™ ISO1H801G Electrical Characteristics Datasheet 16 Version 2.3, 2009-09-16 ISOFACE™ ISO1H801G Electrical Characteristics Datasheet 17 Version 2.3, 2009-09-16 ISOFACE™ ISO1H801G Package Outlines Package Outlines 0.65 0.25 +0.13 15.74 ±0.1 (Heatslug) 6.3 (Mold) 5˚ ±3˚ 0.02 2.8 0.1 C B 0.25 +0.07 - 0 +0.1 1.1 ±0.1 11 ±0.15 1) 1.3 (Plastic Dual Small Outline Package) 3.25 ±0.1 PG-DSO-36 3.5 MAX. 5 Heatslug 0.95 ±0.15 36x 0.25 M A B C 14.2 ±0.3 0.25 B 19 19 1 18 10 36 5.9 ±0.1 (Metal) 36 3.2 ±0.1 (Metal) Bottom View Index Marking 1 x 45˚ 15.9 ±0.1 1) (Mold) 1) Figure 11 Datasheet A 13.7 -0.2 (Metal) Does not include plastic or metal protrusion of 0.15 max. per side 1 Heatslug gps09181_1 PG-DSO-36 18 Version 2.3, 2009-09-16 Total Quality Management Qualität hat für uns eine umfassende Bedeutung. Wir wollen allen Ihren Ansprüchen in der bestmöglichen Weise gerecht werden. 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