INFINEON TLE5012

September 2009
TLE5012
TLE5012-E0318
TLE5012-E0742
GMR-Based Angular Sensor
for Rotor Position Sensing
Target
Data Sheet
V 0.46
Sensors
Edition 2009-09
Published by
Infineon Technologies AG
81726 München, Germany
© 2008 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
TLE5012
TLE5012 GMR-Based Angular Sensor
Revision History: 2009-09, V 0.46
Previous Version: V0.41
Page
Subjects (major changes since last revision)
13
PRO-SIL Disclaimer added
17
Table 2, Magnetic Field Induction and Storage Temperature amended
22
Table 8, Angle Delay Time with Prediction added, Figure 12 updated
27
Table 13, Lock updated; more detailed description of CMD word
28
Table 14, STAT updated
31-46
Registertype updated
47
Table 16 notes amended
52
Chapter 3.6 addded
general
Correction of typing errors
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Target Data Sheet
3
V 0.46, 2009-09
TLE5012
1
1.1
1.2
1.3
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.1
2.2
2.3
2.4
2.5
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.5.6
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Internal Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SD-ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Digital Signal Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Safety Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.5
3.5.1
3.5.1.1
3.5.1.2
3.5.1.3
3.5.1.3.1
3.5.2
3.5.3
3.5.4
3.6
3.6.1
3.7
3.7.1
3.7.2
3.7.3
3.7.4
Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GMR Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Angle Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Supply (CLK Timing Definition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous Serial Communication (SSC) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSC Timing Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSC Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLE5012 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulse Width Modulation Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hall Switch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Incremental Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Test Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Supply Voltage Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VDD Overvoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GND - Off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VDD - Off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
14
17
17
19
19
19
20
21
21
23
24
24
25
27
30
31
46
48
50
52
52
53
53
53
53
54
4
4.1
4.2
4.3
4.4
4.5
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
55
55
56
56
56
Target Data Sheet
4
7
7
8
8
V 0.46, 2009-09
TLE5012
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Sensitive Bridges of the GMR Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ideal Output of the GMR Sensor Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Configuration (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
TLE5012 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PRO-SILTM Logo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Application Circuit for TLE5012 with SSC and PWM Interface (using internal CLK) . . . . . . . . . . . 14
Application Circuit for TLE5012 with HS Mode (using internal CLK) . . . . . . . . . . . . . . . . . . . . . . . 15
Application Circuit for TLE5012 with SSC and IIF Interface (using external CLK) . . . . . . . . . . . . . 15
Application Circuit for TLE5012 with only PWM Interface (using internal CLK) . . . . . . . . . . . . . . . 16
Offset and Amplitude Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
TLE5012 Signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Delay of Sensor Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
External CLK Timing Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SSC Configuration in Sensor-Slave Mode with Push-Pull Outputs (High Speed Application) . . . . 24
SSC Configuration in Sensor-Slave Mode and Open Drain (Safe Bus Systems) . . . . . . . . . . . . . 25
SSC Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SSC Data Transfer (Data Read Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SSC Data Transfer (Data Write Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SSC Bit Ordering (Read Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Fast CRC Polynomial Division Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Typical Example for a PWM Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Hall Switch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
HS Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Incremental Interface Protocol with symbolically illustration of SPI-Interface. . . . . . . . . . . . . . . . . 51
IIF Index Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
ADC Test Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
OV Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
GND - Off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
VDD - Off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
PG-DSO-8 Package Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Footprint PG-DSO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Tape and Reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Target Data Sheet
5
V 0.46, 2009-09
TLE5012
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic GMR Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Angle Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLK Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAD Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSC Push-Pull Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSC Open Drain Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Structure of the Command Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Structure of the Safety Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hall Switch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Incremental Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Target Data Sheet
6
11
17
17
19
19
20
21
22
23
24
25
26
27
28
30
47
48
51
53
55
V 0.46, 2009-09
TLE5012
1
Product Description
1.1
Overview
The TLE5012 is a 360° angle sensor that detects the orientation of a
magnetic field. This is achieved by measuring sine and cosine angle
components with monolithic integrated Giant Magneto Resistance
(iGMR) elements.
High precision angle values are achieved over temperature and lifetime
using internal autocalibration algorithm.
Data communications are accomplished with a bi-directional SSC
Interface that is SPI compatible.
The absolute angle value and other values are transmitted via SSC or via a Pulse-Width-Modulation (PWM)
Protocol. Also the sine and cosine raw values can be read out. These raw signals are digitally processed internally
to calculate the angle orientation of the magnetic field (magnet).
The TLE5012 is a precalibrated sensor. The calibration parameters are stored in laser fuses. At start-up the values
of the fuses are written into Flip-Flops, where these values can be changed by the application specific parameters.
The TLE5012-E0318 and TLE5012-E0742 are especially configured in a Hall-Switch emulation mode for motors
with three or seven pole pairs.
Online diagnostic functions are provided to ensure reliable operation.
Product Type
Marking
Ordering Code
Package
TLE5012
5012
SP000477068
PG-DSO-8
TLE5012-E0318
5012E03
SP000611246
PG-DSO-8
TLE5012-E0742
5012E07
SP000611250
PG-DSO-8
Target Data Sheet
7
V 0.46, 2009-09
TLE5012
Product Description
1.2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Features
Giant Magneto Resistance (GMR)-based principle
Integrated magnetic field sensing for angle measurement
Full calibrated 0 - 360° angle measurement with revolution counter and angle speed measurement
Two separate highly accurate single bit SD-ADC
15 bit representation of absolute angle value on the output (resolution of 0.01°)
16 bit representation of sine / cosine values on the interface
Max. 1.0° angle error over lifetime and temperature with activated auto-calibration
Bi-directional SSC Interface up to 8Mbit/s
Supports SIL3 with diagnostic functions and status information
Interfaces: SSC, PWM, Incremental Interface (IIF), Hall Switch Mode (HSM)
0.25 µm CMOS technology
Automotive qualified: -40°C to 150°C (Junction Temperature)
ESD > 2kV (HBM)
Green package with lead-free (Pb-free) plating
1.3
Application Example
The TLE5012 GMR-Based Angular Sensor is designed for angular position sensing in automotive applications,
such as:
•
•
•
•
Electrical Commutated Motor (e.g. used in Electric Power Steering (EPS))
Rotary Switch
Steering Angle
General Angular Sensing
Target Data Sheet
8
V 0.46, 2009-09
TLE5012
Functional Description
2
Functional Description
2.1
General
The GMR sensor is implemented using vertical integration. This means that the GMR sensitive areas are
integrated above the logic portion of the TLE5012 device. These GMR elements change their resistance
depending on the direction of the magnetic field.
Four individual GMR elements are connected to one Wheatstone Sensor Bridge. These GMR elements sense one
of two components of the applied magnetic field:
•
•
X component, Vx (cosine) or the
Y component, Vy (sine)
The advantage of a full-bridge structure is that the amplitude of the GMR signal is doubled and temperature effects
cancel out each other.
90°
GMR Resistors
S
0°
VX
N
ADCX +
Figure 1
VY
ADCX -
GND
ADCY+
ADCY-
VDD
Sensitive Bridges of the GMR Sensor
Note: In Figure 1, the arrows in the resistors symbolize the direction of the Reference Layer, which is used for the
further explanation.
The output signal of each bridge is only unambiguous over 180° between two maxima. Therefore two bridges are
orientated orthogonally to each other to measure 360°.
With the trigonometric function ARCTAN, the true 360° angle value can be calulated which is represented by the
relation of X and Y signals.
Because only the relative values influence the result, the absolute size of the two signals is of minor importance.
Therefore, most influences to the amplitudes are compensated.
Target Data Sheet
9
V 0.46, 2009-09
TLE5012
Functional Description
Y Component (SIN)
VY
X Component (COS)
VX
V
VX (COS)
0°
90°
180°
270°
360°
Angle α
VY (SIN)
Figure 2
Ideal Output of the GMR Sensor Bridges
Target Data Sheet
10
V 0.46, 2009-09
TLE5012
Functional Description
2.2
Pin Configuration
8
7
6
5
1
2
3
4
Figure 3
Pin Configuration (Top View)
2.3
Pin Description
Table 1
Pin Description
Center of Sensitive
Area
Pin No.
Symbol
In/Out
Function
1
CLK
I
External Clock (must be
connected to GND for PWM
output)
2
SCK
I
SSC Clock
3
CSQ
I
SSC Chip Select
4
DATA / HS3
I/O
SSC Data / IIF Index / Hall
Switch Signal 3
5
IFA
(IIF_A / HS1 / PWM)
O
Interface A:
IIF Phase A; Hall Switch Signal
1 or PWM output (depends on
external application circuit)
6
VDD
-
Supply Voltage
7
GND
-
Ground
8
IFB
(IIF_B / HS2)
O
Interface B:
IIF Phase B or Hall Switch
Signal 2
Target Data Sheet
11
V 0.46, 2009-09
TLE5012
Functional Description
2.4
Block Diagram
TLE5012
VDD
Osc
VRG
VRA
VRD
PLL
X
GMR
SDADC
CSQ
Digital
Signal
Processing
Y
GMR
SDADC
Temp
SDADC
CLK
SSC
Interface
SCK
DATA
CCU
Cordic
Incremental IF
PWM
HSM
Fuses
IFA
IFB
GND
Figure 4
TLE5012 Block Diagram
2.5
Functional Block Description
2.5.1
Internal Power Supply
The internal stages of the TLE5012 are supplied with different voltage regulators.
•
•
•
GMR Voltage Regulator VRG
Analog Voltage Regulator VRA
Digital Voltage Regulator VRD (derived from VRA)
These regulators are directly connected to the supply voltage VDD.
2.5.2
Oscillator and PLL
The internal frequency oscillator feeds the Phase Locked Loop (PLL). Also the external clock (CLK) can be used
therefore.
2.5.3
SD-ADC
The SD-ADCs transform the analog GMR-voltages and temperature-voltage into the digital domain.
Target Data Sheet
12
V 0.46, 2009-09
TLE5012
Functional Description
2.5.4
Digital Signal Processing Unit
The Digital Signal Processing Unit (DSPU) contains the:
•
•
•
Capture Compare Unit (CCU), which is used to generate the PWM signal
COordinate Rotation DIgital Computer (CORDIC), which contains the trigonometric function for angle
calculation
Fuses, which contain the calibration parameters
2.5.5
Interfaces
Different Interfaces can be selected:
•
•
•
•
SSC Interface
PWM
Incremental Interface
Hall Switch Mode
2.5.6
Safety Features
The TLE5012 offers a multiplicity on safety features to support Safety Integrity Level (SIL). Sensors with this
performance are identified by the following logo:
Figure 5
PRO-SILTM Logo
Safety features are:
•
•
•
•
•
•
Test vectors switchable to ADC- input
Inversion or combination of filter input streams
Data transmission check via 8bit Cyclic Redundancy Check (CRC)
Self test routines
Two independent active interfaces possible
Overvoltage and undervoltage detection
Disclaimer
PRO-SIL™ is a Registered Trademark of Infineon Technologies AG.
The PRO-SIL™ Trademark designates Infineon products which contain SIL Supporting Features.
SIL Supporting Features are intended to support the overall System Design to reach the desired SIL (according
to IEC61508) or A-SIL (according to ISO26262) level for the Safety System with high efficiency.
SIL respectively A-SIL certification for such a System has to be reached on system level by the System
Responsible at an accredited Certification Authority.
SIL stands for Safety Integrity Level (according to IEC 61508)
A-SIL stands for Automotive-Safety Integrity Level (according to ISO 26262)
Target Data Sheet
13
V 0.46, 2009-09
TLE5012
Specification
3
Specification
3.1
Application Circuit
The application circuit in Figure 6, Figure 7, Figure 8 and Figure 9 show the different communication possibilities
of TLE5012.
TLE5012
VDD (4.5 – 5.5V)
100n
Osc
VRG
VRA
1 kΩ
VRD
CLK
PLL
X
GMR
CSQ
SDADC
Digital
Signal
Processing
Y
GMR
SDADC
SCK
SSC
Interface
DATA
SDADC
*)
CCU
Cordic
Temp
SSC
Fuses
IFA (PWM)
Incremental IF
PWM
HSM
IFB
10 kΩ
GND
PWM
IFB could be remain open or
connected via 10 kΩ resistor to
GND.
* recommended , e.g. 470 Ω
Figure 6
Application Circuit for TLE5012 with SSC and PWM Interface (using internal CLK)
Figure 6 shows a basic block-diagram of the TLE5012 with PWM- Interface. This interface is selectable by
connecting CLK to GND. Additionally to the PWM the SSC Interface could be used. Within the SSC- Interface the
PWM mode is selectable between Push-Pull and Open Drain.
Target Data Sheet
14
V 0.46, 2009-09
TLE5012
Specification
TLE5012
VRG
VRA
VRD
CLK
PLL
X
GMR
Digital
Signal
Processing
SDADC
Temp
SDADC
*)
*)
*)
CSQ
SDADC
Y
GMR
VDD (4.5 – 5.5V)
100n
Osc
SSC
Interface
SCK
DATA (HS3)
CCU
Cordic
IFA (HS1)
Incremental IF
PWM
HSM
Fuses
IFB (HS2)
GND
* recommended , e.g. 2.2 kΩ
Figure 7
Application Circuit for TLE5012 with HS Mode (using internal CLK)
Figure 7 shows a basic block-diagram of the TLE5012 with HS Mode. This interface is selectable by connecting
CLK to GND and CSQ to VDD. Additionally to the HSM the SSC Interface could be used by pulling CSQ to GND.
Within the SSC- Interface the HS Mode is selectable between Push-Pull and Open Drain.
VDD (4.5 – 5.5V)
TLE5012
100n
Osc
VRG
VRA
VRD
**)
CLK
***)
PLL
X
GMR
SDADC
SSC
Interface
SDADC
SCK
DATA
*)
SSC
CCU
Cordic
Temp
PLL
CSQ
SDADC
Digital
Signal
Processing
Y
GMR
µC
Fuses
IFA (IIF_A)
Incremental IF
PWM
HSM
IFB (IIF_B)
CCU
GND
*) recommended , e.g. 470 Ω
**) connected to V DD for use of internal CLK
***) connected to microcontroller for use of external CLK
Figure 8
Application Circuit for TLE5012 with SSC and IIF Interface (using external CLK)
Figure 8 shows a basic block-diagram of an angle sensor system using a TLE5012 and a microcontroller for rotor
positioning applications. The depicted Interface-Configuration is needed for High-Speed applications like electrical
commutated motor drives. It is possible to connect the TLE5012 to a microcontroller via Incremental Interface and
for safety reasons also via SSC-Interface.
Target Data Sheet
15
V 0.46, 2009-09
TLE5012
Specification
TLE5012
VRG
VRA
VDD (4.5 – 5.5V)
100 n
Osc
1 kΩ
VRD
CLK
PLL
X
GMR
CSQ
SDADC
Digital
Signal
Processing
Y
GMR
SDADC
SCK
SSC
Interface
DATA
CCU
Cordic
Temp
SD ADC
10 kΩ
Fuses
DATA and IFB could be remain
open or connected via 10 kΩ
resistor to GND .
IFA (PWM)
Incremental IF
PWM
HSM
IFB
10 kΩ
GND
Figure 9
Application Circuit for TLE5012 with only PWM Interface (using internal CLK)
Target Data Sheet
16
V 0.46, 2009-09
TLE5012
Specification
3.2
Absolute Maximum Ratings
Table 2
Absolute Maximum Ratings
Parameter
Symbol
Values
Unit Note / Test Condition
Min.
Typ.
Max.
Voltage on VDD pin respect to
ground (VSS)
VDD
-0.5
-
6.5
V
max 40 h/Lifetime
Voltage on any pin respect to
ground (VSS)
VIN
-0.5
-
6.5
V
additionally VDD + 0.5 V may
not be exceeded
Junction Temperature
TJ
-40
-
150
°C
-
-
150
°C
for 1000h not additive
-
-
125
mT
max. 5 min @ tA = 25°C
-
-
100
mT
max. 5 h @ tA = 25°C
-
-
70
mT
max. 1000h @ tA = 85°C; not
additive
-
-
60
mT
max. 1000h @ tA = 100°C; not
additive
-40
-
150
°C
without magnetic field
Magnetic Field Induction
Storage Temperature
B
TST
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the device.
3.3
Operating Range
The following operating conditions must not be exceeded in order to ensure correct operation of the TLE5012. All
parameters specified in the following sections refer to these operating conditions, unless otherwise noticed.
Table 3 is valid for -40°C < TJ < 150°C.
Table 3
Operating Range
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note / Test Condition
Supply Voltage
VDD
4.5
5.0
5.5
V
1)
Output Current (DATA-Pad)
IQ
-
-
-25
mA
PAD_DRV =’0x’, sink current2)
-
-
-5
mA
PAD_DRV =’10’, sink current2)
-
-
-0.4
mA
PAD_DRV =’11’, sink current2)
-
-
-15
mA
PAD_DRV =’0x’, sink current2)
-
-
-5
mA
PAD_DRV =’1x’, sink current2)
-0.3
-
5.5
V
VDD + 0.3 V may not be
exceeded
Output Current (IFA / IFB-Pad)
Input Voltage
Target Data Sheet
IQ
VIN
17
V 0.46, 2009-09
TLE5012
Specification
Table 3
Operating Range (cont’d)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note / Test Condition
Magnetic Induction
BXY
30
-
50
mT
Angle Range
Ang
0
-
360
°
in X/Y direction3)
1) Directly blocked with 100nF ceramic capacitor
2) Max. current to GND over Open Drain Output
3) Values refer to an homogenous magnetic field (BXY) without vertical magnetic induction (BZ = 0mT).
Note: The thermal resistances listed in Table 20 “Package Parameters” on Page 55 must be used to calculate
the corresponding ambient temperature.
Calculation of the Junction Temperature
The total power dissipation PTOT of the chip increases its temperature above the ambient temperature.
The power multiplied by the total thermal resistance RthJA (Junction to Ambient) leads to the final junction
temperature. RthJA is the sum of the addition of the values of the two components Junction to Case and Case to
Ambient.
(1)
RthJA = RthJC + RthCA
TJ = TA + ∆T
∆T = RthJA × PTOT = RthJA × (VDD × I DD + VOUT × I OUT )
(IDD, I OUT > 0, if direction is into IC)
Example (assuming no load on Vout):
(2)
VDD = 5V
I DD = 12mA
K 
∆T = 150  × 5[V ]× 0.012[A] + 0[VA] = 9 K
W 
For moulded sensors, the calculation with RthJC is more adequate.
Target Data Sheet
18
V 0.46, 2009-09
TLE5012
Specification
3.4
Characteristics
3.4.1
Electrical Parameters
The indicated electrical parameters apply to the full operating range, unless otherwise specified. The typical values
correspond to a supply voltage VDD = 5.0 V and 25 °C, unless individually specified. All other values correspond
to -40 °C < TJ < 150°C.
Table 4
Electrical Parameters
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Note / Test Condition
Supply Current
IDD
-
12
13
mA
POR Level
VPOR
2.0
-
2.9
V
POR Hysteresis
VPORhy
-
30
-
mV
Power On Time
tPon
-
4
5
ms
Input Signal Low Level
VL
-
-
0.3 VDD
V
Input Signal High Level
VH
0.7 VDD -
-
V
Pull-Up Current
IPU
-10
-
-225
µA
CSQ
-10
-
-150
µA
DATA
10
-
225
µA
SCK
10
-
150
µA
CLK, IFA, IFB
-
-
1
V
DATA; IQ = - 25 mA
(PAD_DRV=’0x’), IQ = - 5 mA
(PAD_DRV=’10’), IQ = - 0.4 mA
(PAD_DRV=’11’)
-
-
1
V
IFA,IFB; IQ = - 15 mA
(PAD_DRV=’0x’), IQ = - 5 mA
(PAD_DRV=’1x’)
Unit
Notes
Pull-Down Current
Output Signal Low Level
IPD
VOL
Power On Reset
VDD > VDDmin1)
1) Within “Power On Time” write access is not permitted
3.4.2
ESD Protection
Table 5
ESD Protection
Parameter
ESD Voltage
Symbol
Values
min.
max.
VHBM
-
±2.0
kV
Human Body Model1)
VSDM
-
±0.5
kV
Socketed Device Model2)
1) Human Body Model (HBM) according to: JEDEC EIA/JESD22-A114-B
2) Socketed Device Model (SDM) according to: ESD ASS.STD.DS5.3-93
Target Data Sheet
19
V 0.46, 2009-09
TLE5012
Specification
3.4.3
GMR Parameters
All parameters apply over the full operating range, unless otherwise specified.
Table 6
Basic GMR Parameters
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
RGADC
-
-
±23230
digits
AX, AY
6000
9500
15781
digits
at calibration conditions
3922
-
20620
digits
operating range
k
87.5
100
112.49
%
at calibration conditions
OX, OY
-2048 0
+2047
digits
at calibration conditions
X, Y orthogonality error
ϕ
-11.25 0
+11.24
°
at calibration conditions
X, Y without field
X 0, Y0
-5000 -
+5000
digits
without magnet 4)
X, Y output range
X, Y amplitude
1)
X, Y synchronism 2)
X, Y offset
1)
2)
3)
4)
3)
see Figure 10
k = 100*(AX/AY)
OY=(YMAX + YMIN) / 2; OX = (XMAX + XMIN) / 2
Not tested
VY
+A
0
Offset
0°
90°
180°
270°
360°
Angle
-A
Figure 10
Offset and Amplitude Definition
Target Data Sheet
20
V 0.46, 2009-09
TLE5012
Specification
3.4.4
Angle Performance
After internal calculation the sensor has a remaining error, as shown in Table 7. The error value refers to BZ = 0mT
and the operating conditions given in Table 3 “Operating Range” on Page 17.
The overall angle error represents the relative angle error. This error describes the deviation to the reference line
after zero angle definition.
Table 7
Angle Performance
Parameter
Symbol
Values
Min.
Typ.
Note / Test Condition
Max.
1)
1.0
°
including lifetime and
temperature drift2)3)
1.6
°
including temperature
drift2)3)
αErr
-
0.6
Overall Angle Error (without auto- αErr
calibration)
-
0.61)
Overall Angle Error (with autocalibration)
Unit
1) At 25°C, B =30 mT
2) Including hysteresis error, caused by revolution direction change.
3) Only with calibrated GMR-compensation parameters of customer setup; Relative error after zero angle definition.
Autocalibration
The autocalibration enables online parameter calculation and reduces therefore the angle error due to
misalignments.
After start-up the parameters out of the fuses get loaded into flip-flops. The TLE5012 updates these parameters
after a full revolution. The update can be chosen within the Autocalibration Mode (AUTOCAL) bit. It is possible to
do the update after every 22.5°, 11.25° or after tupd.
3.4.5
Signal Processing
The signal path of the TLE5012 is depicted in Figure 11. It consists of the GMR-bridge, ADC, filter and angle
calculation. Depending on the filter configuration a different total delay time is achieved. Additional to this delay
time, the delay time of the interface has to be considered. The delay time leads to an additional angle error at
higher speeds. With enabling the prediction, the signal delay time will be reduced (Figure 12).
TLE5012
Microcontroller
tupd
X
GMR
SDADC
Filter
Angle
Calculation
Y
GMR
SDADC
Filter
tdelIF
tdel
Figure 11
IF
TLE5012 Signal path
At FIR_MD = 0 only raw values can be read out, due to the more time consuming angle calculation.
Target Data Sheet
21
V 0.46, 2009-09
TLE5012
Specification
Table 8
Signal Processing
Parameter
Symbol
Update Rate at Interface
tupd
Angle Delay Time3)
tdel
Angle Delay Time with
Prediction3)
tdel
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
-
21.3
-
µs
FIR_MD = 0 (only raw
values)1)2)
-
42.7
-
µs
FIR_MD = 11)2)
-
85.3
-
µs
FIR_MD = 2 (default)1)2)
-
170.6
-
µs
FIR_MD = 31)2)
-
60
70
µs
FIR_MD = 11)2)
-
80
95
µs
FIR_MD = 21)2)
-
120
140
µs
FIR_MD = 31)2)
-
20
30
µs
FIR_MD = 1; PREDICT = 1
1)2)
-
5
20
µs
FIR_MD = 2; PREDICT = 1
1)2)
-
-40
-20
µs
FIR_MD = 3; PREDICT = 1
1)2)
Angle Noise
NAngle
-
0.11
-
°
FIR_MD = 0, (1 Sigma)2)
-
0.08
-
°
FIR_MD = 1, (1 Sigma)2)
-
0.05
-
°
FIR_MD = 2, (1 Sigma)2)
(default)
-
0.04
-
°
FIR_MD = 3, (1 Sigma)2)
1) depends on internal oscillator frequency variation (Chapter 3.4.6)
2) guaranteed by laboratory characterization
3) valid at constant rotation speed
Sensor output
Angle
Magnetic field
direction
tdel
Figure 12
tupd
With
Prediction
Without
Prediction
time
Delay of Sensor Output
Target Data Sheet
22
V 0.46, 2009-09
TLE5012
Specification
3.4.6
Clock Supply (CLK Timing Definition)
If the external clock supply is selected, the clock signal input ’CLK’ must fulfill certain requirements which are
described in the following:
•
•
•
The high or low pulse width must not exceed the specified values, because the PLL needs a minimum pulse
width and must be spike filtered.
The duty cycle factor should be 0.5 but can deviate to the values limited by tCLKh(f_min) and tCLKl(f_min).
The PLL is triggered at the positive edge of the clock. If more than 2 edges are missing, a chip reset is
generated automatically.
tCLK
tCLKh
tCLKl
VH
VL
t
Figure 13
External CLK Timing Definition
Table 9
CLK Timing Specification
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
fCLK
3.8
4.0
4.2
MHz
CLKDUTY
30
50
70
%
CLK Rise Time
tCLKr
-
-
30
ns
from VL to VH
CLK Fall Time
tCLKf
-
-
30
ns
from VH to VL
Digital Clock
fDIG
22.8
24
25.2
MHz
Internal Oscillator Frequency
fCLK
3.8
4.0
4.2
MHz
Input Frequency
CLK Duty Cycle
1)2)
1) Minimum Duty Cycle Factor: tCLKh(f_min) / tCLK(f_min) with tCLK(f_min)= 1 / fCLK(f_min)
2) Maximum Duty Cycle Factor: tCLKh(f_max) / tCLK(f_min) with tCLKh(f_max)= tCLK(f_min) - tCLKl(min)
Target Data Sheet
23
V 0.46, 2009-09
TLE5012
Specification
3.5
Interfaces
Within the register MOD_3, the driver strength and so the slope can be varied of the sensor output. The driver
strength is specified in Table 3 and the slope fall and rise time in Table 10.
Table 10
PAD Characteristic
Parameter
Symbol
Output Fall Time
tfall, trise
Output Rise Time
3.5.1
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
-
-
8
ns
DATA, 50pF,
PAD_DRV=’00’
-
-
28
ns
DATA, 50pF,
PAD_DRV=’01’
-
-
45
ns
DATA, 50pF,
PAD_DRV=’10’
-
-
130
ns
DATA, 20pF,
PAD_DRV=’11’
-
-
10
ns
IFA/IFB, 20pF,
PAD_DRV=’0x’
-
-
tbd
ns
IFA/IFB, 20pF,
PAD_DRV=’1x’
Synchronous Serial Communication (SSC) Interface
The 3-pin SSC Interface has a bi-directional push-pull data line, serial clock signal and chip select. The SSC
Interface is designed to communicate with a microcontroller peer to peer for fast applications.
SSC Communication
for peer to peer Data Transmission between TLE5012 and µC
(SSC Slave) TLE 5012
µC (SSC Master)
DATA
Shift Reg.
**)
MRST
EN
MTSR
SCK
CSQ
*)
*)
SCK
Shift Reg.
EN
Clock Gen.
CSQ
*) optional , e.g. 100 Ω
**) optional , e.g. ≥ 470 Ω
Figure 14
SSC Configuration in Sensor-Slave Mode with Push-Pull Outputs (High Speed Application)
Target Data Sheet
24
V 0.46, 2009-09
TLE5012
Specification
Another possibility is a 3-pin SSC Interface with bidirectional open-drain data line, serial clock signal and chip
select. This setup is designed to communicate with a microcontroller in a bus system, together with other SSC
slaves (e.g. two TLE5012 for redundancy reasons). This mode can be activated using bit SSC_OD.
(SSC Slave) TLE 5012
µC (SSC Master)
typ. 1kΩ
DATA
Shift Reg.
*)
*)
MRST
Shift Reg.
MTSR
SCK
*)
CSQ
*)
SCK
Clock Gen.
CSQ
*) optional , e.g. 100 Ω
Figure 15
SSC Configuration in Sensor-Slave Mode and Open Drain (Safe Bus Systems)
3.5.1.1
SSC Timing Definition
tCSs
tCSh
tSCKp
tCSoff
CSQ
tSCKh
tSCKl
SCK
DATA
tDATAs
Figure 16
tDATAh
SSC Timing
SSC Inactive Time (CSoff)
The SSC inactive time defines the delay time after a transfer before the TLE5012 can be selected again.
Table 11
SSC Push-Pull Timing Specification
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
SSC Baud Rate
fSSC
-
8.0
-
Mbit/s
CSQ Setup Time
tCSs
105
-
-
ns
CSQ Hold Time
tCSh
105
-
-
ns
Target Data Sheet
25
Note / Test Condition
V 0.46, 2009-09
TLE5012
Specification
Table 11
SSC Push-Pull Timing Specification (cont’d)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note / Test Condition
SSC inactive time
CSQ off
tCSoff
600
-
-
ns
SCK Period
tSCKp
120
125
-
ns
SCK High
tSCKh
40
-
-
ns
SCK Low
tSCKl
30
-
-
ns
DATA Setup Time
tDATAs
25
-
-
ns
DATA Hold Time
tDATAh
40
-
-
ns
Write Read Delay
twr_delay
130
-
-
ns
Table 12
SSC Open Drain Timing Specification
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note / Test Condition
Pull-up Resistor = 1kΩ
SSC Baud Rate
fSSC
-
2.0
-
Mbit/s
CSQ Setup Time
tCSs
300
-
-
ns
CSQ Hold Time
tCSh
400
-
-
ns
CSQ off
tCSoff
600
-
-
ns
SCK Period
tSCKp
500
-
-
ns
SCK High
tSCKh
-
190
-
ns
SCK Low
tSCKl
-
190
-
ns
DATA Setup Time
tDATAs
25
-
-
ns
DATA Hold Time
tDATAh
40
-
-
ns
Write Read Delay
twr_delay
130
-
-
ns
Target Data Sheet
26
SSC inactive time
V 0.46, 2009-09
TLE5012
Specification
3.5.1.2
SSC Data Transfer
The SSC data transfer is word aligned. The following transfer words are possible:
•
•
•
Command word (to access and change operating modes of the TLE5012)
Data words (any data transferred in any direction)
Safety word (confirms the data transfer and provide status information)
twr_delay
COMMAND
READ Data 1
READ Data 2
SAFETY-WORD
SSC-Master is driving DATA
SSC-Slave is driving DAT A
Figure 17
SSC Data Transfer (Data Read Example)
twr_delay
COMMAND
WRITE Data 1
SAFETY-WORD
SSC-Master is driving DATA
SSC-Slave is driving DAT A
Figure 18
SSC Data Transfer (Data Write Example)
Command Word
The TLE5012 is controlled by a command word. It is sent first at every data transmission.The structure of the
command word is shown in Table 13, where the UPD-bit allows the access to current values or updated values.
If an update command is issued and the update bit (UPD) is set, the immediate values are stored in the update
buffer simultaneously. This enables a snapshot of all necessary system parameters at the same time. Bits with an
update buffer are marked by an “u” in type of register description. The initialization of such an update is descripted
on page 29.
Table 13
Structure of the Command Word
Name
Bits
Description
RW
[15]
Read - Write
0:Write
1:Read
Lock
[14..11]
4 bit Lock Value
0000B: Default Operating Access for addresses 0x00:0x04
1010B: Config- Access for addresses 0x05:0x11
Target Data Sheet
27
V 0.46, 2009-09
TLE5012
Specification
Table 13
Structure of the Command Word
Name
Bits
Description
UPD
[10]
Update-Register Access
0: Access to current values
1: Access to updated values
ADDR
[9..4]
6 bit Address
ND
[3..0]
4 bit Number of Data-Words
Safety Word
The safety word contains following bits:
Table 14
Structure of the Safety Word
Name
Bits
Description
STAT
Chip and Interface Status
[15]
Indication of Chip-Reset (resets after readout) via SSC
0: Reset occurred
1: No reset
Reset: 1B
[14]
System Error (e.g. Overvoltage; Undervoltage; VDD-, GND- off; ROM;...)
0: Error occurred (S_VR; S_DSPU; S_OV; S_XYOL: S_MAGOL; S_ADCM)
1: No error
[13]
Interface Access Error (access to wrong address; wrong lock)
0: Error occurred
1: No error
[12]
Valid Angle Value (no system error; no interface error; NO_GMR_A = ’0’;
NO_GMR_XY=’0’)
0: Angle value invalid
1: Angle value valid
RESP
[11..8]
Sensor Number Response Indicator
The sensor no. bit is pulled low and the other bits are high.
CRC
[7..0]
Cyclic Redundancy Check (CRC)
Target Data Sheet
28
V 0.46, 2009-09
TLE5012
Specification
Data Communication via SSC
SSC Transfer
twr_delay
Command Word
Data Word (s)
SCK
DATA
MSB
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
MSB
1
LSB
CSQ
RW
LOCK
UPD
ADDR
LENGTH
SSC -Master is driving DAT A
SSC -Slave is driving DAT A
Figure 19
SSC Bit Ordering (Read Example)
The data communication via SSC interface has the following characteristic:
•
•
•
•
•
•
•
•
•
•
•
•
The data transmission order is “Most Significant Bit (MSB) first”.
Data is put on the data line with the rising edge on SCK and read with the falling edge on SCK.
The SSC Interface is word-aligned. All functions are activated after each transmitted word.
A “high” condition on the negated Chip Select pin (CSQ) of the selected TLE5012 interrupts the transfer
immediately. The CRC calculator is automatically reset.
After changing the data direction, a delay (twr_delay) has to be considered before continuing the data transfer.
This is necessary for internal register access.
Every access to the TLE5012 with the number of data (ND) ≥ 1 is performed with address auto-increment.
At an overflow at address 3FH the transfer continuous at address 00H.
With ND = 0 no auto-increment is done and a continuously readout of the same address can be realized.
Afterwards no Safety Word is send and the transfer ends with high condition on CSQ.
After every data transfer with ND ≥ 1 the 16 bit Safety Word will be appended by the selected TLE5012.
At a rising edge of CSQ without data transfer before (no SCK-pulse), the update-registers are updated with
according values.
After sending the Safety Word the transfer ends. To start another data transfer, the CSQ has to be deselected
once for tCSoff.
The SSC is default Push-Pull. The Push-Pull driver is only active, if the TLE5012 has to send data, otherwise
the Push-Pull is disabled for receiving data from the microcontroller.
Cyclic Redundancy Check (CRC)
•
•
•
•
•
•
This CRC is according to the J1850 Bus-Specification.
Every new transfer resets the CRC generation.
Every Byte of a transfer will be taken into account to generate the CRC (also the sent command(s)).
Generator-Polynomial: X8+X4+X3+X2+1, but for the CRC generation the fast-CRC generation circuit is used
(see Figure 20)
The remainder of the fast CRC circuit is initial set to ’11111111B’.
Remainder is inverted before transmission.
Serial
CRC
output
X7
1
X6
1
X5
1
X4
1
xor
X3
1
X2
xor
1
X1
xor
1
X0
1
&
xor
Input
TX_CRC
parallel
Remainder
Figure 20
Fast CRC Polynomial Division Circuit
Target Data Sheet
29
V 0.46, 2009-09
TLE5012
Specification
3.5.1.3
Registers Chapter
This chapter defines the registers of the TLE5012. It also defines the read/write access rights of the specific
registers. Table 15 identifies the values with symbols. Access to the registers is accomplished via the SSC
Interface.
Table 15
Registers Overview
Register Short Name
Register Long Name
Offset Address
Page Number
Registers Chapter, TLE5012 Register
STAT
Status Register
00H
31
ACSTAT
Activation Status Register
01H
33
AVAL
Angle Value Register
02H
34
ASPD
Angle Speed Register
03H
35
AREV
Angle Revolution Register
04H
35
FSYNC
Frame Synchronization Register
05H
36
MOD_1
Interface Mode1 Register
06H
37
SIL
SIL Register
07H
38
MOD_2
Interface Mode2 Register
08H
39
MOD_3
Interface Mode3 Register
09H
40
OFFX
Offset X
0AH
41
OFFY
Offset Y
0BH
42
SYNCH
Synchronicity
0CH
42
IFAB
IFAB Register
0DH
43
MOD_4
Interface Mode4 Register
0EH
44
TCO_Y
Temperature Coeffizient Register
0FH
45
ADC_X
X-raw value
10H
45
ADC_Y
Y-raw value
11H
46
The register is addressed wordwise.
Target Data Sheet
30
V 0.46, 2009-09
TLE5012
Specification
3.5.1.3.1
TLE5012 Register
Status Register
STAT
Offset
Status Register
Reset Value
00H
5'B67
6B15
8001H
12B*05B
$
12B*05B
;<
6B520
6B$'&7
5HV
U
UZ
UX
UX
U
UX
6B0$*2/
6B;<2/
6B29
6B'638
6B)86(
6B95
6B:'
6B567
UX
UX
UX
UX
UX
UX
UX
UX
Field
Bits
Type
Description
RD_ST
15
r
Read Status
0B
after readout
1B
status values changed
Reset: 1B
S_NR
14:13
rw
Slave Number
is given at startup by the external circuit of IFA and IFB.
Reset: 00B
NO_GMR_A
12
ru
No GMR Angle Value
0B
valid GMR angle value on the interface
1B
no valid GMR angle value on the interface
Reset: 0B
NO_GMR_XY
11
ru
No GMR XY Values
0B
valid GMR_XY values on the interface
1B
no valid GMR_XY values on the interface
Reset: 0B
S_ROM
10
r
Status ROM
0B
after readout, CRC ok
1B
CRC fail or running
Reset: 0B
S_ADCT
9
ru
Status ADC-Test
0B
after readout
1B
Test vectors out of limit
Reset: 0B
Target Data Sheet
31
V 0.46, 2009-09
TLE5012
Specification
Field
Bits
Type
Description
S_MAGOL
7
ru
Status Magnitude Out of Limit
0B
after readout
1B
GMR-magnitude out of limit (>23230 digits)
Reset: 0B
S_XYOL
6
ru
Status X,Y Data Out of Limit
0B
after readout
1B
X,Y data out of limit (>23230 digits)
Reset: 0B
S_OV
5
ru
Status Overflow
0B
after readout
1B
DSPU overflow occurred
Reset: 0B
S_DSPU
4
ru
Status Digital Signal Processing Unit
0B
after readout
1B
DSPU self test not ok, or selftest is running
Reset: 0B
S_FUSE
3
ru
Status Fuse CRC
0B
after readout, Fuse CRC ok
1B
Fuse CRC fail
Reset: 0B
S_VR
2
ru
Status Voltage Regulator
0B
after readout
1B
VDD overvoltage; VDD undervoltage; VDD-off; GNDoff; or VOVG; VOVA; VOVD too high
Reset: 0B
S_WD
1
ru
Status Watchdog
0B
after chip reset
1B
watchdog counter expired
Reset: 0B
S_RST
0
ru
Status Reset
0B
after readout
1B
indication of power-up, short power-break or active
reset
Reset: 1B
Target Data Sheet
32
V 0.46, 2009-09
TLE5012
Specification
Activation Status Register
ACSTAT
Offset
Activation Status Register
Reset Value
01H
5EFEH
5HV
$6B$'&7
5HV
UZ
UZ
$6B9(&B
0$*
$6B9(&B
;<
$6B29
$6B'638
$6B)86(
$6B95
$6B:'
$6B567
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
Res
15:10
rw
Reserved
Reset: 010111B
AS_ADCT
9
rw
Enable GMR Vector check
Reset: 1B
AS_VEC_MAG
7
rw
Activation of ADC-Redundancy-BIST
0B
after execution
1B
activation of redundancy BIST
Reset: 1B
AS_VEC_XY
6
rw
Activation of ADC-BIST
0B
after execution
1B
activation of BIST
Reset: 1B
AS_OV
5
rw
Enable of DSPU Overflow Check
Reset: 1B
AS_DSPU
4
rw
Activation DSPU BIST
0B
after execution
1B
activation of DSPU BIST
Reset: 1B
AS_FUSE
3
rw
Activation Fuse CRC
0B
after execution
1B
activation of Fuse CRC
Reset: 1B
AS_VR
2
rw
Enable Voltage Regulator Check
Reset: 1B
AS_WD
1
rw
Enable DSPU Watchdog-HW-Reset
Reset: 1B
Target Data Sheet
33
V 0.46, 2009-09
TLE5012
Specification
Field
Bits
Type
Description
AS_RST
0
rw
Activation of Hardware Reset
Activation occurs after CSQ switches from ’0’ to ’1’ after
SSC transfer.
0B
after execution
1B
activation of HW Reset
Reset: 0B
Angle Value Register
AVAL
Offset
Angle Value Register
Reset Value
02H
8000H
5'B$9
$1*B9$/
U
UX
$1*B9$/
UX
Field
Bits
Type
Description
RD_AV
15
r
Read Status, Angle Value
0B
after readout
1B
new angle value (ANG_VAL) present
Reset: 1B
ANG_VAL
14:0
ru
Calculated Angle Value
(ANG_RANGE = 0x080)
4000H -180°
0000H 0°
3FFFH +179.99°
Reset: 0H
Target Data Sheet
34
V 0.46, 2009-09
TLE5012
Specification
Angle Speed Register
ASPD
Offset
Angle Speed Register
Reset Value
03H
8000H
5'B$6
$1*B63'
U
UX
$1*B63'
UX
Field
Bits
Type
Description
RD_AS
15
r
Read Status, Angle Speed
0B
after readout
1B
new angle speed value (ANG_SPD) present
Reset: 1B
ANG_SPD
14:0
ru
Calculated Angle Speed
Without prediction difference between two consecutive
angle values. With prediction, difference between three
consecutive angle values.
Reset: 0H
Angle Revolution Register
AREV
Offset
Angle Revolution Register
Reset Value
04H
8000H
5'B5(9
)&17
5(92/
U
UZX
UX
5(92/
UX
Target Data Sheet
35
V 0.46, 2009-09
TLE5012
Specification
Field
Bits
Type
Description
RD_REV
15
r
Read Status, Revolution
0B
after readout
1B
new value (REVOL) present
Reset: 1B
FCNT
14:9
rwu
Frame Counter (unsigned 6 bit value)
Counts every new angle value
Reset: 0H
REVOL
8:0
ru
Number of Revolutions (signed 9 bit value)
If prediction is enabled, revolution counter is one
schedule delayed related to ANG_VAL.
Reset: 0H
Frame Synchronization Register
FSYNC
Offset
Frame Synchronization Register
Reset Value
05H
0000H
5HV
)6<1&
UZX
5HV
Field
Bits
Type
Description
FSYNC
15:9
rwu
Frame Synchronization Counter Value
Sub counter within one frame.
Reset: 0H
Target Data Sheet
36
V 0.46, 2009-09
TLE5012
Specification
Interface Mode1 Register
MOD_1
Offset
Interface Mode1 Register
Reset Value
06H
8001H
),5B0'
5HV
UZ
5HV
&/.B6(/
66&B2'
'638B+2
/'
,,)B02'
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
FIR_MD
15:14
rw
Filter Decimation Setting
00B 21.3µs
01B 42.7µs
10B 85.3µs
11B 170.6µs
Reset: 10B
CLK_SEL
4
rw
Clock Source Select
0B
internal oscillator
1B
external 4MHz clock
Reset: 0B
SSC_OD
3
rw
SSC-Interface
0B
Push-Pull
1B
Open Drain (default within TLE5012-E0318 and
TLE5012-E0742)
Reset: 0B
DSPU_HOLD
2
rw
Hold DSPU Operation
0B
DSPU in normal schedule operation
1B
DSPU is on hold
Reset: 0B
IIF_MOD
1:0
rw
Incremental Interface Mode
00B IIF disabled
01B A/B operation with Index on DATA
10B not allowed
11B not allowed
Reset: 01B
Target Data Sheet
37
V 0.46, 2009-09
TLE5012
Specification
SIL Register
SIL
Offset
SIL Register
Reset Value
07H
0000H
),/7B3$
5
),/7B,1
9
UZ
UZ
5HV
$'&79B(
1
$'&79B<
$'&79B;
UZ
UZ
UZ
)86(B5(
/
5HV
5HV
UZ
Field
Bits
Type
Description
FILT_PAR
15
rw
Filter Parallel
0B
filter parallel disabled
1B
filter parallel enabled (source: X-value)
Reset: 0B
FILT_INV
14
rw
Filter Inverted
0B
filter inverted disabled
1B
filter inverted enabled
Reset: 0B
FUSE_REL
10
rw
Fuse Reload
0B
fuse reload disabled
1B
fuse parameters reloaded to DSPU at next cycle
start
Reset: 0B
ADCTV_EN
6
rw
ADC-Test vectors
0B
ADC-Test vectors disabled
1B
ADC-Test vectors enabled
Reset: 0B
ADCTV_Y
5:3
rw
Test vector Y
000B 0V
001B +70%
010B +100%
011B +Overflow
101B -70%
110B -100%
111B -Overflow
Reset: 0H
Target Data Sheet
38
V 0.46, 2009-09
TLE5012
Specification
Field
Bits
Type
Description
ADCTV_X
2:0
rw
Test vector X
000B 0V
001B +70%
010B +100%
011B +OV
101B -70%
110B -100%
111B -OV
Reset: 0H
Interface Mode2 Register
MOD_2
Offset
Interface Mode2 Register
Reset Value
08H
0800H
5HV
$1*B5$1*(
UZ
$1*B5$1*(
$1*B',5
35(',&7
$872&$/
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
ANG_RANGE
14:4
rw
Angle Range
Angle Range [°] = 360° * (27 / ANG_RANGE)
200H represents 90°
080H represents 360°
Reset: 080H
ANG_DIR
3
rw
Angle Direction
0B
counterclockwise rotation of magnet
1B
clockwise rotation of magnet
Reset: 0B
PREDICT
2
rw
Prediction
0B
prediction disabled
1B
prediction enabled (default within TLE5012-E0318
and TLE5012-E0742)
Reset: 0B
Target Data Sheet
39
V 0.46, 2009-09
TLE5012
Specification
Field
Bits
Type
Description
AUTOCAL
1:0
rw
Autocalibration Mode
00B no autocalibration
01B autocalibration time mode (1LSB parameter
change every tupd) (default within TLE5012-E0318
and TLE5012-E0742)
10B autocalibration angle mode1 (1LSB parameter
change every 22.5°)
11B autocalibration angle mode2 (1LSB parameter
change every 11.25°)
Reset: 00B
Interface Mode3 Register
MOD_3
Offset
Interface Mode3 Register
Reset Value
09H
0000H
$1*B%$6(
UZ
$1*B%$6(
63,.()
5HV
UZ
UZ
Field
Bits
Type
Description
ANG_BASE
15:4
rw
Angle Base
800H -180°
000H 0°
001H 0.0879°
7FFH +179.912°
Reset: 000H
SPIKEF
3
rw
Analog Spike Filters of Input Pads
0B
spike filter disabled
1B
spike filter enabled
Reset: 0B
Target Data Sheet
40
3$'B'59
UZ
V 0.46, 2009-09
TLE5012
Specification
Field
Bits
Type
Description
PAD_DRV
1:0
rw
Configuration of Pad-Driver
00B IFA/IFB: strong driver, DATA: strong driver, fast
edge
01B IFA/IFB: strong driver, DATA: strong driver, slow
edge
10B IFA/IFB: weak driver, DATA: medium driver, fast
edge (default within TLE5012-E0318 and
TLE5012-E0742)
11B IFA/IFB: weak driver, DATA: weak driver, slow
edge
Reset: 00B
Offset X Register
OFFX
Offset
Offset X
Reset Value
0AH
0000H
;B2))6(7
UZ
5HV
;B2))6(7
UZ
Field
Bits
Type
Description
X_OFFSET
15:4
rw
Offset Correction of X-value
Reset: 0H
Target Data Sheet
41
V 0.46, 2009-09
TLE5012
Specification
Offset Y Register
OFFY
Offset
Offset Y
Reset Value
0BH
0000H
<B2))6(7
UZ
5HV
<B2))6(7
UZ
Field
Bits
Type
Description
Y_OFFSET
15:4
rw
Offset Correction of Y-value
Reset: 0H
Synchronicity Register
SYNCH
Offset
Synchronicity
Reset Value
0CH
0000H
6<1&+
UZ
5HV
6<1&+
UZ
Field
Bits
Type
Description
SYNCH
15:4
rw
Amplitude Synchronicity
+2047D 112.494%
0D
100%
-2048D 87.500%
Reset: 0H
Target Data Sheet
42
V 0.46, 2009-09
TLE5012
Specification
IFAB Register
IFAB
Offset
IFAB Register
Reset Value
0DH
0003H
257+2
UZ
257+2
5HV
,)$%B2'
,)$%B+<67
UZ
UZ
UZ
Field
Bits
Type
Description
ORTHO
15:4
rw
Orthogonality Correction of X and Y Components
+2047D 11.2445°
0D
0°
-2048D -11.2500°
Reset: 0H
IFAB_OD
2
rw
IFA & IFB Open Drain
0B
Push-Pull
1B
Open Drain (default within TLE5012-E0318 and
TLE5012-E0742)
Reset: 0B
IFAB_HYST
1:0
rw
HSM Hysteresis
00B 0°
01B 0.09°
10B 0.27°
11B 0.625°
Reset: 11B
Target Data Sheet
43
V 0.46, 2009-09
TLE5012
Specification
Interface Mode4 Register
MOD_4
Offset
Interface Mode4 Register
Reset Value
0EH
0000H
7&2B;B7
5HV
UZ
+60B3/3
,)$%B5(6
,)B0'
UZ
UZ
UZ
Field
Bits
Type
Description
TCO_X_T
15:9
rw
Offset Temperature Coefficient for X-Component
Reset: 0H
HSM_PLP
7:5
rw
Hall Switch Mode; Polepair Configuration
000B 2 pole pairs
001B 3 pole pairs (default within TLE5012-E0318)
010B 4 pole pairs
011B 6 pole pairs
100B 7 pole pairs (default within TLE5012-E0742)
101B 8 pole pairs
110B 12 pole pairs
111B 16 pole pairs
Reset: 000B
IFAB_RES
4:3
rw
IFAB Resolution
00B 12bit = 0.088° (244Hz)
01B 11bit = 0.176° (488Hz)
10B 10bit = 0.352° (977Hz)
11B 9bit = 0.703° (1953Hz)
Reset: 00B
IF_MD
2:0
rw
Interface Mode
PWM, HSM if CLK is connected to GND at startup.
Note: Not mentioned combinations are not allowed
000B SSC mode; IIF
001B SSC mode; PWM
010B SSC mode; HSM (default within TLE5012-E0318
and TLE5012-E0742)
Reset: 000B
Target Data Sheet
44
V 0.46, 2009-09
TLE5012
Specification
Temperature Coeffizient Register
TCO_Y
Offset
Temperature Coeffizient Register
Reset Value
0FH
0000H
5HV
7&2B<B7
&5&B3$5
UZ
UZ
Field
Bits
Type
Description
TCO_Y_T
15:9
rw
Offset Temperature Coefficient for Y-Component
Reset: 0H
CRC_PAR
7:0
rw
CRC of Parameters
CRC of parameters from address 08H to 0FH
Reset: 0H
X-raw Value Register
ADC_X
Offset
X-raw value
Reset Value
10H
0000H
$'&B;
U
Field
Bits
Type
Description
ADC_X
15:0
r
ADC value of X-GMR
Read out of this register will update ADC_Y
Reset: 0H
Target Data Sheet
45
V 0.46, 2009-09
TLE5012
Specification
Y-raw Value Register
ADC_Y
Offset
Y-raw value
Reset Value
11H
0000H
$'&B<
U
Field
Bits
Type
Description
ADC_Y
15:0
r
ADC value of Y-GMR
Updated when ADC_X or ADC_Y is read.
Reset: 0H
3.5.2
Pulse Width Modulation Interface
The Pulse Width Modulation (PWM) Interface can be selected by connecting CLK to VDD.
The PWM update rate can be programmed within the register 0EH (IFAB_RES) in following steps:
•
•
•
•
0.25 kHz with 12 bit resolution
0.5 kHz with 11 bit resolution
1.0 kHz with 10 bit resolution (default)
2.0 kHz with 9 bit resolution
PWM uses a square wave with constant frequency whose duty cycle is modulated resulting in an average value
of the waveform.
Figure 21 shows the principle behavior of a PWM with different duty cycles and the definition of timing values. The
duty cycle of a PWM is defined by following general formulas:
Duty Cycle =
ton
t PWM
t PWM = t on + toff
f PWM =
1
t PWM
(3)
The range between 0 - 6.25% and 93.75 - 100% is used only for diagnostic purposes. More details are given in
Table 16.
Target Data Sheet
46
V 0.46, 2009-09
TLE5012
Specification
ON = High level
UIFA
tON
OFF = Low level
Duty cycle = 5%
Vdd
tPWM
t OFF
‚0'
UIFA
Vdd
UIFA
‚0'
Vdd
Duty cycle = 50%
t
Duty cycle = 95%
t
‚0'
t
Figure 21
Typical Example for a PWM Signal
Table 16
PWM Interface
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note / Test Condition
PWM Output Frequency
fPWM
244
-
1953
Hz
selectable by IFAB_RES1)
Output Duty Cycle Range
DYPWM
6.25
-
93.75
%
Absolute Angle
-
2
-
%
Electrical Error (S_RST;
S_VR)
-
98
-
%
System Error (S_FUSE;
S_OV; S_XYOL;
S_MAGOL; S_ADCT)
0
-
1
%
Short to GND
99
-
100
%
Short to VDD, Power-Loss
-5
-
5
%
2)
PWM Period Variation
tPWMvar
IFAB_RES
1) fPWM = (fDIG * 2
) / (24 * 4096)
2) depends on internal oscillator frequency variation (Chapter 3.4.6)
Target Data Sheet
47
V 0.46, 2009-09
TLE5012
Specification
3.5.3
Hall Switch Mode
The Hall Switch Mode (HSM) within the TLE5012 allows to emulate the output of three Hall switches. Hall switches
are often used in electrical commutated motors to get information of the rotor position. With these three output
signals the motor will be commutated in the right way. Depending on the used pole pairs of the rotor, different
amount of electrical periods have to be realized. This is selectable within 0EH (HSM_PLP). Within the TLE5012E0318 three polepairs and within the TLE5012-E0742 seven polepairs are fused. Figure 22 depicts the three
output signals with the relationship between electrical angle and mechanical angle. The mechanical 0° point is
always used as reference.
Hall-Switch-Mode: 3phase Generation
Electrical Angle
0°
60°
120°
180°
240°
300°
360°
HS1
HS2
HS3
Angle
Mech. Angle with
8 Pole Pairs
0°
7.5°
15°
22.5°
30°
37.5°
45°
Mech. Angle with
3 Pole Pairs
0°
20°
40°
60°
80°
100°
120°
Figure 22
Hall Switch Mode
The HSM Interface can be selected by connecting CLK to GND and CSQ has to be logic “1”.
Table 17
Hall Switch Mode
Parameter
Rotation Speed
Target Data Sheet
Symbol
n
Values
Min.
Typ.
Max.
-
-
10000
48
Unit
Note / Test Condition
rpm
V 0.46, 2009-09
TLE5012
Specification
Table 17
Hall Switch Mode
Parameter
Electrical Angle Accuracy
Symbol
αelect
Values
Unit
Note / Test Condition
°
2 polepairs with
autocalibration1)2)
Min.
Typ.
Max.
-
1.2
2
-
1.8
3
3 polepairs with autocal.1)2)
-
2.4
4
4 polepairs with autocal.1)2)
-
3.6
6
6 polepairs with autocal.1)2)
-
4.2
7
7 polepairs with autocal.1)2)
-
4.8
8
8 polepairs with autocal.1)2)
-
7.2
12
12 polepairs with autocal.1)2)
-
9.6
16
16 polepairs with autocal.1)2)
Mechanical Angle Switching
Hysteresis
αHShystm
0
-
0.625
°
selectable by IFAB_HYST3)
Electrical Angle Switching
Hysteresis4)
αHShystel
-
1.25
-
°
2 polepairs;
IFAB_HYST=111)2)
-
1.88
-
3 polepairs;
IFAB_HYST=111)2)
-
2.50
-
4 polepairs;
IFAB_HYST=111)2)
-
3.75
-
6 polepairs;
IFAB_HYST=111)2)
-
4.38
-
7 polepairs;
IFAB_HYST=111)2)
-
5.00
-
8 polepairs;
IFAB_HYST=111)2)
-
7.50
-
12 polepairs;
IFAB_HYST=111)2)
-
10
-
16 polepairs;
IFAB_HYST=111)2)
Fall Time
tHSfall
-
0.02
1
µs
RL = 2.2kΩ; CL < 50pF
Rise Time
tHSrise
-
0.4
1
µs
RL = 2.2kΩ; CL < 50pF
1)
2)
3)
4)
depends on internal oscillator frequency variation (Chapter 3.4.6)
guaranteed by design
including GMR hysteresis
The hysteresis has to be considered only at change of rotation direction.
To avoid switching on mechanical vibrations of the rotor, a hysteresis is recommended (Figure 23).
Target Data Sheet
49
V 0.46, 2009-09
TLE5012
Specification
Ideal Switching Point
α HShystel αHShystel
αelect
Figure 23
HS Hysteresis
3.5.4
Incremental Interface
0°
αelect
The Incremental Interface (IIF) uses an up/down counter of a microcontroller for the angle transmission. The
synchronization is done by the parallel active SSC-Interface. The angle value read out by the SSC-Interface can
be compared with the stored counter value. In case of a non-synchronization, the microcontroller add the
difference to the actual counter value to synchronize the TLE5012 with the microcontroller. The resolution of the
IIF can be selected within the interface mode4 register (MOD_4) under IFAB_RES.
A/B Mode
The phase shift between phase A and B indicates a clockwise (B follows A) or a counterclockwise (A follows B)
rotation of the magnet.
Target Data Sheet
50
V 0.46, 2009-09
TLE5012
Specification
VDD
µC
CSQ
N
SSC
iGMRSensor
S
SSC
SCK
DATA
INC
IFA
A
IFB
B
12bit
Up/Down
Counter
GND
CSQ
SPI
Interface
SCK
DATA
D0
D1
D2
D11
D3
D13
D14
3
2
D15
90° el. Phase shift
Phase A VH
VL
Incremental
Interface
Phase B VH
VL
Counter
Figure 24
0
1
2
3
4
1
Incremental Interface Protocol with symbolically illustration of SPI-Interface
Index Signal
The Index-Signal is generated via Data pin, while CSQ is high (no SSC-communication). The Index-Signal is
coded in quadrants via a PWM-sequence, Figure 25.
Angle
0°
90°
180°
270°
0°
INDEX
t0°
t 90°
Figure 25
IIF Index Coding
Table 18
Incremental Interface
Parameter
Incremental output Frequency
Target Data Sheet
t180°
Symbol
fInc
Values
Min.
Typ.
Max.
-
-
1.0
51
t270°
Unit
Note / Test Condition
MHz
Frequency of Phase A and
Phase B
V 0.46, 2009-09
TLE5012
Specification
Table 18
Incremental Interface (cont’d)
Parameter
Symbol
Index
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
t0°
-
5
-
µs
0°
t90°
-
10
-
µs
90°
t180°
-
15
-
µs
180°
t270°
-
20
-
µs
270°
3.6
Test Structure
3.6.1
ADC Test Vectors
It is possible to feed the ADCs with appropriate values to simulate a certain magnet position and other GMR
effects. This test can be activated within SIL register (ADCTV_EN). With ADCTV_Y and ADCTV_X the vector
length can be adjusted like Figure 26.
The values are generated with resistors on the chip.
The following X/Y ADC values can be programmed:
•
•
•
•
4 points, circle amplitude = 70% (0°,90°, 180°, 270°)
8 points, circle amplitude = 100% (0°, 45°, 90°, 135°, 180°, 225°, 270°, 315°)
8 points, circle amplitude = 122.1% (35.3°, 54.7°, 125.3°, 144.7°, 215.3°, 234.7°, 305.3°, 324.7°)
4 points, circle amplitude = 141.4% (45°, 135°, 225°, 315°)
ADCTV_Y
122.1%
141.4%
100 .0%
0%
70%
Figure 26
ADCTV_X
ADC Test Vectors
Target Data Sheet
52
V 0.46, 2009-09
TLE5012
Specification
3.7
Overvoltage Comparators
Various comparators monitor the voltage in order to ensure error free operation. The overvoltages must be active
at least 256 periods of tDIG to set the test comparator bits in the SSC Interface registers. This works as digital spike
suppression.
Table 19
Test Comparators
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
VOVG
-
2.80
-
V
VOVA
-
2.80
-
V
VOVD
-
2.80
-
V
VDD Overvoltage
VDDOV
-
6.05
-
V
VDD Undervoltage
VDDUV
-
2.70
-
V
GND - Off Voltage
VGNDoff
-
-0.55
-
V
VDD - Off Voltage
VVDDoff
-
0.55
-
V
Spike Filter Delay
tDEL
-
10
-
µs
Overvoltage Detection
3.7.1
Note / Test Condition
Internal Supply Voltage Comparators
Every voltage regulator has an overvoltage comparator to detect a malfunction. If the nominal output voltage of
2.5 V is larger than VOVG, VOVA and VOVD, then this overvoltage comparator is activated.
VDDA
-
REF
VDD
VRG
VRA
VRD
10µs
Spike
Filter
+
GND
Figure 27
OV Comparator
3.7.2
VDD Overvoltage Detection
xxx_OV
GND
The Overvoltage Detection Comparator monitors the external supply voltage at the VDD pin. It activates the S_VR
bit.(Figure 27)
3.7.3
GND - Off Comparator
The GND - Off Comparator is used to detect a voltage difference between the GND pin and SCK. It activates the
S_VR bit of the SSC - Interface. This circuit can detect a disconnection of the Supply GND Pin.
Target Data Sheet
53
V 0.46, 2009-09
TLE5012
Specification
VDD
VDDA
Diodereference
SCK
+dV
-
1µs
Mono
Flop
+
GND
10µs
Spike
Filter
GND_OFF
GND
Figure 28
GND - Off Comparator
3.7.4
VDD - Off Comparator
The VDD - Off Comparator detects a disconnection of the VDD pin supply voltage. In this case, the TLE5012 is
supplied by the SCK and CSQ input pins via the ESD structures. It activates the S_VR bit.
VDDA
-
VDD
1µs
Mono
Flop
VVDDoff
CSQ
SCK
-dV
GND
Figure 29
+
10µs
Spike
Filter
VDD _OFF
GND
VDD - Off Comparator
Target Data Sheet
54
V 0.46, 2009-09
TLE5012
Package Information
4
Package Information
4.1
Package Parameters
Table 20
Package Parameters
Parameter
Symbol Limit Values
Unit
Notes
min. typ. max.
Thermal Resistance
RthJA
-
150 200
K/W
Junction to Air1)
RthJC
-
-
75
K/W
Junction to Case
RthJL
-
-
85
K/W
Junction to Lead
Soldering Moisture Level
MSL 3
Lead Frame
260°C
Cu
Plating
Sn 100%
> 7 µm
1) according to Jedec JESD51-7
Package Outline
0.35 x 45˚
+0.06
B
2)
0.41 +0.1
-0.06
0.2
M
A
C 1.22 ±0.18
0.19
1.27
4 -0.2 1)
8˚MAX.
1.75 MAX.
0.175 ±0.07
(1.45)
4.2
0.64 ±0.25
0.1
A B 8x SEATING
PLANE
E
6 ±0.2
0.2
M
C 8x
4)
D
4
0.32 MIN.
1
A
ø0.6 Sensitive Area 3)
5
8
Index
Marking
Detail A
3 x 1.27 = 3.81
0.75 D E
CENTER OF
SENSITIVE
AREA
5 -0.2 1)
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Lead width can be 0.61 max. in dambar area
3) Max. 3˚ tilt of sensitive area to preference "B"
4) Reference "D" is defined with the center of all 8 pins
P-PG-DSO-08-16-S-PO V03
Figure 30
PG-DSO-8 Package Dimension
Target Data Sheet
55
V 0.46, 2009-09
TLE5012
Package Information
Footprint
1.31
4.3
5.69
0.65
1.27
Figure 31
Footprint PG-DSO-8
4.4
Packing
0.3
5.2
12 ±0.3
8
1.75
6.4
2.1
Figure 32
Tape and Reel
4.5
Marking
Position
Marking
Description
1st Line
5012xx
See ordering table on page 7
2nd Line
xxx
Lot code
3rd Line
Gxxxx
G..green, 4-digit..date code
Processing
Note: For processing recommendations, please refer to Infineon’s Notes on processing
Target Data Sheet
56
V 0.46, 2009-09
www.infineon.com
Published by Infineon Technologies AG