RENESAS M62464BFP

M62464BFP
Dolby Pro Logic Surround Decoder with Discrete 5.1ch Analog
Input
REJ03F0218-0201
Rev.2.01
Mar 31, 2008
Description
The M62464BFP is a Single Chip Dolby Pro Logic Surround Decoder with Discrete 5.1ch Analog Input. This LSI has
all of required functions for Dolby Pro Logic Surround and also 5.1ch analog input. for Dolby Digital.
Note: Dolby and the double-D symbol are trademarks of Dolby Laboratories Licensing Corporation. San Francisco,
CA94103-4813, USA.
This device available only to licensees of Dolby Lab.
Licensing and application information may be obtained from Dolby Lab.
Features
•
•
•
•
•
•
•
•
Includes all functions necessary for Dolby Pro Logic Surround
Includes 5.1ch (L, R, C, SL, SR, SW) analog input for Dolby Digital
4ch (C, SL, SR, SW) Master Volume
Digital Space Surround such as Disco, Hall and Live
Pseudo Stereo Surround for Digital Space Surround
Digital Echo for Karaoke Function Delay time 123,184 ms
3-lines MCU control
Current control oscillation circuit for system clock
System Block Diagram
M62464FP
Volume
L
LTIN
decoder
R
C
RTIN
Digital space surround
MICIN
LOUT
Pro logic
Digital echo
SL
SR
ROUT
Trimmer Volume
COUT
LIN
SLOUT
RIN
CIN
SROUT
SLIN
SRIN
SWIN
SWOUT
VRSWIN
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REJ03F0218-0201 Rev.2.01 Mar 31, 2008
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L+R
2
3
4
1
DI-SW
Input
auto-balance
2
L−R
Adaptive
matrix
F.B.VOL
Logic
10 Kbit SRAM
Digital delay
S'
Noise
sequencer
Selector
MICIN 20
VRSWIN 80
SWIN 79
SRIN 78
SLIN 77
CIN 76
RTIN 75
LTIN 74
RIN 73
LIN 72
DO-SW
LPF
D/A
A/D
LPF
ECHOOUT
41
2
1
Mute
+/−
23
24
DATA SCK REQ
22
MCU
interface
SWVOL
SWtrim
SRtrim
SLtrim
SW-SW
2
1
2
3
1
SR-SW
2
3
1
SL-SW
2
1
5
1
5
1
R-SW
2
3
4
4
2
3
L-SW
Ctrim
5.1ch
Bypass
Space
Mute
+
C-SW
S
BNR-SW
2
3
1
Pseudo SL
stereo SR
Pro logic
Modified
BNR
Wide
normal
phantom
off
Center
mode
control
DELAYVOL
C
R
L
Pro logic
5.1ch
Bypass
Space
9
3
17
14
SWBP-SW
2
1
SRVOL
SLVOL
CVOL
2
1
SWVOL
OUT
SRVOL
OUT
SLVOL
OUT
CVOL
OUT
ROUT
LOUT
M62464BFP
Block Diagram
M62464BFP
Pin Arrangement
24
23
22
21
20
19
18
17
16
DVss
25
80
VRSWIN
15
DSELOUT
26
79
SRIN
14
DIN
27
SWIN
13
LPF1IN1
28
SLIN
78
77
CIN
SRVOLIN
12
LPF1IN2
29
76
RTIN
SRVOLOUT
SROUT
11
LPF1OUT
30
75
SWOUT
SLOUT
10
ADINTIN
31
74
LTIN
SWVOLIN
SLVOLIN
9
ADINTOUT
32
73
RIN
SWVOLOUT
SLVOLOUT
8
ADCONT
33
LIN
CMC
PSRIN
7
DACONT
34
72
AGND
PSLIN
6
DAINTIN
35
71
MICIN
SOUT
5
DAINTOUT
36
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DVDD
COUT
4
LPF2IN1
37
Outline: PRQP0080GB-A (80P6N-A)
DATA
CVOLIN
3
LPF2IN2
38
(Top view)
SCK
CVOLOUT
2
LPF2OUT
IREF
ABL
70
RBPF1
VREF1
RBPF2
AVcc
LBPF1
69
RLC6
LBPF2
68
57
RLC8
NGC1
56
RLC3
67
55
RLC7
NGC2
54
RLC4
NGC3
53
RLC1
66
52
RLC2
65
51
RLC5
ABR
50
PSC4
REQ
ROUT
1
DVOLOUT
39
41
44
45
46
47
48
49
PSC1
59
PSC5
60
PSC2
61
PSC6
62
PSC3
63
DBC3
64
DBC2
58
DBC1
42
BNR IN
43
ECHOOUT
40
M62464BFP
LOUT
M62464BFP
Functional Description
Function
1
Description
•
•
•
•
Fundamental function for Dolby Pro Logic
surround decoder
Adaptive Matrix
Input Auto–Balance
Noise Sequencer
Center Mode Control
ON/OFF
WIDE/NORMAL/PHANTOM
• Modified Dolby B type Noise Reduction
• 4ch (L, R, C, S), 3ch (L, R, C) Mode Switch
2
3
4
5
6
5.1ch Analog Input for Dolby Digital
C, SL, SR, SW ch master volume
C, SL, SR, SW ch Trimmer
RAM for digital delay
Circuit for space surround and echo
7
8
Pseudo stereo surround
Digital delay time
9
10
11
12
13
Feedback volume
Delay effect volume
Bypass switch
Output mute
MCU interface
14
Current control oscillation circuit
L, R, C, SL, SR, SW ch Analog Input Support
0 to −79 dB/1 dB step, and − ∞
0 to −31 dB/1 dB step
10 K-bit RAM
Digital delay circuit can be used for Space Surround such as a
Disco, Hall or Live, and Karaoke echo.
Pseudo Stereo Surround is available in Space Surround.
Short Delay 15.4, 20.5, 25.6, 29.2, 51.2 ms
Long Delay 123, 184 ms
Delay Signal Feedback Volume −3 to −21 dB/3 dB step, and − ∞
Delay Signal Effect Volume 0 to −18 dB/3 dB step, and − ∞
Bypass the decode circuit
Mute the Lch and Rch output
Controlled by 3-lines serial data from MCU Including the Chip
Address (2 bit)
Including the oscillation circuit without external parts.
Absolute Maximum Ratings
(Ta = 25°C, unless otherwise noted)
Item
Supply voltage
Power dissipation
Operating temperature
Storage temperature
Symbol
VCC
VDD
Pd
Topr
Tstg
Ratings
10.5
6.5
1.4
−20 to +75
−40 to +125
Unit
V
V
W
°C
°C
Condition
Recommended Operating Condition
Min
Limits
Typ
Max
Unit
Input voltage (L)
VCC
VDD
VIL
8
4.5
0
9
5
—
10
5.5
0.8
V
V
V
22, 23, 24 pin
Input voltage (H)
VIH
2.2
—
VDD
V
22, 23, 24 pin
Item
Supply voltage
Symbol
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Condition
M62464BFP
Electrical Characteristics
(Ta = 25°C, VCC = 9V, VDD = 5 V, 0dBd = 300 mVrms, at COUT, f = 1 kHz Unless otherwise noted)
Item
Total
Circuit current
Circuit current
Auto-balance
Capture range
Error collection
Adaptive Matrix
Output level accuracy
relative to Cch
Matrix rejection
Head room
Total harmonic
distortion
S/N ratio
Noise Sequencer
Output noise level
Symbol
Min
Limits
Typ
Max
Unit
ICC
IDD
—
—
30
15
45
25
mA
mA
CPR
CER
—
—
5
4
—
—
dB
dB
∆VoL
−0.5
0
0.5
dB
L, R, S’ch output
MR
HRAM
25
15
40
17
—
—
dB
dB
L, R, C, S’ch output
THD = 1%, L, R, C ch output
THDAM
—
0.05
0.2
%
L, R, C ch output 30kHz LPF
SNAM
70
80
—
dB
Rg = 0Ω, weighted CCIR/ARM
Vno
−15
−12.5
−10
dB
∆Vno
−0.5
0
0.5
dB
Noise level accuracy
relative to Cch
Modified B–type Noise Reduction (0dB reference is 300mVrms/100Hz at SOUT)
Gain between input and
output
Decode character1
Decode character2
Decode character3
No signal
No signal
L, R, C, S’ch output
L, R, S’ch output
VGNR
3.8
6.8
9.8
dB
Vin = 0dBd, f = 100Hz
DEC1
DEC2
DEC3
−1.6
−3.0
−6.8
−0.1
−1.5
−5.3
1.4
0
−3.8
dB
Vin = 0dBd, f = 1.0kHz
Vin = −15dBd, f = 1.4kHz
Vin = −40dBd, f = 5.0kHz
—
0.07
0.3
%
15
68
17
78
—
—
dB
dB
Vin = 0dBd, f = 1kHz,
30kHz LPP
THD = 1%
Rg = 0Ω, weighted CCIR/ARM
—
−3.0
0.5
0.2
85
−95
0
1.0
1.0
95
−87
3.0
1.5
1.8
—
dB
dB
dB
dB
dB
ATT = −∞, Vi = 2Vrms
ATT = 0dB, TRIM = 0dB
ATT = 0 to −40dB, TRIM = 0dB
ATT = −40 to −76dB, TRIM = 0dB
ATT = −∞, CCIR/ARM
−34
−3.0
0.6
−31
0
1.0
−28
3.0
1.4
dB
dB
dB
TRIM = −31dB, VOLATT = 0dB
TRIM = 0dB, VOLATT = 0dB
VOLATT = 0dB
THDLN
—
0.002
0.05
%
30kHz LPF
SNLN
CTLN
Zi
95
70
11
100
80
22
—
—
44
dB
dB
kΩ
DIN-AUDIO
THDNR
Total harmonic
distortion
Head room
HRNR
S/N ratio
SNNR
Cch/SLch/SRch/SWch Master Volume
Maximum attenuation
ATTmax
Minimum attenuation
ATTmin
Volume step1
VOLS1
Volume step2
VOLS2
S/N ratio
SNVOL
Cch/SLch/SRch/SWch Trimmer
Maximum attenuation
TRIMmax
Minimum attenuation
TRIMmin
Trimmer step
TRIMS
Line (Bypass)
Total harmonic
distortion
S/N ratio
Line cross–talk
Input impedance
Conditions
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Page 5 of 23
M62464BFP
(Ta = 25°C, VCC = 9 V, VDD = 5 V, 0dBd = 300 mVrms, at COUT, f = 1 kHz Unless otherwise noted)
Item
Symbol
Min
Limits
Typ
Max
Unit
Conditions
Digital delay
GvD
−3.0
0
+3.0
dB
DIN-DVOLOUT, DVOL = 0dB
Td
17.4
—
—
20.5
0.5
1.2
23.6
0.9
2.2
ms
Td = 20.5ms
%
30kHzLPF
—
—
—
—
3.0
−92
−84
−80
5.6
−80
−70
−65
Vomax
0.7
1.0
—
Vrms
LPFfc
6.0
—
7.0
3.0
8.0
—
kHz
kHz
Td = 15.4 to 51.2ms Gv = −3dB
Td = 123 to 184ms Gv = −3dB
Feedback volume
Maximum attenuation
Minimum attenuation
Volume step
FBATTmax
FBATTmin
FBVOLS
—
−6.0
1.5
−70
−3.0
3.0
−60
0
4.5
dB
dB
dB
ATT = −∞
ATT = −3dB
Delay volume
Maximum attenuation
Minimum attenuation
Volume step
DLATTmax
DLATTmin
DLVOLS
—
−3.0
1.5
−70
0
3.0
−60
3.0
4.5
dB
dB
dB
ATT = −∞
ATT = 0dB
Input/output voltage
gain
Delay time
Total harmonic
distortion
THDD
Output noise voltage
NoD
Maximum output
voltage
LPF cut-off frequency
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dBV
Vin = 0Vrms
JIS-A
Td = 20.5ms
Td = 51.2ms
Td = 184ms
Td = 20.5ms
Td = 51.2ms
Td = 184ms
THD = 10%
M62464BFP
Serial Data Control Format
(1) Data Input Format
DATA is read at the rising edge of SCK, and loaded last 16 bits at the rising edge of REQ.
D0
DATA
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 D11 D12 D13 D14 D15
SCK
REQ
D0
D1
D2
D3
D4
L
L
L
—
Mode Set
Pro
Logic
Mode
H
H
L
L
—
L
H
"L"
Delay Time
Delay Volume
Space Surround Mode
Cch Volume
SLch Volume
H
H
L
H
Feedback
Volume
—
—
L
H
L
H
H
D5
D6
SWVOL
Set
L
—
Cch Trimmer
H
—
SLch Trimmer
Test Mode (user inhibit)
D7
D8
Center
Mode
D9
D10
AutoBalance
D11
D12
D13
Noise Sequencer
D14
D15
L
H
Chip
Address
Chip
Address
SRch Volume
SWch Volume
SWch Trimmer
SRch Trimmer
(2) Control condition
1
2
3
4
5
Control Mode
Mode set
Pro logic mode
Center mode
Delay time
Noise sequencer
6
7
Auto-balance
Space surround mode
8
9
10
11
12
13
Delay volume
Feedback volume
Master volume
Trimmer
SW volume set
Chip address
Contents
5.1ch Input / Normal Stereo / Dolby Pro Logic / Space Surround / Echo / Mute
4ch Pro Logic / 3ch stereo
Wide / Normal / Phantom / OFF
15.4, 20.5, 25.6, 29.2, 51.2 ms (Short delay) 123, 184 ms (Long delay)
ON / OFF
Lch / Rch / Cch / Sch
Input Auto-Balance ON / OFF
L/R Output: Dolby Pro Logic / Space Surround
Delay input: S’/L−R/ (L+R) /2/MICIN
Delay output mixing, BNR: ON/OFF
Surround signal: Monaural/Pseudo Stereo
0 to −18 dB/3 dB step & −∞
−3 to −21 dB/3 dB step & −∞
C, SL, SR, SWch Master Volume 0 to −79 dB/1 dB step & −∞
C, SL. SR, SWch Trimmer 0 to −31 dB/1 dB step
SW Volume: Volume/Bypass
Input date effect or not
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M62464BFP
(3) Set Condition
a. Mode Set
(D0 = “L”, D1 = “L”, D2 = “L”)
D4
L
L
L
L
H
H
D5
L
L
H
H
L
L
D6
L
H
L
H
L
H
Condition
5.1ch Signal input
Normal stereo (bypass)
Dolby Pro Logic Surround
Space surround
Echo
Output mute
b. Pro Logic Mode
(D0 = “L”, D1 = “L” , D2 = “L”)
D7
L
H
Condition
4ch Pro Logic
3ch Stereo
c. Center Mode
(D0 = “L”, D1 = “L”, D2 = “L”)
D8
L
D9
L
Condition
Wide
L
H
H
H
L
H
Normal
Phantom
OFF
d. Delay Time
(D0 = “L”, D1 = “L”, D2 = “H”)
D5
L
L
L
L
H
H
H
D6
L
L
H
H
L
L
H
D7
L
H
L
H
L
H
L
Delay Time
15.4 ms
20.5 ms
25.6 ms
29.2 ms
51.2 ms
123 ms
184 ms
Sampling Frequency
500 kHz
500 kHz
400 kHz
333 kHz
200 kHz
83.3 kHz
55.6 kHz
LPF Cut-off Frequency
7 kHz
3 kHz
e. Noise Sequencer
(D0 = “L”, D1 = “L”, D2 = “L”)
D11
L
H
D12
—
L
L
H
H
D13
—
L
H
L
H
Condition
Noise Sequencer OFF
Noise Sequencer ON
—
Lch
Rch
Cch
Sch
f. Auto-Balance
(D0 = “L”, D1 = “L”, D2 = “L”)
D10
L
Condition
Auto-Balance OFF
H
Auto-Balance ON
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Page 8 of 23
M62464BFP
g. Space Surround Mode
(D0 = “L”, D1 = “L”, D2 = “H”)
L/R Output
D8
L
H
Condition
Dolby Pro Logic
Space Surround
Delay Mixing Polarity
D9
L
H
Mixing Polarity
L+Delay signal / R+Delay signal
L+Delay signal / R−Delay signal
Delay Input
D10
L
H
H
Note:
D11
X
L
H
Delay Input
S’
L−R
(L+R) /2
L or H
BNR
D12
L
H
BNR
OFF
ON
D13
L
H
Surround Signal
Monaural
Pseudo Stereo
Surround Signal
h. Delay Volume
(D0 = “L”, D1 = “H”, D2 = “L”, D3 = “L”)
D4
L
L
L
L
H
H
H
H
D5
L
L
H
H
L
L
H
H
D6
L
H
L
H
L
H
L
H
Volume
0 dB
−3 dB
−6 dB
−9 dB
−12 dB
−15 dB
−18 dB
−∞
i. Feedback Volume
(D0 = “L”, D1 = “H”, D2 = “L”, D3 = “H”)
D4
L
L
L
L
H
H
H
H
D5
L
L
H
H
L
L
H
H
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D6
L
H
L
H
L
H
L
H
Volume
−3 dB
−6 dB
−9 dB
−12 dB
−15 dB
−18 dB
−21 dB
−∞
M62464BFP
j. C, SL, SR, SW ch Volume
(D0 = “L”, D1 = “H”)
Volume Level
0 dB
−2 dB
−4 dB
−6 dB
−8 dB
−10 dB
−12 dB
−14 dB
−16 dB
−18 dB
−20 dB
−22 dB
−24 dB
−26 dB
−28 dB
−30 dB
−32 dB
−34 dB
−36 dB
−38 dB
−40 dB
−42 dB
−44 dB
−48 dB
−52 dB
−56 dB
−60 dB
−64 dB
−68 dB
−72 dB
−76 dB
−∞
D11
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
D10
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
D9
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
D8
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
D7
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Volume Level
D13
D12
0 dB
−1 dB
−2 dB
−3 dB
L
L
H
H
L
H
L
H
SW Volume Setting
D6 (D0 = “L”, D1 = “H”, D2 = “H”, D3 = “H”)
L
H
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Page 10 of 23
Condition
SW Volume Bypass
SW Volume Controlled
SWBP-SW
2
1
M62464BFP
k. C, SL, SR, SW ch Trimmer
(D0 = “H”, D1 = “L”)
Trimmer Level
D8
D13
D7
D12
D6
D11
D5
D10
D4
D9
0 dB
−1 dB
−2 dB
−3 dB
−4 dB
−5 dB
−6 dB
−7 dB
−8 dB
−9 dB
−10 dB
−11 dB
−12 dB
−13 dB
−14 dB
−15 dB
−16 dB
−17 dB
−18 dB
−19 dB
−20 dB
−21 dB
−22 dB
−23 dB
−24 dB
−25 dB
−26 dB
−27 dB
−28 dB
−29 dB
−30 dB
−31 dB
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Note:
When (Trimmer level) + (Master Volume) is less than −87 dB, total attenuation level is set to −87 dB.
l. Chip Address
D14
L
D15
H
Others
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Page 11 of 23
Date Read
Enable
Unable
M62464BFP
Relation between Mode Setting and Switch Condition
Space Surround Mode
(D0 = L, D1 = L, D2 = H)
Pro
Logic
Mode
(D0 = L,
D1 = L,
D2 = L)
D7
D8
D10
D11
D12
D13
L–
SW
RSW
CSW
SLSW
SRSW
SWSW
DISW
DOSW
BNR
-SW
5.1ch
Signal
Input
X
X
X
X
X
X
1
1
1
1
1
1
4
2
3
Normal
stereo
L(Note 3)
X
2
2
2
2
2
2
1
1
2
3
3
2
2
2
2
3
1
1
2
1
1
Mode
Setting
Dolby
Pro
Logic
Surround
Space
Surround
Echo
Mute
H
L
H
X
X
X
X
Switch Condition
L
X
L
L
(Note
(Note
(Note
(Note
2)
2)
3)
1)
H
L
H
X
H
X
X
H
X
X
4
4
2
2
1
3
1
3
L
L
X
L
L
4
4
2
2
(Note
(Note
(Note
(Note
(Note
(Note
(Note
(Note
(Note
(Note
(Note
4)
2)
2)
3)
1)
4)
4)
1)
1)
2)
3)
H
H
L
H
H
3
3
3
3
2
1
X
X
H
X
X
1
1
3
4
4
X
X
X
X
X
X
2
5
2
5
1
1
1
1
2
2
2
2
Notes: X: L or H
At Bypass or Space Surround Mode, the condition of SL-SW, SR-SW, DI-SW and BNR-SW depend on D7, D10,
D11, D12 and D13 settings.
1. SL-SW, SR-SW: depend on D13
2. DI-SW: depend on D10 and D11
3. BNR-SW: depend on D7 and D12
4. At Space Surround Mode, the condition of L-SW and R-SW depend on D8
REJ03F0218-0201 Rev.2.01 Mar 31, 2008
Page 12 of 23
2
3
3
M62464BFP
(4) Data Timing
t1, t2
VDD = 5 V
2.2 V
DATA
0.8 V
t6
t7
t1
t4
t2
2.2 V
SCK
0.8 V
t10
t5
t9
t3
t8
2.2 V
REQ
0.8 V
t1
Name
Signal rise time
Signal fall time
SCK clock width
SCK “H” pulse width
SCK “L” pulse width
DATA setup time
DATA hold time
REQ rise hold time
REQ “H” pulse width
SCK setup time
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
REJ03F0218-0201 Rev.2.01 Mar 31, 2008
Page 13 of 23
t2
Min
Typ
Max
Units
—
—
2
0.8
0.8
0.8
0.8
1.6
0.8
1.6
—
—
—
—
—
—
—
—
—
—
0.5
0.5
—
—
—
—
—
—
—
—
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
REJ03F0218-0201 Rev.2.01 Mar 31, 2008
Page 14 of 23
L+R
2
3
4
1
DI-SW
Input
auto-balance
2
L−R
Adaptive
matrix
F.B.VOL
Logic
10 Kbit SRAM
Digital delay
S'
Noise
sequencer
Selector
MICIN 20
VRSWIN 80
SWIN 79
SRIN 78
SLIN 77
CIN 76
RTIN 75
LTIN 74
RIN 73
LIN 72
DO-SW
LPF
D/A
A/D
LPF
ECHOOUT
41
2
1
Space
Mute
+/−
23
24
DATA SCK REQ
22
MCU
interface
SWVOL
SWtrim
SRtrim
SLtrim
SW-SW
2
1
2
3
1
SR-SW
2
3
1
SL-SW
2
1
5
1
5
1
R-SW
2
3
4
4
2
3
L-SW
Ctrim
5.1ch
Bypass
Space
Mute
+
C-SW
S
BNR-SW
2
3
1
Pseudo SL
stereo SR
Pro logic
Modified
BNR
Wide
normal
phantom
off
Center
mode
control
DELAYVOL
C
R
L
Pro logic
5.1ch
Bypass
9
3
17
14
SWBP-SW
2
1
SRVOL
SLVOL
CVOL
2
1
SWVOL
OUT
SRVOL
OUT
SLVOL
OUT
CVOL
OUT
ROUT
LOUT
M62464BFP
Mode Example
(1) 5.1ch Input
REJ03F0218-0201 Rev.2.01 Mar 31, 2008
Page 15 of 23
L+R
2
3
4
1
DI-SW
Input
auto-balance
2
L−R
Adaptive
matrix
F.B.VOL
Logic
10 Kbit SRAM
Digital delay
S'
Noise
sequencer
Selector
MICIN 20
VRSWIN 80
SWIN 79
SRIN 78
SLIN 77
CIN 76
RTIN 75
LTIN 74
RIN 73
LIN 72
DO-SW
LPF
D/A
A/D
LPF
ECHOOUT
41
2
1
Mute
+/−
23
24
DATA SCK REQ
22
MCU
interface
SWVOL
SWtrim
SRtrim
SLtrim
SW-SW
2
1
2
3
1
SR-SW
2
3
1
SL-SW
2
1
5
1
5
1
R-SW
4
2
3
4
2
3
L-SW
Ctrim
5.1ch
Bypass
Space
Mute
+
C-SW
S
BNR-SW
2
3
1
Pseudo SL
stereo SR
Pro logic
Modified
BNR
Wide
normal
phantom
off
Center
mode
control
DELAYVOL
C
R
L
Pro logic
5.1ch
Bypass
Space
9
3
17
14
SWBP-SW
2
1
SRVOL
SLVOL
CVOL
2
1
SWVOL
OUT
SRVOL
OUT
SLVOL
OUT
CVOL
OUT
ROUT
LOUT
M62464BFP
(2) Pro Logic Surround
REJ03F0218-0201 Rev.2.01 Mar 31, 2008
Page 16 of 23
L+R
2
3
4
1
DI-SW
Input
auto-balance
2
L−R
Adaptive
matrix
F.B.VOL
Logic
10 Kbit SRAM
Digital delay
S'
Noise
sequencer
Selector
MICIN 20
VRSWIN 80
SWIN 79
SRIN 78
SLIN 77
CIN 76
RTIN 75
LTIN 74
RIN 73
LIN 72
DO-SW
LPF
D/A
A/D
LPF
ECHOOUT
41
2
1
Mute
+/−
23
24
DATA SCK REQ
22
MCU
interface
SWVOL
SWtrim
SRtrim
SLtrim
SW-SW
2
1
2
3
1
SR-SW
2
3
1
SL-SW
2
1
5
1
5
1
R-SW
3
4
2
3
4
2
L-SW
Ctrim
5.1ch
Bypass
Space
Mute
+
C-SW
S
BNR-SW
2
3
1
Pseudo SL
stereo SR
Pro logic
Modified
BNR
Wide
normal
phantom
off
Center
mode
control
DELAYVOL
C
R
L
Pro logic
5.1ch
Bypass
Space
9
3
17
14
SWBP-SW
2
1
SRVOL
SLVOL
CVOL
2
1
SWVOL
OUT
SRVOL
OUT
SLVOL
OUT
CVOL
OUT
ROUT
LOUT
M62464BFP
(3) Space Surround
REJ03F0218-0201 Rev.2.01 Mar 31, 2008
Page 17 of 23
L+R
2
3
4
1
DI-SW
Input
auto-balance
2
L−R
Adaptive
matrix
F.B.VOL
Logic
10 Kbit SRAM
Digital delay
S'
Noise
sequencer
Selector
MICIN 20
VRSWIN 80
SWIN 79
SRIN 78
SLIN 77
CIN 76
RTIN 75
LTIN 74
RIN 73
LIN 72
DO-SW
LPF
D/A
A/D
LPF
ECHOOUT
41
2
1
Space
Mute
+/−
23
24
DATA SCK REQ
22
MCU
interface
SWVOL
SWtrim
SRtrim
SLtrim
SW-SW
2
1
2
3
1
SR-SW
2
3
1
SL-SW
2
1
5
1
5
1
R-SW
3
4
2
4
3
2
L-SW
Ctrim
5.1ch
Bypass
Space
Mute
+
C-SW
S
BNR-SW
2
3
1
Pseudo SL
stereo SR
Pro logic
Modified
BNR
Wide
normal
phantom
off
Center
mode
control
DELAYVOL
C
R
L
Pro logic
5.1ch
Bypass
9
3
17
14
SWBP-SW
2
1
SRVOL
SLVOL
CVOL
2
1
SWVOL
OUT
SRVOL
OUT
SLVOL
OUT
CVOL
OUT
ROUT
LOUT
M62464BFP
(4) Echo
M62464BFP
Level Diagram
(1) Dolby Pro Logic Surround Mode
Cch
LTIN
RTIN
Signal level
Input
balance
−3 dB
C-SW
Center
mode
control
Adaptive
matrix
−3.2 dB
−3.2 dB
+3 dB
Ladder
Buffer
−3.2 dB
0 dB
CVOLOUT
2
0 dB
Gain
Trimmer&Volume
0 dB
+3.2 dB
Vref = 4.5 V
Vref = 3.6 V
Vref = 2.5 V
Sch
LTIN
RTIN
Signal level
S' DI-SW
Input
balance
Adaptive
matrix
1
DO-SW
1
Digital
delay
BNR-SW SL-SW
BNR 1
Trimmer&Volume
Ladder
SLVOL
OUT
Buffer
2
−3 dB
Gain
0 dB
+3 dB
−6.8 dB −6.8 dB
−3.2 dB 0 dB
Vref = 4.5 V
−6.8 dB
0 dB
0 dB
−3.2 dB −3.2 dB
+6.8 dB −3.2 dB 0 dB
0 dB
+3.2 dB
Vref = 3.6 V
Vref = 4.5 V
Vref = 2.5 V
Vref = 2.5 V
Lch, Rch
LTIN
RTIN
Signal level
Input
balance
Adaptive
matrix
Center
mode
control
LOUT
ROUT
0 dB
Vref = 4.5 V
Signal level: 0 dB = 300 mVrms (typ.)
REJ03F0218-0201 Rev.2.01 Mar 31, 2008
Page 18 of 23
M62464BFP
(2) 5.1ch Signal Input Mode
C-SW
SL-SW
SR-SW
SW-SW
C, SL, SR, SW ch
CIN
SLIN
SRIN
SWIN
CVOLOUT
SLVOLOUT
SRVOLOUT
SWVOLOUT
Trimmer&Volume
Ladder
Buffer
2
Signal level
−3.2 dB
0 dB
Gain
−3.2 dB
−3.2 dB
0 dB
0 dB
+3.2 dB
Vref = 4.5 V
Vref = 3.6 V
Vref = 2.5 V
Signal level: 0 dB = 300 mVrms (typ.)
(3) Space Surround Mode
Delay Signal
DI-SW
LIN
RIN
L−R
2
(L+R) / 2
3
Signal level
0 dB
Gain
Digital Delay
vol
delay
−6.8 dB
−6.8 dB
−6.8 dB
DO-SW
1
0 dB
BNR-SW
BNR
1
2
−6.8 dB
0 dB
to L/R Mix
0 dB
+6.8 dB
Vref = 4.5 V
Vref = 4.5 V
Vref = 2.5 V
Signal level: 0 dB = 300 mVrms (typ.)
(4) Echo Mode
DI-SW
MICIN
4
Signal level
DO-SW
Digital
delay
0 dB
0 dB
Vref = 4.5 V
Delay
vol
ECHOOUT
2
0 dB
Vref = 4.5 V
Vref = 2.5 V
REJ03F0218-0201 Rev.2.01 Mar 31, 2008
Page 19 of 23
Signal level: 0 dB = 300 mVrms (typ.)
M62464BFP
Notice
Relation AVCC and DVDD at power supply Digital VDD must be supplied less than 0.7 seconds from analog VCC supply.
AVCC
(AVCC > DVDD)
DVDD
Internal
reset signal
Automatic reset cancel
0.7 s (Min)
REJ03F0218-0201 Rev.2.01 Mar 31, 2008
Page 20 of 23
M62464BFP
Application Example
C38
1000 pF
C34
C33
0.22 µF 0.22 µF
C35
0.1 µF
C37
C31
0.1 µF
C29
1000 pF
C28
C26
1 µF
4700 pF
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
ECHOOUT
MCU
24
21
20
19
18
+
17
16
15
Trim
SW
+
14
SR
12
13
Trim
C10
10 µF
SLVOLOUT
9
+
10
Trim
VOL
5
L-SW
1
C-SW
VOL
+
C4
10 µF
3
+
Servo
8
6
2
1
VCA
C7
0.1 µF
5
C
4
3
2
C8 0.1 µF
7
1
Auto
balance
CVOLOUT
R
2
C3 10 µF
+
L−R
5
L+R
+
C73
10 µF
+
C74
10 µF
+
C75
10 µF
+
C76
10 µF
+
C77
10 µF
+
C78
10 µF
22 kΩ
79
22 kΩ
78
22 kΩ
77
22 kΩ
76
22 kΩ
75
74
22 kΩ
+
C79
10 µF
+
22 kΩ
C80
10 µF
+
+
C72
10 µF
22 kΩ
73
72
+
R71
100 kΩ
AVCC
+9 V
REJ03F0218-0201 Rev.2.01 Mar 31, 2008
Page 21 of 23
C69
100 µF
+
L
1
C70
220 µF
C68
4.7 µF
C1 10 µF
22 kΩ
71
69
+
VREF IREF
70
AVcc
68
65
64
+
C2 10 µF
Noise
sequencer
R63 75 kΩ
67
60
BPF
61
62
C63 0.01 µF
4
3
2
+/−
Selector
66
C65
0.01 µF
C12
10 µF
4
56
R-SW
+
R61 75 kΩ
C62 680 pF
R62 47 kΩ
SRVOLOUT
C9 10 µF
Pseudo
surround
55
S'
VCA
BPF
RA62
150 kΩ
C61 0.01 µF
63
C64
0.01 µF
VOL
2
1
SL-SW
Combining
networks
C59 0.1 µF
C60 680 pF
R60 47 kΩ
SL
R
11
C
Trim
Log
difference
amplifiers
2
1
3
L
C
C15
10 µF
C14 10 µF
3
Center mode
control
R
C17 10 µF
1
3
MICIN
SWVOLOUT
1
2
1
2
59
C58 0.022 µF
SW-SW
L+R
2
BNR-SW
Full wave
rectifier
C57 0.022 µF
3
L−R
L
57
C56 0.1 µF
2
SR-SW
58
C55 0.1 µF
54
C53 0.047 µF
C54 0.047 µF
4
VOL
51
53
C52 0.1 µF
2
1
DVDD
+5 V
C18
0.1 µF
SWBP-SW
DI-SW
52
C51 0.22 µF
50
C49 4.7 µF
C50 0.22 µF
F.B.
VOL
Dual-time constant
and threshold switches
48
+
C48 4.7 µF
C21
0.1 µF
C20 1 µF
AGND
46
47
+
49
C47 0.22 µF
CLK
10 Kbit
SRAM
C45 0.68 µF
C46 0.22 µF
DVdd
Modified
B-tipe
NR decoder
43
44
45
R45 330 kΩ
Logic
80
+
C44 0.047 µF
+
DO-SW
C43 5600 pF
23
2
1
22
+
LPF
A/D
MCU interface
41
D/A
+
42
LPF
+
+
C42
1 µF
Delay
vol
DATA SCK REQ
DVss
C41
1 µF
RA60
150 kΩ
25
+
4700 pF
LIN
RIN
SRIN VRSWIN
LTIN
CIN
SLIN
RTIN
SWIN
ROUT
LOUT
M62464BFP
External Parts List
Parts No.
C1
C2
C3
C4
C7
C8
C9
C10
C12
C14
C15
C17
C18
C20
C21
C26
C28
C29
C31
C33
C34
C35
C37
C38
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
C55
C56
Values
10
10
10
10
0.1
0.1
10
10
10
10
10
10
0.1
1.0
0.1
1.0
4700
1000
0.1
0.22
0.22
0.1
4700
1000
1.0
1.0
5600
0.047
0.68
0.22
0.22
4.7
4.7
0.22
0.22
0.1
0.047
0.047
0.1
0.1
Unit
µF
µF
µF
µF
µF
µF
µF
µF
µF
µF
µF
µF
µF
µF
µF
µF
pF
pF
µF
µF
µF
µF
pF
pF
µF
µF
pF
µF
µF
µF
µF
µF
µF
µF
µF
µF
µF
µF
µF
µF
REJ03F0218-0201 Rev.2.01 Mar 31, 2008
Page 22 of 23
Tol.
10%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
10%
10%
10%
20%
20%
10%
10%
20%
5%
5%
20%
20%
Parts No.
C57
C58
C59
C60
C61
C62
C63
C64
C65
C68
C69
C70
C72
C73
C74
C75
C76
C77
C78
C79
C80
Values
0.022
0.022
0.1
680
0.01
680
0.01
0.01
0.01
4.7
100
220
10
10
10
10
10
10
10
10
10
Unit
µF
µF
µF
pF
µF
pF
µF
µF
µF
µF
µF
µF
µF
µF
µF
µF
µF
µF
µF
µF
µF
Tol.
5%
5%
20%
5%
5%
5%
5%
5%
5%
R45
R60
RA60
R61
R62
RA62
R63
R71
330
47
150
75
47
150
75
100
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
10%
5%
5%
5%
5%
5%
5%
5%
M62464BFP
Package Dimensions
JEITA Package Code
P-QFP80-14x20-0.80
RENESAS Code
PRQP0080GB-A
Previous Code
80P6N-A
MASS[Typ.]
1.6g
HD
*1
D
64
41
65
HE
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
ZE
*2
E
40
Reference
Symbol
80
25
1
ZD
24
D
E
A2
HD
HE
A
A1
bp
c
c
Index mark
A
A2
F
*3
y
bp
L
A1
e
Detail F
REJ03F0218-0201 Rev.2.01 Mar 31, 2008
Page 23 of 23
e
y
ZD
ZE
L
Dimension in Millimeters
Min Nom Max
19.8 20.0 20.2
13.8 14.0 14.2
2.8
22.5 22.8 23.1
16.5 16.8 17.1
3.05
0.1 0.2
0
0.3 0.35 0.45
0.13 0.15 0.2
0°
10°
0.65 0.8 0.95
0.10
0.8
1.0
0.4 0.6 0.8
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes
warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property
rights or any other rights of Renesas or any third party with respect to the information in this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a
result of errors or omissions in the information included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability
of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular
application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications
or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality
and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or
undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall
have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as
swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.
Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have
any other inquiries.
http://www.renesas.com
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2377-3473
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2008. Renesas Technology Corp., All rights reserved. Printed in Japan.
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