M66311P/FP 16-Bit LED Driver with Shift Register and Latch REJ03F0177-0201 Rev.2.01 Mar 31, 2008 Description M66311P/FP is a LED array driver having a 16 bit serial-input and parallel output shiftregister function with direct coupled reset input and output latch function. This product guarantees the output electric current of 24 mA which is sufficient for anode common LED drive, capable of flowing 16 bits continuously at the same time. Parallel output is open drain output. In addition, as this product has been designed in complete CMOS, power consumption can be greatly reduced when compared with conventional BIPOLAR or Bi-CMOS products. Furthermore, pin lay–out ensures the realization of an easy printed circuit. Features • Anode common LED drive • High output current all parallel output IOL = 24 mA simultaneous lighting available • Low power dissipation: 100 µW/package (max) (VCC = 5 V, Ta = 25°C, quiescent state) • High noise margin schmitt input circuit provides responsiveness to a long line length. • Equipped with direct-coupled reset • Open drain output (except serial data output) • Wide operating temperature range: Ta = −40 to +85°C • Pin lay-out facilitates printed circuit wiring. (This lay-out facilitates cascade connection and LED connection.) Application LED array drive of BUTTON TELEPHONE LED array drive of ERASER of a PPC copier Other various LED modules REJ03F0177-0201 Rev.2.01 Mar 31, 2008 Page 1 of 9 M66311P/FP Logic Diagram Parallel data outputs 5 QA QB QC QD QE QF QG QH QI QJ QK QL QM QN QO QP 1 2 24 23 22 21 20 19 18 17 16 15 14 13 11 12 0 CK D S 0 CK D S 0 CK D S 0 CK D S 0 CK D S 0 CK D S 0 CK D S 0 CK D S 0 CK D S 0 CK D S 0 CK D S 0 CK D S 0 CK D S 0 CK D S 0 CK D S 0 CK D S 1 CK D S 1 CK D S 1 CK D S 1 CK D S 1 CK D S 1 CK D S 1 CK D S 1 CK D S 1 CK D S 1 CK D S 1 CK D S 1 CK D S 1 CK D S 1 CK D S 1 CK D S 1 CK D S 4 8 A OE Enable Serial input data input Parallel data output Serial data output Pin Arrangement M66311P/FP QA ← 1 QA QC 24 → QC QB ← 2 QB QD 23 → QD QE 22 → QE A QF 21 → QF OE QG 20 → QG CKL QH 19 → QH R QI 18 → QI CKS QJ 17 → QJ QK 16 → QK SQP QL 15 → QL QO ← 11 QO QM 14 → QM QP ← 12 QP QN 13 → QN VCC 3 Serial data input A→ 4 Enable input OE → 5 Latch clock input CKL → 6 Direct reset input R→ 7 Shift clock input CKS → 8 GND 9 Serial data output SQP ← 10 Parallel data outputs (Top view) Outline: PRDP0024AA-A (24P4D) (24P2N-B) REJ03F0177-0201 Rev.2.01 Mar 31, 2008 Page 2 of 9 10 7 3 6 9 CKS CKL GND R Shift Direct Latch clock reset clock input input input Output format Parallel data outputs Serial data output SQP VCC Parallel data outputs M66311P/FP Functional Description As M66311P/FP uses silicon gate CMOS process, it realizes high-speed and high-output currents sufficient for LED drive while maintaining low power consumption and allowance for high noises. Each bit of a shiftregister consists of two flip–flops having independent clocks for shifting and latching. As for clock input, shift clock input CKS and latch clock input CKL are independent from each other, shift and latch operations being made when “L” changes to “H”. Serial data input A is the data input of the first–step shiftregister and the signal of A shifts shifting registers one by one when a pulse is impressed to CKS. When A is “H”, the signal of “L” shifts. When the pulse is impressed to CKL, the contents of the shifting register at that time are stored in a latching register, and they appear in the outputs from QA to QP. Outputs from QA to QP are open drain outputs. To extend the number of bits, use the serial data output SQP which shows the output of the shifting register of the 16th bit. If CKS and CKL are connected, the state of the shifting register with one clock delay is outputted to QA to QP. When reset input R is changed to “L”, QA to QP and SQP are reset. In this case, shifting and latching registers are set. If “H” is impressed to output enable input OE, QA to QP reaches the high impedance state, but SQP does not reach the high impedance state. Furthermore, change in OE does not affect shift operation. Function Table (Note) Input Parallel Data Output Operation Mode R A OE QA QB QC QD QE QF QG QH QI QJ QK QL QM QN QO QP Reset L X X X X Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z X H L CKS CKL Shift Shift t1 H ↑ latch Latch t2 H X ↑ X L H ↑ X L L H X ↑ X L Z qA0 qB0 qC0 qD0 qE0 qF0 X X X X H Z Z Z Z Z Z Z operation Shift t1 Latch t2 Output disable Note QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 qB0 qC0 qD0 qG0 qH0 qI0 QI0 QJ0 QK0 QL0 QM0 QN0 QO0 QP0 qO0 qG0 qH0 qI0 qJ0 qK0 qL0 qM0 qN0 qO0 qO0 Z Z Z Z Z Z Z Z Z qP ↑: Change from low-level to high-level Q0: Output state Q before CKL changed X: Irrelevant q0: Contents of shift register before CKS changed q: Contents of shift register t1, t2: t2 is set after t1 is set Z: High impedance REJ03F0177-0201 Rev.2.01 Mar 31, 2008 Page 3 of 9 qE0 qF0 L QJ0 QK0 QL0 QM0 QN0 QO0 QP0 qO0 QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 L qA0 QI0 Serial Data Output SQP Remarks qJ0 qK0 qL0 qM0 qN0 qO0 qO0 – Output lighting "H" Output lights-out "L" – M66311P/FP Absolute Maximum Ratings (Ta = −40 to +85°C, unless otherwise noted) Item Symbol Supply voltage Input voltage Output voltage Input protection diode current VCC VI VO IIK Output parasitic diode current IOK Output current per output pin QA to QP SQP IO Supply/GND current Power dissipation Storage temperature range Note: ICC Pd Tstg Ratings −0.5 to +7.0 −0.5 to VCC + 0.5 −0.5 to VCC + 0.5 −20 20 −20 20 50 ±25 −20, +410 500 −65 to +150 Unit V V V mA mA Conditions VI < 0 V VI > VCC VO < 0 V VO > VCC mA mA mW °C VCC, (Note) GND M66311FP; Ta = −40 to +70°C, Ta = 70 to 85°C are derated at −6 mW/°C. Recommended Operating Conditions (Ta = −40 to +85°C, unless otherwise noted) Item Supply voltage Input voltage Output voltage Operating temperature range REJ03F0177-0201 Rev.2.01 Mar 31, 2008 Page 4 of 9 Symbol VCC VI VO Topr Min Limits Typ Max Unit 4.5 0 0 −40 5 — — — 5.5 VCC VCC +85 V V V °C M66311P/FP Electrical Characteristics (VCC = 4.5 to 5.5V, unless otherwise noted) Limits Sy mb ol Min Positive-going threshold voltage VT+ 0.35×VCC — 0.7×VCC 0.35×VCC 0.7×VCC V VO = 0.1 V, VCC−0.1 V IO = 20 µA Negative-going threshold voltage VT– 0.2×VCC — 0.55×VCC 0.2×VCC 0.55×VCC V VO = 0.1 V, VCC−0.1 V IO = 20 µA Low-level output voltage QA to QP VOL — — — — — — 0.1 0.44 0.73 — — — 0.1 0.53 0.94 V VI = VT+, VT– VCC = 4.5 V High-level output voltage SQP VOH VCC−0.1 3.83 — — — — VCC−0.1 3.66 — — V VI = VT+, VT– VCC = 4.5 V IOH = −20 µA IOH = −4 mA Low-level output voltage SQP VOL — — — — 0.1 0.44 — — 0.1 0.53 V VI = VT+, VT– VCC = 4.5 V IOL = 20 µA IOL = 4 mA High-level input current IIH — — 0.5 — 5.0 µA VI = VCC, VCC = 5.5 V Low-level input current IIL — — −0.5 — −5.0 µA VI = GND, VCC = 5.5 V Maximum output leakage current QA to QP IO — — — — 1.0 −1.0 — — 10.0 −10.0 µA VI = VT+, VT– VCC = 5.5 V Quiescent supply current ICC — — 20.0 — 200.0 µA VI = VCC, GND, VCC = 5.5 V Item Note: Ta = 25°C Typ Max Ta = −40 to +85°C Min Max Unit Conditions IOL = 20 µA IOL = 24 mA IOL = (Note) 40 mA VO = VCC VO = GND M66311 is used under the condition of an output current IOL = 40 mA, the number of simultaneous drive outputs is restricted as shown in the Duty Cycle-IOL of Standard characteristics. REJ03F0177-0201 Rev.2.01 Mar 31, 2008 Page 5 of 9 M66311P/FP Switching Characteristics (VCC = 5 V) Limits Min Ta = 25°C Typ Max fmax tPLH tPHL 5 — — — — — — 100 100 4 — — High-level to low-level output propagation time (RSQP) tPHL — — 100 Low-level to high-level output propagation time (RQA to QP) tPLZ — — Low-level to high-level and high-level to low-level output propagation time (CKL-QA to QP) tPZL tPLZ — — Output enable time to lowlevel and high-level (OE−QA to QP) Input Capacitance Output Capacitance tPZL tPLZ CI CO Power dissipation (Note 1) Capacitance CPD Item Maximum clock frequency Low-level to high-level and high-level to low-level output propagation time (CKS-SQP) Note: Symbol Ta = −40 to +85°C Min Max Unit Conditions — 130 130 MHz ns ns CL = 50 pF RL = 1 kΩ — 130 ns 150 — 200 ns — — 100 150 — — 130 200 ns ns — — 100 — 130 ns — — 150 — 200 ns — — — — — 5 10 15 — — — — 10 15 — pF pF pF (Note 2) OE = VCC 1. CPD is the internal capacitance of the IC calculated from operation supply current under no-load conditions. (per latch) The power dissipated during operation under no-load conditions is calculated using the following formula: 2 PD = CPD • VCC • fI + ICC • VCC Timing Requirements (VCC = 5 V) Limits Symbol Min Ta = 25°C Typ Max CKS, CKL, R pulse width tw A setup time with respect to CKS tsu 100 100 — — — — 130 130 — — ns ns CKS setup time with respect to CKL tsu 100 — — 130 — ns A hold time with respect to CKS th 10 — — 15 — ns R, recovery time with respect to CKS, CKL trec 50 — — 70 — ns Item REJ03F0177-0201 Rev.2.01 Mar 31, 2008 Page 6 of 9 Ta = −40 to +85°C Min Max Unit Conditions (Note 2) M66311P/FP Note: 2. Test Circuit VCC Input VCC RL PG SQP DUT 50 Ω QA to QP CL CL GND (1) The pulse generator (PG) has the following characteristics (10% to 90%): tr = 6 ns, tf = 6 ns (2) The capacitance CL includes stray wiring capacitance and the probe input capacitance. Typical Characteristics Duty Cycle vs. IOL (VCC = 4.5 V, Ta = 25°C) 50 50 30 ⋅ Repetition frequency > 10 Hz ⋅ Numbers in ( ) indicate the number of output circuits that operate simultaneously. ⋅ Current values are per circuit. 10 (1) to (9) (10) (11) (12) (13) (14) (15) (16) 40 (1) to (16) IOL (mA) IOL (mA) 40 20 Duty Cycle vs. IOL (VCC = 4.5 V, Ta = 85°C) 30 ⋅ Repetition frequency > 10 Hz ⋅ Numbers in ( ) indicate the number 20 of output circuits that operate simultaneously. ⋅ Current values are per circuit. 10 0 0 0 20 40 60 80 Duty Cycle (%) REJ03F0177-0201 Rev.2.01 Mar 31, 2008 Page 7 of 9 100 0 20 40 60 Duty Cycle (%) 80 100 M66311P/FP Timing Chart tw VCC VCC CKS 50% 50% 50% tPLH tPHL 50% CKL GND GND tPZL VOH 50% 50% SQP VOL 50% QA to QP VOL tPLZ tw VCC R 50% 50% trec QA to QP VCC VCC A 50% 50% GND GND tPHL tsu th VOH SQP VCC 50% VOL tPLZ QA to QP VOL GND 50% CKS 10% 10% 50% CKS GND VOL VCC VCC OE 50% CKS 50% tPZL GND tsu GND tPLZ 50% tw VCC QA to QP 50% 10% REJ03F0177-0201 Rev.2.01 Mar 31, 2008 Page 8 of 9 CKL VOL 50% 50% GND M66311P/FP Package Dimensions RENESAS Code PRDP0024AA-A Previous Code 24P4D MASS[Typ.] 1.6g 13 1 12 c *1 E 24 e1 JEITA Package Code P-DIP24-6.3x29.2-2.54 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. D Reference Dimension in Millimeters Symbol e1 D E A A1 A2 bp b2 b3 c L A1 A A2 *2 bp e SEATING PLANE *3 *3 b3 b2 e L 24P2N-B Min Nom Max 7.32 7.62 7.92 29.0 29.2 29.4 6.15 6.3 6.45 4.5 0.51 3.3 0.4 0.5 0.6 0.9 1.0 1.3 1.4 1.5 1.8 0.22 0.27 0.34 0° 15° 2.29 2.54 2.79 3.0 Plastic 24pin 300mil SOP EIAJ Package Code SOP24-P-300-1.27 JEDEC Code — Weight(g) Lead Material Cu Alloy 24 e b2 E HE e1 I2 13 Recommended Mount Pad Symbol F 1 12 A D G A2 e b x M L L1 y A1 A A1 A2 b c D E e HE L L1 z Z1 x y c z Z1 Detail G REJ03F0177-0201 Rev.2.01 Mar 31, 2008 Page 9 of 9 Detail F b2 e1 I2 Dimension in Millimeters Min Nom Max — — 2.1 0 0.1 0.2 — — 1.8 0.35 0.4 0.5 0.18 0.2 0.25 14.92 15.02 15.12 5.2 5.3 5.4 — — 1.27 7.82 8.12 8.42 0.3 0.5 0.7 — — 1.41 — — 0.525 — — 0.675 — — 0.25 — — 0.1 0° 10° — 0.76 — — — — 7.62 — — 1.27 Sales Strategic Planning Div. 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