M62465FP Dolby Pro Logic Surround REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Description The M62465FP is a single chip LSI supporting the Dolby Pro Logic surround. This LSI contains all functions necessary for Dolby Pro Logic surround. In addition, it has Digital Space Surround functions (Disco, Hall, Live mode etc.) and echo function for karaoke. Note: Use of this LSI requires the license of Dolby Laboratories Licensing Corporation Dolby and the double-D symbol are trademarks of Dolby Laboratories Licensing Corporation. San Francisco, CA94103-4813, USA. This device available only to licensees of Dolby Lab. Licensing and application information may be obtained from Dolby Lab. Features (Mode) • Upper compatible for M62460FP and less external parts than M62460FP. • Includes all functions requires for Dolby Pro Logic Surround. Adaptive Matrix. Noise Sequencer by digital noise source and switched capacitor filter. Center Mode Control (Wide/Normal/PHANTOM/OFF). Modified Dolby B Type Noise Reduction. 4ch/3ch Stereo Selectable. Digital Delay: 15.4, 20, 28.6 ms for Dolby Pro Logic Surround. • C/Sch Trimmer: 0 to −31 dB/1 dB Step. • Digital Space Surround Mode: Disco/Hall/Live mode and 5 delay time positions. • Digital Echo function for KARAOKE: (Short echo) Delay time = 147.5 ms, (Long echo) Delay time = 196.6 ms. • BY-PASS Mode: Input signal through output. System Block Diagram L Rch IN Adaptive matrix R C S L+R 2 L−R 2 MIC IN 7 kHz LPF Digital noise sequencer LPF-IN Digital delay Modified S dolby B-NR LPF-OUT NR-IN L R Center trim C Surround trim S MCU interface DATA SCK REQ REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 1 of 24 Lch Master volume control Input autobalance control Center/operating mode control Lch IN Rch CENTER SURROUND LLI RLC6 66 65 69 67 RBPF 70 LBPF LT 71 68 RT 72 RLI LIN 73 BPF BPF 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 − Auto balance VCA Servo S L C R L R C 8 S' −6.0 dB ATT +9.2 dB +3.2 dB Selector2 MCU interface 15 16 17 18 19 DATA SCK REQ 14 Test CNT S' ATT −3.2 dB 13 DVdd 12 Selector3 11 AGND 10 + − 9 Center mode control 7 Trimmer + − +/− S 6 ST 20 21 AVdd DVss AVss VREFD 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 AVdd VREFD MIX OUT DELAY IN LPF1 IN1 LPF1 IN2 LPF1 OUT AD INT IN AD INT OUT AD CONT DA CONT DA INT IN DA INT OUT LPF2 IN1 LPF2 IN2 LPF2 OUT VOL 61 S 5 Trimmer C SFB MOS Modified B-type NR decoder 62 4 CT + 3 R Dual-time constant and threshold switches 63 Selector 2 LOG difference amplifiers 64 VREFA Full wave rectifier VOL OUT 22 23 AVss RIN DELAY SIG IN LPF D/A A/D 24 LPF DVss 74 DELAY SIG OUT XOUT HOLDC FBIN EC Logic XIN AVcc FBIN SU LO3 75 S' OUT LO2 AVcc DBIN LO1 76 LPIN REQ VREFA DBC1 + SCK 77 DBC2 + DATA VREFG DBC3 TEST CNT 78 PSC3 DVdd IREF PSC6 L+R 2 L−R 2 MIC IN MIX CLK PSC2 AGND 79 PSC5 SMRI REF OUT PSC1 SMRO 80 PSC4 Combinning networks CMC NSQ RLC5 VCA SOUT L REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 2 of 24 RLC2 ST 1 The function of pin No.1, 79, 80 is different from that of M62460FP. Note: RLC1 COUT EC RLC4 CT SU RLC7 Selector1 ROUT 16 K SRAM RLC3 L−R L+R Digital noise sequencer LOUT MIC RLC8 IREF VREF 1/2 Vcc FILTER + − M62465FP Block Diagram M62465FP Pin Arrangement M62465FP RLC6 65 69 66 70 LLI RBPF 71 67 LT 72 68 RT 73 RLI LIN 74 LBPF RIN 75 76 AVcc 77 HOLDC VREFA 78 79 IREF 80 VREFG NSQ REF OUT 61 60 59 58 57 56 55 54 53 52 PSC3 51 DBC3 50 DBC2 49 DBC1 48 LPIN FBIN SU XIN 44 FBIN EC XOUT 43 DELAY SIG OUT DVss 42 DELAY SIG IN AVss 41 LO3 S' OUT 45 DBIN LO2 46 LO1 24 REQ 23 SCK 22 DATA 21 TEST CNT 20 DVdd 47 62 PSC6 MIC IN 19 PSC2 18 PSC5 AGND 17 PSC1 SMRI 16 PSC4 15 RLC5 14 RLC2 13 RLC1 12 RLC4 11 RLC7 10 RLC3 9 63 8 RLC8 SMRO VOL OUT 35 36 37 38 39 40 AD CONT DA CONT DA INT IN DA INT OUT LPF2 IN1 LPF2 IN2 LPF2 OUT LPF1 IN2 34 LPF1 IN1 AD INT OUT 30 DELAY IN 33 29 MIX OUT AD INT IN 28 VREFD LPF1 OUT 27 AVdd 32 26 31 25 (Top view) Outline: PRQP0080GB-A (80P6N-A) Note: 64 7 CMC 6 SOUT 5 ST 4 COUT 3 CT 2 LOUT ROUT 1 FILTER The function of pin No.1, 79, 80 is different from that of M62460FP. REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 3 of 24 M62465FP Pin Description No. 2 3 Symbol LOUT ROUT Function Lch output Rch output 4 CT Cch output 5 COUT Cch output 6 ST Voltage 4V Sch output 7 SOUT Sch output 9 SMRO Amplifier output 4V Description Direct output R-/Lchannel when the operation mode is BYPASS. When the mode is 4channel, they output Dolby Pro Logic R-/Lchannel signals. No output any signals when the operation mode is center mode is OFF or set to PHANTOM. Equivalent Circuit VCC This pin output surround signals. Output is selected from BNRout, Dout No output signal when the operation mode is 3STEREO/MUTE. 3 4 5 6 7 VCC COUT is output from C. Trimmer. 4V 2 VCC SOUT is output from S. Trimmer. 4V This is a amplifier to control mixed level of surround output with external resistance. VCC 9 10 SMRI Amplifier input VCC 10 12 MIC IN MIC input 4V Microphone input with ECHO MODE VCC 12 REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 4 of 24 M62465FP No. Symbol 14 TEST CNT Function Voltage TEST control 0 Description Equivalent Circuit Fixed to GND 14 15 DATA — Serial data “DATA” input buffer Input via serial data from MCU. 15 16 SCK 0 Serial data “SCK” input 16 17 17 REQ Serial data “REQ” input 18 19 20 LO1 LO2 LO3 Port output — Open collector output pin (NPN Tr) — Connect 4 MHz ceramic resonator 21 XIN Oscillator input 22 XOUT Oscillator output buffer buffer 18 19 20 21 26 VREFD Reference output 2.5 V 22 1/2 VCC output Connect a filter capacitor. 26 27 MIX OUT 4V S′, L+R, L–R and MIC output Signal output precedent to delay generator. That is S′, L+R, L−R and MIC output. VCC 27 28 DELAY IN Delay input 2.5 V This is s delay input. Please input by AC coupling. 28 40 41 LPF2 OUT VOL OUT Delay signal output 2.5 V Output of a delay volume REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 5 of 24 Delay signal output 40 This is output of a delay volume that possible to control +3 dB to −∞. 41 M62465FP No. Symbol 42 DELAYSIG IN Function Voltage — 4V Description Delay signal input to a mixing amplifier Equivalent Circuit VCC 42 43 DELAYSIG OUT Input from mixing amplifier 4V Delay signal output from a mixing amplifier VCC 43 44 FBIN EC 45 FBIN SU Feedback signal input 4V Feedback signal input with ECHO MODE Feedback signal input with SURROUND MODE VCC 44 45 46 47 48 S′OUT DBIN LPIN Sch output LPF output Negative input of LPF 4V 4V Sorround channel output precedent to delay generator. Always outputs signals, irrespectiv of the operation mode (2-/3-/4channel) VCC This amplifier compornent 7 kHz-LPF with external resistances and capaciters. LPF output is conected to input of Modifide BNR. VCC 46 47 VCC 48 REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 6 of 24 M62465FP No. 72 73 Symbol LIN RIN Function Voltage Description 4V Input of Lch and Rch that is non-inverted input type. Please pul-up to VREF by external resistances for DC bias. Lch input Rch input Equivalent Circuit VCC 72 73 70 LT Autobalance Lch output 71 RT Autobalance Rch output 4V Autobalance output. VCC 70 71 76 VREFA Reference voltage input — 77 VREFG Reference voltage output 4V It is a reference voltage input terminal to each circuit inside the IC. Reference voltage output. Voltage is the fixed at 4V. 76 VCC 77 1 79 FILTER 1/2VCC New future of M62465FP Auxiliary 1/2VCC reference generator. REFOUT 1/2VCC output New future of M62465FP Auxiliary 1/2VCC reference generator. 1/2VCC 1/2VCC The terminal which make a 1/2VCC voltage by the resistance. When it is used, a filter capacitor is connected. VCC 1/2VCC voltage output. It is used to change reference voltage except 4V. VCC 1 79 80 NSQ Noise sequencer monitor New future of M62465FP 4V Noise sequencer monitor output. It is only for test. VCC 80 REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 7 of 24 M62465FP Absolute Maximum Ratings (Ta = 25°C, unless otherwise noted) Item Supply voltage Symbol Ratings Unit Condition VCC 10.5 V VDD 6.5 V Power dissipation Pd 1.37 W Thermal derating Kθ 13.7 mW/°C Operating temperature Topr −20 to +75 °C Storage temperature Tstg −40 to +125 °C Standard board Ta ≥ 25°C Thermal Derating Power Dissipation Pd (W) 1.5 1.37 1.0 0.685 0.5 0 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) Note: Standard board board size: 70mm × 70mm board thickness: 1.6 mm board material: glass epoxy copper pattern: 18 µm copper thickness: 0.25 mm (width) copper size: 30 mm (length/lead) Recommended Operating Condition Item Symbol Min Limits Typ Max Unit Analog supply voltage VCC 8.0 9.0 10.0 V Digital supply voltage OSC clock VDD fck 4.5 — 5.0 4 5.5 — V MHz REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 8 of 24 Condition M62465FP Electrical Characteristics (Decoder) (VCC = 9 V, VDD = 5 V, 0dB Reference = 300 mVrms/1 kHz at C-OUT unless otherwise noted. (Cch Trimmer = 0 dB)) Item Overall Circuit current Circuit current Reference voltage Input auto valance Capture range Error correction Adaptive matrix Symbol Min Limits Typ Max Unit Conditions ICC IDD Vref — — 3.5 25 25 4.0 50 50 4.5 mA mA V CPR CER — — ±5 ±4 — — dB dB Output level accuracy relative to Cch Matrix rejection relative. Headroom ∆VOL −0.5 0 0.5 dB L, R, S′ch out MR HRAM THDAM 40 17 0.05 — — 0.2 dB dB Total harmonic Distortion 25 15 — L, R, C, S′ch out L, R, C, S′ out L, R, C, S′ch out 4ch mode Signal to noise ratio SNAM — 75 0.002 80 0.05 — 95 100 — % Quiescent Quiescent Quiescent L, Rch out 2ch mode dB Rg = 0 Ω, weighted CCIR/AMR 4ch mode L, Rch out 2ch mode — — ±0.3 mVp-p measurement time = 4ch mode 40ms — — ±0.3 2ch mode Noise sequencer (0 dBd Reference is input at NR–IN when adjust to 0 dB (300 mVrms/100 Hz) at S out. Output noise level Vno −15 −12.5 −10 dB Peak noise NopAM ∆Vno Output level accuracy relative to Cch Output noise peak Vnop Modified B type noise reduction Voltage gain VGNR Decode response 1 DEC1 Decode response 2 DEC2 Decode response 3 DEC3 Decode response 4 DEC4 −0.5 0 0.5 dB — — ±550 mVp-p — −1.6 −3.0 −4.9 −6.8 9.2 −0.1 −1.5 −3.4 −5.3 — 1.4 0 −1.9 −3.8 dB dB Vin = 0 dBd, f = 100 Hz Vin = 0 dBd, f = 1.0 kHz Vin = −15 dBd, f = 1.4 kHz Vin = −20 dBd, f = 1.4 kHz Vin = −40 dBd, f = 5.0 kHz — 0.0 0.3 % Vin = 0 dBd, f = 1 kHz 15 73 — 717 78 — — — ±0.3 dB dB mVp-p −14 −37 0.6 −12 −31 1.0 −10 −25 1.4 dB dB dB Digital input = −12 Digital input = −31 THDSU — 0.05 0.2 % Vin = 0 dBd, f = 1 kHz SNSU 85 90 — dB Rg = 0 Ω weighted CCIR/AMR THDNR Total harmonic distortion Headroom HRNR Signal to noise ratio SNNR Peak noise NoPNR C, Sch trimmer Attenuation level: –12dB ATT–12dB Maximum attenuation ATTmax Trimmer step TS Surround (L+R, L−R) <MIXOUT> Total harmonic distortion Signal to noise ratio REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 9 of 24 L, R, S′ch out Measurement time = 6 s THD = 1% Rg = 0 Ω weighted CCIR/AMR Measurement time = 40 ms M62465FP Electrical Characteristics (Digital Delay) (Ta = 25°C, VCC = 9 V, VDD = 5 V, Vin = 200 mVrms, fck = 4 MHz unless otherwise noted) Item Symbol Min Limits Typ Max Unit Conditions 12.4 17.0 25.6 38.0 46.2 137.5 186.6 −3.0 — — — — — — — 15.4 20.0 28.6 41.0 49.2 147.5 196.6 0 0.3 0.3 0.5 0.6 0.7 1.5 2.0 18.4 23.0 31.6 44.0 52.2 157.5 206.6 3.0 0.6 0.6 1.0 1.2 1.4 3.0 4.0 ms See delay time control (15/24) fordelay time setting. Digital delay Delay time Td Input-output gain Output distortion Gv THD Maximum output voltage Output noise voltage Vomax No 0.7 — — — — — — — 1.0 −92 −92 −92 −90 −90 −82 −77 — −80 −80 −80 −75 −75 −67 −62 Vrms dBv 30kHz LPF, THD = 10% Td = 15.4 ms Rg = 620 Ω, Vi = 0 mVrms, Td = 20.0 ms IHF-A Td = 28.6 ms Td = 41.0 ms Td = 49.2 ms Td = 147.5 ms Td = 196.6 ms Delay volume (VOL OUT) Input-output gain Maximum attenuation Gv ATTmax 0 — 3 −70 6 −60 dB dB Volume max Delay off mode, Volume min, IHF-A REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 10 of 24 dB % 30 kHz LPF Td = 15.4 ms Td = 20.0 ms Td = 28.6 ms Td = 41.0 ms Td = 49.2 ms Td = 147.5 ms Td = 196.6 ms REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 11 of 24 + + 220 µF 4.7 MΩ + + S74 + 100 kΩ Digital noise sequencer VREF IREF 1/2 VCC + + C + 5 + 6 ST S + 7 8 + 10 10 kΩ 9 11 + 12 13 14 14 16 16 15 15 1 17 17 18 2 18 16 K SRAM 4 Test CNT DATA SCK REQ MCU interface 1 19 2 1 19 20 2 2 20 SU + Selector1 CT DVdd 1 1 µF Sout 10 µF 10 µF Cout 10 µF 10 µF Rout 10 µF Lout 10 µF 27 pF 4 MHz 1 MΩ 1 S21 22 43 CLK 21 Logic 3 R AGND + 2 + − Selector3 S' MIC L Trimmer +/− MIX 1 S + − Trimmer − 44 42 23 24 DGND AGND (5 V) (5 V) 2 25 AVdd DVss AVss 27 28 29 30 31 32 33 34 35 36 37 38 39 40 26 VOL 41 VREFD 0.1 µF 80 S + −3.2 dB ATT Selector2 45 LPF 79 78 VREFA AVcc L−R 2 77 76 75 74 L+R 2 22 kΩ 73 Servo L R C 46 A/D AVcc +9 V 22 µF 72 ATT + 10 µF 10 µF L+R L−R Selector −6.0 dB +3.2 dB 47 MOS 71 VCA Auto balance Center mode control VCA L C R Combining networks 70 BPF +9.2 dB Modified B-type NR decoder 48 D/A 22 kΩ 7.5 kΩ 0.1 µF 69 68 S' Dual-time constant and threshold switches 49 LPF Vi73 Vi72 47 kΩ 0.022 µF 0.1 µF 0.022 µF 67 0.1 µF 7.5 kΩ 0.1 µF 680 pF 0.047 µF 15 kΩ 0.22 µF 0.1 µF 0.047 µF BPF 0.1 µF 47 kΩ 0.22 µF 50 SFB 66 4.7 µF LOG difference amplifiers 0.22 µF Full wave rectifier 51 EC 0.1 µF 15 kΩ 65 + 0.1 µF 4.7 µF 52 330 kΩ 680 pF 0.22 µF 53 0.68 µF 54 0.047 µF 55 24 kΩ 0.0056 µF 56 10 µF + − + 57 Vo46 58 0.1 µF 59 Vi45 60 0.1 µF 61 Vo43 62 Vi48 0.1 µF 63 0.1 µF 64 Vi44 0.1 µF 100 kΩ 100 kΩ Vo41 Vo40 22 µF 1 µF 1 µF 0.01 µF AVdd +5 V Vo27 Vi28 0.0018 µF 0.068 µF* 0.1 µF* 0.1 µF* 0.068 µF* 0.01 µF 0.0018 µF 0.1 µF + Vi42 24 kΩ M62465FP Test Circuit 1 kΩ Vo22 Vi21 2 kΩ Vo20 2 kΩ Vo19 2 kΩ Vo18 S18 DVdd +5 V 1 µF Vi12 10 kΩ Vi10 0.1 µF Vo7 Vo6 Vo5 Vo4 Vo3 Vo2 100 µF Note: The capacitors marked with * should be of relative precision ±5% Max. M62465FP Digital Control Specifications (1) Data timing REQ t7 t4 t2 t3 t8 SCK t1 DATA 0 1 2 t5 t6 3 4 5 6 7 8 9 10 11 Notes: 1. SCK is disable when REQ is high. 2. REQ must turn to high after SCK pulse turn to high. Item Symbol Min Typ Max Unit SCK clock duration SCK “H” pulse width SCK “L” pulse width t1 t2 t3 2 0.8 0.8 — — — — — — µs µs µs REQ hold time DATA setup time DATA hold time SCK setup time REQ “H” pulse width t4 t5 t6 t7 t8 1.6 0.8 0.8 0.8 1.6 — — — — — — — — — — µs µs µs µs µs (2) Data Format BIT0 BIT1 BIT2 BIT3 ADD/SUB NOISE SEQ SELECTOR2 SELECTOR3 Cch. TRIMMER S1 S2 S3 V1 Serial Data Format Data BIT4 BIT5 BIT6 BIT7 SELECTOR1 CENTER MODE MIX LO1 LO2 LO3 Sch. TRIMMER V2 V3 V4 SFB BIT8 No use No use MOS BIT9 MIC Address BIT10 BIT11 0 0 0 1 1 0 1 1 (3) Decoder Address (BIT10, 11) = 0, 0 ADD/SUB Mode BIT0 0 1 ADD SUB NOISE SEQ Mode OFF ON BIT1 0 1 REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 12 of 24 Mode L C R S BIT2 0 0 1 1 BIT3 0 1 0 1 M62465FP SELECTOR 1 Mode PRO LOGIC BY-PASS OTHER SUR L/R MUTE Mode WIDE NORMAL PHANTOM OFF BIT4 0 0 1 1 BIT5 0 1 0 1 CENTER MODE BIT6 0 0 1 1 BIT7 0 1 0 1 SELECTOR 2 BIT0 0 0 1 1 BIT1 0 1 0 1 SELECTOR 3 BIT2 0 0 1 1 BIT3 0 1 0 1 Delay Mix Switch DMIXSW OFF ON Remarks Mixing OFF Mixing ON Address (BIT10, 11) = 0, 1 Mode S′ L+R L−R MIC Mode BNR OUT D OUT 3STEREO/MUTE BIT4 (MIX) 0 1 LO (LOGIC DATA OUT) Open Collector Mode Output data “L” Output data “H” BIT5 (LO1) 0 1 BIT6 (LO2) 0 1 BIT7 (LO3) 0 1 Address (BIT10, 11) = 1, 0 DATA 0 1 BIT0 ±0 dB −1 dB Cch. TRIMMER BIT1 BIT2 ±0 dB ±0 dB −2 dB −4 dB DATA 0 1 BIT5 ±0 dB −1 dB Sch. TRIMMER BIT6 BIT7 ±0 dB ±0 dB −2 dB −4 dB REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 13 of 24 BIT3 ±0 dB −8 dB BIT4 ±0 dB −16 dB BIT8 ±0 dB −8 dB BIT9 ±0 dB −16 dB M62465FP Volume Code ATT(dB) ±0 −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15 BIT0(5) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 BIT1(6) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BIT2(7) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C(S)ch. TRIMMER BIT3(8) BIT4(9) ATT(dB) 0 0 −16 0 0 −17 0 0 −18 0 0 −19 0 0 −20 0 0 −21 0 0 −22 0 0 −23 1 0 −24 1 0 −25 1 0 −26 1 0 −27 1 0 −28 1 0 −29 1 0 −30 1 0 −31 BIT0(5) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 BIT1(6) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BIT2(7) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BIT3(8) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BIT4(9) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (4) Delay Address (BIT10, 11) = 1, 1 BIT0(S1) 0 0 0 0 1 1 1 1 BIT1(S2) 0 0 1 1 0 0 1 1 BIT2(S3) 0 1 0 1 0 1 0 1 BIT7 (SFB) 0 1 Note: Delay Time Control DELAY TIME (Sampling frequency) Delay LPF (Cut-off frequency) 15.4 ms (1 MHz) 7.0 kHz 20.0 ms (667 kHz) 28.6 ms (500 kHz) 41.0 ms (400 kHz) 49.2 ms (333 kHz) 147.5 ms (111.1 kHz) 3.0 kHz 196.6 ms (83.3 kHz) Delay off mode (clock off) Feedback Switch SFB SW OFF ON Remarks Feedback OFF Feedback ON In surround mode only Mode Selector BIT8 (MOS) 0 1 REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 14 of 24 MODESEL SU line EC line M62465FP Microphone Mixing Switch MICMIXSW OFF ON BIT9 (MIC) 0 1 Note: Remarks Mic mixing OFF Mic mixing ON 1. Settings in power up When power is turned on, data is setting in under table by power on reset circuit. DECODER DELAY Mode Settings ADD/SUB Noise SEQ SELECTOR1 Center mode SELECTOR2 SELECTOR3 LO (LOGIC OUT) Cch. Trimmer ADD OFF PROLOGIC WIDE S′ BNR OUT “L” 0 dB, ATT (−) Sch. Trimmer 0 dB, ATT (−) Mode Delay time control Volume control Feedback switch Mode selector Delay mix switch Microphone mixing switch Settings 20.0 ms −∞ OFF SU line OFF OFF Notes: 2. The digital the noise sequencer stop when the clock is off. BIT3 (V1) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 BIT4 (V2) 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 Volume Control BIT5 (V3) 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 BIT6 (V4) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VOL Attenuation +3 dB 0 dB −2 dB −3 dB −4 dB −6 dB −8 dB −9 dB −10 dB −12 dB −15 dB −∞ −∞ −∞ −∞ 0 0 0 0 −∞ REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 15 of 24 REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 16 of 24 Pro Logic 1 3 BNROUT/ 3 Stereo 2 S' Selector Wide td = 195.5 ms Long echo BW = 3 kHz td = 20.0 ms td = 147.5 ms Short echo Option 5 step delay time (BW = 7 kHz, fck = 4 MHz) td = 28.6 ms Live Hall * Delay time can be set to 5 position (15.4, 20.0, 28.6, 41.0, td = 49.2 ms and 49.2 ms) td = 20 ms Disco –31 dB * Pro Logic decoder function is alive. For example C/S trimmer can be available. –∞ –∞ –15 dB –12 dB –10 dB –9 dB –8 dB –6 dB –4 dB –3 dB –2 dB 0 dB Bypass Bypass DOUT ADD Phantom SUB S' MIC 3 Stereo 3 Stereo OFF OFF ADD ADD S'/ BNROUT/ Wide/ ADD/ L+R/ 3 Stereo/ Normal/ SUB L–R DOUT Phantom L+R VOL ATT Other L–R SUR +3 dB — OFF ON OFF OFF SU EC SU SU OFF OFF ON/ OFF OFF ON OFF OFF ON OFF OFF S' MIC (L+R) 2 (L–R) 2 S' Digital Center ADD/ Delay Delay Mode SUB MIX SW Mode Feedback MIC MIX Input Phantom VOL OFF (0 dB) Delay VOL Phantom 0 to –31 dB 0 to –31 dB 1 dB/step 1 dB/step Sch Trimmer Normal td = 15.4 ms, 20.0 ms, 28.6 ms Digital Delay Cch Trimmer Switch Condition Normal Wide By-pass By-pass Karaoke/ echo Digital space surround Dolby Pro Logic Mode SUBMode Volume Level Feedback level can be changed by output port control (see block diagram) Note M62465FP Function Mode (Example) M62465FP Function Block Diagram By-pass Plo logic Other mute Selector1 Lout Input balance Lin Selector4 Noise sequencer Rin (L+R) 2 Rout L R C Adaptive matrix Center mode control C.Trimmer (0 to −31 dB) CT Wide normal phantom OFF ADD/SUB 3-stereo/mute S' Selector3 Selector2 Modified BNR (L−R) 2 MIC MIX MIC BNR OUT + − S.Trimmer (0 to −31 dB) DOUT MIC Dout MOS EC Digital delay MCU Interface VOL + Feedback SU − AGND 7 kHz LPF AVDD VDD (+5 V) Block Name REQ SCK DATA 4 MHz Surround filter Center mode control C.Trimmer, S.Trimmer Modified BNR LO1 LO2 LO3 GND Echo filter Input balance Noise sequencer Adaptive matrix Sout Delay mix SW VREFA AVcc (+9 V) Cout Function Revises a level error between the input Lch and Rch for optimum decoder performance. A simple noise sequencer circuit adjustment of output level. Continuously analyze the two-channel matrixes audio input to determine the direction and relative magnitude of encoded sound fields. Possible to select 4-center mode position. (WIDE, NORMAL, PHANTOM, OFF) This is the level adjustment volume of Cch and Sch. (0 to −30 dB: 1 dB/step) This block restores the signal to its original spectrum while reducing noise and certain cross talk signals in a final stage of the surround chain. ADD/SUB Select a positive phase signal or a negative phase signal with DIGITAL SPACE SURROUND MODE. Selector1 This is a selective switch to select the output signal of Lout and Rout from BY-PASS, PRO LOGIC, OTHER SUR and MUTE. This is a selective switch to select the output signal of Sout from S′, L+R, L−R and MIC. Selector2 Selector3 Selector4 Digital delay Feedback Mode sel (MOS) VOL MIC MIX Delay mix SW This is a selective switch to select the output signal of Sout from BNR out, Dout and 3STEREO/MUTE. This is a switch to connect a simple noise sequencer output to ADAPTIVE MATRIX stage for level adjustment. Make 7 kinds of delay signal s. (15.4 ms to196.6 ms) The delay function and CLK signal stop at the time of DELAY OFF MODE. This mode is for suppress bad effect of digital noise. This is a switch to select feedback mode (ON/OFF) for SURROUND MODE. This is a switch to select feedback signal from surround signal and echo signal. Control the ATT level of delay signal from 3 dB to −∞ (12-step) This is a switch to mix microphone signal to a main signal (Lch, Rch) . This is a switch to select output or not a mixed signal to DOUT pin. REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 17 of 24 M62465FP Level Diagram Dolby Pro Logic Mode Sout Gv 0 dB (300 mV) 3 dB 0 dB (300 mV) 9.2 dB VCC = 9 V VCC = 9 V VDD = 5 V Vref = 4 V Vref = 4 V Vref = 2.5 V GND Lin Input balance Rin Adaptive matrix S' −6 dB ATT −3.2 dB Digital delay Modified BNR SOUT Lout, Rout, Cout 0 dB (300 mV) Gv 3 dB VCC = 9 V Vref = 4 V Cout GND 0 dB (300 mV) Gv VCC = 9 V Vref = 4 V Lout, Rout GND Lin Rin Input balance REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 18 of 24 Adaptive matrix Center mode control Cout Lout Rout M62465FP Digital Space Surround Mode Sout Gv 0 dB (300 mV) 3 dB VCC = 9 V 0 dB (300 mV) VCC = 9 V VDD = 5 V Vref = 4 V Vref = 4 V GND Vref = 2.5 V L+R 2 L−R 2 Lin Rin ATT −3.2 dB Digital delay SOUT Selector3 Selector2 Lout, Rout 0 dB (300 mV) Gv VCC = 9 V Vref = 4 V Lout, Rout GND Lin Rin Input balance REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 19 of 24 Adaptive matrix Center mode control Lout Rout M62465FP Auto Mute Function The IC carries out auto mute function at the time of powering up, delay time setting change, and cancelling delay off mode, in order to suppress shock noise that the digital delay may produce. • At power up * Transient noise common with power up occurs. Reset time Power up Mute time Freed from resetting Freed from muting Internal delay time setting • At delay time setting change Delay signal before change Delay signal after change Mute time Instruction to change delay time Freed from muting Internal delay time change • At canceling delay off mode Mute time Canceling delay off mode Freed from muting Mute time changes depending on set (or preset) delay time. Delay time 15.4 to 49.2 ms 147.5, 196.6 ms REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 20 of 24 Mute time 123 ms 492 ms REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 21 of 24 AVcc +9 V C72 C73 + + R77 + 10 µF VREF IREF (Example) Feedback Level Control + 1/2 VCC + Selector1 + 4 + 5 6 ST S + 7 8 9 10 11 + 12 13 DVdd 14 Test CNT 15 MCU 16 17 DATA SCK REQ 18 16 K SRAM 3 C AGND + MCU interface 19 45 C21 20 44 4 MHz R21 22 43 CLK 21 Logic + 2 CT + − Selector3 46 SU 1 R Digital noise sequencer L Trimmer +/− S' MIC 0.0056 µF S + − Trimmer − 47 MIX 80 79 S + −3.2 dB ATT Selector2 ATT +3.2 dB +9.2 dB 48 42 R22 C22 23 24 25 AVdd DVss AVss 27 28 29 30 31 32 33 34 35 36 37 38 39 40 26 VOL 41 VREFD LPF 220 kΩ 78 77 VREFA AVcc L−R 2 R78 76 75 74 L R C 49 C41 A/D + + R74 Servo L+R 2 R73 C74 73 72 50 Modified B-type NR decoder 51 + R72 −6.0 dB 52 RA44 C44 D/A Rin Lin L C R S' Auto balance Center mode control VCA L+R L−R Selector 53 MOS 71 C61 VCA 70 69 Combining networks R69 54 R44 LPF C71 C64 BPF C63 68 C62 R68 C60 C68 C59 C69 C57 RA68 C58 BPF C56 67 C55 R67 C54 R66 55 C53 Dual-time constant and threshold switches 56 C52 C70 57 R51 66 58 C51 LOG difference amplifiers 59 C50 Full wave rectifier 60 EC C67 RA66 65 61 C47 SFB C66 C65 62 + 63 C49 + − + 64 R48 R47 RA45 C45 C48 C25 C27 C30 C32 C36 C39 C40 + C26 C29 C34 C35 C38 + R45 M62465FP Application Example 1 (Upper compatible for M62460FP) The example is fixed 4 V reference voltage type. AVdd +5 V R9 DGND LO3 LO2 LO1 DVdd +5 V C12 MIC in R6 C8 C6 Sout C5 Cout C3 Rout C2 Lout 47 µF C75 Note: It's recommended to remove these external parts of M62460FP. (These external parts don't affect the function of M62465FP actually.) REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 22 of 24 AVcc +9 V C72 C73 + + C75 (Example) Feedback Level Control VREF IREF 1/2 VCC + + Selector1 + 4 + 5 6 ST S + 7 8 9 10 11 + 12 13 DVdd 14 Test CNT 15 MCU 16 17 DATA SCK REQ 18 16 K SRAM 3 C AGND 19 45 C21 20 44 4 MHz R21 22 43 CLK 21 Logic + 2 CT + − MCU interface 46 SU 1 Digital noise sequencer R Trimmer Selector3 + L Trimmer +/− S' MIC 80 S + − 47 MIX 79 78 S + − −3.2 dB ATT Selector2 ATT +3.2 dB +9.2 dB 48 42 R22 C22 23 24 25 AVdd DVss AVss 27 28 29 30 31 32 33 34 35 36 37 38 39 40 26 VOL 41 VREFD LPF C79 R78 VREFA AVcc L−R 2 77 76 75 74 49 C41 A/D + + R74 73 Servo L R C L+R 2 R73 C74 72 50 Modified B-type NR decoder 51 + R72 −6.0 dB 52 RA44 C44 D/A Rin Lin L C R S' Auto balance Center mode control VCA L+R L−R Selector 53 MOS 71 C61 VCA 70 69 Combining networks R69 54 R44 LPF C71 C64 C69 C63 BPF C62 68 C60 R68 C59 C68 C57 RA68 C58 BPF C56 67 C55 R67 C54 R66 55 C53 Dual-time constant and threshold switches 56 C52 C70 57 R51 66 58 C51 LOG difference amplifiers 59 C50 Full wave rectifier 60 SFB C66 65 61 C47 EC C67 RA66 C65 62 + 63 C49 + − + 64 R48 R47 RA45 C45 C48 C25 C27 C30 C32 C36 C39 C40 + C26 C29 C34 C35 C38 + R45 M62465FP Application Example 2 The example is 1/2VCC reference voltage type. AVdd +5 V R9 C2 C1 DGND LO3 LO2 LO1 DVdd +5 V C12 MIC in R6 C8 C6 Sout C5 Cout C3 Rout Lout M62465FP External Parts List Parts No. C1 C2 C3 C5 C6 C8 C12 C21 C22 C25 C26 C27 C29 C30 C32 C34 C35 C36 C38 C39 C40 C41 C44 C45 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 Values 47 10 10 10 10 0.1 1 27 27 100 22 1 0.01 0.0018 0.068 0.1 0.1 0.068 0.01 0.0018 0.1 0.1 1200 470 680 0.1 0.0056 0.047 0.68 0.22 0.22 4.7 4.7 0.22 0.22 0.1 0.047 0.047 0.1 0.1 0.022 Unit µF µF µF µF µF µF µF pF pF µF µF µF µF µF µF µF µF µF µF µF µF µF pF pF pF µF µF µF µF µF µF µF µF µF µF µF µF µF µF µF µF 0.022 µF REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 23 of 24 Tol. 10% 5% 5% 5% 5% 5% 5% 5% 5% 5% 10% 5% 5% 10% 10% 10% 20% 20% 10% 10% 20% 5% 5% 20% 20% 5% 5% Parts No. C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C77 C79 R6 R9 R21 R22 RA44 RA45 R44 R45 R47 R48 R51 R66 RA66 R67 R68 RA68 R69 R72 R73 R74 R78 Values 0.1 680 0.1 680 0.1 0.1 0.1 10 10 22 100 220 220 Unit µF pF µF pF µF µF µF µF µF µF µF µF µF 10 20 1 1 51 51 Vol Vol 24 24 330 47 15 7.5 47 15 7.5 22 22 4.7 100 kΩ kΩ MΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ MΩ kΩ Tol. 20% 5% 5% 5% 5% 5% 5% 20% 5% 5% 10% 5% 5% 5% 5% 5% 5% 10% 1% M62465FP Package Dimensions JEITA Package Code P-QFP80-14x20-0.80 RENESAS Code PRQP0080GB-A Previous Code 80P6N-A MASS[Typ.] 1.6g HD *1 D 64 41 65 HE NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. ZE *2 E 40 Reference Symbol 80 25 1 ZD 24 D E A2 HD HE A A1 bp c c Index mark A A2 F *3 y bp L A1 e Detail F REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 24 of 24 e y ZD ZE L Dimension in Millimeters Min Nom Max 19.8 20.0 20.2 13.8 14.0 14.2 2.8 22.5 22.8 23.1 16.5 16.8 17.1 3.05 0.1 0.2 0 0.3 0.35 0.45 0.13 0.15 0.2 0° 10° 0.65 0.8 0.95 0.10 0.8 1.0 0.4 0.6 0.8 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. 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