LSK489 LOW NOISE, LOW CAPACITANCE MONOLITHIC DUAL N-CHANNEL JFET FEATURES ULTRA LOW NOISE en = 1.8nV/√Hz LOW INPUT CAPACITANCE Features Ciss = 4pF Benefits Reduced Noise due to process improvement Monolithic Design High slew rate Low offset/drift voltage Low gate leakage lgss & lg High CMRR 102 dB Applications Tight differential voltage match vs. current Improved op amp speed settling time accuracy Minimum Input Error trimming error voltage Lower intermodulation distortion Wide band differential Amps High speed temperature compensated single ended input amplifier amps High speed comparators Impedance Converters Description The LSK 489 series of high performance monolithic dual JFETs features extremely low noise, tight offset voltage and low drift over temperature specifications, and is targeted for use in a wide range or precision instrumentation applications. This series has a wide selection of offset and drift specifications. The SST series SO-8 package provided ease of manufacturing and the symmetrical pinout prevents improper orientation. The SO-8 package is available with tape and reel options for compatibility with automatic assembly methods. (See packaging data) ABSOLUTE MAXIMUM RATINGS @ 25 °C (unless otherwise stated) 1 SOIC-A Maximum Temperatures Storage Temperature -55 to +150°C Junction Operating Temperature -55 to +150°C TO-71 TOP VIEW Maximum Power Dissipation, TA = 25°C Continuous Power Dissipation, per side Power Dissipation, total 4 5 300mW 500mW Maximum Currents Gate Forward Current IG(F) = 10mA SOT-23 TOP VIEW • Maximum Voltages Gate to Source VGSO = 60V Gate to Drain VGDO = 60V * For equivalent single version, see LSK186 Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201151 05/07/2013 Rev#A26 ECN# LSK489 MATCHING CHARACTERISTICS @ 25°C (unless otherwise stated) SYMBOL CHARACTERISTIC VGS1 - VGS2 Differential Gate to Source Cutoff Voltage IDSS1 IDSS2 CMRR SYMBOL Gate to Source Saturation Current Ratio COMMON MODE REJECTION RATIO -20 log│∆VGS1-2/∆VDS│ CHARACTERISTIC MIN TYP 0.9 MAX UNITS 20 mV 1.0 CONDITIONS VDS = 10V, ID = 1mA VDS = 10V, VGS = 0V 95 102 dB VDS = 10V to 20V, ID = 200µA MIN TYP MAX UNITS CONDITIONS en Noise Voltage 1.8 2.0 nV/√Hz VDS = 15V, ID = 2.0mA, f = 1kHz, NBW = 1Hz en Noise Voltage 2.8 3.5 nV/√Hz VDS = 15V, ID = 2.0mA, f = 10Hz, NBW = 1Hz 4 8 pF 3 pF MAX UNITS CISS Common Source Input Capacitance CRSS Common Source Reverse Transfer Capacitance VDS = 15V, ID = 500µA, f = 1MHz ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise stated) SYMBOL BVGSS CHARACTERISTIC MIN Gate to Source Breakdown Voltage -60 V(BR)G1 - G2 Gate to Gate Breakdown Voltage ±30 VGS(OFF) Gate to Source Pinch-off Voltage -1.5 VGS Gate to Source Operating Voltage -0.5 Drain to Source Saturation Current 2.5 2 IDSS IG Gate Operating Current ±45 -3.5 Gate to Source Leakage Current Gfs Full Conductance Transconductance 1500 Gfs Transconductance 1000 GOS Full Output Conductance GOS Output Conductance NF Noise Figure CONDITIONS V VDS = 0, ID = -1nA V IG= ±1µA, ID=IS=0 A (Open Circuit) V VDS = 15V, ID = 1nA VDS = 15V, ID = 500µA -3.5 V 5 15 mA VDG = 15V, VGS = 0 -2 -25 pA VDG = 15V, ID = 200µA -10 nA -100 pA VDG = -15V, VDS = 0 µS VDG = 15V, VGS = 0, f = 1kHz µS VDG = 15V, ID = 500µA 35 µS VDG = 15V, VGS = 0 2 µS VDG = 15V, ID = 200µA 0.5 dB VDS = 15V, VGS = 0, RG = 10MΩ, f = 100Hz, NBW = 6Hz -0.8 IGSS Linear Integrated Systems TYP 1500 0.2 TA = 125°C • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201151 05/07/2013 Rev#A26 ECN# LSK489 PACKAGE DIMENSIONS SOT-23 Six Lead 0.95 1.90 0.210 0.170 1 6 2 5 3 4 0.35 0.50 2.80 3.00 1.50 1.75 2.60 3.00 0.90 1.30 0.09 0.20 0.00 0.15 0.10 0.60 DIMENSIONS IN MILLIMETERS DIMENSIONS IN INCHES All dimensions in inches. 1. Absolute maximum ratings are limiting values above which serviceability may be impaired. 2. Pulse width ≤2ms. 3. All MIN/TYP/MAX Limits are absolute values. Negative signs indicate electrical polarity only. 4. Derate 2.4 mW/°C above 25°C. 5. Derate 4 mW/°C above 25°C. Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems. Linear Integrated Systems (LIS) is a 25-year-old, third-generation precision semiconductor company providing high-quality discrete components. Expertise brought to LIS is based on processes and products developed at Amelco, Union Carbide, Intersil and Micro Power Systems by company President John H. Hall. Hall, a protégé of Silicon Valley legend Dr. Jean Hoerni, was the director of IC Development at Union Carbide, co-founder and vice president of R&D at Intersil, and founder/president of Micro Power Systems. Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201151 05/07/2013 Rev#A26 ECN# LSK489 Typical Characteristics Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201151 05/07/2013 Rev#A26 ECN# LSK489 Typical Characteristics (Cont’d) Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201151 05/07/2013 Rev#A26 ECN# LSK489 Typical Characteristics (Cont’d) Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201151 05/07/2013 Rev#A26 ECN# LSK489