HD74LS390 Dual Decade Counters REJ03D0485-0400 Rev.4.00 May 10, 2006 This circuit contains eight master-slave flip-flops and additional gating to implement two individual four-bit counters. The HD74LS390 incorporates dual divide-by-two and divide-by-five counters, which can be used to implement cycle lengths equal to any whole and / or cumulative multiples of 2 and / or 5 up to divide-by-100. When connected as a biquinary counter, the separate divide-by-two circuit can be used to provide symmetry (a square wave) at the final output stage. Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74LS390P DILP-16 pin PRDP0016AE-B (DP-16FV) P — PRSP0016DH-B FP (FP-16DAV) Note: Please consult the sales office for the above package availability. HD74LS390FPEL SOP-16 pin (JEITA) EL (2,000 pcs/reel) Pin Arrangement 1A 1 16 VCC 1Clear 2 15 2A 14 2Clear 13 2QA Output 12 2B 1QA Output 3 1B 4 CLR 1QA 1A 1B 1QB 5 1QB CLR 2QA 2A 2B Outputs 1QC 6 1QC 2QB 11 2QB 1QD 7 1QD 2QC 10 2QC GND 8 2QD 9 2QD (Top view) Rev.4.00, May 10, 2006, page 1 of 5 Outputs HD74LS390 Function Table BCD Count Sequence (Notes 1) Count 0 1 2 3 4 5 6 7 8 9 Outputs QD L L L L L L L L H H QC L L L L H H H H L L QA L QD L QB L L H H L L H H L L QA L H L H L H L H L H QC L QB L L H H L L L H H L H L H L L H L H L Bi-quinary (Notes 2) Count 0 Outputs 1 L L 2 L L 3 L L 4 L H 5 H L 6 H L 7 H L 8 H L 9 H H Notes: 1. Output QA is connected to input B for BCD count. 2. Output QD is connected to input A for bi-quinary count. 3. H; high level, L; low level, X; irrelevant Rev.4.00, May 10, 2006, page 2 of 5 HD74LS390 Block Diagram (1/2) QA QA T A Clear Inputs QB QB B T QB Outputs Clear QC QC T QC Clear QD T QD QD Clear Clear Input Absolute Maximum Ratings Item Symbol Ratings Unit VCC 7 V Clear VIN 7 A, B VIN 5.5 Supply voltage Input voltage Power dissipation V PT 400 mW Storage temperature Tstg –65 to +150 °C Operating temperature Topr –20 to +75 °C Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Recommended Operating Conditions Item Supply voltage Output current Operating temperature Count frequency A input B input Symbol Min Typ VCC 4.75 5.00 5.25 V IOH — — –400 µA B input IOL — — 8 mA –20 25 75 °C ƒcount 0 — 25 0 — 20 20 — — tw 25 — — 20 — — tsu 25↓ — — Clear Clear setup time Rev.4.00, May 10, 2006, page 3 of 5 Unit Topr A input Pulse width Max MHz ns ns HD74LS390 Electrical Characteristics (Ta = –20 to +75 °C) Item Input voltage Symbol VIH VIL min. 2.0 — typ.* — — max. — 0.7 Unit V V VOH 2.7 — — V IIH — — — — — — — — 0.4 0.5 20 100 µA VCC = 5.25 V, VI = 2.7 V IIL — — — — — — 200 –0.4 –1.6 mA VCC = 5.25 V, VI = 0.4 V II — — — — — — –2.4 0.1 0.2 mA IOS ICC — –20 — — — 15 0.4 –100 26 mA mA Output voltage VOL Clear Input A Input B Clear Input A Input B Clear Input A Input current Input B Short-circuit output current Supply current V Condition VCC = 4.75 V, VIH = 2 V, VIL = 0.7 V, IOH = –400 µA IOL = 4 mA VCC = 4.75 V, IOL = 8 mA VIH = 2 V, VIL = 0.7 V VI = 7 V VI = 5.5 V VCC = 5.25 V VCC = 5.25 V VCC = 5.25 V Input clamp voltage VIK — — –1.5 V VCC = 4.75 V, IIN = –18 mA Notes: * VCC = 5 V, Ta = 25°C ** ICC is measured with all outputs open, both Clear inputs grounded following momentary connection to 4.5 V, and all other inputs grounded. Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Symbol Maximum count frequency ƒmax Propagation delay time tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL Inputs A B Outputs QA QB min. 25 20 — — — — typ. 35 30 12 13 37 39 max. — — 20 20 60 60 A QA A QC B Unit QB — — 13 14 21 21 ns B QC — — 24 26 39 39 ns B QD Clear Any — — — 13 14 24 21 21 39 Condition MHz ns ns CL = 15 pF, RL = 2 kΩ ns ns Note: Refer to Test Circuit and Waveform of the Common Item "TTL Common Matter (Document No.: REJ27D00050100)". Rev.4.00, May 10, 2006, page 4 of 5 HD74LS390 Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g D 9 E 16 1 8 b3 0.89 A1 A Z L Reference Symbol θ bp e e1 D E A A1 bp b3 c θ e Z L c e1 ( Ni/Pd/Au plating ) JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV Dimension in Millimeters Min Nom Max 7.62 19.2 20.32 6.3 7.4 5.06 0.51 0.40 0.48 0.56 1.30 0.19 0.25 0.31 0° 15° 2.29 2.54 2.79 1.12 2.54 MASS[Typ.] 0.24g D F 16 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 9 c HE *2 E bp Index mark Terminal cross section ( Ni/Pd/Au plating ) 1 Z 8 e *3 bp x Reference Dimension in Millimeters Symbol M A L1 A1 θ y L Detail F Rev.4.00, May 10, 2006, page 5 of 5 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 10.06 10.5 5.50 0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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