HD74LS164 8-Bit Parallel-Out Serial-in Shift Register REJ03D0448–0200 Rev.2.00 Feb.18.2005 This 8-bit shift register features gated serial inputs and an asynchronous clear. The gated serial inputs (A and B) permit complete control over incoming data as a low at either (or both) input(s) inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input which will them determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but only information meeting the setup requirements will be entered. Clocking occurs on the low-to-high-level transition of the clock input. Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74LS164P DILP-14 pin PRDP0014AB-B (DP-14AV) P — HD74LS164FPEL SOP-14 pin (JEITA) PRSP0014DF-B (FP-14DAV) FP EL (2,000 pcs/reel) HD74LS164RPEL SOP-14 pin (JEDEC) PRSP0014DE-A (FP-14DNV) RP EL (2,500 pcs/reel) Note: Please consult the sales office for the above package availability. Pin Arrangement A Serial Inputs 1 14 VCC A B 2 B QH 13 QH QA 3 QA QG 12 QG QB 4 QB QF 11 QF QC 5 QC QE 10 QE QD 6 QD CLR 9 Clear GND 7 8 Clock Outputs Outputs CK (Top view) Rev.2.00, Feb.18.2005, page 1 of 8 HD74LS164 Function Table Inputs Clear L H H H H Clock X L ↑ ↑ ↑ A X X H L X B X X H X L Outputs QB……QH L QB0 QAn QAn QAn QA L QA0 H L L L QH0 QGn QGn QGn Notes: 1. H; high level, L; low level, X; irrelevant 2. ↑; transition from low to high level 3. QA0, QB0, QH0; the level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established. 4. QAn, QGn; the level of QA or QG before the most-recent ↑ transition of the clock; indicates a one-bit shift. Block Diagram Clear Clock Serial Inputs A B Clear Clear Clear Clear Clear Clear Clear Clear R QA R QB R QC R QD R QE R QF R QG R QH CK CK CK CK CK S QB S QC S QD S QE S QF CK S QA Output QA Output QB Output QC Output QD Output QE CK CK S QG Output QF S QH Output QG Output QH Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage VCC 7 V Input voltage VIN 7 V PT 400 mW Tstg –65 to +150 °C Power dissipation Storage temperature Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Recommended Operating Conditions Item Supply voltage Output current Operating temperature Symbol Min Typ Max Unit VCC 4.75 5.00 5.25 V IOH — — –400 µA IOL — — 8 mA Topr –20 25 75 °C Clock frequency ƒclock 0 — 25 MHz Clock pulse width tw (CK) 20 — — ns Clear pulse width tw (CLR) 20 — — ns Data setup time tsu 15 — — ns Data hold time th 5 — — ns Rev.2.00, Feb.18.2005, page 2 of 8 HD74LS164 Electrical Characteristics (Ta = –20 to +75 °C) Item Input voltage Symbol VIH VIL min. 2.0 — typ.* — — max. — 0.8 Unit V V VOH 2.7 — — V — — — — — — — — — — 0.4 0.5 20 –0.4 0.1 Output voltage VOL Input current IIH IIL II V µA mA mA Condition VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = –400 µA IOL = 4 mA VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V IOL = 8 mA VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V, VI = 7 V Short-circuit output –20 — –100 mA VCC = 5.25 V IOS current Supply current** ICC — 16 27 mA VCC = 5.25 V Input clamp voltage VIK — — –1.5 V VCC = 4.75 V, IIN = –18 mA Notes: * VCC = 5 V, Ta = 25°C ** ICC is measured with outputs open, serial inputs grounded, the clock input at 2.4 V, and a momentary grounded, then 4.5 V applied to clear. Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Maximum clock frequency Propagation delay time Symbol ƒmax tPHL tPLH tPHL Rev.2.00, Feb.18.2005, page 3 of 8 Inputs Outputs Clear Clock Clock Q Q Q min. 25 — — — typ. 36 24 17 21 max. — 36 27 32 Unit MHz ns ns ns Condition CL = 15 pF, RL = 2 kΩ HD74LS164 Typical Clear, Shift, and Clear Sequences Clear Serial Inputs A B Clock QA QB QC QD Outputs QE QF QG QH Clear Rev.2.00, Feb.18.2005, page 4 of 8 Clear HD74LS164 Testing Method Test Circuit VCC Output 4.5V RL Load circuit 1 QA CK CL A Input QB See Testing Table P.G. Zout = 50Ω Output B Input QC Output QD Same as Load Circuit 1. Same as Load Circuit 1. Same as Load Circuit 1. Output P.G. Zout = 50Ω QH CLR Notes: Output Same as Load Circuit 1. GND 1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H). Testing Table Item ƒmax tPLH tPHL From input to output Clear→Q CK→Q Inputs Outputs CLR CK A B QA QB QC QD QE QF QG QH 4.5V IN 4.5V IN IN IN IN IN IN 4.5V 4.5V 4.5V OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Rev.2.00, Feb.18.2005, page 5 of 8 HD74LS164 Waveform tw (CLR) tTHL ≥ 20ns tTLH 10% 10% 90% 1.3V 3V Clear 90% 1.3V 0V tw (CK) tTHL tTLH 90% 90% 1.3V ≥ 20ns Clock 1.3V 3V 1.3V tsu th 10% 10% tsu 0V th tTHL 90% A 1.3V 10% tPHL QA 90% 1.3V 10% tTLH 1.3V tPLH 3V 1.3V 1.3V 0V tPHL 1.3V VOH 1.3V VOL Notes: 1. Input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, (Clock, Clear), PRR = 500 kHz (A or B) 2. QA output is illustrated. Relationship of serial input A and B data to other Q outputs is illustrated in the timing chart. Rev.2.00, Feb.18.2005, page 6 of 8 HD74LS164 Package Dimensions JEITA Package Code P-DIP14-6.3x19.2-2.54 RENESAS Code PRDP0014AB-B MASS[Typ.] 0.97g Previous Code DP-14AV D 8 E 14 1 7 b3 Z A1 A Reference Symbol Nom e1 7.62 D 19.2 E 6.3 L A θ bp e Dimension in Millimeters Min e1 A1 0.51 bp 0.40 JEITA Package Code P-SOP14-5.5x10.06-1.27 RENESAS Code PRSP0014DF-B *1 Previous Code FP-14DAV D 0.48 0.56 c 0.19 θ 0° e 2.29 0.25 0.31 2.54 2.79 15° 2.39 L 2.54 MASS[Typ.] 0.23g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 14 7.4 1.30 Z ( Ni/Pd/Au plating ) 20.32 5.06 b3 c Max 8 c HE *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) 1 Z *3 Nom Max D 10.06 10.5 E 5.50 A2 7 e A1 bp Dimension in Millimeters Min x M 0.00 0.10 0.20 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 A L1 2.20 bp b1 c A c A1 θ y L Detail F 1 θ 0° HE 7.50 e 1.27 x 0.12 y 0.15 1.42 Z L L Rev.2.00, Feb.18.2005, page 7 of 8 8° 0.50 1 0.70 1.15 0.90 HD74LS164 JEITA Package Code P-SOP14-3.95x8.65-1.27 RENESAS Code PRSP0014DE-A *1 MASS[Typ.] 0.13g Previous Code FP-14DNV NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F D 14 8 c *2 Index mark HE E bp Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) Dimension in Millimeters Min Nom Max D 8.65 9.05 E 3.95 A2 A1 7 1 Z e *3 bp x M 0.14 A c A1 θ L Detail F 0.34 0.40 0.46 0.15 0.20 0.25 6.10 6.20 b1 c y 0.25 1.75 bp L1 1 θ 0° HE 5.80 e 8° 1.27 0.25 x y 0.15 Z 0.635 L L Rev.2.00, Feb.18.2005, page 8 of 8 0.10 A 0.40 1 0.60 1.08 1.27 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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