RENESAS HD74LS174RPEL

HD74LS174 / HD74LS175
Hex / Quadruple D-type Flip-Flops (with clear)
REJ03D0451–0300
Rev.3.00
Jul.15.2005
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct
clear input, and the HD74LS175 features complementary outputs from each flip-flops. Information at the D inputs
meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock
triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse.
When the clock input is at either the high or low level, the D input signal has no effect at the outputs.
Features
• Ordering Information
• HD74LS174
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LS174P
DILP-16 pin
PRDP0016AE-B
(DP-16FV)
P
—
HD74LS174FPEL
SOP-16 pin (JEITA)
PRSP0016DH-B
(FP-16DAV)
FP
EL (2,000 pcs/reel)
HD74LS174RPEL
SOP-16 pin (JEDEC)
PRSP0016DG-A
(FP-16DNV)
RP
EL (2,500 pcs/reel)
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LS175P
DILP-16 pin
PRDP0016AE-B
(DP-16FV)
P
—
HD74LS175FPEL
SOP-16 pin (JEITA)
PRSP0016DH-B
(FP-16DAV)
FP
EL (2,000 pcs/reel)
• HD74LS175
PRSP0016DG-A
RP
(FP-16DNV)
Note: Please consult the sales office for the above package availability.
HD74LS175RPEL
SOP-16 pin (JEDEC)
Rev.3.00, Jul.15.2005, page 1 of 8
EL (2,500 pcs/reel)
HD74LS174 / HD74LS175
Pin Arrangement
HD74LS174
Clear
1
1Q
2
1D
3
2D
4
2Q
5
3D
6
3Q
7
GND
8
CLR
D CK
Q
CLR
CK D
D CK
CLR
Q
CK D
CLR
Q
D CK
CLR
Q
CK D
CLR
Q
Q
HD74LS175
16
VCC
Clear
1
16
VCC
15
6Q
1Q
2
15
4Q
14
6D
1Q
3
14
4Q
13
5D
1D
4
13
4D
12
5Q
2D
5
12
3D
11
4D
2Q
6
11
3Q
10
4Q
2Q
7
10
3Q
9
Clock
GND
8
9
Clock
(Top view)
Q CLR
CK
Q
D
Q
D
CK
Q CLR
CLR Q
CK
D
Q
Q
D
CK
CLR Q
(Top view)
Function Table
Clear
L
H
H
H
Notes: 1.
2.
3.
4.
Inputs
Clock
X
↑
↑
L
Outputs
D
X
H
L
X
Q
L
H
L
Q0
H; high level, L; low level, X; irrelevant
↑; transition from low to high level
Q0; the level of Q before the indicated steady-state input conditions were established.
Q is applied to HD74LS175 only.
Rev.3.00, Jul.15.2005, page 2 of 8
Q
H
L
H
Q0
HD74LS174 / HD74LS175
Block Diagram
HD74LS174
1D
2D
HD74LS175
Q
1Q
CK
CK
Clear
Q
Clear
1Q
D
Q
2Q
Q
Clear
2Q
D
D
Q
Q
1Q
D
1D
2Q
2D
CK
CK
Clear
Data
Inputs
Data
Inputs
3D
D
Q
Outputs
3Q
CK
Outputs
D
3D
Clear
4D
D
Q
Q
3Q
Q
Clear
3Q
D
Q
4Q
Q
Clear
4Q
CK
4Q
CK
4D
Clear
5D
CK
Clock
D
Q
5Q
Clear
CK
Clear
6D
D
Q
6Q
CK
Clock
Clear
Clear
Absolute Maximum Ratings
Symbol
Ratings
Unit
Supply voltage
Item
VCC
7
V
Input voltage
VIN
7
V
Power dissipation
PT
400
mW
Tstg
–65 to +150
°C
Storage temperature
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Rev.3.00, Jul.15.2005, page 3 of 8
HD74LS174 / HD74LS175
Recommended Operating Conditions
• HD74LS174
Item
Supply voltage
Output current
Operating temperature
Symbol
Min
Typ
Max
Unit
VCC
4.75
5.00
5.25
V
IOH
—
—
–400
µA
IOL
—
—
8
mA
Topr
–20
25
75
°C
Clock frequency
ƒclock
0
—
30
MHz
Clock pulse width
tw (CK)
20
—
—
ns
Clear pulse width
Setup time
tw (CLR)
20
—
—
ns
Data input
tsu (data)
20
—
—
ns
Clear inactivestate
tsu (CLR)
25
—
—
ns
th (data)
5
—
—
ns
Data hold time
• HD74LS175
Item
Symbol
Min
Typ
Max
Unit
VCC
4.75
5.00
5.25
V
IOH
—
—
–400
µA
IOL
—
—
8
mA
Operating temperature
Topr
–20
25
75
°C
Clock frequency
ƒclock
0
—
30
MHz
Clock pulse width
tw (CK)
20
—
—
ns
Clear pulse width
tw (CLR)
20
—
—
ns
Data input
tsu (data)
20
—
—
ns
Clear inactivestate
tsu (CLR)
25
—
—
ns
th (data)
5
—
—
ns
Supply voltage
Output current
Setup time
Data hold time
Electrical Characteristics
(Ta = –20 to +75 °C)
Item
Input voltage
Symbol
VIH
VIL
min.
2.0
—
typ.*
—
—
max.
—
0.8
Unit
V
V
VOH
2.7
—
—
V
—
—
—
—
—
0.5
0.4
20
–0.4
0.1
µA
mA
mA
VCC = 5.25 V, VI = 2.7 V
VCC = 5.25 V, VI = 0.4 V
VCC = 5.25 V, VI = 7 V
Output voltage
Condition
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V,
IOH = –400 µA
IOL = 8 mA
VCC = 4.75 V, VIH = 2 V,
VIL = 0.8 V
IOL = 4 mA
II
—
—
—
—
—
Short-circuit output
current
IOS
–20
—
–100
mA
VCC = 5.25 V
Supply current**
ICC
—
—
—
16
11
—
26
18
–1.5
mA
HD74LS174
VCC = 5.25 V
HD74LS175
VCC = 4.75 V, IIN = –18 mA
VOL
Input current
IIH
IIL
V
Input clamp voltage
VIK
V
Notes: * VCC = 5 V, Ta = 25°C
** With all outputs open and 4.5 V applied to all data and cleat inputs, ICC is measured after a momentary
grounded, then 4.5 V, is applied to clock.
Rev.3.00, Jul.15.2005, page 4 of 8
HD74LS174 / HD74LS175
Switching Characteristics
• HD74LS174
(VCC = 5 V, Ta = 25°C)
Item
Maximum clock frequency
Propagation delay time
Symbol
ƒmax
tPHL
tPLH
tPHL
Inputs
Clock
Clear
Clock
Clock
Outputs
Q
Q
Q
Q
min.
30
—
—
—
typ.
40
23
20
21
max.
—
35
30
30
Inputs
Clock
Outputs
Q, Q
Q
Q
Q, Q
Q, Q
min.
30
—
—
—
—
typ.
40
16
20
13
16
max.
—
25
30
25
25
VCC
Out
Unit
MHz
ns
Condition
CL = 15 pF,
RL = 2 kΩ
• HD74LS175
(VCC = 5 V, Ta = 25°C)
Item
Maximum clock frequency
Propagation delay time
Symbol
ƒmax
tPLH
tPHL
tPLH
tPHL
Clear
Clock
Clock
Unit
MHz
ns
Condition
CL = 15 pF,
RL = 2 kΩ
Testing Method
Test Circuit
Load circuit 1
In
RL
P.G.
Zout = 50Ω
Q
P.G.
Zout = 50Ω
Notes:
See Testing Table
In
D
CL
CK
Out
CLR
Q
Same as Load Circuit 1.
1. Test is put into the each flip-flop.
2. CL includes probe and jig capacitance.
3. All diodes are 1S2074(H).
Testing Table
Item
ƒmax
tPLH
tPHL
From input to output
CK→Q, Q*
CK→Q, Q*
CLR→Q, Q*
Note: *. HD74LS175 only
Rev.3.00, Jul.15.2005, page 5 of 8
CLR
4.5 V
4.5 V
Inputs
CK
IN
IN
D
IN
IN
Outputs
IN
IN
4.5 V
Q
Q
OUT
OUT
HD74LS174 / HD74LS175
Waveform
tTLH
tTHL
3V
tw (CLR)
CLR
1.3V
1.3V
0V
tTLH
tTHL
tsu (CLR) t
w (CK)
tw (CK)
3V
CK
90% 90%
10%
1.3V 1.3V
1.3V 1.3V
0V
10%
tsu
th
tsu
th
3V
D
1.3V
1.3V
1.3V
0V
tPHL
tPLH
tPHL
VOH
Q
1.3V
1.3V
1.3V
VOL
tPLH
tPHL
tPLH
VOH
Q
(HD74LS175 only)
Note:
1.3V
1.3V
1.3V
Input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, and: for ƒmax, tTLH = tTHL ≤ 2.5 ns.
Rev.3.00, Jul.15.2005, page 6 of 8
VOL
HD74LS174 / HD74LS175
Package Dimensions
JEITA Package Code
P-DIP16-6.3x19.2-2.54
RENESAS Code
PRDP0016AE-B
MASS[Typ.]
1.05g
Previous Code
DP-16FV
D
9
E
16
1
8
b3
0.89
Z
A1
A
Reference
Symbol
L
e
Nom
θ
c
e1
D
19.2
E
6.3
JEITA Package Code
P-SOP16-5.5x10.06-1.27
RENESAS Code
PRSP0016DH-B
*1
Previous Code
FP-16DAV
7.4
A1
0.51
b
p
0.40
b
3
0.48
0.56
1.30
c
0.19
θ
0°
e
2.29
0.25
0.31
2.54
2.79
15°
1.12
L
2.54
MASS[Typ.]
0.24g
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
D
F
16
20.32
5.06
Z
( Ni/Pd/Au plating )
Max
7.62
1
A
bp
e
Dimension in Millimeters
Min
9
c
HE
*2
E
bp
Index mark
Reference
Symbol
Terminal cross section
( Ni/Pd/Au plating )
1
Z
*3
bp
Nom
D
10.06
E
5.50
Max
10.5
A2
8
e
Dimension in Millimeters
Min
x
A1
M
0.00
0.10
0.20
0.34
0.40
0.46
0.15
0.20
0.25
7.80
8.00
A
L1
2.20
bp
b1
c
A
c
A1
θ
y
L
Detail F
1
θ
0°
HE
7.50
e
1.27
x
0.12
y
0.15
0.80
Z
L
L
Rev.3.00, Jul.15.2005, page 7 of 8
8°
0.50
1
0.70
1.15
0.90
HD74LS174 / HD74LS175
JEITA Package Code
P-SOP16-3.95x9.9-1.27
RENESAS Code
PRSP0016DG-A
*1
Previous Code
FP-16DNV
MASS[Typ.]
0.15g
D
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
F
16
9
c
*2
Index mark
HE
E
bp
Reference
Symbol
Terminal cross section
( Ni/Pd/Au plating )
Dimension in Millimeters
Min
Nom
Max
D
9.90
10.30
E
3.95
A2
8
1
Z
e
*3
bp
x
A1
0.10
0.14
0.25
0.34
0.40
0.46
0.15
0.20
0.25
6.10
6.20
1.75
A
M
L1
bp
b1
c
A
c
A1
θ
L
y
Detail F
1
θ
0°
HE
5.80
1.27
e
x
0.25
y
0.15
0.635
Z
0.40
L
L
Rev.3.00, Jul.15.2005, page 8 of 8
8°
1
0.60
1.08
1.27
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