HD74LS166A 8-bit Shift Register REJ03D0450-0400 Rev.4.00 May 10, 2006 The inputs are buffered to lower the drive requirements to one series 74 or 74LS standard load, respectively. Input clamping diodes minimize switching transients and simplify system design. This parallel in or serial-in, serial-out shift register has a complexity of 77 equivalent gates on a monolithic chip. This device features gated clock inputs and an overriding clear input. The parallel-in or serial-in modes are established by the shift / load input. When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside) data inputs are enabled and synchronous loading occurs on the next clock pulse, during parallel loading, serial data flow is inhibited. This, of course, allows the system clock to be free running and the register can be stopped on command with the other clock input. The clock-inhibit input should be changed to the high level only while the clock input is high. A buffered, direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero. Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74LS166AP DILP-16 pin PRDP0016AE-B (DP-16FV) P — Pin Arrangement Serial Input 1 16 VCC A 2 15 B 3 14 Shift/ Load Parallel Input H C 4 13 Output QH D 5 12 G Clock Inhibit 6 11 F Clock 7 10 E GND 8 9 Clear Parallel Inputs (Top view) Rev.4.00, May 10, 2006, page 1 of 7 Parallel Inputs HD74LS166A Function Table Inputs Clear Shift Load Clock Inhibit Clock Serial L H H H H H X X L H H X X L L L L H X L ↑ ↑ ↑ ↑ X X X H L X Parallel A…H X X a…h X X X Internal outputs QA L QA0 a H L QA0 QB L QB0 b QAn QAn QB0 Output QH L QH0 h QGn QGn QH0 Notes: 1. H; high level, L; low level, X; irrelevant 2. ↑; transition from low to high level 3. a to h; the level of steady-state input at inputs A to H respectively 4. QA0 to QH0; the level of QA to QH, respectively, before the indicated steady-state input conditions were established. 5. QAn to QGn; the level of QA to QG, respectively, before the most recent ↑ transition of the clock. Rev.4.00, May 10, 2006, page 2 of 7 HD74LS166A Block Diagram Clear Serial Input Shift/Load A R CK S QA B R CK S QB C R CK S QC D R CK S QD E R CK S QE F R CK S QF G R CK S QG H Clock R CK S Clock Inhibit QH Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage VCC 7 V Input voltage VIN 7 V Power dissipation PT 400 mW Tstg –65 to +150 °C Storage temperature Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Rev.4.00, May 10, 2006, page 3 of 7 HD74LS166A Recommended Operating Conditions Item Symbol Min Typ Max Unit VCC 4.75 5.00 5.25 V IOH — — –400 µA IOL — — 8 mA Operating temperature Topr –20 25 75 °C Clock frequency ƒclock 0 — 25 MHz Clock and clear pulse width tw 20 — — ns Mode control setup time tsu 30 — — ns Data setup time tsu 20 — — ns Hold time th 0 — — ns Supply voltage Output current Electrical Characteristics (Ta = –20 to +75 °C) Item Input voltage Symbol VIH VIL min. 2.0 — typ.* — — max. — 0.8 Unit V V VOH 2.7 — — V II — — — — — — — — — — 0.4 0.5 20 –0.4 0.1 µA mA mA VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V, VI = 7 V IOS –20 — –100 mA VCC = 5.25 V ICC VIK — — 20 — 32 –1.5 mA V VCC = 5.25 V VCC = 4.75 V, IIN = –18 mA Output voltage VOL Input current Short-circuit output current Supply current** Input clamp voltage IIH IIL V Condition VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = –400 µA IOL = 4 mA VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V IOL = 8 mA Notes: * VCC = 5 V, Ta = 25°C ** With the outputs open, 4.5 V applied to the serial input and all other inputs except the clock grounded, ICC is measured after a momentary ground, then 4.5 V, is applied to clock. Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Maximum clock frequency Propagation delay time Symbol ƒmax tPHL tPHL tPLH Rev.4.00, May 10, 2006, page 4 of 7 Inputs Clear Clock min. 25 — 7 5 typ. 35 19 14 11 max. — 30 25 20 Unit MHz ns ns ns Condition CL = 15 pF, RL = 2 kΩ HD74LS166A Testing Method Test Circuit VCC 4.5V P.G. Zout = 50Ω Notes: See Testing Table Input Clear Serial Input Shift/Load A QH B C D E F G H Clock Clock Inhibit RL Output CL 1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H). Testing table Data inputs Data H Serial-in Rev.4.00, May 10, 2006, page 5 of 7 Shift / Load 0V 4.5 V Output QH QH Bit time tn + 1 tn + 8 HD74LS166A Waveform tw (Clear) 3V Clear Input 1.3V 1.3V 0V tn tn + 1 tn + 1 tn 3V Clock Input 1.3V 1.3V 1.3V 1.3V 0V tsu tw (Clock) th tsu th 3V Data Input 1.3V 1.3V 1.3V 1.3V 0V tPHL tPLH tPHL VOH Output QH 1.3V 1.3V 1.3V VOL Notes: 1. Input pulse; ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle 50% Clock input; tw ≥ 20 ns Clear inpu; tw ≥ 20 ns, th = 10 ns, when testing ƒmax, vary the clock PRR. 2. Propagation delay time (tPLH and tPHL) are measured at tn + 1. Proper shifting of data is verified at tn + 8 with a functional test. 3. tn; bit time before clocking transition. tn + 1; bit time after one clocking transition. tn + 8; bit time after eight clocking transition. Typical Clear, Shift, Load, Inhibit, and Shift Sequences Clock Clock Inhibit Clear Serial Input Shift / Load A H L B C Parallel Inputs H L D E H L F G H H H Output QH H Clear Rev.4.00, May 10, 2006, page 6 of 7 Serial Shift Load Inhibit H L H L H L Serial Shift H L HD74LS166A Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g D 9 E 16 1 8 b3 0.89 A1 A Z L Reference Symbol e bp θ c e1 ( Ni/Pd/Au plating ) Rev.4.00, May 10, 2006, page 7 of 7 e1 D E A A1 bp b3 c θ e Z L Dimension in Millimeters Min Nom Max 7.62 19.2 20.32 6.3 7.4 5.06 0.51 0.40 0.48 0.56 1.30 0.19 0.25 0.31 0° 15° 2.29 2.54 2.79 1.12 2.54 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. 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