MX23L6454 64M-BIT Low Voltage, Serial MASK ROM with 50MHz SPI Bus Interface GENERAL DESCRIPTION The MX23L6454 is a 64Mbit (8M Bytes) Serial Mask ROM accessed by a high speed Serial peripheral interface. KEY FEATURES • • • • • Operating voltage ranges from 3.0V to 3.6V Serial Peripferal Interface compatible-mode 0 and 3 High performance : "fast read" mode at 50MHz and "normal read" at 20MHz Low power consumption : 8mA for fast read mode or 4mA for normal read mode Low standby current : 15uA PIN CONFIGURATIONS PIN DESCRIPTION SYMBOL SCLK SI SO CS# HOLD# 16-PIN SOP (300 mil) HOLD# VCC NC NC NC NC CS# SO 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SCLK SI NC NC NC NC VSS NC VCC VSS DESCRIPTION Serial Clock Serial Data Input Serial Data Output Chip Select Hold to pause the device without deselecting the device Power Supply Ground Note: 1. NC=No Connection 2. See page 15 for package dimensions, and how to identify pin-1. ORDER INFORMATION Part No. MX23L6454MC-20G Speed 20ns Package 16-SOP P/N: PM1127 1 Remark Pb-free REV. 1.8, NOV. 09, 2007 MX23L6454 MEMORY ORGANIZATION The memory is organized as: - 8M bytes BLOCK DIAGRAM Address Generator X-Decoder SI CS# Data Register Mode Logic Memory Array Y-Decoder State Machine Sense Amplifier Output Buffer HOLD# SO SCLK Clock Generator P/N: PM1127 2 REV. 1.8, NOV. 09, 2007 MX23L6454 DEVICE OPERATION Stand-by Mode When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps in standby mode until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. Active Mode When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS# rising edge. SPI Feature Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The difference of SPI mode 0 and mode 3 is shown as Figure 1. Figure 1. SPI Modes Supported CPOL CPHA shift in (SPI mode 0) 0 0 SCLK (SPI mode 3) 1 1 SCLK SI shift out MSB SO MSB Note: CPOL indicates clock polarity of SPI master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which SPI mode is supported. P/N: PM1127 3 REV. 1.8, NOV. 09, 2007 MX23L6454 HOLD FEATURE HOLD# pin signal goes low to hold any serial communications with the device. The operation of HOLD requires Chip Select(CS#) to stay low and starts on falling edge of HOLD# pin signal while Serial Clock (SCLK) signal keeps to be low (if Serial Clock signal does not keep to be low, HOLD operation will not start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal keeps to be low( if Serial Clock signal does not keep to be low, HOLD operation will not end until Serial Clock being low), Please refer to Figure 2. Figure 2. Hold Condition Operation CS# SCLK HOLD# Hold Condition (standard) Hold Condition (non-standard) The Serial Data Output (SO) is a high impedance, that both Serial Data Input (SI) and Serial Clock (SCLK) are "don't care" during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start the communication with chip, the HOLD# must be kept as high and CS# must be kept as low. P/N: PM1127 4 REV. 1.8, NOV. 09, 2007 MX23L6454 Table 1. COMMAND DEFINITION Command Set RDID 1st byte 9Fh 03h (read data) Fast Read (fast read data) 3rd byte 4th byte 5th byte 6th byte Manufacturer Memory type Memory ID ID density ID AD1 AD2 AD3 Data out Note 1 (A23-A16) (A15-A8) (A7-A0) (D7-D0) AD1 AD2 AD3 Dummy Data out (A23-A16) (A15-A8) (A7-A0) Cycle (D7-D0) Code (read ID) READ 2nd byte 0Bh Notes: 1. n bytes are read out until CS# goes high. 2. It is not recommended to adopt any code not in the above command definition table. P/N: PM1127 5 REV. 1.8, NOV. 09, 2007 MX23L6454 COMMAND DESCRIPTION (1) Read Identification (RDID) The RDID instruction is for reading the manufacturer ID of 1-byte and is followed by Device ID of 2-byte. The MXIC Manufacturer ID is C2h, the memory type ID is 05h as the first-byte device ID, and the individual device ID of second-byte ID is:17h. The sequence of issuing RDID instruction is: CS# goes low-> sending RDID instruction code -> 24-bits ID data is sent out on SO -> to end RDID operation which can use CS# to be high at any time during data out. (see Figure 3) When CS# goes high, the device is at standby stage. Table of ID Definitions: RDID manufacturer ID memory type memory density 9Fh C2h 05h 17h (2) Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: CS# goes low-> sending READ instruction code-> 3-byte address is sent on SI -> data out on SO-> to end READ operation which can use CS# to be high at any time during data out. (see Figure 4) (3) Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing FAST_READ instruction is: CS# goes low-> send FAST_READ instruction code-> 3-byte address is sent on SI-> 1-dummy byte address is sent on SI->data out on SO-> to end FAST_READ operation which can use CS# to be high at any time during data out. (see Figure 5) While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. P/N: PM1127 6 REV. 1.8, NOV. 09, 2007 MX23L6454 Figure 3. Read Identification (RDID) Sequence (Command 9F) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 SCLK Command SI 9F Manufacturer Identification High-Z SO 7 6 5 3 2 1 Device Identification 0 15 14 13 MSB 3 2 1 0 MSB Figure 4. Read Data Bytes (READ) Sequence (Command 03) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK command SI 03 24-Bit Address 23 22 21 3 2 1 0 MSB Data Out 1 High-Z 7 SO 6 5 4 3 2 Data Out 2 1 0 7 MSB P/N: PM1127 7 REV. 1.8, NOV. 09, 2007 MX23L6454 Figure 5. Read at Higher Speed (FAST_READ) Sequence (Command 0B) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI SO 24 BIT ADDRESS 23 22 21 0B 3 2 1 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Byte SI 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 SO 7 6 5 4 3 2 1 0 7 MSB MSB P/N: PM1127 8 6 5 4 3 2 1 0 7 MSB REV. 1.8, NOV. 09, 2007 MX23L6454 ELECTRICAL SPECIFICATIONS NOTICE: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage of the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions in long period of time may affect reliability. 2. Specifications contained within the following Table 2 and 3 are subjects to change. 3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Figure 3,4. ABSOLUTE MAXIMUM RATINGS RATING VALUE Ambient Operating Temperature 0°C to 70°C Storage Temperature -65°C to 150°C Applied Input Voltage -0.6V to 4.0V Applied Output Voltage -0.6V to 4.0V VCC to Ground Potential -0.6V to 4.0V Figure 7. Maximum Positive Overshoot Waveform Figure 6.Maximum Negative Overshoot Waveform 20ns 20ns 20ns Vss Vcc + 2.0V Vss - 2.0V Vcc 20ns 20ns 20ns CAPACITANCE TA = 25°°C, f = 20 MHz SYMBOL PARAMETER CIN COUT MIN. MAX. UNIT Input Capacitance 6 pF VIN = 0V Output Capacitance 8 pF VOUT = 0V P/N: PM1127 9 TYP CONDITIONS REV. 1.8, NOV. 09, 2007 MX23L6454 Figure 8. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL Input timing referance level 0.8VCC 0.7VCC 0.3VCC Output timing referance level AC Measurement Level 0.5VCC 0.2VCC Note: The rise and fall time of input pulse < 5ns Figure 9. OUTPUT LOADING DEVICE UNDER TEST 2.7K ohm +3.3V CL 6.2K ohm DIODES=IN3064 OR EQUIVALENT The condition "CL=30pF" includes jig capacitance P/N: PM1127 10 REV. 1.8, NOV. 09, 2007 MX23L6454 Table 2. DC CHARACTERISTICS (Temperature = 0°°C to 70°°C, VCC = 3.0V ~ 3.6V) SYMBOL PARAMETER ISB1 VCC Standby NOTES MIN. TYP 1 MAX. UNITS 15 uA Current ICC1 VCC Read TEST CONDITIONS VIN = VCC or GND CS# = VCC 1 8 mA f=50MHz SCLK=0.1VCC/0.9VCC, SO=Open 4 mA f=20MHz SCLK=0.1VCC/0.9VCC, SO=Open ILI Input Load ±2 1 uA Current ILO Output Leakage VCC = VCC Max VIN = VCC or GND ±2 1 uA Current VCC = VCC Max VIN = VCC or GND VIL Input Low Voltage -0.5 VOL Output Low Voltage VIH Input High Voltage 0.7VCC VOH Output High Voltage VCC-0.2 0.3VCC V 0.4 V VCC+0.4 V V P/N: PM1127 11 IOL = 1.6mA IOH = -100uA REV. 1.8, NOV. 09, 2007 MX23L6454 Table 3. AC CHARACTERISTICS (Temperature = 0°°C to 70°°C, VCC = 3.0V ~ 3.6V) Symbol Alt. Parameter Min. fSCLK fC Clock Frequency for FAST_READ, RDID D.C. Commands Typ. Max. Unit 50 MHz (Condition:30pF) fRSCLK fR tCH(1) tCLH Clock High Time 9 ns tCL(1) tCLL Clock Low Time 9 ns tSLCH tCSS CS# Active Setup Time (relative to SCLK) 5 ns CS# Not Active Hold Time (relative to SCLK) 5 ns tCHSL Clock Frequency for READ Commands D.C. 20 MHz tDVCH tDSU Data In Setup Time 2 ns tCHDX tDH Data In Hold Time 5 ns tCHSH CS# Active Hold Time (relative to SCLK) 5 ns tSHCH CS# Not Active Setup Time (relative to SCLK) 5 ns 100 ns tSHSL tCSH CS# Deselect Time tSHQZ(2) tDIS Output Disable Time 8 ns tCLQV tV Clock Low to Output Valid 8 ns tCLQX tHO Output Hold Time 0 ns tCLCH(2) Clock Rise Time (3) (peak to peak) 0.1 V/ns tCHCL(2) Clock Fall Time (3) (peak to peak) 0.1 V/ns tHHQX(2) tLZ HOLD to Output Low-Z 8 ns tHLQZ(2) tHZ HOLD# to Output High-Z 8 ns tHLCH HOLD# Setup Time (relative to SCLK) 5 ns tCHHH HOLD# Hold Time (relative to SCLK) 5 ns tHHCH HOLD Setup Time (relative to SCLK) 5 ns tCHHL HOLD Hold Time (relative to SCLK) 5 ns Notes: (1). tCH + tCL must be greater than or equal to 1/ fC (2). The values in the table are guaranteed by characterization, not 100% tested in production. (3). Indicated as a slew rate. P/N: PM1127 12 REV. 1.8, NOV. 09, 2007 MX23L6454 Figure 10. Input Timing tSHSL CS# tCHSL tSLCH tCHSH tSHCH SCLK tDVCH tCHCL tCHDX tCLCH LSB MSB SI High-Z SO Figure 11. Output Timing CS# tCH SCLK tCLQV tCLQX tCL tCLQV tSHQZ tCLQX LSB SO tQLQH tQHQL SI ADDR.LSB IN P/N: PM1127 13 REV. 1.8, NOV. 09, 2007 MX23L6454 Figure 12. Hold Timing CS# tHLCH tCHHL tHHCH SCLK tCHHH tHLQZ tHHQX SO HOLD# * SI is "don't care" during HOLD operation. P/N: PM1127 14 REV. 1.8, NOV. 09, 2007 MX23L6454 PACKAGE INFORMATION P/N: PM1127 15 REV. 1.8, NOV. 09, 2007 MX23L6454 REVISION HISTORY Revision 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Description 1. Removed "Preliminary" on page 1 1. Added "Industrial Grade" 1. Added "Read Identification (RDID)" information 1. Modified Table 2. Read Identification (RDID) Data-Out Sequence 1. Modified memory type & memory capacity 1. Modified Table 9. AC Characteristics 1. Modified supply voltage from 2.7~3.6V to 3.0~3.6V 1. Added statement 1. Tightened maximum standby current from 50uA to 15uA 2. Changed format arrangement P/N: PM1127 16 Page P1 P1,11 P7 P7 P7 P14 P1,12 P19 P1,11 All Date MAR/02/2005 MAR/09/2005 SEP/23/2005 SEP/27/2005 OCT/21/2005 NOV/03/2005 DEC/05/2005 NOV/07/2006 NOV/09/2007 REV. 1.8, NOV. 09, 2007 MX23L6454 Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. Macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of Macronix's products in the prohibited applications. MACRONIX INTERNATIONAL CO., LTD. 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