RENESAS M37274EFSP

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI MICROCOMPUTERS
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M37274EFSP
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
DESCRIPTION
The M3727EFSP is a single-chip microcomputer designed with CMOS
silicon gate technology. It is housed in a 52-pin shrink plastic molded
DIP.
In addition to their simple instruction sets, the ROM, RAM and I/O
addresses are placed on the same memory map to enable easy programming.
The M3727EFSP has a OSD function and a data slicer function, so it
is useful for a channel selection system for TV with a closed caption
decoder.
FEATURES
• Number of basic instructions ..................................................... 71
• Memory size
•
•
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•
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ROM ....................................................... 60 K bytes
RAM ........................................................ 1024 bytes
ROM correction memory ............................. 64 bytes
ROM for OSD ....................................... 11072 bytes
RAM for OSD .......................................... 1920 bytes
Minimum instruction execution time
......................................... 0.5 µs (at 8 MHz oscillation frequency)
Power source voltage ................................................... 5 V ± 10 %
Subroutine nesting ............................................. 128 levels (Max.)
Interrupts ....................................................... 18 types, 16 vectors
8-bit timers .................................................................................. 6
Programmable I/O ports (Ports P0, P1, P2, P30, P31) .............. 26
Input ports (Ports P40–P46, P63, P64, P70–P72) ...................... 12
Output ports (Ports P52–P55) ...................................................... 4
12 V withstand ports .................................................................... 7
LED drive ports ........................................................................... 2
Serial I/O ............................................................ 8-bit ✕ 1 channel
Multi-master I2C-BUS interface ................................ 1 (2 systems)
A-D converter (8-bit resolution) .................................... 6 channels
PWM output circuit ......................................... 14-bit ✕ 1, 8-bit ✕ 7
Power dissipation
In high-speed mode .......................................................... 165mW
(at VCC = 5.5V, 8MHz oscillation frequency, CRT on, and Data
slicer on)
In low-speed mode ........................................................... 0.33mW
(at VCC = 5.5V, 32kHz oscillation frequency)
Data slicer
ROM correction function
• OSD function
Display characters ............................... 40 characters ✕ 16 lines
Kinds of characters ..................................................... 256 kinds
(In EXOSD mode, they can be combined with 16 kinds of extra
fonts)
Character display area ........................ CC mode : 16 ✕ 26 dots
OSD mode : 16 ✕ 20 dots
EXOSD mode : 16 ✕ 26 dots
Kinds of character sizes ............................... CC mode : 2 types
OSD mode : 14 types
EXOSD mode : 6 types
Kinds of character background colors
CC mode : 7 kinds (a character unit)
OSD mode : 7 kinds (a character unit)
EXOSD mode : 5 kinds (a character unit)
It can be specified by a screen unit (maximum 7 kinds).
Extra font coloring, raster coloring, border coloring
Kinds of character colors ............... CC mode : 7 kinds (R, G, B)
OSD mode : 7 kinds (R, G, B)
EXOSD mode : 5 kinds (R, G, B)
Display position
Horizontal ................................................................ 256 levels
Vertical .................................................................. 1024 levels
Attribute ...................... CC mode : smooth italic, underline, flash
OSD mode : border
EXOSD mode : border,
extra font (16 kinds)
Automatic solid space function
Window function
Dual layer OSD function
APPLICATION
TV with a closed caption decoder
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
PIN CONFIGURATION (TOP VIEW)
HSYNC
1
52
P52/R
VSYNC
2
51
3
50
P41/INT2
4
49
P55/OUT1
P42/TIM2
5
48
P04/PWM0
P43/TIM3
6
47
P05/PWM1
P24/AD3
7
46
P06/PWM2
P25/AD2
8
45
P26/AD1
9
44
P07/PWM3
P20
P27/AD5
P00/PWM4
10
43
P21
42
P22
P01/PWM5
12
41
P02/PWM6
P17/SIN
P44/INT1
P45/SOUT
13
38
P23
P10/OUT2
P11/SCL1
P12/SCL2
16
37
P13/SDA1
P46/SCLK
AVCC
17
36
18
35
P14/SDA2
P15
HLF/AD6
19
34
P72/RVCO
20
33
P71/VHOLD
21
32
P70/CVIN
CNV SS
XIN
22
31
P30
P31
23
30
RESET
24
29
XOUT
VSS
25
28
P64/OSC2/XCOUT
P63/OSC1/XCIN
26
27
VCC
11
14
15
M37274EFSP
P40/AD4
P53/G
P54/B
40
39
Outline 52P4B
2
P16/INT3
P03/DA
14 34 35 36 37 38 39 40
I/O port P1
32 31
Processor
status
register
PS (8)
I/O ports
P30, P31
P1 (8)
Multi-master
I2C-BUS interface
SDA2
SDA1
SCL2
SCL1
Y (8)
X (8)
TIM3
TIM2
23
P0 (8)
14bit
PWM
Stack
pointer
S (8)
I/O port P2
I/O port P0
22
8-bit
PWM circuit
Instruction
register (8)
Instruction
decoder
29
P5 (4)
ROM
correction
function
49 50 51 52
Output port P5
CRT circuit
28
17 16 15 6 5 4 3
P6 (2)
A-D converter
Control signal
19
Input ports P6 3, P64
Clock input for OSD/ Clock output for OSD/
sub-clock input sub-clock output
OSC1 OSC2
Input ports P4 0–P46
P4 (7)
Timer 6
T6 (8)
Timer 5
T5 (8)
Timer 4
T4 (8)
Timer 3
T3 (8)
Timer 2
T2 (8)
Timer 1
T1 (8)
20
Data slicer
21
VHOLD
HLF
RVCO
CV IN
Pins for data slicer
Input ports P7 0–P72
Timer count source
selection circuit
P7 (3)
SI/O (8)
10 9 8 7 41 42 43 44 45 46 47 48 33 13 12 11
P2 (8)
A-D
converter
26
VSS CNV SS
ROM
60 K bytes
Index
register
PC L (8)
PC H (8)
27
Index
register
Program
counter
18
Progam
counter
30
Reset input
RESET AVCC VCC
Data bus
RAM
1024 bytes
Accumulator
A (8)
Address bus
8-bit
arithmetic
and
logical unit
P3 (2)
25
Clock
generating
circuit
24
OUT2
INT3
XIN XOUT
Clock input Clock output
SIN
SCLK
SOUT
FUNCTIONAL BLOCK DIAGRAM of M37274EFSP
INT1
INT2
2
1
Sync
signal input
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HSYNC
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PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
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MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
3
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
FUNCTIONS
Parameter
Number of basic instructions
Functions
71
0.5 µs (the minimum instruction execution time, at 8 MHz oscillation frequency)
Instruction execution time
Clock frequency
Memory size
8 MHz (maximum)
ROM
60 K bytes
RAM
1024 bytes
ROM correction memory
64 bytes
11072 bytes
OSD ROM
1920 bytes
OSD RAM
Input/Output ports
P00–P02,
P04–P07
I/O
7-bit ✕ 1 (N-channel open-drain output structure, can be used as 8-bit
PWM output pins)
P03
I/O
1-bit ✕ 1
(CMOS input/output structure, can be used as 14-bit PWM output pin)
P10, P15–P17
I/O
4-bit ✕ 1 (CMOS input/output structure, can be used as OSD output pin,
INT input pin, serial input pin)
P11–P14
I/O
4-bit ✕ 1 (N-channel open-drain output structure, can be used as multimaster I2C-BUS interface)
P2
I/O
8-bit ✕ 1 (CMOS input/output structure, can be used as A-D input pins)
I/O
Input
2-bit ✕ 1 (CMOS input/output structure)
P40–P44
P45, P46
Input
2-bit ✕ 1 (N-channel open-drain output structure when serial I/O is used,
can be used as serial I/O pins)
P52–P55
Output
P30, P31
4
5-bit ✕ 1 (can be used as A-D input pins, INT input pins, external clock
input pins)
4-bit ✕ 1 (CMOS output structure, can be used as OSD output)
P63
Input
1-bit ✕ 1 (can be used as sub-clock input pin, OSD clock input pin)
P64
Input
1-bit ✕ 1 (CMOS output structure when LC is oscillating, can be used as
sub-clock output pin, OSD clock output pin)
P70–P72
Input
3-bit ✕ 1 (can be used as data slicer input/output)
Serial I/O
8-bit ✕ 1
Multi-master I2C-BUS interface
1
A-D converter
6 channels (8-bit resolution)
PWM output circuit
14-bit ✕ 1, 8-bit ✕ 7
Timers
8-bit timer ✕ 6
Subroutine nesting
128 levels (maximum)
Interrupt
External interrupt ✕ 3, Internal timer interrupt ✕ 6, Serial I/O interrupt ✕ 1,
OSD interrupt ✕ 1, Multi-master I 2 C-BUS interface interrupt ✕ 1,
Data slicer interrupt ✕ 1, f(XIN)/4092 interrupt ✕ 1, VSYNC interrupt ✕ 1, AD conversion interrupt ✕ 1, BRK instruction interrupt ✕ 1
Clock generating circuit
2 built-in circuits (externally connected to a ceramic resonator or a quartzcrystal oscillator)
Data slicer
Built in
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
FUNCTIONS (continued)
Parameter
Number of display characters
OSD function
Character display area
Functions
40 characters ✕ 16 lines
CC mode: 16 ✕ 26 dots (dot structure: 16 ✕ 20 dots)
OSD mode: 16 ✕ 20 dots
EXOSD mode: 16 ✕ 26 dots
Kinds of characters
256 kinds
(In EXOSDmode, they can be combined with 16 kinds of extra fonts)
Kinds of character sizes
CC mode: 2 kinds
OSD mode: 14 kinds
EXOSD mode: 6 kinds
Kinds of character colors
CC mode: 7 kinds (R, G, B)
OSD mode: 7 kinds (R, G, B)
EXOSD mode: 5 kinds (R, G, B)
Display position (horizontal, vertical)
Power source voltage
Power dissipation
5 V ± 10 %
In high-speed OSD ON Data slicer ON
mode
OSD OFF Data slicer OFF
In low-speed
mode
In stop mode
256 levels (horizontal) ✕ 1024 levels (vertical)
OSD OFF Data slicer OFF
165 mW typ. (at oscillation frequency f(XIN) = 8 MHz, fOSC = 13 MHz)
82.5 mW typ. (at oscillation frequency f(XIN) = 8 MHz)
0.33mW typ. (at oscillation frequency f(XCIN ) = 32 kHz, f(XIN) = stopped)
0.055 mW (maximum)
Operating temperature range
–10 °C to 70 °C
Device structure
CMOS silicon gate process
Package
52-pin shrink plastic molded DIP
5
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
PIN DESCRIPTION
Pin
Name
VCC,
AVCC,
VSS
Power source
CNVSS
CNVSS
Input/
Output
Functions
Apply voltage of 5 V ± 10 % (typical) to VCC and AVCC, and 0 V to VSS.
Connected to VSS.
_____
RESET
Reset input
Input
To enter the reset state, the reset input pin must be kept at a “L” for 2 µs or more (under
normal VCC conditions).
If more time is needed for the quartz-crystal oscillator to stabilize, this “L” condition should
be maintained for the required time.
XIN
Clock input
Input
XOUT
Clock output
This chip has an internal clock generating circuit. To control generating frequency, an
external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and
XOUT. If an external clock is used, the clock source should be connected to the XIN pin and
the XOUT pin should be left open.
P00/PWM4–
P02/PWM6,
P03/DA,
P04/PWM0–
P07/PWM3
I/O port P0
P10/OUT2,
P11/SCL1,
P12/SCL2,
P13/SDA1,
P14/SDA2,
P15,
P16/INT3,
P17/SIN
Output
I/O
Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually
programmed as input or output. At reset, this port is set to input mode. The output structure
of P03 is CMOS output, that of P00–P02 and P04–P07 are N-channel open-drain output.
See notes at end of Table for full details of port P0 functions.
DA output
Output
Pin P03 is also used as 14-bit PWM output pin DA. The output structure is CMOS output.
8-bit PWM output
Output
Pins P00–P02 and P04–P07 are also used as PWM output pins PWM4–PWM6 and PWM0–
PWM3 respectively. The output structure is N-channel open-drain output.
I/O port P1
I/O
Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure of P10 and P15–P17 is CMOS output, that of P11–P14 is N-channel open-drain
output.
OSD output
Output
Pin P10 is also used as OSD output pin OUT2. The output structure is CMOS output.
Multi-master
I2C-BUS interface
External interrupt
input
Output
Pin P11 is used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master I2CBUS interface is used. The output structure is N-channel open-drain output.
Serial I/O data
input
Input
Pin P16 is also used as external interrupt input pin INT3.
Input
Pin P17 is also used as serial I/O data input pin SIN.
Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output.
P20–P23
P24/AD3–
P26/AD1,
P27/AD5
I/O port P2
P30, P31
I/O port P3
P40/AD4,
P41/INT2,
P42/TIM2,
P43/TIM3,
P44/INT1,
P45/SOUT,
P46/SCLK
Input port P4
Input
Analog input
Input
Pin P40 is also used as analog input pin AD4.
External interrupt
input
Input
Pins P41, P44 are also used as external interrupt input pins INT2, INT1.
External clock input
Input
Pins P42 and P43 are also used as external clock input pins TIM2, TIM3 respectively.
Analog input
Serial I/O data
output
Serial I/O
synchronous clock
input/output
P52/R,P53/G, Output port P5
P54/B,
P55/OUT1
OSD output
6
I/O
Input
I/O
Pins P24–P26, P27 are also used as analog input pins AD3–AD1, AD5 respectively.
Ports P30 and P31 are 2-bit I/O ports and have basically the same functions as port P0.
The output structure is CMOS output.
Ports P40–P46 are a 7-bit input port.
Output
Pin P45 is used as serial I/O data output pin SOUT. The output structure is N-channel opendrain output.
I/O
Pin P46 is used as serial I/O synchronous clock input/output pin SCLK. The output structure
is N-channel open-drain output.
Output
Ports P52–P55 are 4-bit output ports. The output structure is CMOS output.
Output
Pins P52–P55 are also used as OSD output pins R, G, B, OUT1 respectively.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
PIN DESCRIPTION (continued)
Pin
Name
P63/OSC1/ Input port
XCIN,
Clock input for OSD
P64/OSC2/
Clock output for OSD
XCOUT
Sub-clock output
Sub-clock input
P70/CVIN, Input port P7
P71/VHOLD,
Input for data slicer
P72/RVCO
Input/output for
data slicer
Input/
Output
Functions
Input
Ports P63 and P64 are 2-bit input port.
Input
Pin P63 is also used as OSD clock input pin OSC1.
Output
Pin P64 is also used as OSD clock output pin OSC2. The output structure is CMOS output.
Output
Pin P64 is also used as sub-clock output pin XCOUT. The output structure is CMOS output.
Input
Pin P63 is also used as sub-clock input pin XCIN.
Input
Ports P70–P72 are 3-bit input port.
Input
Pins P70, P71 are also used as data slicer input pins CVIN, VHOLD respectively. When
using data slicer, input composite video signal through a capacitor. Connect a capacitor
between VHOLD and VSS.
I/O
Pins P72 pin is also used as input/output pin for data slicer RVCO. When using data slicer,
connect a resistor between RVCO and VSS.
When using data slicer, connect a filter using of a capacitor and a resistor between HLF
and VSS.
HLF/AD6
HSYNC
Analog input
HSYNC input
Input
Input
This is an analog input pin AD6.
This is a horizontal synchronous signal input for OSD.
VSYNC
VSYNC input
Input
This is a vertical synchronous signal input for OSD.
Note : As shown in the memory map (Figure 5), port P0 is accessed as a memory at address 00C016 of zero page. Port P0 has the port P0
direction register (address 00C116 of zero page) which can be used to program each bit as an input (“0”) or an output (“1”). The pins
programmed as “1” in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are
programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the
output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the
output “L” voltage has risen, for example, because a light emitting diode was directly driven. The input pins float, so the values of the pins
can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Ports P0 3, P10, P15–P1 7, P2, P30, P31
Direction register
CMOS output
Data bus
Port latch
Ports P03, P10, P15–P17,
P2, P30, P31
Note : Each port is also used as follows :
P03/DA
P10 : OUT2
P16 : INT3
P17 : SIN
P24–P26 : AD3–AD1
P27 : AD5
Ports P0 0–P02, P04–P0 7
N-channel open-drain output
Direction register
Ports P00–P02, P04–P07
Data bus
Port latch
Note : Each port is also used as follows :
P0 0–P02 : PWM4–PWM6
P04–P07 : PWM0–PWM3
Ports P1 1–P14
N-channel open-drain output
Direction register
Port P11-P14
Data bus
Fig. 1. I/O Pin Block Diagram (1)
8
Port latch
Note : Each port is also used as follows :
P11 : SCL1
P12 : SCL2
P13 : SDA1
P14 : SDA2
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
SOUT, SCLK
N-channel open-drain output
Direction register
Ports P45, P46
Note : Each pin is also used
as follows :
P45 : SOUT
P46 : SCLK
Data bus
HSYNC, VSYNC
P52–P55
Schmidt input
Internal circuit
CMOS output
HSYNC, VSYNC
Internal circuit
P52–P55
Note : Each port is also used
as follows :
P52 : R P54 : B
P53 : G P55 : OUT1
Ports P40–P4 4
Input
Data bus
Ports P40–P44
Note : Each port is also used as below :
P40 : AD4
P41 : INT2
P42 : TIM2
P43 : TIM3
P44 : INT1
Fig. 2. I/O Pin Block Diagram (2)
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
CPU Mode Register
The M37274EFSP uses the standard 740 Family instruction set. Refer
to the table of 740 Family addressing modes and machine instructions or the SERIES 740 <Software> User’s Manual for details on
the instruction set.
Machine-resident 740 Family instructions are as follows:
The FST, SLW instruction cannot be used.
The MUL, DIV, WIT and STP instructions can be used.
The CPU mode register contains the stack page selection bit and
internal system clock selection bit. The CPU mode register is allocated at address 00FB16.
CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
1 1
0 0
CPU mode register (CPUM) (CM) [Address FB16]
B
Name
Processor
mode bits
0, 1
(CM0, CM1)
2
Stack page selection
bit (CM2) (See note)
Functions
RW
1
RW
1
RW
0: LOW drive
1: HIGH drive
1
RW
0: Oscillating
1: Stopped
0
RW
0: X IN–XOUT selected
(high-speed mode)
1: X CIN–XCOUT selected
(high-speed mode)
0
RW
0
0
1
1
0: Single-chip mode
1:
0:
Not available
1:
0: 0 page
1: 1 page
3, 4 Fix these bits to “1.”
5 XCOUT drivability
selection bit (CM5)
6 Main Clock (X IN–XOUT)
stop bit
(CM6)
7
Internal system clock
selection bit
(CM7)
Note: This bit is set to “1” after the reset release.
Fig. 3. CPU Mode Register
10
After reset R W
0
b1 b0
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
MEMORY
Special Function Register (SFR) Area
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
The special function register (SFR) area in the zero page contains
control registers such as I/O ports and timers.
Zero Page
ROM
The 256 bytes from addresses 000016 to 00FF16 are called the zero
page area. The internal RAM and the special function registers (SFR)
are allocated to this area.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
ROM is used for storing user programs as well as the interrupt vector
area.
Special Page
RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
RAM for OSD
RAM for display is used for specifying the character codes and colors to display.
ROM for OSD
The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.
ROM Correction Memory (RAM)
ROM for display is used for storing character data.
This is used as the program area for ROM correction.
000016
10000 16
Not used
10800 16
RAM
(1024 bytes)
00C0 16
00FF16
010016
Zero page
SFR1 area
020016
024816
SFR2 area
155FF 16
Not used
02C0 16
02FF16
030016
Not used
ROM correction memory
Block 1 : addresses 02C0 16 to 02DF 16
Block 2 : addresses 02E0 16 to 02FF 16
18000 16
ROM for OSD
(11072 bytes)
053F16
Not used
RAM for OSD (Note)
(1920 bytes)
080016
0FF716
Not used
100016
ROM
(60 K bytes)
1E41F 16
Not used
FF0016
FFDE16
FFFF16
1FFFF 16
Interrupt vector area
Special page
Note : Refer to Table 13. Contents of OSD RAM.
Fig. 4. Memory map
11
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
■ SFR1 area (addresses C0 16 to DF16)
< Bit allocation >
:
Name
< State immediately after reset >
0 : “0” immediately after reset
Function bit
:
1 : “1” immediately after reset
: No function bit
? : Indeterminate immediately
after reset
0 : Fix to this bit to “0”
(do not write to “1”)
1 : Fix to this bit to “1”
(do not write to “0”)
Address
Register
Bit allocation
State immediately after reset
b7
C016
C116
C216
C316
C416
C516
C616
C716
C816
C916
CA16
CB16
CC16
CD16
CE16
CF16
D016
D116
D216
D316
D416
D516
D616
D716
D816
D916
DA16
DB16
DC16
DD16
DE16
DF16
b0 b7
Port P0 direction register (D0)
Port P1 (P1)
Port P1 direction register (D1)
Port P2 (P2)
Port P2 direction register (D2)
Port P3 (P3)
Port P3 direction register (D3)
P6IM T3SC
Port P4 (P4)
Port P4 direction register (D4)
0
P46D P45D
Port P5 (P5)
OSD port control register (PF)
Port P6 (P6)
Port P7 (P7)
OSD control register (OC)
0
OUT2 OUT1
B
G
R
0
0
0
OC7 OC6 OC5 OC4 OC3 OC2 OC1 OC0
Horizontal position register (HP) HP7 HP6 HP5 HP4 HP3
Block control register 1 (BC1)
BC17 BC16 BC 15 BC14 BC 13
Block control register 2 (BC2)
BC27 BC26 BC 25 BC24 BC 23
Block control register 3 (BC3)
BC37 BC36 BC 35 BC34 BC 33
HP2 HP1 HP0
BC12 BC 11 BC10
BC22 BC 21 BC20
BC32 BC 31 BC30
Block control register 4 (BC4)
BC47 BC46 BC 45 BC44 BC 43 BC42 BC 41 BC40
Block control register 5 (BC5)
BC57 BC56 BC 55 BC54 BC 53 BC52 BC 51 BC50
Block control register 6 (BC6)
BC67 BC66 BC 65 BC64 BC 63 BC62 BC 61 BC60
Block control register 7 (BC7)
BC77 BC76 BC 75 BC74 BC 73 BC72 BC 71 BC70
Block control register 8 (BC8)
BC87 BC86 BC 85 BC84 BC 83 BC82 BC 81 BC80
Block control register 9 (BC9)
BC97 BC96 BC 95 BC94 BC 93 BC92 BC 91 BC90
Block control register 10 (BC10)
BC107 BC106 BC105 BC104 BC103 BC102 BC101 BC100
Block control register 11 (BC11)
BC117 BC116 BC115 BC114 BC113 BC112 BC111 BC110
Block control register 12 (BC12)
Block control register 13 (BC13)
Block control register 14 (BC14)
Block control register 15 (BC15)
Block control register 16 (BC16)
BC127 BC126 BC125 BC124 BC123 BC122 BC121 BC120
BC137 BC136 BC135 BC134 BC133 BC132 BC131 BC130
BC147 BC146 BC145 BC144 BC143 BC142 BC141 BC140
BC157 BC156 BC155 BC154 BC153 BC152 BC151 BC150
BC167 BC166 BC165 BC164 BC163 BC162 BC161 BC160
Fig. 5. Memory Map of Special Function Register 1 (SFR1) (1)
12
b0
Port P0 (P0)
0
0
?
0016
?
0016
?
0016
?
0016
?
0016
?
0016
?
0 0
0016
0016
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
■ SFR1 area (addresses E016 to FF16)
< Bit allocation >
:
Name
< State immediately after reset >
0 : “0” immediately after reset
Function bit
:
1 : “1” immediately after reset
: No function bit
? : Indeterminate immediately
after reset
0 : Fix to this bit to “0”
(do not write to “1”)
1 : Fix to this bit to “1”
(do not write to “0”)
Address
Register
Bit allocation
b7
E016
E116
E216
E316
E416
E516
E616
E716
E816
E916
EA16
EB16
EC16
ED16
EE16
EF16
F016
F116
F216
F316
F416
F516
F616
F716
F816
F916
FA16
FB16
FC16
FD16
FE16
FF16
Caption position register (CP)
Start bit position register (SP)
Window register (WN)
Sync slice register (SSL)
1
0
State immediately after reset
b0 b7
0 CP4 CP3 CP2 CP1 CP0
b0
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
0
SSL7
0 WN5 WN4 WN3 WN2 WN1 WN0
0 0 0 0 1 0 1
Caption data register 1 (CD1)
Caption data register 2 (CD2)
Clock run-in register 1 (CR1)
Clock run-in register 2 (CR2)
Clock run-in detect register 1 (CRD1)
0
1
1
0
0
0
1
1
CR13 CR12 CR11 CR10
1
1
CR21
1
CRD17 CRD15 CRD15 CRD15 CRD15
Clock run-in detect register 2 (CRD2)
CRD27 CRD25 CRD25 CRD25 CRD25 CRD22 CRD21 CRD20
Data slicer control register 1 (DSC1)
Data slicer control register 2 (DSC2)
DSC17
DSC27
0
0
DSC15
DSC25
0
0
0
0
DSC22 DSC21 DSC20
?
?
0
0
?
?
ADIN2 ADIN1 ADIN0
0
?
0
0
0
0
0
0
1
DSC12 DSC11 DSC10
Caption data register 3 (CD3)
Caption data register 4 (CD4)
A-D conversion register (AD)
A-D control register (ADCON)
Timer 1 (TM1)
Timer 2 (TM2)
Timer 3 (TM3)
Timer 4 (TM4)
Timer mode register 1 (TM1)
Timer mode register 2 (TM2)
I2C data shift register (S0)
I2C address register (S0D)
I2C status register (S1)
I2C control register (S1D)
I2C clock control register (S2)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
0
0
ADVREF ADSTR
TM17 TM16 TM15 TM14 TM13 TM12 TM11 TM10
TM27 TM26 TM25 TM24 TM23 TM22 TM21 TM20
D7
D6
D5
D4
D3
D2
D1
D0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
MST TRX BB
PIN
AL AAS AD0 LRB
BSEL1 BSEL0 10 BIT ALS ES0 BC2 BC1 BC0
SAD
ACK FAST
ACK BIT
CCR4 CCR3 CCR2 CCR1 CCR0
MODE
CM7 CM6 CM5
1
1
CM2
0
0
ADR VSCR CRTR TM4R TM3R TM2R TM1R
0
T56R IICR INT2R
CK01MSR SIOR DSR INT1R
ADE VSCE CRTE TM4E TM3E TM2E TM1E
T56S T56E IICE INT2E 1MSE SIOE DSE INT1E
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0 0
0 0
0016
0016
?
0 1
FF16
0716
FF16
0716
0016
0016
?
0016
1 0
0016
0016
1 1
0016
0016
0016
0016
0
?
0
0
0
0
0
0
0
0
0
?
1
0
0
Fig. 6. Memory Map of Special Function Register 1 (SFR2) (2)
13
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
■ SFR2 area (addresses 20016 to 21F16)
< Bit allocation >
:
Name
< State immediately after reset >
0 : “0” immediately after reset
Function bit
:
1 : “1” immediately after reset
: No function bit
? : Indeterminate immediately
after reset
0 : Fix to this bit to “0”
(do not write to “1”)
1 : Fix to this bit to “1”
(do not write to “0”)
Address
Register
Bit allocation
State immediately after reset
b7
20016
20116
20216
20316
20416
20516
20616
20716
20816
20916
20A16
20B16
20C16
20D16
20E16
20F16
21016
21116
21216
21316
21416
21516
21616
21716
21816
21916
21A16
21B16
21C16
21D16
21E16
21F16
b0 b7
PWM1 register (PWM1)
PWM2 register (PWM2)
PWM3 register (PWM3)
PWM4 register (PWM4)
PWM5 register (PWM5)
PWM6 register (PWM6)
Clock run-in detect register 3 (CRD3) CRD35 CRD34 CRD33 CRD32 CRD31
CR36 CR35 CR34 CR33 CR32 CR31 CR30
Clock run-in register (CR3)
PWM mode register 1 (PN)
PWM mode register 2 (PW)
PN3 PN2 PN1 PN0
?
?
?
1
0
0
0 PW6 PW5 PW4 PW3 PW2 PW1 PW0
Timer 5 (TM5)
Timer 6 (TM6)
0016
Sync pulse counter register (SYC)
SYC5 SYC4 SYC3 SYC2 SYC1 SYC0
Data slicer control register 3 (DSC3)
DSC37 DSC36 DSC35 DSC34 DSC33 DSC32 DSC31 DSC30
Interrupt input polarity register (IP)
AD/INT3 INT3
SEL
POL
Serial I/O mode register (SM)
0
0
0
INT2 INT1
RE3
POL POL
0
0
0
RE5
SM5 SM4 SM3
RE3 SM2
RE2 SM1
RE1 SM0
Serial I/O register (SIO)
Clock source control register (CS)
I/O polarity control register (PC)
Raster color register (RC)
Extra font color register (EC)
Border color register (FC)
Window H register 1 (WH1)
Window L register 1 (WL1)
Window H register 2 (WH2)
INT3
0
RE5
RE3 RE2 RE1
CS6
POL CS5 CS4 CS3 CS2 CS1 CS0
AD/INT3
PC7
SEL
AD/INT3
RC7
SEL
PC6
RE5 PC4 RE3
PC5
RE2 PC1
RE1 PC0
0 PC2
POL
INT3
INT3
RC6
RE5
POL RC5
RE5
0
0
0
0
0
0
0
0
RC2
RE2 RC1
RE1 RC0
RE2
EC2 RE1
EC1 EC0
0
0
0
FC2 FC1 FC0
WH17 WH16 WH15 WH14 WH13 WH12 WH11 WH10
WL17 WL16 WL15 WL14 WL13 WL12 WL21 WL20
Window L register 2 (WL2)
Fig. 7. Memory Map of Special Function Register 2 (SFR2) (1)
14
b0
PWM0 register (PWM0)
WH21 WH20
WL21 WL20
?
?
?
?
?
?
?
?
0016
?
? 0
0016
0716
FF16
0016
0016
0016
?
0016
0016
?
?
0016
0 0
0016
0016
0016
0016
?
?
?
?
0
0
0
0
0
0
MITSUBISHI MICROCOMPUTERS
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M37274EFSP
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Not e para
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
■ SFR2 area (addresses 22016 to 24816)
< State immediately after reset >
<Bit allocation >
:
Name
0 : “0” immediately after reset
Function bit
:
1 : “1” immediately after reset
: No function bit
? : Indeterminate immediately
after reset
0 : Fix to this bit to “0”
(do not write to “1”)
1 : Fix to this bit to “1”
(do not write to “0”)
Address
22016
22116
22216
22316
22416
22516
22616
22716
22816
22916
22A16
22B16
22C16
22D16
22E16
22F16
23016
23116
23216
23316
23416
23516
23616
23716
23816
23916
23A16
23B16
23C16
23D16
23E16
23F16
24016
24116
24216
24316
24416
24516
24616
24716
24816
Register
b7
Bit allocation
b0 b7
Vertical position register 11 (VP11)
VP117 VP116 VP1 15 VP114 VP1 13 VP112 VP1 11 VP1 10
Vertical position register 12 (VP12)
VP127 VP126 VP1 25 VP124 VP1 23 VP122 VP1 21 VP1 20
Vertical position register 13 (VP13)
Vertical position register 14 (VP14)
VP137 VP136 VP1 35 VP134 VP1 33 VP132 VP1 31 VP1 30
Vertical position register 15 (VP15)
Vertical position register 16 (VP16)
VP157 VP156 VP1 55 VP154 VP1 53 VP152 VP1 51 VP1 50
Vertical position register 17 (VP17)
VP177 VP176 VP1 75 VP174 VP1 73 VP172 VP1 71 VP1 70
Vertical position register 18 (VP18)
Vertical position register 19 (VP19)
VP187 VP186 VP1 85 VP184 VP1 83 VP182 VP1 81 VP1 80
Vertical position register 110 (VP110)
VP1107 VP1106 VP1 105 VP1104 VP1103 VP1102 VP1101 VP1100
Vertical position register 111 (VP111)
Vertical position register 112 (VP112)
VP1117 VP1116 VP1 115 VP1114 VP1113 VP1112 VP1111 VP1110
Vertical position register 113 (VP113)
Vertical position register 114 (VP114)
VP1137 VP1136 VP1 135 VP1134 VP1133 VP1132 VP1131 VP1130
Vertical position register 115 (VP115)
Vertical position register 116 (VP116)
Vertical position register 21 (VP21)
VP1157 VP1156 VP1 155 VP1154 VP1153 VP1152 VP1151 VP1150
State immediately after reset
b0
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
VP147 VP146 VP1 45 VP144 VP1 43 VP142 VP1 41 VP1 40
VP167 VP166 VP1 65 VP164 VP1 63 VP162 VP1 61 VP1 60
VP197 VP196 VP1 95 VP194 VP1 93 VP192 VP1 91 VP1 90
VP1127 VP1126 VP1 125 VP1124 VP1123 VP1122 VP1121 VP1120
VP1147 VP1146 VP1 145 VP1144 VP1143 VP1142 VP1141 VP1140
VP1167 VP1166 VP1 165 VP1164 VP1163 VP1162 VP1161 VP1160
VP211 VP210
Vertical position register 22 (VP22)
VP221 VP220
Vertical position register 23 (VP23)
VP231 VP230
Vertical position register 24 (VP24)
VP241 VP240
Vertical position register 25 (VP25)
Vertical position register 26 (VP26)
VP251 VP250
Vertical position register 27 (VP27)
VP271 VP270
Vertical position register 28 (VP28)
Vertical position register 29 (VP29)
VP281 VP280
Vertical position register 210 (VP210)
VP2101 VP2100
Vertical position register 211 (VP211)
Vertical position register 212 (VP212)
VP2111 VP2110
Vertical position register 213 (VP213)
VP2131 VP2130
Vertical position register 214 (VP214)
VP2141 VP2140
Vertical position register 215 (VP215)
Vertical position register 216 (VP216)
DA-H register (DA-H)
VP2151 VP2150
VP261 VP260
VP291 VP290
VP2121 VP2120
VP2161 VP2160
0
DA-L register (DA-L)
ROM correction address 1 (high-order)
ROM correction address 1 (low-order)
ROM correction address 2 (high-order)
ROM correction address 2 (low-order)
ROM correction enable register (RCR)
0
0016
0
0
RCR1 RCR0
0
0
0
?
? ?
0016
0016
0016
0016
0016
0016
0016
?
?
?
Fig. 8. Memory Map of Special Function Register 2 (SFR2) (2)
15
MITSUBISHI MICROCOMPUTERS
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M37274EFSP
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s
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T
:
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Not e para
Som
PR
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
< State immediately after reset >
< Bit allocation >
:
Name
0 : “0” immediately after reset
Function bit
:
1 : “1” immediately after reset
: No function bit
? : Indeterminate immediately
after reset
0 : Fix to this bit to “0”
(do not write to “1”)
1 : Fix to this bit to “1”
(do not write to “0”)
Register
Bit allocation
State immediately after reset
b0 b7
b7
Processor status register (PS)
Program counter (PCH)
N
V
T
B
D
I
Z
C
Program counter (PCL)
Fig. 9. Internal State of Processor Status Register and Program Counter at Reset
16
b0
?
? ? ? ? 1 ? ?
Contents of address FFFF 16
Contents of address FFFE 16
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Not e para
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
INTERRUPTS
Interrupt Causes
Interrupts can be caused by 18 different sources consisting of 4 external, 12 internal, 1 software, and reset. Interrupts are vectored interrupts with priorities as shown in Table 1. Reset is also included in
the table because its operation is similar to an interrupt.
When an interrupt is accepted,
(1) The contents of the program counter and processor status
register are automatically stored into the stack.
(2) The interrupt disable flag I is set to “1” and the corresponding
interrupt request bit is set to “0.”
(3) The jump destination address stored in the vector address enters
the program counter.
Other interrupts are disabled when the interrupt disable flag is set to
“1.”
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits are
in interrupt request registers 1 and 2 and the interrupt enable bits are
in interrupt control registers 1 and 2. Figures 11 to 15 show the interrupt-related registers.
Interrupts other than the BRK instruction interrupt and reset are accepted when the interrupt enable bit is “1,” interrupt request bit is “1,”
and the interrupt disable flag is “0.” The interrupt request bit can be
set to “0” by a program, but not set to “1.” The interrupt enable bit can
be set to “0” and “1” by a program.
Reset is treated as a non-maskable interrupt with the highest priority.
Figure 10 shows interrupt control.
(1) VSYNC and OSD interrupts
The VSYNC interrupt is an interrupt request synchronized with
the vertical sync signal.
The OSD interrupt occurs after character block display to the
CRT is completed.
(2) INT1, INT2, INT3 interrupts
With an external interrupt input, the system detects that the level
of a pin changes from “L” to “H” or from “H” to “L,” and generates
an interrupt request. The input active edge can be selected by
bits 3, 4 and 6 of the interrupt input polarity register (address
021216) : when this bit is “0,” a change from “L” to “H” is detected;
when it is “1,” a change from “H” to “L” is detected. Note that all
bits are cleared to “0” at reset.
(3) Timer 1, 2, 3 and 4 interrupts
An interrupt is generated by an overflow of timer 1, 2, 3 or 4.
(4) Serial I/O interrupt
This is an interrupt request from the clock synchronous serial
I/O function.
(5) f(XIN)/4096 interrupt
This interrupt occurs regularly with a f(XIN)/4096 period. Set bit 0
of the PWM mode register 1 to “0.”
(6) Data slicer interrupt
An interrupt occurs when slicing data is completed.
(7) Multi-master I2C-BUS interface interrupt
This is an interrupt request related to the multi-master I2C-BUS
interface.
(8) A-D conversion interrupt
An interrupt occurs at the completion of A-D conversion. Since
A-D conversion interrupt and the INT3 interrupt share the same
vector, an interrupt source is selected by bit 7 of the interrupt
interval determination control register (address 021216).
Table 1. Interrupt Vector Addresses and Priority
Interrupt Source
Priority
Vector Addresses
Remarks
Reset
1
FFFF16, FFFE16
OSD interrupt
2
FFFD16, FFFC16
INT1 interrupt
3
FFFB16, FFFA16
Data slicer interrupt
4
FFF916, FFF816
Serial I/O interrupt
5
FFF716, FFF616
Timer 4 interrupt
6
FFF516, FFF416
f(XIN)/4096 interrupt
7
FFF316, FFF216
VSYNC interrupt
8
FFF116, FFF016
Timer 3 interrupt
9
FFEF16, FFEE16
Timer 2 interrupt
10
FFED16, FFEC16
Timer 1 interrupt
11
FFEB16, FFEA16
A-D convertion · INT3 interrupt
12
FFE916, FFE816
INT2 interrupt
13
FFE716, FFE616
Multi-master I2C-BUS interface interrupt
14
FFE516, FFE416
Timer 5 · 6 interrupt
15
FFE316, FFE216
Software switch by software (See note)
BRK instruction interrupt
16
FFDF16, FFDE16
Non-maskable (software interrupt)
Non-maskable
Active edge selectable
Active edge selectable
Software switch by software (See note)/
When selecting INT3 interrupt, active edge selectable.
Active edge selectable
Note : Switching a source during a program causes an unnecessary interrupt occurs. Accordingly, set a source at initializing of program.
17
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(9)Timer 5 · 6 interrupt
An interrupt is generated by an overflow of timer 5 or 6. Their
priorities are same, and can be switched by software.
(10)BRK instruction interrupt
This software interrupt has the least significant priority. It does
not have a corresponding interrupt enable bit, and it is not affected by the interrupt disable flag I (non-maskable).
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction
Reset
Fig. 10. Interrupt Control
18
Interrupt
request
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Interrupt Request Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address 00FC16]
B
0
Name
Functions
After reset R W
0 : No interrupt request issued
Timer 1 interrupt
1 : Interrupt request issued
request bit (TM1R)
Timer 2 interrupt
0 : No interrupt request issued
request bit (TM2R)
1 : Interrupt request issued
0 : No interrupt request issued
Timer 3 interrupt
1 : Interrupt request issued
request bit (TM3R)
0 : No interrupt request issued
Timer 4 interrupt
1 : Interrupt request issued
request bit (TM4R)
OSD interrupt request 0 : No interrupt request issued
1 : Interrupt request issued
bit (CRTR)
0 : No interrupt request issued
V SYNC interrupt
request bit (VSCR) 1 : Interrupt request issued
A-D conversion • INT3
0 : No interrupt request issued
interrupt request bit (ADR) 1 : Interrupt request issued
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
1
2
3
4
5
6
7
0
R ✽
0
R ✽
0
R ✽
0
R ✽
0
R ✽
0
R ✽
0
R ✽
0
R —
✽: “0” can be set by software, but “1” cannot be set.
Fig. 11. Interrupt Request Register 1
Interrupt Request Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt request register 2 (IREQ2) [Address 00FD16]
B
Name
Functions
After reset R W
INT1 interrupt
request bit (INT1R)
1 Data slicer interrupt
request bit (DSR)
2 Serial I/O interrupt
request bit (SIOR)
3 f(XIN)/4096 interrupt
request bit (1MSR)
4 INT2 interrupt
request bit (INT2R)
5 Multi-master I 2C-BUS
interrupt request bit (IICR)
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
R ✽
0
R ✽
0
R ✽
0
R ✽
0
R ✽
0
R ✽
6
Timer 5 • 6 interrupt
request bit (T56R)
0 : No interrupt request issued
1 : Interrupt request issued
0
R ✽
7
Fix this bit to “0.”
0
R W
0
✽: “0” can be set by software, but “1” cannot be set.
Fig. 12. Interrupt Request Register 2
19
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Interrupt Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address 00FE16]
B
0
1
2
3
4
5
6
7
Name
Timer 1 interrupt
enable bit (TM1E)
Timer 2 interrupt
enable bit (TM2E)
Timer 3 interrupt
enable bit (TM3E)
Timer 4 interrupt
enable bit (TM4E)
OSD interrupt enable bit
(CRTE)
VSYNC interrupt enable
bit (VSCR)
A-D conversion • INT3
interrupt enable bit (ADE)
Functions
After reset R W
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Nothing is assigned. This bit is a write disable
bit. When this bit is read out, the value is “0.”
0
R W
0
R W
0
R W
0
R W
0
R W
0
R W
0
R W
0
R —
Fig. 13. Interrupt Control Register 1
Interrupt Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2 (ICON2) [Address 00FF 16]
B
Name
0
INT1 interrupt
enable bit (INT1E)
Data slicer interrupt
enable bit (DSR)
Serial I/O interrupt
enable bit (SIOE)
f(XIN)/4096 interrupt
enable bit (1MSE)
INT2 interrupt enable
bit (INT2E)
0
R W
0
R W
0
R W
0
R W
0
R W
5
Multi-master I 2C-BUS interface 0 : Interrupt disabled
interrupt enable bit (IICE)
1 : Interrupt enabled
0
R W
6
Timer 5 • 6 interrupt
enable bit (T56E)
0 : Interrupt disabled
1 : Interrupt enabled
0
R W
7
Timer 5 • 6 interrupt
switch bit (TM56S)
0 : Timer 5
1 : Timer 6
0
R W
2
3
4
20
After reset R W
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
1
Fig. 14. Interrupt Control Register 2
Functions
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Interrupt Input Polarity Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
Interrupt input polarity register (IP) [Address 021216]
B
Name
Functions
0 to 2, Fix these bits to “0.”
5
After reset
R W
0
R W
3
INT1 polarity switch bit
(INT1POL)
0 : Positive polarity
1 : Negative polarity
0
R W
4
INT2 polarity switch bit
(INT2POL)
0 : Positive polarity
1 : Negative polarity
0
R W
6
INT3 polarity switch bit
(INT3POL)
0 : Positive polarity
1 : Negative polarity
0
R W
7
A-D conversion • INT3
interrupt source selection
bit (RE7)
0 : Positive polarity
1 : Negative polarity
0
R W
Fig. 15. Interrupt Input Polarity Register
21
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
TIMERS
(5) Timer 5
The M37271MF-XXXSP has 6 timers: timer 1, timer 2, timer 3,
timer 4, timer 5, and timer 6. All timers are 8-bit timers with the 8-bit
timer latch. The timer block diagram is shown in Figure 18.
All of the timers count down and their divide ratio is 1/(n+1), where n
is the value of timer latch. By writing a count value to the corresponding timer latch (addresses 00F016 to 00F316 : timers 1 to 4, addresses
020C16 and 020D16 : timers 5 and 6), the value is also set to a timer,
simultaneously.
The count value is decremented by 1. The timer interrupt request bit
is set to “1” by a timer overflow at the next count pulse, after the
count value reaches “0016”.
Timer 5 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
Timer 2 overflow signal
Timer 4 overflow signal
The count source of timer 3 is selected by setting bit 6 of timer mode
register 1 (address 00F416) and bit 7 of timer mode register 2 (address 00F516). When overflow of timer 2 or 4 is a count source for
timer 5, either timer 2 or 4 functions as an 8-bit prescaler. Either
f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Timer 5 interrupt request occurs at timer 5 overflow.
•
•
•
(6) Timer 6
(1) Timer 1
Timer 1 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
f(XIN)/4096 or f(XCIN)/4096
External clock from the P42 TIM2 pin
The count source of timer 1 is selected by setting bits 5 and 0 of
timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is
selected by bit 7 of the CPU mode register.
Timer 1 interrupt request occurs at timer 1 overflow.
•
•
•
(2) Timer 2
Timer 2 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
Timer 1 overflow signal
External clock from the TIM2 pin
The count source of timer 2 is selected by setting bits 4 and 1 of
timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is
selected by bit 7 of the CPU mode register. When timer 1 overflow
signal is a count source for the timer 2, the timer 1 functions as an 8bit prescaler.
Timer 2 interrupt request occurs at timer 2 overflow.
•
•
•
(3) Timer 3
Timer 3 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
f(XCIN)
External clock from the TIM3 pin
The count source of timer 3 is selected by setting bit 0 of timer mode
register 2 (address 00F516) and bit 6 at address 00C716. Either f(XIN)
or f(XCIN) is selected by bit 7 of the CPU mode register.
Timer 3 interrupt request occurs at timer 3 overflow.
•
•
•
(4) Timer 4
Timer 4 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
f(XIN)/2 or f(XCIN)/2
f(XCIN)
The count source of timer 3 is selected by setting bits 1 and 4 of
timer mode register 2 (address 00F516). Either f(XIN) or f(XCIN) is
selected by bit 7 of the CPU mode register. When timer 3 overflow
signal is a count source for the timer 4, the timer 3 functions as an 8bit prescaler.
Timer 4 interrupt request occurs at timer 4 overflow.
•
•
•
22
Timer 6 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
Timer 5 overflow signal
The count source of timer 6 is selected by setting bit 7 of timer mode
register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit
7 of the CPU mode register. When timer 5 overflow signal is a count
source for timer 6, timer 5 functions as an 8-bit prescaler.
Timer 6 interrupt request occurs at timer 6 overflow.
•
•
At reset, timers 3 and 4 are connected by hardware and “FF16” is
automatically set in timer 3; “0716” in timer 4. The f(XIN) ✽ /16 is selected as the timer 3 count source. The internal reset is released by
timer 4 overflow in this state and the internal clock is connected.
At execution of the STP instruction, timers 3 and 4 are connected by
hardware and “FF16” is automatically set in timer 3; “0716” in timer 4.
However, the f(XIN) ✽ /16 is not selected as the timer 3 count source.
So set both bit 0 of timer mode register 2 (address 00F516) and bit 6
at address 00C716 to “0” before execution of the STP instruction
(f(XIN) ✽ /16 is selected as the timer 3 count source). The internal
STP state is released by timer 4 overflow in this state and the internal clock is connected.
As a result of the above procedure, the program can start under a
stable clock.
✽ : When bit 7 of the CPU mode register (CM7) is “1,” f(XIN) becomes f(XCIN).
The structure of timer-related registers is shown in Figure 16 and 17.
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Timer Mode Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer mode register 1 (TM1) [Address 00F416]
B
Name
0 Timer 1 count source
selection bit 1 (TM10)
Functions
After reset R W
0: f(XIN)/16 or f(X CIN)/16 (Note)
0
R W
1: Count source selected by bit 5 of TM1
1
Timer 2 count source
selection bit 1 (TM11)
0: Count source selected by bit 4 of TM1
1: External clock from TIM2 pin
0
R W
2
Timer 1 count
stop bit (TM12)
Timer 2 count stop
bit (TM13)
0: Count start
1: Count stop
0: Count start
1: Count stop
0
R W
0
R W
4
Timer 2 count source
selection bit 2
(TM14)
0: f(XIN)/16 or f(X CIN)/16 (See note)
1: Timer 1 overflow
0
R W
5
Timer 1 count source
selection bit 2 (TM15)
0: f(XIN)/4096 or f(X CIN)/4096 (See note)
1: External clock from TIM2 pin
0
R W
6
Timer 5 count source
selection bit 2 (TM16)
0: Timer 2 overflow
1: Timer 4 overflow
0
R W
7
Timer 6 internal count
source selection bit
(TM17)
0: f(XIN)/16 or f(X CIN)/16 (See note)
1: Timer 5 overflow
0
R W
3
Note: Either f(X IN) or f(X CIN) is selected by bit 7 of the CPU mode register.
Fig. 16. Timer Mode Register 1
Timer Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer mode register 2 (TM2) [Address 00F516]
B
Name
0 Timer 3 count source
selection bit (TM20)
1, 4 Timer 4 count source
selection bits
(TM21, TM24)
Functions
(b6 at address 00C7 16)
b0
0 0 : f(X IN)/16 or f(X CIN)/16 (See note)
0 1 : f(X CIN)
1 0:
External clock from TIM3 pin
1 1:
b4
0
0
1
1
b1
0 : Timer 3 overflow signal
1 : f(X IN)/16 or f(X CIN)/16 (See note)
0 : f(X IN)/2 or f(XCIN)/2 (See note)
1 : f(X CIN)
After reset R W
0
R W
0
R W
2
Timer 3 count
stop bit (TM22)
0: Count start
1: Count stop
0
R W
3
Timer 4 count stop bit
(TM23)
0: Count start
1: Count stop
0
R W
5
Timer 5 count stop bit
(TM25)
0: Count start
1: Count stop
0
R W
6
Timer 6 count stop bit
(TM26)
0: Count start
1: Count stop
0
R W
7
Timer 5 count source
selection bit 1
(TM27)
0: f(XIN)/16 or f(X CIN)/16 (See note)
1: Count source selected by bit 6
of TM1
0
R W
Note: Either f(X IN) or f(X CIN) is selected by bit 7 of the CPU mode register.
Fig. 17. Timer Mode Register 2
23
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Data bus
8
XCIN
CM7
TM15
Timer 1 latch (8)
1/4096
8
XIN
1/2
1/8
Timer 1
interrupt request
Timer 1 (8)
TM10
TM12
8
TM14
8
Timer 2 latch (8)
8
TIM2
Timer 2
interrupt request
Timer 2 (8)
TM11
TM13
8
8
FF16
TM3EL
Reset
STP instruction
Timer 3 latch (8)
8
Timer 3
interrupt request
Timer 3 (8)
TIM3
TM20
TM22
8
8
TM21
07 16
Timer 4 latch (8)
8
Timer 4
interrupt request
Timer 4 (8)
TM21
TM24
TM23
8
8
TM16
Timer 5 latch (8)
Selection gate : Connected to
black side at
reset
8
Timer 5
interrupt request
Timer 5 (8)
TM1 : Timer mode register 1
TM2 : Timer mode register 2
TM3EL : Timer 3 count source
switch bit (address 00C7 16)
CM : CPU mode register
TM27
TM25
8
8
Timer 6 latch (8)
8
Timer 6
interrupt request
Timer 6 (8)
TM17
TM26
8
Notes 1: HIGH pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more.
2: When the external clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal.
3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used.
Fig. 18. Timer Block Diagram
24
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
SERIAL I/O
The M37274EFSP has a built-in serial I/O which can either transmit
or receive 8-bit data serially in the clock synchronous mode.
The serial I/O block diagram is shown in Figure 19. The synchronous
clock I/O pin (SCLK), and data output pin (SOUT) also function as port
P4, data input pin (SIN) also functions as port P1.
Bit 2 of the serial I/O mode register (address 021316) selects whether
the synchronous clock is supplied internally or externally (from the
P46/SCLK pin). When an internal clock is selected, bits 1 and 0 select
whether f(XIN) or f(XCIN) is divided by 8, 16, 32, or 64. To use SOUT
and P46/SCLK pins for serial I/O, set the corresponding bits of the
port P4 direction register (address 00C916) to “0.” To use SIN pin for
serial I/O, set the corresponding bit of the port P1 direction register
(address 00C316) to “0.”
The operation of the serial I/O is described below. The operation of
the serial I/O differs depending on the clock source; external clock or
internal clock.
XCIN
1/2
XIN
1/2
Data bus
Frequency divider
1/2
CM7
1/2
1/16
SM1
SM0
SM2
Synchronous
circuit
S
SCLK
SOUT
1/4 1/8
CM : CPU mode register
SM : Serial I/O mode register
Serial I/O
interrupt request
Serial I/O counter (8)
SM5 : LSB
Selection gate: Connect to
black side at
reset.
MSB
(Note)
SIN
Serial I/O shift register (8)
8 (Address 0214 16)
Note : When the data is set in the serial I/O register (address 0214 16), the register functions as the serial I/O shift register.
Fig. 19. Serial I/O Block Diagram
25
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Internal clock : The serial I/O counter is set to “7” during the write
cycle into the serial I/O register (address 021416), and the transfer
clock goes “H” forcibly. At each falling edge of the transfer clock after
the write cycle, serial data is output from the SOUT pin. Transfer direction can be selected by bit 5 of the serial I/O mode register. At
each rising edge of the transfer clock, data is input from the SIN pin
and data in the serial I/O register is shifted 1 bit.
After the transfer clock has counted 8 times, the serial I/O counter
becomes “0” and the transfer clock stops at HIGH. At this time the
interrupt request bit is set to “1.”
External clock : The an external clock is selected as the clock source,
the interrupt request is set to “1” after the transfer clock has been
counted 8 counts. However, transfer operation does not stop, so the
clock should be controlled externally. Use the external clock of 500kHz
or less with a duty cycle of 50%.
The serial I/O timing is shown in Figure 20. When using an external
clock for transfer, the external clock must be held at HIGH for initializing the serial I/O counter. When switching between an internal clock
and an external clock, do not switch during transfer. Also, be sure to
initialize the serial I/O counter after switching.
Notes 1: On programming, note that the serial I/O counter is set by
writing to the serial I/O register with the bit managing instructions, such as SEB and CLB.
2: When an external clock is used as the synchronous clock,
write transmit data to the serial I/O register when the transfer clock input level is HIGH.
Synchronous clock
Transfer clock
Serial I/O register
write signal
(Note)
Serial I/O output
SOUT
D0
D1
D2
D3
D4
D5
D6
D7
Serial I/O input
S IN
Interrupt request bit is set to “1”
Note : When an internal clock is selected, the S OUT pin is at high-impedance after transfer is completed.
Fig. 20. Serial I/O Timing (for LSB first)
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Serial I/O Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Serial I/O mode register (SM) [Address 0213 16]
B
Name
0, 1 Internal synchronous
clock selection bits
(SM0, SM1)
Functions
b1
0
0
1
1
b0
0: f(X IN)/4 or f(X CIN)/4
1: f(X IN)/16 or f(X CIN)/16
0: f(X IN)/32 or f(X CIN)/32
1: f(X IN)/64 or f(X CIN)/64
After reset R W
R W
0
2
Synchronous clock
selection bit (SM2)
0: External clock
1: Internal clock
0
R W
3
Port function
selection bit (SM3)
0: P1 1, P1 3
1: SCL1, SDA1
0
R W
4
Port function
selection bit (SM4)
0: P1 2, P1 4
1: SCL2, SDA2
0
R W
5
Transfer direction
selection bit (SM5)
0: LSB first
1: MSB first
0
R W
0
R W
6, 7 Fix these bits to “0.”
Fig. 21. Serial I/O Mode Register
27
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
PWM OUTPUT FUNCTION
(4) Operating of 14-bit PWM
The M37274EFSP is equipped with a 14-bit PWM (DA) seven 8-bit
PWMs (PWM0–PWM6). DA has a 14-bit resolution with the minimum resolution bit width of 0.25 µ s and a repeat period of
4096 ms (for f(XIN) = 8 MHz). PWM0–PWM6 have the same circuit
structure and an 8-bit resolution with minimum resolution bit width of
4 µs and repeat period of 1024 µs (for f(XIN) = 8 MHz) .
Figure 22 shows the PWM block diagram. The PWM timing generating circuit applies individual control signals to PWM0–PWM6 using
f(XIN) divided by 2 as a reference signal.
As with 8-bit PWM, set the bit 0 of the PWM mode register 1 (address 020A16) to “0” (at reset, bit 0 is already set to “0” automatically), so that the PWM count source is supplied. Pin DA is also used
as port P03. Select output mode by setting bit 3 of the port P0 direction register. Next, select the output polarity by bit 3 of the PWM
mode register 1. Then, the 14-bit PWM outputs from the D-A output
pin by setting bit 1 of the PWM mode register 1 to “0” (at reset, this bit
already set to “0” automatically) to select the DA output.
The output example of the 14-bit PWM is shown in Figure 23.
The 14-bit PWM divides the data of the DA latch into the low-order 6
bits and the high-order 8 bits.
The fundamental waveform is determined with the high-order 8-bit
data “DH.” A “H” level area with a length τ ✕ DH(“H” level area of
fundamental waveform) is output every short area of “t” = 256τ =
64 ms (τ is the minimum resolution bit width of 0.25 µs). The “H” level
area increase interval (tm) is determined with the low-order 6-bit data
“DL.” The “H” level are of smaller intervals “tm” shown in Table 6 is
longer by τ than that of other smaller intervals in PWM repeat period
“T” = 64t. Thus, a rectangular waveform with the different “H” width is
output from the D-A pin. Accordingly, the PWM output changes by τ
unit pulse width by changing the contents of the DA-H and DA-L
registers. A length of entirely “H” output cannot be output, i. e. 256/
256.
(1) Data Setting
When outputting DA, first set the high-order 8 bits to the DA-H register (address 024016), then the low-order 6 bits to the DA-L register
(address 024116). When outputting PWM0–PWM6, set 8-bit output
data to the PWMi register (i means 0 to 6; addresses 020016 to
020616).
(2) Transmitting Data from Register to PWM circuit
Data transfer from the 8-bit PWM register to the 8-bit PWM circuit is
executed at writing data to the register.
The signal output from the 8-bit PWM output pin corresponds to the
contents of this register.
Also, data transfer from the DA register (addresses 024016 and
024116) to the 14-bit PWM circuit is executed at writing data to the
DA-L register (address 024116). Reading from the DA-H register (address 024016) means reading this transferred data. Accordingly, it is
possible to confirm the data being output from the D-A output pin by
reading the DA register.
(3) Operating of 8-bit PWM
The following explains PWM operation.
First, set the bit 0 of PWM mode register 1 (address 020A16) to “0”
(at reset, bit 0 is already set to “0” automatically), so that the PWM
count source is supplied.
PWM0–PWM3 are also used as pins P04–P07, PWM4–PWM6 are
also used as pins P00–P02, respectively. Set the corresponding bits
of the port P0 direction register to “1” (output mode). And select each
output polarity by bit 3 of PWM mode register 1 (address 020A16).
Then, set bits 7 to 0 of PWM mode register 2 to “1” (PWM output).
The PWM waveform is output from the PWM output pins by setting
these registers.
Figure 23 shows the 8-bit PWM timing. One cycle (T) is composed
of 256 (28) segments. The 8 kinds of pulses, relative to the weight of
each bit (bits 0 to 7), are output inside the circuit during 1 cycle.
Refer to Figure 20 (a). The 8-bit PWM outputs waveform which is
the logical sum (OR) of pulses corresponding to the contents of bits
0 to 7 of the 8-bit PWM register. Several examples are shown in
Figure 23 (b). 256 kinds of output (HIGH area: 0/256 to 255/256) are
selected by changing the contents of the PWM register. A length of
entirely HIGH cannot be output, i.e. 256/256.
28
(5) Output after Reset
At reset, the output of ports P00–P02 and P04–P07 is in the highimpedance state and the contents of the PWM register and the PWM
circuit are undefined. Note that after reset, the PWM output is undefined until setting the PWM register.
MITSUBISHI MICROCOMPUTERS
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M37274EFSP
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Table 2. Relation Between Low-order 6-bit Data and High-level
Area Increase Interval
Low-order 6 bits of Data Area Longer by τ Than That of Other tm (m = 0 to 63)
LSB
000000
000001
Nothing
000010
m = 16, 48
000100
m = 8, 24, 40, 56
001000
m = 4, 12, 20, 28, 36, 44, 52, 60
010000
m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62
100000
m = 1, 3, 5, 7, ................................. 57, 59, 61, 63
m = 32
Data bus
DA-H register
(Address : 0240 16)
b7
b0
DA-L register (Note)
(Address : 0241 16)
DA latch
(14 bits)
MSB
LSB
8
14
6
6
PN2
P03
D03
D-A
14-bit PWM circuit
PN1
XIN
PWM timing
generating
circuit
1/2
PN0
PWM0 register
(Address 0200 16)
b7
b0
8
POL
P04
D04
PWM0
D05
PWM1
D06
PWM2
D07
PWM3
D00
PWM4
D01
PWM5
D02
PWM6
8-bit PWM circuit
PW0
P05
PWM1 register (Address 0201 16)
PW1
P06
PWM2 register (Address 0202 16)
PW2
P07
PWM3 register (Address 0203 16)
PW3
P00
PWM4 register (Address 0204 16)
PW4
P01
PWM5 register (Address 0205 16)
PW5
P02
Selection gate :
Connected to
black side at
reset.
Inside of
PWM6 register (Address 0206 16)
is as same contents with the others.
PW6
PN : PWM mode register 1 (address 020A 16)
PW : PWM mode register 2 (address 020B 16)
P0 : Port P0 register (address 00C0 16)
D0 : Port P0 direction register (address 00C116)
Fig. 22. PWM Block Diagram
29
30
Fig. 23. 8-bit PWM Timing
t
8
60
80
100
110
120
130
140
150
160
170
180
190
200
210
220
230
240
5
250 255
104
108
112
116
120
124
128
132
136
140
144
148
152
156
T = 256 t
t = 4 µs T = 1024 µs
f(XIN) = 8 MHz
(b) Example of 8-bit PWM
PWM output
(a) Pulses showing the weight of each bit
100
160
164
168
172
176
180
184
188
192
196
200
204
208
212
216
224
220
228
232
236
240
244
248
252
98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254
96
94
92
90
90
88
86
84
82
80
78
76
74
72
70
70
68
66
64
62
60
58
56
54
52
50
50
48
46
44
42
40
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
30
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18 16 (24)
0116 (1)
00 16 (0)
Bit 0
Bit 1
Bit 2
4
6
20
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Bit 3
2
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Bit 4
Bit 5
Bit 6
Bit 7
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
RY
A
IMIN
MITSUBISHI MICROCOMPUTERS
M37274EFSP
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REL
P
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Set “2816” to DA-L register.
Set “2C 16” to DA-H register.
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
[DA-H
0 0 1 0 1 1 0 0 DH
register]
1
[DA-L register]
0
1
0
0
0
DL
Undefined
At writing of DA-L
At writing of DA-L
b13
[DA latch]
0
b6 b5
0
1
0
1
1
0
0
These bits decide “H” level area of
fundamental waveform.
“H” level area of
fundamental waveform
=
Minimum
resolution bit
width 0.25 µs
✕
1
b0
0
1
0
0
0
These bits decide smaller interval “tm” in which “H” leval
area is [“H” level area of fundamental waveform + τ ].
High-order 8-bit
value of DA latch
Fundamental
waveform
Waveform of smaller interval “tm” specified by low-order 6 bits
0.25 µs ✕ 44
0.25 µs ✕ 45
0.25 µs
14-bit
PWM output 2C 2B 2A … 03 02 01 00
14-bit
PWM output 2C 2B 2A … 03 02 01 00
8-bit
counter
8-bit
counter
FF FE FD … D6 D5 D4 D3 … 02 01 00
FF FE FD … D6 D5 D4 D3 … 02 01 00
Fundamental waveform of smaller interval
“tm” which is not specified by low-order 6
bits is not changed.
τ = 0.25 µs
0.25 µs ✕ 44
14-bit PWM output
t0
t1
t2
t3
t4
t5
t59
t60
t61
t62
t63
Low-order 6-bit output
of DA latch
Repeat period
T = 4096 µs
Fig. 24. 14-bit PWM Output Example (f(XIN) = 8MHz)
31
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
PWM Mode Register 1
b7 b6 b5 b4 b3 b2 b1 b0
PWM mode register 1 (PN) [Address 020A16]
B
0
Name
PWM counts source
selection bit (PN0)
1
Functions
After reset
R W
0 : Count source supply
1 : Count source stop
0
R W
DA/P03 output
selection bit (PN1)
0 : P03 output
1 : DA output
0
R W
2
DA output polarity
selection bit (PN2)
0 : Positive polarity
1 : Negative polarity
0
R W
3
PWM output polarity
selection bit (PN3)
0 : Positive polarity
1 : Negative polarity
0
R W
4
to
7
Nothing is assigned. These bits are write disable bits. Indeterminate R —
When these bits are read out, the values are “0.”
Fig. 25. PWM Mode Register 1
PWM Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Fig. 26. PWM Mode Register 2
32
PWM mode register 2 (PW) [Address 020B16]
B
Name
0 P04/PWM0 output
selection bit (PW0)
Functions
0 : P0 4 output
1 : PWM0 output
After reset R W
0
R W
1
P05/PWM1 output
selection bit (PW1)
0 : P0 5 output
1 : PWM1 output
0
R W
2
P06/PWM2 output
selection bit (PW2)
0 : P0 6 output
1 : PWM2 output
0
R W
3
P07/PWM3 output
selection bit (PW3)
0 : P0 7 output
1 : PWM3 output
0
R W
4
P00/PWM4 output
selection bit (PW4)
0 : P0 0 output
1 : PWM4 output
0
R W
5
P01/PWM5 output
selection bit (PW5)
0: P01 output
1: PWM5 output
0
R W
6
P02/PWM6 output
selection bit (PW6)
0: P02 output
1: PWM6 output
0
R W
7
Fix this bit to “0.”
0
R W
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
A-D CONVERTER
(1)A-D Conversion Register (AD)
A-D conversion reigister is a read-only register that stores the result
of an A-D conversion. This register should not be read during A-D
conversion.
(3)Comparison Voltage Generator (Resistor
Ladder)
The voltage generator divides the voltage between VSS and VCC by
256, and outputs the divided voltages to the comparator as the reference voltage Vref.
(2)A-D Control Register (ADCON)
The A-D control register controls A-D conversion. Bits 1 and 0 of this
register select analog input pins. When these pins are not used as
anlog input pins, they are used as ordinary I/O pins. Bit 3 is the A-D
conversion completion bit, A-D conversion is started by writing “0” to
this bit. The value of this bit remains at “0” during an A-D conversion,
then changes to “1” when the A-D conversion is completed.
Bit 4 controls connection between the resistor ladder and VCC. When
not using the A-D converter, the resistor ladder can be cut off from
the internal VCC by setting this bit to “0,” accordingly providing lowpower dissipation.
(4)Channel Selector
The channel selector connects an analog input pin, selected by bits
1 and 0 of the A-D control register, to the comparator.
(5)Comparator and Control Circuit
The conversion result of the analog input voltage and the reference
voltage “Vref” is stored in the A-D conversion register. The A-D conversion completion bit and A-D conversion interrupt request bit are
set to “1” at the completion of A-D conversion.
Data bus
b7
b0
A-D control register
(address 00EF16)
2
A-D conversion
interrupt request
A-D control circuit
AD2
AD3
AD4
AD5
Channel selector
AD1
AD6
Comparator
A-D conversion register
8
( address 00EE 16 )
Switch tree
Resistor ladder
VSS VCC
Fig. 27. A-D Comparator Block Diagram
33
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
A-D Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
A-D control register (ADCON) [Address 00EF16 ]
B
Name
0
to
2
Analog input pin selection
bits
(ADIN0 to ADIN2)
b2
0
0
0
0
1
1
1
1
3
A-D conversion completion
bit (ADSTR)
4
VCC connection selection bit
(ADVREF)
6
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is indeterminate.
5, 7 Fix these bits to “0.”
Fig. 28. A-D Control Register
34
Functions
b1
0
0
1
1
0
0
1
1
b0
0 : AD1
1 : AD2
0 : AD3
1 : AD4
0 : AD5
1 : AD6
0:
Do not set.
1:
After reset R W
0
R W
0: Conversion in progress
1: Convertion completed
Indeterminate
R W
0: OFF
1: ON
Indeterminate
R W
Indeterminate
R —
0
R —
ARY
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(6) Conversion Method
(7) Internal Operation
1Set bit 7 of the interrupt input polarity register (address 021216) to
“1” to generate an interrupt request at completion of A-D conversion.
2Set the A-D conversion • INT3 interrupt request bit to “0” (even
when A-D conversion is started, the A-D conversion • INT3 interrupt reguest bit is not set to “0” automatically).
3When using A-D conversion interrupt, enable interrupts by setting
A-D conversion • INT3 interrupt request bit to “1” and setting the
interrupt disable flag to “0.”
4Set the VCC connection selection bit to “1” to connect VCC to the
resistor ladder.
5Select analog input pins by the analog input selection bit of the AD control register.
6Set the A-D conversion completion bit to “0.” This write operation
starts the A-D conversion. Do not read the A-D conversion register during the A-D conversion.
7Verify the completion of the conversion by the state (“1”) of the
A-D conversion completion bit, the state (“1”) of A-D conversion •
INT3 interrupt reguest bit, or the occurrence of an A-D conversion
interrupt.
8Read the A-D conversion register to obtain the conversion results.
When the A-D conversion starts, the following operations are automatically performed.
1The A-D conversion register is set to “0016.”
2The most significant bit of the A-D conversion register becomes
“1, ” and the comparison voltage “Vref” is input to the comparator.
At this point, Vref is compared with the analog input voltage “VIN .”
3Bit 7 is determined by the comparison results as follows.
When Vref < VIN : bit 7 holds “1”
When Vref > VIN : bit 7 becomes “0”
With the above operations, the analog value is converted into a digital value. The A-D conversion terminates in a maximum of 50 machine cycles (12.5 µs at f(X IN) = 8 MHz) after it starts, and the conversion result is stored in the A-D conversion register.
An A-D conversion interrupt request occurs at the same time as A-D
conversion completion, the A-D conversion • INT3 interrupt request
bit becomes “1.” The A-D conversion completion bit also becomes
“1.”
Table 3. Expression for Vref and VREF
A-D conversion register contents “n”
(decimal notation)
Vref (V)
0
0
1 to 255
VREF
✕ (n – 0.5)
256
Note : When the ladder resistor is disconnect from VCC, set the VCC
connection selection bit to “0” between steps 7and 8.
Note: VREF indicates the voltage of internal VCC.
Contents of A-D conversion register
Reference voltage (Vref)
[V]
A-D conversion start
0 0 0 0 0 0 0 0
0
1st comparison start
1 0 0 0 0 0 0 0
2nd comparison start
1 1 0 0 0 0 0 0
3rd comparison start
1 2 1 0 0 0 0 0
VREF – VREF
2
512
VREF VREF
VREF
±
–
2
4
512
VREF ± VREF ± VREF
VREF
–
2
4
8
512
8th comparison start
1 2 3 4 5 6 7 1
A-D conversion completion
1 2 3 4 5 6 7 8
(8th comparison completion)
VREF ± VREF ± VREF ± .....
2
4
8
VREF
V
REF
....... ±
–
512
256
Digital value corresponding to
analog input voltage.
m
: Value determined by mth (m = 1 to 8) result
Fig. 29. Changes in A-D Conversion Register and Comparison Voltage during A-D Conversion
35
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(8) Definition of A-D Conversion Accuracy
• Differential non-linearity error
The deviation of the input voltage required to change output data
by “1,” from the corresponding ideal A-D conversion characteristics between 0 and VREF.
The definition of A-D conversion accuracy is described below.
1 Relative accuracy
• Zero transition error (V0T)
The deviation of the input voltage at which A-D conversion output
data changes from “0” to “1,” from the corresponding ideal A-D
conversion characteristics between 0 and VREF.
V0T =
Differential non-linearity error =
[ LSB]
• Full-scale transition error (VFST)
The deviation of the input voltage at which A-D conversion output
data changes from “255” to “254,” from the corresponding ideal AD conversion characteristics between 0 and VREF.
VFST =
(VREF – 3/2 ✕ VREF/256) – V254
Absolute accuracy error =
[ LSB]
1LSB
Vn – (1LSB ✕ n + V0)
Vn – 1LSBA ✕ (n + 1/2)
[ LSB]
1LSBA with respect to absolute accuracy =
V254 – V0
254
VREF
256
255
Full-scale transition error
(VFST)
254
3
LSBA
2
Differential nonlinearity error
1LSB
n+1
n
Actual A-D
conversion
characteristics
Non-linearity error
Absolute accuracy
1LSB A
1
LSB A
2
Ideal A-D conversion characteristics
between V 0 and V254
1LSB
0
V0 V1
Vn Vn+1
Zero transition error (V 0T)
Fig. 30. Definition of A-D Conversion Accuracy
36
[ LSB]
1LSBA
1LSB with respect to relative accuracy =
1LSB
Output
data
[ LSB]
Note: The analog input voltage “Vn” at which A-D conversion output
data changes from “n” to “n + 1” (n ; 0 to 254) is as follows
(refer to Figure 30) :
• Non-linearity error
The deviation of the actual A-D conversion characteristics, from the
ideal A-D conversion characteristics between V0 and V254.
Non-linearity error =
1LSB
2Absolute accuracy
• Absolute accuracy error
The deviation of the actual A-D conversion characteristics, from the
ideal A-D conversion characteristics between 0 and VREF.
(V0 – 1/2 ✕ VREF/256)
1LSB
(Vn+1 – Vn) – 1LSB
V254
VREF
Analog input
voltage ( V )
[V]
[V]
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
DATA SLICER
When the data slicer function is not used, the data slicer circuit can
be cut off by setting bit 0 of data slicer control register 1 (address
00EA16) to “0.” Also, the timing signal generating circuit can be cut
off by setting bit 0 of data slicer control register 2 (address 00EB16)
to “0.” These settings can realize the low-power dissipation.
The M37274EFSP includes the data slicer function for the closed
caption decoder (referred to as the CCD). This function takes out the
caption data superimposed in the vertical blanking interval of a
composite video signal. A composite video signal which makes the
sync chip’s polarity negative is input to the CVIN pin.
Composite
video
signal
0.1 µF
470Ω
1 kΩ
560 pF
Hundred of kiloohms
to 1 MΩ
CV IN
1 µF
15 kΩ
Sync pulse counter
register
(address 020F 16)
200 pF
HLF
HSYNC
RVCO
Synchronizing
signal counter
Clamping
circuit
Low-pass
filter
Sync slice
circuit
Data slicer control register 2
(address 00EB 16)
0
0 0
Synchronizing
separation
circuit
Timing signal
generating
circuit
VHOLD
Reference
voltage
generating
1000 pF circuit
+
Clock run-in
determination
circuit
–
Comparator
Data slice line
specification
circuit
Data slicer control
register 3
(address 0210 16)
Clock run-in detect
register 3
(address 0208 16)
Clock run-in
register 3
(address 0209 16)
External circuit
Note: Make the length of wiring which is
connected to V HOLD , HLF, RVCO
and CVIN pin as short as possible
so that a leakage current may
not be generated when mounting
a resistor or a capacitor on each
pin.
Start bit detecting
circuit
Data clock
generating circuit
16-bit shift register
high-order
Data slicer control register 1
(address 00EA 16)
0
0 0
Data slicer ON/OFF
Window register
(address 00E2 16)
0 0
0 1 0 1
Clock run-in register 1
(address 00E6 16)
1 0 0
Caption position register
(address 00E0 16)
Start bit position register
(address 00E1 16)
Clock run-in detect register 1
(address 00E8 16)
low-order
Clock run-in detect register 2
(address 00E9 16)
Data register 2
(address 00E5 16)
Sync slice register 3
(address 00E3 16)
0 0 0 0 1 0 1
Clock run-in register 2
(address 00E7 16)
1 0 0 1 1 1
1
Data register 4
(address 00ED 16)
Data register 1
(address 00E4 16) Interrupt request
generating circuit
Data slicer
interrupt
request
Data register 3
(address 00EC 16)
Data bus
Fig. 31. Data Slicer Block Diagram
37
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Figures 32 to 34 show the data slicer control registers.
Data Slicer Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
Data slicer control register 1(DSC1) [Address 00EA16]
B
0
Bit
Data slicer control bit
(DSC10)
1, 2 Field to be sliced data
selection bit
(DSC11, DSC12)
Functions
After reset
R W
0: Data slicer stopped
1: Data slicer operating
0
R W
Field of main
b1 data slice line
0
F2
1
F1
0
F1 and F2
1
F1 and F2
0
R W
0
R W
b2
0
0
1
1
Field for setting
refernce voltage
F2
F1
F2
F1
3, 4, Fix these bits to “0.”
6
5
Field determination
flag
(DSC15)
Indeterminate R —
0 : Hsep
Vsep
1 : Hsep
Vsep
7
Data latch completion
flag for caption data in
main data slice line
(DSC17)
0: Data is not yet latched
1: Data is latched
Definition of fields 1 (F1) and 2 (F2)
F1 : Hsep
VSYNC
Vsep
F2 : Hsep
VSYNC
Vsep
Fig. 32. Data Slicer Control Register 1
38
Indeterminate R W
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Data slicer Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
Data slicer Control register 2 (DSC2) [Address 00EB16]
B
After reset
R W
0
Timing signal generating
circuit control bit (DSC20)
Name
0: Stopped
1: Operating
Functions
0
R W
1
Reference clock source
selection bit (DSC21)
0: Video signal
1: HSYNC signal
0
R W
Indeterminate R —
Read-only
2, 7 Test bit
5
R W
0
3, 4, Fix these bits to “0.”
6
V-pulse shape determination 0: Match
flag (DSC25)
1: Mis match
Indeterminate R —
Fig. 33. Data Slicer Control Register 2
Data Slicer Control Register 3
b7 b6 b5 b4 b3 b2 b1 b0
Data slicer control register 3 (DSC3) [Address 021016]
B
0
Bit
Line selection bit for
slice voltage (DSC30)
1, 2 Field to be sliced data
selection bit
(DSC31, DSC32)
3
to
7
Functions
0: Main data slice line
1: Sub-data slice line
b2
0
0
1
1
Setting bit of sub-data
slice line
(DSC33 to DSC37)
Field of subb1 data slice line
0
F2
1
F1
0
F1 and F2
1
F1 and F2
Field for setting
refernce voltage
After reset
R W
0
R W
0
R W
0
R W
F2
F1
F2
F1
Definition of fields 1 (F1) and 2 (F2)
F1 : Hsep
VSYNC
Vsep
F2 : Hsep
VSYNC
Vsep
Fig. 34. Data Slicer Control Register 3
39
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(1) Clamping Circuit and Low-pass Filter
(2) Sync Slice Circuit
This filter attenuates the noise of the composite video signal input
from the CVIN pin. The CVIN pin to which composite video signal is
input requires a capacitor (0.1 µF) coupling outside. Pull down the
CVIN pin with a resistor of hundreds of kiloohms to 1 M . In addition,
we recommend to install externally a simple low-pass filter using a
resistor and a capacitor at the CVIN pin (refer to Figure 25).
This circuit takes out a composite sync signal from the output signal
of the low-pass filter. Figure 25 shows the structure of the sync slice
register.
Sync Slice Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
1
0
1
Sync slice register (SSL) [Address 00E3 16]
After reset
R W
Fix these bits to “1.”
0
R W
1, Fix these bits to “0.”
3 to 6
0
R W
0
R W
B
0, 2
7
Fig. 35. Sync Slice Register
40
Name
Vertical synchronous
signal (V sep) generating
method selection bit
(SSL7)
Functions
0: Method 1
1: Method 2
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(3) Synchronous Signal Separation Circuit
This circuit separates a horizontal synchronous signal and a vertical
synchronous signal from the composite sync signal taken out in the
sync slice circuit.
➀Horizontal synchronous signal (Hsep)
A one-shot horizontal synchronous signal Hsep is generated at
the falling edge of the composite sync signal.
➁Vertical synchronous signal (Vsep)
As a Vsep signal generating method, it is possible to select one of
the following 2 methods by using bit 7 of the sync slice register
(address 00E316).
•Method 1 The “L” level width of the composite sync signal is
measured. If this width exceeds a certain time, a Vsep
signal is generated in synchronization with the rising
of the timing signal immediately after this “L” level.
•Method 2 The “L” level width of the composite sync signal is
measured. If this width exceeds a certain time, it is
detected whether a falling of the composite sync
signal exits or not in the “L” level period of the timing
signal immediately after this “L” level. If a falling exists,
a Vsep signal is generated in synchronization with
the rising of the timing signal (refer to Figure 36).
Figure 36 shows a Vsep generating timing. The timing signal shown
in the figure is generated from the reference clock which the timing
generating circuit outputs.
Reading bit 5 of data slicer control register 2 permits determinating
the shape of the V-pulse portion of the composite sync signal. As
shown in Figure 38, when the A level matches the B level, this bit is
“0.” In the case of a mismatch, the bit is “1.”
For the pins RVCO and the HLF, connect a resistor and a capacitor
as shown in Figure 31. Make the length of wiring which is connected
to these pins as short as possible so that a leakage current may not
be generated.
Note: It takes a few tens of milliseconds until the reference clock
becomes stable after the data slicer and the timing signal
generating circuit are started. In this period, various timing
signals, Hsep signals and Vsep signals become unstable. For
this reason, take stabilization time into consideration when
programming.
Composite
sync signal
Measure “L” period
Timing
signal
V sep signal
A Vsep signal is generated at a rising of the timing signal
immediately after the “L” level width of the composite
sync signal exceeds a certain time.
Fig. 36. Vsep Generating Timing (method 2)
41
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(4) Timing Signal Generating Circuit
This circuit generates a reference clock which is 832 times as large
as the horizontal synchronous signal frequency. It also generates
various timing signals on the basis of the reference clock, horizontal
synchronous signal and vertical synchronizing signal. The circuit
operates by setting bit 0 of data slicer control register 2 (address
00EB16) to “1.”
The reference clock can be used as a display clock for OSD function
in addition to the data slicer. The HSYNC signal can be used as a
count source instead of the composite sync signal. However, when
the HSYNC signal is selected, the data slicer cannot be used. A count
source of the reference clock can be selected by bit 1 of data slicer
control register 2 (address 00EB16).
Bit 5 of
DSC2
0
Composite
sync signal
1
1
A
Fig. 37. Determination of V-pulse Waveform
42
B
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(5) Data Slice Line Specification Circuit
1Specification of data slice line
M37274MA-XXXSP has 2 data slice line specification circuits for
slicing arbitrary 2 Hsep in 1 field. The following 2 data slice lines
are specified .
<Main data slice line>
This line is specified by the caption position register (address
00E016).
<Sub-data slice line>
This line is specified by the data slicer control register 3 (address
00EB16).
The counter is reset at the falling edge of Vsep and is incremented
by 1 every Hsep pulse. When the counter value matched the value
specified by bits 4 to 0 of the caption position register (in case of
the sub-data slice line, by bits 3 to 7 of the data slicer control register
3), this Hsep is sliced.
The values of “0016” to “1F16” can be set in the caption position
register. Bit 7 to bit 5 are used for testing. Set “1002.” Figure 38
shows the signals in the vertical blanking interval. Figure 39 shows
the structure of the caption position register.
2 Selection of field to be sliced data
In the case of the main data slice line, the field to be sliced data is
selected by bits 2 and 1 of the data slicer control register 1 (address
00EA16). In the case of the sub-data slice line, the field is selected
by bits 2 and 1 of the data slicer control register 3. When bit 2 of
the data slicer control register 1 is set to “1,” it is possible to slice
data of both fields (refer to Figures 32 to 34).
3 Specification of line to set slice voltage
The reference voltage for slicing (slice voltage) is generated by
integrating the amplitude of the clock run-in pulse in the particular
line (refer to Table 4).
4 Field determination
The field determination flag can be read out by bit 5 of the data
slicer control register 1. This flag charge at the falling edge of
Vsep.
Vertical blanking interval
Video signal
Composite
video signal
Vsep
Line 21
Hsep
Count value to be set in the caption position register (“11 16” in this case)
Magnified
drawing
Hsep
Clock run-in
Composite video
signal
Start bit + 16-bit data
min. max.
Start bit
Time to be set in the
start bit position register
Fig. 38. Signals in Vertical Blanking Interval
43
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Table 4. Specifying of Field Whose Sets Reference Voltage
Bit 0 of DSC3
Field
Line
0
Field specified by bit 1 of DSC1
0: F2
1: F1
Line specified by bits 4 to 0 of CP
(Main data slice line)
1
Field specified by bit 1 of DSC3
0: F2
1: F1
Line specified by bits 7 to 3 of DSC3
(Sub-data slice line)
DSC1 : Data slice control register 1
DSC3 : Data slice control register 3
CP : Caption position register
(6) Reference Voltage Generating Circuit and
Comparator
The composite video signal clamped by the clamping circuit is input
to the reference voltage generating circuit and the comparator.
1 Reference voltage generating circuit
This circuit generates a reference voltage (slice voltage) by using
the amplitude of the clock run-in pulse in line specified by the data
slice line specification circuit. Connect a capacitor between the
VHOLD pin and the VSS pin, and make the length of wiring as short
as possible so that a leakage current may not be generated.
2 Comparator
The comparator compares the voltage of the composite video signal
with the voltage (reference voltage) generated in the reference
voltage generating circuit, and converts the composite video signal
into a digital value.
Caption Position Register
b7 b6 b5 b4 b3 b2 b1 b0
1
0
0
Caption Position Register (CP) [Address 00E0 16]
B
Name
0 Specification main data
to slice line (CP0 to CP4)
4
5, 6 Fix these bits to “0.”
7
Fig. 39. Caption Position Register
44
Fix this bit to “0.”
Functions
After reset
R W
0
R W
0
R W
0
R W
RY
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(7) Start Bit Detecting Circuit
This circuit detects a start bit at line decided in the data slice line
specification circuit. For start bit detection, it is possible to select one
of the following two types by using bit 1 of clock run-in register 2
(address 00E716).
1After the lapse of the time corresponding to the set value of the
start bit position register (address 00E116), the first rising of the
composite video signal is detected as a start bit.
The time is set in bits 0 to 6 of the start bit position register (address
00E1 16) (refer to Figure 40). Set a value fit for the following
conditions.
Figure 40 shows the structure of the start bit position register.
Time from the falling of the horizontal
synchronizing signal to the last rising
of the clock run-in
4 ✕ set value of the start bit position
register ✕ reference clock period
<
<
Time from the faling of the horizontal
synchronous signal to occurrence of
the start bit
Start Bit Position Register
b7 b6 b5 b4 b3 b2 b1 b0
Start bit position register (SP) [Address 00E116]
B
Name
Functions
After reset
R W
0
to
6
Start bit generating time Time from a falling of the horizontal
(SP0 to SP6)
synchronous signal to occurrence
of a start bit =
4 ✕ set value (“00 16” to “7F16”) ✕
reference clock period
0
R W
7
DSC1 bit 7 control bit
(SP7)
0
R W
0 : Generation of 16 pulses
1 : Generation of 16 pulses and
detection of clock run-in
pulse (4 to 6 pulses)
Fig. 40. Start Bit Position Register
45
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2After a falling of the clock run-in pulse set in bits 2 to 0 of clock runin detect register 2 (address 00E9 16) is detected, a start bit is
detected by sampling a comparator output. A sampling clock for
sampling is obtained by dividing the reference clock generated in
the timing signal generating circuit by 13.
Figure 42 shows the structure of clock run-in detect register 2.
The contents of bits 2 to 0 of clock run-in detect register 2 and bit
1 of clock run-in register 2 are written at a falling of the horizontal
synchronous signal. For this reason, even if an instruction for setting
is executed, the contents of the register cannot be rewritten until a
falling of the horizontal synchronous signal.
Clock Run-in Register 2
b7 b6 b5 b4 b3 b2 b1 b0
1
0
0
1
1
1
1
Clock run-in register 2 (CR2) [Address 00E716]
B
Name
Functions
After reset
R W
0
R W
0
R W
0
R W
0,
Fix these bits to “1.”
2 to 4,
7
1
Start bit detecting
method selection bit
(CR21)
5, 6
Fix these bits to “0.”
0: Method 1
1: Method 2
Fig. 41. Clock Run-in Register 2
Clock Run-in Detect Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Clock run-in detect register 2 (CRD2) [Address 00E916]
Fig. 42. Clock Run-in Detect Register 2
46
Functions
After reset
R W
b0
0 : Not available
1 : 1st pulse
0 : 2nd pulse
1 : 3rd pulse
0 : 4th pulse
1 : 5th pulse
0 : 6th pulse
1 : 7th pulse
0
R W
Time from detection of a start
bit to occurrence of a data clock
= (13 + set value) ✕
reference clock period
0
R W
B
Name
0
to
2
Clock run-in pulses for
sampling
(CRD20 to CRD22)
b2
0
0
0
0
1
1
1
1
3
to
7
Data clock generating
time
(CRD23 to CRD27)
b1
0
0
1
1
0
0
1
1
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(8) Clock run-in determination circuit
This circuit sets a window in the clock run-in portion in the composite
video signal, and then determinates clock run-in by counting the
number of pulses in this window. Set the time from a falling of the
horizontal synchronizing signal to a start of the window by bits 0 to 5
of the window register (address 00E216; refer to Figure 43). The
window ends according to the contents of the setting of the start bit
position register (refer to Figure 40).
Window Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Window register (WN) [Address 00E2 16]
B
0
to
5
Name
Window start time
(WN0 to WN5)
6, 7 Fix these bits to “0.”
Functions
Time from a falling of the horizontal
synchronous signal to start of the
window =
4 ✕ set value (“00 16” to “3F16”) ✕
reference clock period
After reset
R W
0
R W
0
R W
Fig. 43. Window Register
47
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
For the main data slice line, the count value of pulses in the window
is stored in clock run-in register 1 (address 00E616; refer to Figure
44). For the sub-data slice line, the count value of pulses in the window
is stored in clock run-in register (address 020916; refer to Figure 45).
When this count value is 4 to 6, it is determined as a clock run-in.
Accordingly, set the count value so that the window may start after
the first pulse of the clock run-in (refer to Figure 46).
The contents to be set in the window register are written at a falling
of the horizontal synchronous signal. For this reason, even if an
instruction for setting is executed, the contents of the register cannot
be rewritten until a falling of the horizontal synchronous signal.
For the main data slice line, reference clock is counted in the period
from a falling of the clock pulse set in bits 0 to 2 of clock run-in detect
register 2 (address 00E916) to the next falling. The count value is
stored in bits 3 to 7 of clock run-in detect register 1 (address 00E816)
(When the count value exceeds “1F16,” “1F16” is held). For the subdata slice line, the count value is stored in bits 3 to 7 of clock run-in
detect register 3 (address 020816). Read out these bits after the
occurence of a data slicer interrupt (refer to (11) Interrupt Request
Generating Circuit).
Figure 48 shows the structure of clock run-in detect registers 1 and
3.
Clock Run-in Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
1
0
1
Clock run-in register 1 (CR1) [Address 00E6 16]
After reset
R W
0
to
3
Clock run-in count value
of main-data slice line
(CR10 to CR13)
0
R W
4, 6
Fix these bits to “1.”
0
R W
5, 7
Fix these bits to “0.”
0
R W
B
Fig. 44. Clock Run-in Register 1
48
Name
Functions
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Clock Run-in Register 3
b7 b6 b5 b4 b3 b2 b1 b0
Clock run-in register 3 (CR3) [Address 020916]
B
Name
Functions
0
to
3
4
Clock run-in count value of
sub-data slice line (CR30
to CR33)
Data latch completion flag
for caption data in subdata slice line (CR34)
5
After reset
R W
0
R W
0: Data is not latched yet
1: Data is latched
Indeterminate R W
Data slice line selection bit
for interrupt request
(CR35)
0: Main data slice line
1: Sub- data slice line
Indeterminate R W
6
Interrupt mode selection bit
(CR36)
0: Interrupt occurs at end
of data slice line
1: Interrupt occurs at
completion of caption
data latch
Indeterminate R W
7
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
Indeterminate R —
Fig. 45. Clock Run-in Register 3
Horizontal
synchronous
signal
Start bit data +
16-bit data
Clock run-in
Composite
video signal
Window
Time to be set in the
window register
Time to be set in
the start bit position
register
✽When the count value
in the window is 4 to 6,
this is determined as a
clock run-in.
Fig. 46. Window Setting
Clock Run-in Detect Register i
b7 b6 b5 b4 b3 b2 b1 b0
Clock run-in detect register i (CRDi) (i=1, 3) [Addresses 00E8 16, 020816]
After reset
R W
0
to
2
Test bits
Read-only
0
R W
3
to
7
Clock run-in detection bits
(CRDi3 to CRDi7)
Number of reference clock s
to be counted one clock runin pulse period
0
R —
B
Name
Functions
Fig. 47. Clock Run-in Detect Registers 1 and 3
49
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(9) Data clock generating circuit
This circuit generates a data clock synchronized with the start bit
detected in the start bit detecting circuit.
Set the time from detection of the start bit to occurrence of the data
clock in bits 3 to 7 of clock run-in detect register 2 (address 00E916).
The time to be set is represented by the following expression:
Time = (13 + set value) ✕ reference clock period
been generated, bit 7 of the data slicer control register is set to “1”
(refer to Figure 32 to 34). When method 1 is already selected as a
start bit detecting method, this bit becomes a logical product (AND)
value with a clock run-in determination result by setting bit 7 of the
start bit position register to “1.”
When method 2 is already selected as a start bit detecting method
and 16 pulses are generated of a data clock regardless of bit 7 of the
start bit position register, this bit is set to “1.” The contents of this bit
are reset at a falling of the vertical synchronizing signal (Vsep).
For a data clock, 16 pulses are generated. When just 16 pulses have
Table 5. Setting Conditions for Caption Data Latch Completion Flag
Conditions for Setting Bit 7 of DSC1 to “1”
Bit 7 of SP
Conditions for Setting Bit 4 of DSC3 to “1”
0
Data clock of 16 pulses has occured in main data slaice line
Data clock of 16 pulses has occured in sub-data slaice line
1
Data clock of 16 pulses has occured in main data slaice line
Data clock of 16 pulses has occured in sub-data slaice line
AND
AND
Clock run-in pulse are detected 4 to 6 times
Clock run-in pulse are detected 4 to 6 times
(10) 16-bit Shift Register
(11) Interrupt Request Generating Circuit
The caption data converted into a digital value by the comparator is
stored into the 16-bit shift register in synchronization with the data
clock. For the main data slice line, the contents of the high-order 8
bits of the stored caption data and the contents of the low-order 8
bits of the same data can be obtained by reading out data register 2
(address 00E516) and data register 1 (address 00E416), respectively.
For the sub-data slice line, the contents of the high-order 8 bits and
the contents of the low-order 8 bits can be obtained by reading out
the data register 4 (address 00ED16) and data register 3 (address
00EC16), respectively. These registers are reset to “0” at a falling of
Vsep. Read out data registers 1 and 2 after the occurence of a data
slicer interrupt (refer to (11) Interrupt Request Generating Circuit).
The interrupt requests as shown in Table 6 are generated by
combination of the following bits; bits 5 and 6 of the clock run-in register
3 (address 020916), bit 1 of the clock run-in register 2 (address
00E716). Read out the contents of data registers 1 to 4 and the
contents of bits 3 to 7 of clock run-in detect registers 1 and 3 after the
occurence of a data slicer interrupt request.
Table 6. Occurence Sources of Interrupt Request
CR3
b5
CR2
b6
b1
Occurence Souces of Interrupt Request
Slice line
0
0
1
Main data slice line
0
0
Data clock of 16 pulses has occured
AND
Clock run-in pulse are detected 4 to 6 times
1
Data clock of 16 pulses has occured
0
At end of data slice line
1
0
1
1
0
1
1
50
Sources
At end of data slice line
Sub-data slice line
Data clock of 16 pulses has occured
AND
Clock run-in pulse are detected 4 to 6 times
Data clock of 16 pulses has occured
MITSUBISHI MICROCOMPUTERS
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M37274EFSP
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(12) Synchronous Signal Counter
The synchronous signal counter counts the composite sync signal
taken out from a video signal in the data slicer circuit or the vertical
synchronous signal Vsep as a count source.
The count value in a certain time (T time) generated by f(XIN)/213 or
f(XIN)/213 is stored into the 5-bit latch. Accordingly, the latch value
changes in the cycle of T time. When the count value exceeds “1F16,”
“1F16” is stored into the latch.
The latch value can be obtained by reading out the sync pulse counter
register (address 020F16). A count source is selected by bit 5 of the
sync pulse counter register.
The synchronous signal counter is used when bit 0 of PWM mode
register 1 (address 02EA16).
Figure 48 shows the structure of the sync pulse counter and Figure
49 shows the synchronous signal counter block diagram.
Sync Pulse Counter Register
b7 b6 b5 b4 b3 b2 b1 b0
Sync pulse counter register (SYC) [Address 020F16]
B
Name
0
to
4
Count value
(SYC0 to SYC4)
5
Count source (SYC5)
Functions
0: HSYNC signal
1: Composite sync signal
6, 7 Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
After reset
R W
0
R —
0
R W
0
R —
Fig. 48. Sync Pulse Counter Register
f(XIN)/213
Composite
sync signal
Reset
HSYNC signal
b5
Selection gate : connected to black
colored side when
reset.
5-bit counter
Counter
Latch (5 bits)
Sync pulse
counter register
Data bus
Fig. 49. Synchronous Signal Counter Block Diagram
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
MULTI-MASTER I2C-BUS INTERFACE
Table 7. Multi-master I2C-BUS Interface Functions
The multi-master I2C-BUS interface is a serial communications circuit, conforming to the Philips I2C-BUS data transfer format. This
interface, offering both arbitration lost detection and a synchronous
functions, is useful for the multi-master serial communications.
Figure 50 shows a block diagram of the multi-master I2C-BUS interface and Table 7 shows multi-master I2C-BUS interface functions.
This multi-master I2C-BUS interface consists of the I2C address register, the I2C data shift register, the I2C clock control register, the I2C
control register, the I2C status register and other control circuits.
Function
Item
Format
In conformity with Philips I2C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
Communication mode
In conformity with Philips I2C-BUS
standard:
Master transmission
Master reception
Slave transmission
Slave reception
SCL clock frequency
16.1 kHz to 400 kHz (at φ = 4 MHz)
φ : System clock = f(XIN)/2
Note: We are not responsible for any third party’s infringement of
patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the I2C control register at address
00F916) for connections between the I2C-BUS interface and
ports (SCL1, SCL2, SDA1, SDA2).
b7
I2C address register (S0D)
b0
Interrupt
generating
circuit
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
Interrupt
request signal
(IICIRQ)
Address comparator
Serial
data
(SDA)
Noise
elimination
circuit
Data
control
circuit
b7
b0
I 2 C data shift register
b7
S0
b0
AL AAS AD0 LRB
MST TRX BB PIN
I 2 C status
register (S1)
AL
circuit
Internal data bus
BB
circuit
Serial
clock
(SCL)
Noise
elimination
circuit
Clock
control
circuit
b7
ACK
b0
ACK FAST
CCR4 CCR3 CCR2 CCR1 CCR0
BIT MODE
I2 C clock control register (S2)
Clock division
Fig. 50. Block Diagram of Multi-master I2C-BUS Interface
52
b7
BSEL1 BSEL0
b0
10BIT
SAD
ALS
ESO BC2 BC1 BC0
I2C clock control register (S1D)
System clock ( )
Bit counter
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(1) I2C Data Shift Register
The I2C data shift register (S0 : address 00F616) is an 8-bit shift
register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to the
outside from bit 7 in synchronization with the SCL clock, and each
time one-bit data is output, the data of this register are shifted one bit
to the left. When data is received, it is input to this register from bit 0
in synchronization with the SCL clock, and each time one-bit data is
input, the data of this register are shifted one bit to the left.
The I2C data shift register is in a write enable status only when the
ESO bit of the I2C control register (address 00F916) is “1.” The bit
counter is reset by a write instruction to the I2C data shift register.
When both the ESO bit and the MST bit of the I2C status register
(address 00F816) are “1,” the SCL is output by a write instruction to
the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ESO bit value.
Note: To write data into the I2C data shift register after setting the
MST bit to “0” (slave mode), keep an interval of 8 machine
cycles or more.
I2C Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0
2
I C data shift register1(S0) [Address 00F6 16]
B
0
to
7
Name
Functions
D0 to D7
This is an 8-bit shift register to store
receive data and write transmit data.
After reset
R W
Indeterminate R W
Note: To write data into the I2C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
Fig. 51. I2C Address Register
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(2) I2C Address Register
The I2C address register (address 00F716) consists of a 7-bit slave
___
address and a read/write bit. In the addressing mode, the slave address written in this register is compared with the address data to be
received immediately after the START condition are detected.
____
■ Bit 0: Read/Write Bit (RBW)
Not used when comparing addresses, in the 7-bit addressing mode.
In the 10-bit addressing mode, the first address data to be received
is compared with the contents (SAD6 to SAD0 + RBW) of the I2C
address register.
The RBW bit is cleared to “0” automatically when the stop condition
is detected.
■ Bits 1 to 7: Slave Address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing mode, the address data transmitted from the master is compared with the contents of these bits.
I2C Address Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C address register (S0D) [Address 00F716]
B
Fig. 52. I2C Address Register
54
0
1
to
7
Name
Functions
After reset R W
Read/write bit
(RBW)
0: Read
1: Write
0
R —
Slave address
(SAD0 to SAD6)
The address data transmitted from
the master is compared with the
contents of these bits.
0
R W
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(3) I2C Clock Control Register
The I2C clock control register (address 00FA16) is used to set ACK
control, SCL mode and SCL frequency.
■ Bits 0 to 4: SCL Frequency Control Bits (CCR0–CCR4)
These bits control the SCL frequency. Refer to Table 7.
■ Bit 5: SCL Mode Specification Bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to “0,” the standard clock mode is set. When the bit is set to “1,” the high-speed
clock mode is set.
■ Bit 6: ACK Bit (ACK BIT)
This bit sets the SDA status when an ACK clock✽ is generated. When
this bit is set to “0,” the ACK return mode is set and SDA goes to
LOW at the occurrence of an ACK clock. When the bit is set to “1,”
the ACK non-return mode is set. The SDA is held in the HIGH status
at the occurrence of an ACK clock.
However, when the slave address matches the address data in the
reception of address data at ACK BIT = “0,” the SDA is automatically
made LOW (ACK is returned). If there is a mismatch between the
slave address and the address data, the SDA is automatically made
HIGH (ACK is not returned).
■ Bit 7: ACK Clock Bit (ACK)
This bit specifies a mode of acknowledgment which is an acknowledgment response of data transmission. When this bit is set to “0,”
the no ACK clock mode is set. In this case, no ACK clock occurs
after data transmission. When the bit is set to “1,” the ACK clock
mode is set and the master generates an ACK clock upon completion of each 1-byte data transmission.The device for transmitting
address data and control data releases the SDA at the occurrence of
an ACK clock (make SDA HIGH) and receives the ACK bit generated by the data receiving device.
Note: Do not write data into the I2C clock control register during transmission. If data is written during transmission, the I 2C clock
generator is reset, so that data cannot be transmitted normally.
✽ACK clock: Clock for acknowledgement
I2C Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0
I2 C clock control register (S2 : address 00FA16)
B
0
to
4
Name
Functions
SCL frequency control bits Setup value of Standard clock
(CCR0 to CCR4)
CCR4–CCR0
mode
00 to 02
After reset R W
High speed
clock mode
0
R W
Setup disabled Setup disabled
03
Setup disabled
04
Setup disabled
333
250
05
100
400 (See note)
06
83.3
166
...
500/CCR value
1000/CCR value
1D
17.2
34.5
1E
16.6
33.3
1F
16.1
32.3
(at φ = 4 MHz, unit : kHz)
5
SCL mode
specification bit
(FAST MODE)
0 : Standard clock mode
1 : High-speed clock mode
0
R W
6
ACK bit
(ACK BIT)
0 : ACK is returned.
1 : ACK is not returned.
0
R W
7
ACK clock bit
(ACK)
0 : No ACK clock
1 : ACK clock
0
R W
Note: At 4000kHz in the high-speed clock mode, the duty is as below .
“0” period : “1” period = 3 : 2
In the other cases, the duty is as below.
“0” period : “1” period = 1 : 1
Fig. 53. I2C Address Register
55
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(4) I2C Control Register
The I2C control register (address 00F916) controls the data communication format.
■ Bits 0 to 2: Bit Counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be
transmitted. An interrupt request signal occurs immediately after the
number of bits specified with these bits are transmitted.
When a START condition is received, these bits become “0002” and
the address data is always transmitted and received in 8 bits.
■ Bit 3: I2C Interface Use Enable Bit (ESO)
This bit enables usage of the multimaster I2C BUS interface. When
this bit is set to “0,” the use disable status is provided, so the SDA
and the SCL become high-impedance. When the bit is set to “1,” use
of the interface is enabled.
When ESO = “0,” the following is performed.
PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I2C
status register at address 00F816 ).
Writing data to the I2C data shift register (address 00F616) is disabled.
•
•
■ Bit 4: Data Format Selection Bit (ALS)
This bit decides whether or not to recognize slave addresses. When
this bit is set to “0,” the addressing format is selected, so that address data is recognized. When a match is found between a slave
address and address data as a result of comparison or when a general call (refer to “(5) I2C Status Register,” bit 1) is received, transmission processing can be performed. When this bit is set to “1,” the
free data format is selected, so that slave addresses are not recognized.
■ Bit 5: Addressing Format Selection Bit (10BIT SAD)
This bit selects a slave address specification format. When this bit is
set to “0,” the 7-bit addressing format is selected. In this case, only
the high-order 7 bits (slave address) of the I2C address register (address 00F716) are compared with address data. When this bit is set
to “1,” the 10-bit addressing format is selected, all the bits of the I2C
address register are compared with address data.
■ Bits 6 and 7: Connection Control Bits between I2C-BUS Interface
and Ports (BSEL0, BSEL1)
These bits controls the connection between SCL and ports or SDA
and ports (refer to Figure 55).
“0”
“1” BSEL0
SCL1/P11
SCL
Multi-master
I2C-BUS
interface
SDA
“0”
“1” BSEL1
SCL2/P12
“0”
“1” BSEL0
SDA1/P1 3
“0”
“1” BSEL1
SDA2/P1 4
Note: When using multi-master I2C-BUS interface, set bits 3 and
4 of the serial I/O mode register (address 021316) to “1.”
Moreover, set the corresponding direction register to “1” to
use the port as multi-master I2C-BUS interface.
Fig. 54. Connection Port Control by BSEL0 and BSEL1
56
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
I2C Control Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C control register (S1D : address 00F9 16)
B
Name
Functions
0
to
2
Bit counter
(Number of transmit/recieve
bits)
(BC0 to BC2)
b2
0
0
0
0
1
1
1
1
3
I2 C-BUS interface use
enable bit (ESO)
4
5
b0
0:
1:
0:
1:
0:
1:
0:
1:
After reset R W
0
R W
0 : Disabled
1 : Enabled
0
R W
Data format selection bit
(ALS)
0 : Addressing mode
1 : Free data format
0
R W
Addressing format selection
bit (10BIT SAD)
0 : 7-bit addressing format
1 : 10-bit addressing format
0
R W
b7 b6 Connection port (See note)
0 0 : None
0 1 : SCL1, SDA1
1 0 : SCL2, SDA2
1 1 : SCL1, SDA1
SCL2, SDA2
0
R W
6, 7 Connection control bits
between I2C-BUS interface
and ports
b1
0
0
1
1
0
0
1
1
8
7
6
5
4
3
2
1
Note: When using ports P1 1 -P14 as I2C-BUS interface, the output structure changes
automatically from CMOS output to N-channel open-drain output.
Fig. 55. I2C Control Register
57
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(5) I2C Status Register
The I2C status register (address 00F816) controls the I2C-BUS interface status. The low-order 4 bits are read-only bits and the highorder 4 bits can be read out and written to.
■ Bit 0: Last Receive Bit (LRB)
This bit stores the last bit value of received data and can also be
used for ACK receive confirmation. If ACK is returned when an ACK
clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit
is set to “1.” Except in the ACK mode, the last bit value of received
data is input. The state of this bit is changed from “1” to “0” by executing a write instruction to the I2C data shift register (address 00F616).
■ Bit 1: General Call Detecting Flag (AD0)
This bit is set to “1” when a general call✽ whose address data is all “0”
is received in the slave mode. By a general call of the master device,
every slave device receives control data after the general call. The
AD0 bit is set to “0” by detecting the STOP condition or START condition.
✽General call: The master transmits the general call address “0016”
to all slaves.
■ Bit 2: Slave Address Comparison Flag (AAS)
This flag indicates a comparison result of address data.
1 In the slave receive mode, when the 7-bit addressing format is
selected, this bit is set to “1” in one of the following conditions.
The address data immediately after occurrence of a START
condition matches the slave address stored in the high-order
7 bits of the I2C address register (address 00F716).
A general call is received.
2 In the slave reception mode, when the 10-bit addressing format is
selected, this bit is set to “1” with the following condition.
When the address data is compared with the I 2C address
register (8 bits consists of slave address and RBW), the first
bytes match.
3 The state of this bit is changed from “1” to “0” by executing a write
instruction to the I2C data shift register (address 00F616). ■ Bit 3:
Arbitration Lost✽ Detecting Flag (AL)
In the master transmission mode, when a device other than the microcomputer sets the SDA to “L,”, arbitration is judged to have been
lost, so that this bit is set to “1.” At the same time, the TRX bit is set to
“0,” so that immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to “0.” When arbitration
is lost during slave address transmission, the TRX bit is set to “0”
and the reception mode is set. Consequently, it becomes possible to
receive and recognize its own slave address transmitted by another
master device.
•
•
•
✽Arbitration lost: The status in which communication as a master is
disabled.
■ Bit 4: I2C-BUS Interface Interrupt Request Bit (PIN)
This bit generates an interrupt request signal. Each time 1-byte data
is transmitted, the state of the PIN bit changes from “1” to “0.” At the
same time, an interrupt request signal is sent to the CPU. The PIN bit
is set to “0” in synchronization with a falling edge of the last clock
(including the ACK clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling edge of the PIN
bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock
58
generation is disabled. Figure 57 shows an interrupt request signal
generating timing chart.
The PIN bit is set to “1” in any one of the following conditions.
Executing a write instruction to the I2C data shift register (address
00F616).
When the ESO bit is “0”
At reset
The conditions in which the PIN bit is set to “0” are shown below:
Immediately after completion of 1-byte data transmission (including when arbitration lost is detected)
Immediately after completion of 1-byte data reception
In the slave reception mode, with ALS = “0” and immediately after
completion of slave address or general call address reception
In the slave reception mode, with ALS = “1” and immediately after
completion of address data reception
■ Bit 5: Bus Busy Flag (BB)
This bit indicates the status of use of the bus system. When this bit is
set to “0,” this bus system is not busy and a START condition can be
generated. When this bit is set to “1,” this bus system is busy and the
occurrence of a START condition is disabled by the START condition duplication prevention function (Note).
This flag can be written by software only in the master transmission
mode. In the other modes, this bit is set to “1” by detecting a START
condition and set to “0” by detecting a STOP condition. When the
ESO bit of the I2C control register (address 00F916) is “0” and at
reset, the BB flag is kept in the “0” state.
•
•
•
•
•
•
•
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
■ Bit 6: Communication Mode Specification Bit (transfer direction
specification bit: TRX)
This bit decides the direction of transfer for data communication. When
this bit is “0,” the reception mode is selected and the data of a transmitting device is received. When the bit is “1,” the transmission mode
is selected and address data and control data are output into the
SDA in synchronization with the clock generated on the SCL.
When the ALS bit of the I2C control register (address 00F916) is “0”
in the slave reception mode is selected,
the TRX bit is set to “1”
__
(transmit) if the least significant bit (R/W bit) of the address data__transmitted by the master is “1.” When the ALS bit is “0” and the R/W bit is
“0,” the TRX bit is cleared to “0” (receive).
The TRX bit is cleared to “0” in one of the following conditions.
When arbitration lost is detected.
When a STOP condition is detected.
When occurence of a START condition is disabled by the START
condition duplication prevention function (Note).
With MST = “0” and when a START condition is detected.
With MST = “0” and when ACK non-return is detected.
At reset
•
•
•
•
•
•
■ Bit 7: Communication Mode Specification Bit (master/slave specification bit: MST)
This bit is used for master/slave specification for data communication. When this bit is “0,” the slave is specified, so that a START
condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with
the clock generated by the master. When this bit is “1,” the master is
specified and a START condition and a STOP condition are generated, and also the clocks required for data communication are generated on the SCL.
The MST bit is cleared to “0” in one of the following conditions.
Immediately after completion of 1-byte data transmission when arbitration lost is detected
When a STOP condition is detected.
When occurence of a START condition is disabled by the START
condition duplication preventing function (Note).
At reset
•
•
•
•
Note: The START condition duplication prevention function disables
the START condition generation, reset of bit counter reset,
and SCL output, when the following condition is satisfied:
• a START condition is set by another master device.
I2C Status Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C status register (S1) [Address 00F816]
B
Name
Functions
0
Last receive bit (LRB)
(See note)
0 : Last bit = “0 ”
1 : Last bit = “1 ”
1
General call detecting flag
(AD0) (See note)
2
After reset R W
Indeterminate
R —
0 : No general call detected
1 : General call detected
0
R —
Slave address comparison
flag (AAS) (See note)
0 : Address mismatch
1 : Address match
0
R —
3
Arbitration lost detecting flag
(AL) (See note)
0 : Not detected
1 : Detected
0
R —
4
I2C-BUS interface interrupt
request bit (PIN)
0 : Interrupt request issued
1 : No interrupt request issued
0
R —
5
Bus busy flag (BB)
0 : Bus free
1 : Bus busy
0
R W
b7
0
0
1
1
0
R W
6, 7 Communication mode
specification bits
(TRX, MST)
b6
0 : Slave recieve mode
1 : Slave transmit mode
0 : Master recieve mode
1 : Master transmit mode
Note : These bits and flags can be read out, but cannnot be written.
Fig. 56. I2C Status Register
59
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
SCL
PIN
IICIRQ
Fig. 57. Interrupt Request Signal Generation Timing
(6) START Condition Generation Method
When the ESO bit of the I2C control register (address 00F916) is “1,”
execute a write instruction to the I2C status register (address 00F816)
to set the MST, TRX and BB bits to “1.” A START condition will then
be generated. After that, the bit counter becomes “0002” and an SCL
for 1 byte is output. The START condition generation timing and BB
bit set timing are different in the standard clock mode and the highspeed clock mode. Refer to Figure 58 for the START condition generation timing diagram, and Table 8 for the START condition/STOP
condition generation timing table.
I2C status register
write signal
SCL
SDA
Setup
time
Set time for
BB flag
BB flag
Setup
time
Fig. 58. START Condition Generation Timing Diagram
(7) RESTART Condition Generation Method
To generate the RESTART condition, take the following sequence:
1Set “2016” to the I2C status register (S1).
2Write a transmit data to the I2C data shift register.
3Set “F016” to the I2C status register (S1) again.
<Example of Setting of RESTART Condition>
I2C status register
; S1 = 2016
I2C data shift register ; S0 = transmit data after restart
I2C status register
; S1 = F016
60
Hold time
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(8) STOP Condition Generation Method
(9) START/STOP Condition Detect Conditions
When the ES0 bit of the I2C control register (address 00F916) is “1,”
execute a write instruction to the I2C status register (address 00F816)
for setting the MST bit and the TRX bit to “1” and the BB bit to “0”. A
STOP condition will then be generated. The STOP condition generation timing and the BB flag reset timing are different in the standard
clock mode and the high-speed clock mode. Refer to Figure 51 for
the STOP condition generation timing diagram, and Table 8 for the
START condition/STOP condition generation timing table.
The START/STOP condition detect conditions are shown in Figure
52 and Table 9. Only when the 3 conditions of Table 9 are satisfied,
a START/STOP condition can be detected.
SCL release time
I2C status register
write signal
SCL
SDA
BB flag
Note: When a STOP condition is detected in the slave mode
(MST = 0), an interrupt request signal “IICIRQ” is generated
to the CPU.
SCL
Setup
time
Hold time
Reset time for
BB flag
SDA
(START condition)
Setup
time
Hold time
Setup
time
Hold time
SDA
(STOP condition)
Fig. 59. STOP Condition Generation Timing Diagram
Fig. 60. START Condition/STOP Condition Detect Timing
Diagram
Table 8. START Condition/STOP Condition Generation Timing
Table
Item
Standard Clock Mode High-speed Clock Mode
Setup time
5.0 µs (20 cycles)
2.5 µs (10 cycles)
Hold time
5.0 µs (20 cycles)
2.5 µs (10 cycles)
Set/reset time
3.0 µs (12 cycles)
1.5 µs (6 cycles)
for BB flag
Table 9. START Condition/STOP Condition Detect Conditions
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles.
High-speed Clock Mode
Standard Clock Mode
1.0 µs (4 cycles) < SCL
6.5 µs (26 cycles) < SCL
release time
release time
3.25 µs (13 cycles) < Setup time 0.5 µs (2 cycles) < Setup time
3.25 µs (13 cycles) < Hold time 0.5 µs (2 cycles) < Hold time
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles.
61
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(10) Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective address communication formats is described below.
➀ 7-bit addressing format
To meet the 7-bit addressing format, set the 10BIT SAD bit of the
I2C control register (address 00F916) to “0.” The first 7-bit address
data transmitted from the master is compared with the high-order
7-bit slave address stored in the I2C address register (address
00F716). At the time of this comparison, address comparison of
the RBW bit of the I2C address register (address 00F716) is not
made. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 61, (1) and (2).
➁ 10-bit addressing format
To meet the 10-bit addressing format, set the 10BIT SAD bit of the
I2C control register (address 00F916) to “1.” An address comparison is made between the first-byte address data transmitted from
the master and the 7-bit slave address stored in the I2C address
register (address 00F716). At the time of this comparison, an address comparison between the RBW
bit of the I2C address regis__
ter (address 00F716) and the R/W bit which is the last bit of the
address data transmitted__from the master is made. In the 10-bit
addressing mode, the R/W bit which is the last bit of the address
data not only specifies the direction of communication for control
data but also is processed as an address data bit.
When the first-byte address data matches the slave address, the
AAS bit of the I2C status register (address 00F816) is set to “1.” After
the second-byte address data is stored into the I2C data shift register
(address 00F616), make an address comparison between the second-byte data and the slave address by software. When the address
data of the 2nd bytes matches the slave address, set the RBW bit of
the I2C address register (address 00F716) to “1” by __
software. This
processing can match the 7-bit slave address and R/W data, which
are received after a RESTART condition is detected, with the value
of the I2C address register (address 00F716). For the data transmission format when the 10-bit addressing format is selected, refer to
Figure 61, (3) and (4).
(11) Example of Master Transmission
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz and in the ACK return mode is shown
below.
➀ Set a slave address in the high-order 7 bits of the I2C address
register (address 00F716) and “0” in the RBW bit.
➁ Set the ACK return mode and SCL = 100 kHz by setting “8516” in
the I2C clock control register (address 00FA16).
➂ Set “1016” in the I2C status register (address 00F816) and hold
the SCL at the HIGH.
➃ Set a communication enable status by setting “4816” in the I2C
control register (address 00F916).
➄ Set the address data of the destination of transmission in the highorder 7 bits of the I2C data shift register (address 00F616) and set
“0” in the least significant bit.
➅ Set “F016” in the I2C status register (address 00F816) to generate
a START condition. At this time, an SCL for 1 byte and an ACK
clock automatically occurs.
62
➆ Set transmit data in the I2C data shift register (address 00F616).
At this time, an SCL and an ACK clock automatically occurs.
➇ When transmitting control data of more than 1 byte, repeat step
➆.
➈ Set “D016” in the I2C status register (address 00F816). After this,
if ACK is not returned or transmission ends, a STOP condition will
be generated.
(12) Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the
SCL frequency of 400 kHz, in the ACK non-return mode, using the
addressing format, is shown below.
➀ Set a slave address in the high-order 7 bits of the I2C address
register (address 00F716) and “0” in the RBW bit.
➁ Set the no ACK clock mode and SCL = 400 kHz by setting “2516”
in the I2C clock control register (address 00FA16).
➂ Set “1016” in the I2C status register (address 00F816) and hold
the SCL at the HIGH.
➃ Set a communication enable status by setting “4816” in the I2C
control register (address 00F916).
➄ When a START condition is received, an address comparison is
made.
➅ •When all transmitted addresses are “0” (general call) :
AD0 of the I2C status register (address 00F816) is set to “1” and
an interrupt request signal occurs.
•When the transmitted addresses match the address set in ➀:
AAS of the I2C status register (address 00F816) is set to “1” and
an interrupt request signal occurs.
•In the cases other than the above :
AD0 and AAS of the I2C status register (address 00F816) are
set to “0” and no interrupt request signal occurs.
➆ Set dummy data in the I2C data shift register (address 00F616).
➇ When receiving control data of more than 1 byte, repeat step ➆.
➈ When a STOP condition is detected, the communication ends.
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S
Slave address R/W
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
A
Data
A
Data
A/A
P
A
P
Data
A
7 bits
“0”
1 to 8 bits
1 to 8 bits
(1) A master-transmitter transmits data to a slave-receiver
S
Slave address R/W
A
Data
A
Data
7 bits
“1”
1 to 8 bits
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
S
Slave address
R/W
1st 7 bits
A
Slave address
2nd byte
A
Data
A/A
P
7 bits
“0”
8 bits
1 to 8 bits
1 to 8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
S
Slave address
R/W
1st 7 bits
A
Slave address
2nd byte
A
Sr
Slave address
R/W
1st 7 bits
Data
7 bits
“0”
8 bits
7 bits
“1” 1 to 8 bits
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
S : START condition
A : ACK bit
Sr : Restart condition
P : STOP condition
R/W : Read/Write bit
A
Data
A
P
1 to 8 bits
From master to slave
From slave to master
Fig. 61. Address Data Communication Format
63
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
OSD FUNCTIONS
Table 10 outlines the OSD functions of the M37274EFSP.
The M37274EFSP incorporates an OSD circuit of 40 characters ✕
16 lines. OSD is controlled by the OSD control register. There are 3
display modes and they are selected by a block unit. The display
modes are selected by block control register i (i = 1 to 16).
The features of each mode are described below.
Note : Note that MASK version has 36 characters ✕ 12 lines when
programming.
Table 10. Features of Each Display Mode
Parameter
Number of display
characters
Character display area
Kinds of characters
Kinds of character sizes
Pre-divide
ratio (Note)
Dot size
CC Mode
(Closed caption mode)
Display Mode
OSD Mode
(On-screen display mode)
EXOSD Mode
(Extra on-screen display mode)
40 characters ✕ 16 lines
16 ✕ 26 dots
16 ✕ 20 dots
16 ✕ 26 dots
(character dot structure : 20 ✕ 16 dots)
256 kinds (In EXOSD mode, they can be combined with 16 kinds of extra fonts)
2 kinds
14 kinds
6 kinds
✕ 1, ✕ 2
✕ 1, ✕ 2, ✕ 3
✕ 1, ✕ 2, ✕ 3
1TC ✕ 1/2H
1TC ✕ 1/2H, 1TC ✕ 1H, 1.5TC ✕ 1/2H,
1.5TC ✕ 1H, 2TC ✕ 2H, 3TC ✕ 3H
Border
1 screen : 7 kinds, Max. 7 kinds (a
character unit)
1TC ✕ 1/2H, 1TC ✕ 1H
Attribute
Character font coloring
Smooth italic, under line, flash
1 screen : 7 kinds, Max. 7 kinds
(a character unit)
Raster coloring
Possible (a screen unit, 1 screen : 7 Possible (a screen unit, 1 screen : Possible (a screen unit, 1 screen :
kinds, max. 7 kinds)
7 kinds, max. 7 kinds)
7 kinds, max. 7 kinds)
Character background
coloring
Possible (a character unit, 1 screen Possible (a character unit, 1 screen Possible (a character unit, 1 screen :
: 7 kinds, max. 7 kinds)
: 7 kinds, max. 7 kinds)
7 kinds, max. 5 kinds)
Border coloring
Possible (a screen unit, 1 screen : Possible (a screen unit, 1 screen :
7 kinds, max. 7 kinds)
7 kinds, max. 7 kinds)
Possible (a screen unit, 1 screen :
7 kinds, max. 7 kinds)
Extra font coloring
OSD output
Function
Border, extra font (16 kinds)
1 screen : 5 kinds, Max. 5 kinds
(a character unit)
R, G, B, OUT1, OUT2
Auto solid space function
Window function
Dual layer OSD function (layer 1)
Possible
R, G, B, OUT1, OUT2
Dual layer OSD function (layer 2)
R, G, B, OUT1, OUT2
Possible
Possible
Display expansion
(multiline display)
Notes 1: The divide ratio of the frequency divider (the pre-divide circuit) is referred as “pre-divide ratio” hereafter.
2: The character size is specified with dot size and pre-divide ratio (refer to (3) Dote size).
64
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
The OSD circuit has an extended display mode. This mode allows
multiple lines (16 lines or more) to be displayed on the screen by
interrupting the display each time one line is displayed and rewriting
data in the block for which display is terminated by software.
Figure 62 shows the configuration of OSD character. Figure 63 shows
the block diagram of the OSD circuit. Figure 64 shows the structure
of the OSD control register. Figure 65 shows the structure of the
block control register i.
CC mode
OSD mode
16 dots
16 dots
26 dots
20 dots
20 dots
Blank area ✽
Underline area ✽
Blank area ✽
✽ : Displayed only in CCD mode.
EXOSD mode
16 dots
16 dots
26 dots
26 dots
20 dots
16 dots
logical
sum
(OR)
Character font
Extra font
Fig. 62. Configuration of OSD Character Display Area
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Main clock
Clock for OSD
XIN
OSC1 OSC2
XOUT
HSYNC VSYNC
Oscillation circuit
Display
oscillation
circuit
Data slicer clock
Control registers for OSD
OSD Control circuit
OSD control register
Horizontal position register
Block control registers
Clock source control register
I/O polarity control register
Raster color register
Extra font color register
Border color register
Window H/L registers
Vertical position registers
(address 00CE 16)
(address 00CF 16)
(addresses 00D0 16 to 00DF 16)
(address 0216 16)
(address 0217 16)
(address 0218 16)
(address 0219 16)
(address 021B 16)
(addresses 021C 16 to 021F 16)
(addresses 0220 16 to 023F16)
RAM for OSD
20 bytes ✕ 40 characters ✕ 16 lines
ROM for OSD
(16 dots✕ 20 dots✕ 256 characters) +
16 dots✕ 26 dots✕ 16 characters)
Shift register 1
16-bit
Output circuit
Shift register 2
16-bit
Data bus
Fig. 63. Block Diagram of OSD Circuit
66
R
G
B
OUT1
OUT2
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
OSD Control Register
b7 b6 b5 b4 b3 b2 b1 b0
OSD control register (OC) [Address 00CE16]
Name
0
OSD control bit
(OC0) (See note 1)
Scan mode selection
bit (OC1)
Border type selection
bit (OC2)
1
2
3
After reset R W
Functions
B
0 : All-blocks display off
1 : All-blocks display on
0 : Normal scnan mode
1 : Bi-scan mode
0 : All bordered
1 : Shadow bordered (See note 2)
Flash mode selection 0 : Color signal of character background
bit (OC3)
part does not flash
1 : Color signal of character background
part flashes
0
R W
0
R W
0
R W
0
R W
4 Automatic solid space
control bit (OC4)
0 : OFF
1 : ON
0
R W
5 Window control bit
(OC5)
0 : OFF
1 : ON
0
R W
0
R W
6, 7 Layer mixing control
bits (OC6, OC7)
(See note 3)
b7 b6
0 0: Logic sum (OR) of layer 1’s
color and layer 2’s color
0 1: Layer 1’s color has priority
1 0: Layer 2’s color has priority
1 1: Do not set.
Notes 1 : Even this bit is switched during display, the display screen
remains unchanged until a rising (falling) of the next V SYNC.
2 : Shadow border is output at right and bottom side of the font.
3 : Set “00” during displaying extra fonts.
Fig. 64. OSD Control Register
Block Control register i
b7 b6 b5 b4 b3 b2 b1 b0
Block control register i (BCi) (i=1 to 16) [Addresses 00D0 16 to 00DF 16](See note 1)
B
Name
0, 1 Display mode
selection bits
(BCi0, BCi1)
2
Border control bit
(BCi2)
3, 4 Dot size selection
bits (BCi3, BCi4)
5, 6 Pre-divide ratio •
layer selection bit
(BCi5, BCi6)
7
OUT2 output control bit
(BCi7) (See note 2)
Functions
b1
0
0
1
1
After reset
b0
0: Display OFF
1: OSD mode
0: CC mode
1: EXOSD mode
0: Border OFF
1: Border ON
b6
R W
Indeterminate R W
b5
0
0
0
1
1
0
1
1
1
1
b4
0
0
1
1
0
0
1
1
0
0
1
1
—
—
0
0
1
1
b3
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Indeterminate R W
CS6 Pre-divide
ratio
—
✕1
—
✕2
—
✕3
0
1
✕1
✕2
Dot size
Display
layer
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
Layer1
3Tc ✕ 3H
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
1Tc ✕ 1/2H
1Tc ✕ 1H
Layer2
1Tc ✕ 1/2H
1Tc ✕ 1H
1.5Tc ✕ 1/2H
1.5Tc ✕ 1H
BC17: Window top boundary
BC27: Window bottom boundary
Indeterminate R W
Indeterminate R W
Indeterminate R W
Notes 1: Note that MASK version the block control registers at addresses 00D0
when programming.
2: Bit 4 of the color code 1 controls OUT1 output when bit 7 is "0".
Bit 4 of the color code 1 controls OUT2 output when bit 7 is "1".
3: CS6 : Bit 6 of the clock control register (address 0216 16)
4: Tc : Pre-devided clock period for OSD
5: H : Hsync
16
to 00DB 16
Fig. 65. Block Control Registers
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(1) Dual Layer OSD
M37274MA-XXXSP has 2 layers; layer 1 and layer 2. These layers
display the OSD for controlling TV and the closed caption display at
the same time and overlayed on each other.
Each block can be assigned to either layer by bits 6 and 5 of the
block control register (refer to Figure 65). For example, only when
both bits 5 and 6 are “1,” the block is assigned to layer 2. Other bit
combinations assign the block to layer 1.
When a block of layer 1 is overlapped with that of layer 2, a screen is
combined (refer to Figure 67) by bits 7 and 6 of the OSD control
register (refer to Figure 64).
Layer 2
Block 9
Block 10
Block 11
Block 12
Block 1
Block 2
Block
...
Note: When using the dual layer OSD, note Table 11.
Block 7
Block 8
Block
Layer 1
Fig. 66. Image of Dual Layer OSD
Table 11. Conditions of Dual Layer
Block
Block in Layer 1
Block in Layer 2
Display mode
CC mode
OSD mode
OSD Clock source
Data slicer clock or OSC1 or main clock
Same as layer 1
Pre-divide ratio
✕ 1 or ✕ 2 (all blocks)
Same as layer 1 (Note)
Dot size
1TC ✕ 1/2H
Horizontal display start position
Arbitrary
Parameter
Pre-divide ratio = 1
Pre-divide ratio = 2
1TC ✕ 1/2H
1TC ✕ 1/2H, 1.5TC ✕ 1/2H
1TC ✕ 1H
1TC ✕ 1H, 1.5TC ✕ 1H
Same position as layer 1
Note: For the pre-divide ratio of the layer 2, select the same as the layer 1’s ratio by bit 6 of the clock control register.
Display example of layer 1 = “HELLO,” layer 2 = “CH5”
CH5
HELLO
Logical sum (OR) of
layer 1’s color and
layer 2’s color
Bit 7 = “0,” bit 6 = “0”
Fig. 67. Display Example of Dual Layer OSD
68
CH5
HELLO
Layer 1’s color has priority
Bit 7 = “0”, bit 6 = “1”
CH5
HELLO
Layer 2’s color has priority
Bit 7 = “1,” bit 6 = “0”
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(2) Display Position
The display positions of characters are specified by a block. There
are 16 blocks, blocks 1 to 16. Up to 40 characters can be displayed
in each block (refer to (6) Memory for OSD).
The display position of each block can be set in both horizontal and
vertical directions by software.
The display position in the horizontal direction can be selected for all
blocks in common from 256-step display positions in units of 4 TOSC
(TOSC = OSD oscillation cycle).
The display position in the vertical direction for each block can be
selected from 1024-step display positions in units of 1 TH ( TH = HSYNC
cycle).
Blocks are displayed in conformance with the following rules:
1 When the display position is overlapped with another block
(Figure 68, (b)), a lower block number (1 to 16) is displayed on
the front.
2 When another block display position appears while one block is
displayed (Figure 68 (c)), the block with a larger set value as the
vertical display start position is displayed. However, do not display block with the dot size of 2TC ✕ 2H or 3TC ✕ 3H during display period ( ✽ ) of another block.
✽ In the case of OSD mode block: 20 dots in vertical from the vertical display start position.
✽ In the case of CC or EXOSD mode block: 26 dots in vertical from
the vertical display start position.
(HR)
VP11, VP21
Block 1
VP12, VP22
Block 2
VP13, VP23
Block 3
(a) Example when each block is separated
(HR)
VP11, VP12 = VP21, VP22
Block 1
(Block 2 is not displayed)
(b) Example when block 2 overlaps with block 1
(HR)
VP11, VP21
VP12, VP22
Block 1
Block 2
(c) Example when block 2 overlaps in process of block 1
Note: VP1i or VP2i (i : 1 to 16) indicates the vertical display start position of display block i.
Fig. 68. Display Position
69
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
The display position in the vertical direction is determined by counting the horizontal sync signal (HSYNC). At this time, when VSYNC and
HSYNC are positive polarity (negative polarity), it starts to count the
rising edge (falling edge) of HSYNC signal from after fixed cycle of
rising edge (falling edge) of VSYNC signal. So interval from rising edge
(falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC
signal needs enough time (2 machine cycles or more) for avoiding
jitter. The polarity of HSYNC and VSYNC signals can select with the
I/O polarity control register (address 021716).
8 machine cycles
or more
VSYNC signal input
0.25 to 0.50 [ µs]
( at f(XIN) = 8MHz)
VSYNC control
signal in
microcomputer
Period of counting
HSYNC signal
(Note 2)
HSYNC
signal input
8 machine cycles
or more
1
2
3
4
5
Not count
When bits 0 and 1 of the I/O polarity control register
(address 0217 16) are set to “1” (negative polarity)
Notes 1 : The vertical position is determined by counting falling edge of
HSYNC signal after rising edge of V SYNC control signal in the
microcomputer.
2 : Do not generate falling edge of H SYNC signal near rising edge
of VSYNC control signal in microcomputer to avoid jitter.
3 : The pulse width of V SYNC and HSYNC needs 8 machine cycles
or more.
Fig. 69. Supplement Explanation for Display Position
70
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
The vertical position for each block can be set in 1024 steps (where
each step is 1T H (TH: HSYNC cycle)) as values “0016” to “FF16” in
vertical position register 1i (i = 1 to 12) (addresses 022016 to 022B16)
and values “0016” to “0316” in vertical position register 2i (i = 1 to 12)
(addresses 023016 to 023B16). The structure of the vertical position
registers is shown in Figure 70 and 71.
Vertical Position Register 1i
b7 b6 b5 b4 b3 b2 b1 b0
Vertical position register 1i (VP1i) (i = 1 to 16) [Addresses 0220 16 to 022F 16]
B
Name
Functions
After reset
R W
0 Control bits of vertical Vertical display start positions
Indeterminate R W
to display start positions (low-order 8 bits)
7 (VP1i0 to VP1i7)
TH ✕
(See note 1)
(setting value of low-order 2 bits of VP2i ✕ 162
+ setting value of low-order 4 bits of VP1i ✕ 161
+ setting value of low-order 4 bits of VP1i ✕ 160)
Notes 1: Set values except “00 16” “0116” to VP1i when VP2i is “00 16.”
2: T H is cycle of H SYNC.
Fig. 70. Vertical Position Register 1
Vertical Position Register 2i
b7 b6 b5 b4 b3 b2 b1 b0
Vertical position register 2i (VP2i) (i = 1 to 16) [Addresses 0230 16 to 023F 16]
B
Name
Functions
After reset
R W
0, 1 Control bits of vertical Vertical display start positions
Indeterminate R W
display start positions (high-order 2 bits)
TH ✕
(VP1i0, VP1i1)
(See note 1)
(setting value of low-order 2 bits of VP2i ✕ 162
+ setting value of low-order 4 bits of VP1i ✕ 161
+ setting value of low-order 4 bits of VP1i ✕ 160)
2 Nothing is assigned. These bits are write disable bits.
to
When these bits are read out, the values are indeterminate.
7
Indeterminate R —
Notes 1: Set values except “00 16” “01 16” to VP1i when VP2i is “00 16.”
2: T H is cycle of H SYNC.
Fig. 71. Vertical Position Register 2
71
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
The horizontal position is common to all blocks, and can be set in
256 steps (where 1 step is 4TOSC, TOSC being the oscillating cycle
for display) as values “0016” to “FF16” in bits 0 to 7 of the horizontal
position register (address 00CF16). The structure of the horizontal
position register is shown in Figure 72.
Horizontal Position Register
b7 b6 b5 b4 b3 b2 b1 b0
Horizontal position register (HP) [Address 00CF 16]
B
Name
0 Control bits of horizontal
to display start positions
7 (HP0 to HP7)
Functions
Horizontal display start positions
4TOSC ✕
(setting value of high-order 4 bits ✕ 161 +
setting value of low-order 4 bits ✕ 160 )
Notes 1. The setting value synchronizes with the V SYNC.
2. TOSC = OSD oscillation period.
Fig. 72. Horizontal Position Register
72
After reset R W
0
R W
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Notes 1 : 1TC (TC : OSD clock cycle divided by prescaler) gap occurs between the horizontal display start position set by
the horizontal position register and the most left dot of the
1st block. Accordingly, when 2 blocks have different predivide ratios, their horizontal display start position will not
match.
Ordinaly, this gap is 1TC regardless of character sizes,
however, the gap is 1.5TC only when the character size is
1.5TC.
2 : The horizontal start position is based on the OSD clock
source cycle selected for each block. Accordingly, when 2
blocks have different OSD clock source cycles, their horizontal display start position will not match.
H SYNC
1TC
Note 1
Block 1 (Pre-divide ratio = 1, clock source = data slicer clock)
1TC
4TOSC ✕ N
Block 2 (Pre-divide ratio = 2, clock source = data slicer clock)
1TC
Block 3 (Pre-divide ratio = 3, clock source = data slicer clock)
1.5TC
Block 4 (Pre-divide ratio = 2, character size = 1.5Tc, clock source = data slicer clock)
Note 2
4TOSC’ ✕ N
1TC
Block 5 (Pre-divide ratio = 3, clock source = OSC1)
N : Value of horizontal position register (decimal notation)
1Tc : OSD clock cycle divided in the pre-divide circuit
Tosc : OSD oscillation cycle
Fig. 73. Notes on Horizontal Display Start Position
73
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(3) Dot Size
ter), refer to Figure 76 (the structure of the clock source control register).
The block diagram of dot size control circuit is shown in Figure 75.
The dot size can be selected by a block unit. The dot size in vertical
direction is determined by dividing HSYNC in the vertical dot size control circuit. The dot size in horizontal is determined by dividing the
following clock in the horizontal dot size control circuit : the clock
gained by dividing the OSD clock source (data slicer clock, OSC1,
main clock) in the pre-divide circuit. The clock cycle divided in the
pre-divide circuit is defined as 1TC.
The dot size of the layer 1 is specified by bits 6 to 3 of the block
control register.
The dot size of the layer 2 is specified by the following bits : bits 3
and 4 of the block control register, bit 6 of the clock source control
register. Refer to Figure 65 (the structure of the block control regis-
Notes 1 : The pre-divide ratio = 3 cannot be used in the CC mode.
2 : The pre-divide ratio of the OSD mode block on the layer 2
must be same as that of the CC mode block on the layer 1
by bit 6 of the clock source control register.
3 : In the bi-scan mode, the dot size in the vertical direction is
2 times as compared with the normal mode. Refer to “(13)
Scan Mode” about the scan mode.
Clock cycle
= 1TC
Main clock
Synchronous
OSC1
circuit
Horizontal dot size
control circuit
Cycle ✕ 2
Cycle ✕ 3
Data slicer
clock
(Note)
Pre-divide circuit
Vertical dot size
control circuit
HSYNC
OSD control circuit
Note: To use data slicer clock, set bit 0 of data slicer control register to “0.”
Fig. 74. Block Diagram of Dot Size Control Circuit
1 dot
1TC
1/2H
1TC
3TC
2TC
Scanning line of F1(F2)
Scanning line of F2(F1)
1H
2H
3H
In normal scan mode
Fig. 75. Definition of Dot Sizes
74
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(4) Clock for OSD
As a clock for display to be used for OSD, it is possible to select one
of the following 4 types.
Main clock (8 MHz)
Data slicer clock output from the data slicer (approximately 26 MHz)
Clock from the LC oscillator supplied from the pins OSC1 and OSC2
Clock from the ceramic resonator or the quartz-crystal oscillator
from the pins OSC1 and OSC2
This OSD clock for each block can be selected by the following bits
: bit 7 of the port P3 direction register, bits 5 and 4 of the clock source
control register (addresses 021616). A variety of character sizes can
be obtained by combining dot sizes with OSD clocks. When not using the pins OSC1 and OSC2 for the OSD clock I/O pins, the pins
can be used as sub-clock I/O pins or port P6.
Table 12. Setting for P63/OSC1/XCIN, P64/OSC2/XCOUT
Sub-clock
Input
OSD Clock
Function
I/O Pin
Port
I/O Pin
Register
•
•
•
•
(Note)
Data slicer clock
Data slicer
circuit
1
b5
1
1
0
0
control register
b4
0
1
0
1
“0”
“1”
CC mode block
CS0
“10”
OSC1 clock
“1”
“10”
CS5, CS4
Ceramic •
quartz-crystal
0
Clock source
“0”
LC
0
register
Except “10”
“00”
32 kHZ
b7 of port P3 direction
“11”
CS2, CS1
Except “10”
CS1
CS2 = “0”
OSD mode block
CS2, CS1
“0”
Except “10”
“1”
EXOSD mode block
CS3
“10”
CS2, CS1
Oscillating mode for OSD
Clock oscillation
circuit
Main clock
Note : To use data slicer clock, set bit 0 of data slicer control register to “1.”
Fig. 76. Block Diagram of OSD Selection Circuit
75
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Clock Source Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Clock source control register (CS) [Address 0216 16 ]
B
0
Name
CC mode clock
selection bit (CS0)
1, 2 OSD mode clock selection
bits (CS1, CS2)
3
EXOSD mode clock
selection bit (CS3)
4, 5 OSD oscillating mode
selection bits (CS4, CS5)
6
Pre-divide ratio of layer 2
selection bit (CS6)
7
Test bit
(See note 3)
Functions
After reset R W
0: Data slicer clock
1: OSC1 clock
0
R W
b2
0
R W
0
R W
0
R W
0
R W
0
R W
0
0
1
1
b1
0: Data slicer clock
1: OSC1 clock
0: Main clock (See note 1)
1: Do not set
0: Data slicer clock
1: OSC1 clock
b5
b4
0 0: 32 kHz oscillating mode
0 1: Input ports P6 3, P64
(See note 2)
1 0: LC oscillating mode
1 1: Ceramic • quartz-crystal
oscillating mode
0: ✕ 1
1: ✕ 2
Notes 1: When setting “10 2,” main clock is set as a clock in the CC mode and
EXOSD mode regardless of bits 0, 3.
2: When selecting input ports P6 3 and P64 , set bit 7 at address 00C7 16
to “0.”
3: Be sure to set bit 7 to “0” for program of the mask and the EPROM
versions. For the emulator MCU version (M37274ERSS), be sure to set
bit 7 to “1” when using the data slicer clock for software debugging.
Fig. 77. Clock Control Register
76
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(5) Field Determination Display
To display the block with vertical dot size of 1/2H, whether an even
field or an odd field is determined through differences in a synchronizing signal waveform of interlacing system. The dot line 0 or 1 (refer to Figure 79) corresponding to the field is displayed alternately.
In the following, the field determination standard for the case where
both the horizontal sync signal and the vertical sync signal are negative-polarity inputs will be explained. A field determination is determined by detecting the time from a falling edge of the horizontal sync
signal until a falling edge of the VSYNC control signal (refer to Figure
69) in the microcomputer and then comparing this time with the time
of the previous field. When the time is longer than the comparing
time, it is regarded as even field. When the time is shorter, it is regarded as odd field
The contents of this field can be read out by the field determination
flag (bit 7 of the I/O polarity control register at address 021716). A dot
line is specified by bit 6 of the I/O polarity control register (refer to
Figure 79).
However, the field determination flag read out from the CPU is fixed
to “0” at even field or “1” at odd field, regardless of bit 6.
I/O Polarity Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
I/O polarity control register (PC) [Address 021716]
B
Name
Functions
After reset R W
0
HSYNC input polarity
switch bit (PC0)
0 : Positive polarity input
1 : Negative polarity input
0
R W
1
VSYNC input polarity
switch bit (PC1)
0 : Positive polarity input
1 : Negative polarity input
0
R W
2
R, G, B output polarity
switch bit (PC2)
0 : Positive polarity output
1 : Negative polarity output
0
R W
3
Fix this bit to "0".
0
R —
4
OUT1 output polarity
switch bit (PC4)
0 : Positive polarity output
1 : Negative polarity output
0
R W
5
OUT2 output polarity
switch bit (PC5)
0 : Positive polarity output
1 : Negative polarity output
0
R W
6
Display dot line selection
bit (PC6) (See note)
0:“
0
R W
1
R —
“
1:“
“
7
Field determination flag
(PC7)
” at even field
” at odd field
” at even field
” at odd field
0 : Even field
1 : Odd field
Note: Refer to Figure 79.
Fig. 78. I/O Polarity Control Register
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Both H SYNC signal and V SYNC signal are negative-polarity input
HSYNC
Field
V SYNC and
VSYNC
control
signal
in microcomputer
Upper :
VSYNC signal
(n – 1) field
(Odd-numbered)
Field
Display dot line
determination
selection bit
flag(Note)
Odd
T1
0.25 to 0.50[ µs] at
f(XIN ) = 8 MHz
(n) field
(Even-numbered)
Even
(n + 1) field
(Odd-numbered)
Odd
When using the field determination flag, be sure to set bit 0 of the PWM mode register 1 (address 020A
2 3 4 5
6 7 8 9 10 11 12 13 14 15 16
1 2
Dot line 1
1
Dot line 0
0
Dot line 0
1
Dot line 1
1 (T3 < T2)
T3
1
0
0 (T2 > T1)
T2
Lower :
VSYNC control
signal in
microcomputer
3 4 5
16)
to “0.”
6 7 8 9 10 11 12 13 14 15 16
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
OSD mode
24
25
26
CC mode · EXOSD mode
When the display dot line selection bit is “0,”
the “
” font is displayed at even field, the
“
” font is displayed at odd field. Bit 7 of the
I/O polarity control register can be read as the
field determination flag : “1” is read at odd field,
“0” is read at even field.
OSD ROM font configuration diagram
Note : The field determination flag changes at a rising edge of the V SYNC control signal (negative-polarity input) in
the microcomputer.
Fig. 79. Relation between Field Determination Flag and Display Font
78
Display dot line
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(6) Memory for OSD
There are 2 types of memory for OSD : ROM for OSD (addresses
1080016 to 155FF16, 1800016 to 1E41F16) used to store character
dot data (masked) and RAM for OSD (addresses 080016 to 0DF316)
used to specify the characters and colors to be displayed. The following describes each type of memory.
1 ROM for OSD (addresses 1080016 to 155FF16, 1800016 to
1E43F16)
The ROM for OSD contains dot pattern data for characters to be
displayed. To actually display the character code and the extra code
stored in this ROM, it is necessary to specify them by writing the
character code inherent to each character (code determined based
on the addresses in the ROM for OSD) into the RAM for OSD.
The OSD ROM of the character font has a capacity of 11072 bytes.
Since 40 bytes are required for 1 character data, the ROM can stores
up to 256 kinds of characters. The OSD ROM of the extra font has a
capacity of 832 bytes. Since 52 bytes are required for 1 character
data, the ROM can stores up to 16 kinds of characters.
Data of the character font and extra font is specified shown in Figure
80.
OSD ROM address of character font data
OSD ROM
address bit
AD16 AD15 AD14 AD13 AD12 AD11 AD10
Line number/character
code/font bit
1
0
AD9
AD8
AD7
AD6
0
Line number
AD5
AD4
AD3
AD2
AD1
AD0
Font
bit
Character code
= “02 16” to “1516”
Line number
Character code = “00 16” to “FFF16”
Font bit
= 0 : left font 1 : right font
OSD ROM address of extra font data
OSD ROM
address bit
AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9
Line number/extra code
/font bit
b7
1
Line number
AD7
AD6
AD5
0
0
0
0
0
AD4
AD3
AD2
AD1
AD0
Font
bit
Extra code
= “00 16” to “19 16”
= “00 16” to “0F 16”
= 0 : left font 1 : right font
Line number
Extra code
Font bit
Line
number
1
AD8
Left
font
b0 b7
Right
font
0216
0316
0416
0516
0616
0716
0816
0916
0A16
0B16
0C16
0D16
0E16
0F16
1016
1116
1216
1316
1416
1516
b0
Data in
Line
OSD
number
ROM
000016
7FF016
7FF816
601C16
600C16
600C16
600C16
600C16
601C16
7FF816
7FF016
630016
638016
61C016
60E016
607016
603816
601C16
600C16
000016
Character font
b7
Left
font
b0 b7
Right
font
b0
Data in
OSD
ROM
FFFE16
FFFF 16
000316
000316
000316
000316
000316
000316
000316
000316
000316
000316
000316
000316
000316
000316
000316
000316
000316
000316
000316
000316
FFFF 16
FFFE16
0016
0116
0216
0316
0416
0516
0616
0716
0816
0916
0A16
0B16
0C16
0D16
0E16
0F16
1016
1116
1216
1316
1416
1516
1616
1716
1816
1916
000016
000016
Extra font
Fig. 80. OSD Character Data Storing Form
79
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2 RAM for OSD (addresses 080016 to 0FF716)
The RAM for OSD is allocated at addresses 080016 to 0FF716, and
is divided into a display character code specification part, color code
1 specification part, and color code 2 specification part for each block.
Table 13 shows the contents of the RAM for OSD.
For example, to display 1 character position (the left edge) in block
1, write the character code in address 080016, write color code 1 at
084016, and write color code 2 at 082816.
The structure of the RAM for OSD is shown in Figure 82.
Note: For the OSD mode block with dot size of 1.5TC ✕ 1/2H and
1.5TC ✕ 1H, the 3nth (n = 1 to 13) character is skipped as
compared with ordinary block✽. Accordingly, maximum 27 characters (the right 1/3 part of the 27th's character area is not
displayed) are only displayed in 1 block. The RAM data for the
3nth character does not effect the display. Any character data
can be stored here (refer to Figure 81).
Mask version has maximum 24 characters in 1 block when
programming.
✽ Blocks with dot size of 1TC ✕ 1/2H and 1TC ✕ 1H, or blocks
on the layer 1
Table 13. Contents of OSD RAM
Block
Block 1
Block 2
Block 3
Block 4
Block 5
80
Display Position (from left)
1st character
2nd character
:
24th character
25th character
:
39th character
40th character
1st character
2nd character
:
24th character
25th character
:
39th character
40th character
1st character
2nd character
:
24th character
25th character
:
39th character
40th character
1st character
2nd character
:
24th character
25th character
:
39th character
40th character
1st character
2nd character
:
24th character
25th character
:
39th character
40th character
Character Code Specification
080016
080116
:
081716
081816
:
082616
082716
088016
088116
:
089716
0E9816
:
08A616
08A716
090016
090116
:
091716
091816
:
092616
092716
098016
098116
:
099716
099816
:
09A616
09A716
0A0016
0A0116
:
0A1716
0A1816
:
0A2616
0A2716
Color Code 1 Specification
084016
084116
:
085716
085816
:
086616
086716
08C016
08C116
:
08D716
08D816
:
08E616
08E716
094016
094116
:
095716
095816
:
096616
096716
09C016
09C116
:
09D716
08D816
:
09E616
09E716
0A4016
0A4116
:
0A5716
0A5816
:
0A6616
0A6716
Color Code 2 Specification
082816
082916
:
083F16
086816
:
087616
087716
08A816
08A916
:
08BF16
08E816
:
08F616
08F716
092816
092916
:
093F16
096816
:
097616
097716
09A816
09A916
:
09BF16
09E816
:
09F616
09F716
0A2816
0A2916
:
0A3F16
0A6816
:
0A7616
0A7716
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Table 13. Contents of OSD RAM (continued)
Block
Block 6
Block 7
Block 8
Block 9
Block 10
Block 11
Block 12
Display Position (from left)
1st character
2nd character
:
24th character
25th character
:
39th character
40th character
1st character
2nd character
:
24th character
25th character
:
39th character
40th character
1st character
2nd character
:
24th character
25th character
:
39th character
40th character
1st character
2nd character
:
24th character
25th character
:
39th character
40th character
1st character
2nd character
:
24th character
25th character
:
39th character
40th character
1st character
2nd character
:
24th character
25th character
:
39th character
40th character
1st character
2nd character
:
24th character
25th character
:
39th character
40th character
Character Code Specification
0A8016
0A8116
:
0A9716
0A9816
:
0AA616
0AA716
0B0016
0B0116
:
0B1716
0B1816
:
0B2616
0B2716
0B8016
0B8116
:
0B9716
0B9816
:
0BA616
0BA716
0C0016
0C0116
:
0C1716
Color Code 1 Specification
0AC016
0AC116
:
0AD716
0AD816
:
0AE616
0AE716
0B4016
0B4116
:
0B5716
0B5816
:
0B6616
0B6716
0BC016
0BC116
:
0BD716
0BD816
:
0BE616
0BE716
0C4016
0C4116
:
0C5716
Color Code 2 Specification
0AA816
0AA916
:
0ABF16
0AE816
:
0AF616
0AF716
0B2816
0B2916
:
0B3F16
0B6816
:
0B7616
0B7716
0BA816
0BA916
:
0BBF16
0BE816
:
0BF616
0BF716
0C2816
0C2916
:
0C3F16
0C1816
:
0C2616
0C2716
0C8016
0C8116
:
0C9716
0C9816
:
0CA616
0CA716
0D0016
0D0116
:
0D1716
0D1816
:
0D2616
0D2716
0D8016
0D8116
:
0D9716
0D9816
:
0DA616
0DA716
0C5816
:
0C6616
0C6716
0CC016
0CC116
:
0CD716
0CD816
:
0CE616
0CE716
0D4016
0D4116
:
0D5716
0D5816
:
0D6616
0D6716
0DC016
0DC116
:
0DD716
0DD816
:
0DE616
0DE716
0C6816
:
0C7616
0C7716
0CA816
0CA916
:
0CBF16
0CE816
:
0CF616
0CF716
0D2816
0D2916
:
0D3F16
0D6816
:
0D7616
0D7716
0DA816
0DA916
:
0DBF16
0DE816
:
0DF616
0DF716
81
MITSUBISHI MICROCOMPUTERS
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PR
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Table 13. Contents of OSD RAM (continued)
Block
Block 13
Block 14
Block 15
Block 16
82
Display Position (from left)
1st character
2nd character
:
24th character
25th character
:
39th character
40th character
1st character
2nd character
:
24th character
25th character
:
39th character
40th character
Character Code Specification
0E0016
0E0116
:
0E1716
0E1816
:
0E2616
0E2716
0E8016
0E8116
:
0E9716
0E9816
:
0FA616
0FA716
Color Code 1 Specification
0E4016
0E4116
:
0E5716
0E5816
:
0E6616
0E6716
0EC016
0EC116
:
0ED716
0ED816
:
0EE616
0EE716
Color Code 2 Specification
0E2816
0E2916
:
0E3F16
0E6816
:
0E7616
0E7716
0EA816
0EA916
:
0EBF16
0EE816
:
0EE616
0EF716
1st character
2nd character
:
24th character
25th character
:
39th character
40th character
1st character
2nd character
:
24th character
25th character
:
39th character
40th character
0F0016
0F0116
:
0F1716
0F1816
:
0F2616
0F2716
0F8016
0F8116
:
0F9716
0F9816
:
0FA616
0FA716
0F4016
0F4116
:
0F5716
0F5816
:
0F6616
0F6716
0FC016
0FC116
:
0FD716
0FD816
:
0FE616
0FE716
0F2816
0F2916
:
0F3F16
0F6816
:
0F7616
0F7716
0FA816
0FA916
:
0FBF16
0FE816
:
0FF616
0FF716
MITSUBISHI MICROCOMPUTERS
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Display
sequence
1
2
3
4
5
6
RAM
address
order
1
2
4
5
7
8
Display
sequence
RAM
address
order
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
1.5Tc size
10 11 13 14 16 17 19 20 22 23 25 26 28 29 31 32 34 35 37 38 40 block
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 3738 39 40
1Tc size
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 block
Fig. 81. RAM Data for 3nth Character
Note: Do not read from and write to addresses shown in Table 14.
Table 14. List of Access Disable Addresses
087816
087916
087A16
08F816
08F916
08FA16
097816
097916
097A16
09F816
09F916
09FA16
0A7816
0A7916
0A7A16
0AF816
0AF916
0AFA16
0B7816
0B7916
0B7A16
0BF816
0BF916
0BFA16
0C7816
0C7916
0C7A16
0CF816
0CF916
0CFA16
0D7816
0D7916
0D7A16
0DF816
0DF916
0DFA16
0E7816
0E7916
0E7A16
0EF816
0EF916
0EFA16
0F7816
0F7916
0F7A16
0FF816
0FF916
0FFA16
83
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Blocks 1 to16
b7
RF7
b0
RF6
RF5 RF4 RF3 RF2
b7
b0
RF1 RF0 RC17 RC16 RC15 RC14 RC13 RC12 RC11 RC10 RC23 RC22 RC21 RC20
Character code
Color code 1
CC mode
Bit
Bit name
b0
b3
Color code 2
OSD mode
Function
Bit name
EXOSD mode
Function
Bit name
Function
RF0
RF1
RF2
RF3
Character code
RF4
(Low-order 8 bits)
RF5
Specification of
character code in
OSD ROM
Character code
(Low-order 8 bits)
Specification of
character code in
OSD ROM
Character code
(Low-order 8 bits)
Specification of
character code in
OSD ROM
RF6
RF7
RC10
RC11
RC12
RC13
RC14
0
0
0
Control of
0: Color signal output OFF
Control of
0: Color signal output OFF
character color R
1: Color signal output ON
character color R
1: Color signal output ON
Control of
Control of
character color G
character color G
Control of
Control of
character color B
character color B
OUT1 control
0: Character output
OUT1 control
1: Background output
RC15
Flash control
RC16
Underline control
Italic control
RC21
RC22
(CC2)
0: Character output
1: Background output
Specification of
(EX0) extra code in OSD
ROM
0: Underline OFF
Extra code 1
Not used
(EX1)
0: Italic OFF
Extra code 2
(EX2)
0: Color signal output OFF Control of background
0: Color signal output OFF Background color code 0
color R
1: Color signal output ON
1: Color signal output ON
color R
Control of background
Control of background
color G
color G
Control of background
Control of background
color B
color B
Not used
Notes 1: Read value of bits 4 to 7 of the color code 2 is undefined.
2: For “not used” bits, the write value is read.
3: Set “0” to RC10.
Specification of
(BCC0) background color
Background color code 1
(BCC1)
Background color code 2
(BCC2)
Extra code 3
Fig. 82. Structure of OSD RAM
0: Character output
1: Background output
Extra code 0
RC23
84
OUT1 control
Control of background
Not used
character color
Character color code 2
1: Italic ON
RC20
Specification of
(CC1)
1: Flash ON
RC17
(CC0)
Character color code 1
0: Flash OFF
1: Underline ON
Character color code 0
Specification of
(EX3) extra code in OSD
ROM
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(7) Character color
The color for each character is displayed by the color code 1. The
kinds and specification method of character color are different depending on each mode.
CC mode .................. 7 kinds
Specified by bits 1 (R), 2 (G), and 3 (B) of
color code 1
OSD mode ............... 7 kinds
Specified by bits 1 (R), 2 (G) and 3 (B)of color
code 1
EXOSD mode .......... 5 kinds
Specified by bits 1 (CC0), 2 (CC1), and
3 (CC2) of color code 1
The correspondence Table of color code 1 and color signal output in
the EXOSD mode is shown in Table 15.
•
•
•
Table 15. Correspondence Table of Color Code 1 and Color
Signal Output in EXOSD Mode
Color Code 1
Color Signal Output
Bit 3
CC2
Bit 2
CC1
Bit 1
CC0
R
G
B
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
1
0
0
1
1
1
1
0
1
0
0
1
1
0
1
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
(8) Character background color
The character background color can be displayed in the character
display area. The character background color for each character is
specified by color code 2. The kinds and specification method of character background color are different depending on each mode.
CC mode .................. 7 kinds
Specified by bits 0 (R), 1 (G), and 2 (B) of
color code 2
OSD mode ............... 7 kinds
Specified by bits 0 (R), 1 (G), and 2 (B) of
color code 2
EXOSD mode .......... 5 kinds
Specified by bits 0 (BCC0), 1 (BCC1), and
2 (BCC2) of color code 2
The correspondence table of the color code 2 and color signal output
in the EXOSD mode is shown in Table 16.
•
•
•
Note : The character background color is displayed in the following
part :
(character display area)–(character font)–(border)–(extra font).
Accordingly, the character background color does not mix with
these color signal.
Table 16. Correspondence Table of Color Code 2 and Color
Signal Output in EXOSD Mode
Color Signal Output
Color Code 2
Bit 2
BCC2
0
0
0
0
1
1
1
1
Bit 1
BCC1
0
0
1
1
0
0
1
1
Bit 0
BCC0
0
1
0
1
0
1
0
1
R
G
B
0
1
0
1
1
1
0
1
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
1
85
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(9) OUT1, OUT2 signals
The OUT1, OUT2 signals are used to control the luminance of the
video signal. The output waveform of the OUT1, OUT2 signals is
controlled by bit 4 of color code 1 (refer to Figure 82), bits 2 and 7 of
Block control register i
OUT2 output
control bit (b7)
Border output
control bit (b2)
OUT1
control
(b4 of color
code 1)
0
the block control register i (refer to Figure 65). The setting values for
controlling OUT1, OUT2 and the corresponding output waveform is
shown in Figure 83.
Output
waveform
OUT1
OUT2
0
1
OUT1
OUT2
0
0
OUT1
OUT2
1
1
OUT1
OUT2
0
OUT1
OUT2
0
1
OUT1
OUT2
1
0
OUT1
OUT2
1
OUT1
1
OUT2
Fig. 83. Setting Value for Controlling OUT1, OUT2 and Corresponding Output Waveform
86
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(10) Attribute
The attributes (flash, underline, italic) are controlled to the character
font. The attributes for each character are specified by the color codes
1 and 2 (refer to Figure 71). The attributes to be controlled are different depending on each mode.
CC mode ..................... Flash, underline, italic
OSD mode .................. Border (all bordered, shadow bordered can
be selected)
EXOSD mode ............. Border (all bordered, shadow bordered can
be selected) , extra font (16 kinds)
1 Under line
The underline is output at the 23th and 24th dots in vertical direction
only in the CC mode. The underline is controlled by bit 6 of color
code 1. The color of underline is the same color as that of the character font.
2 Flash
The parts of the character font, the underline, and the character background are flashed only in the CC mode. The color signals (R, G, B,
OUT1) of the character font and the underline are controlled by bit 5
of color code 1. All of the color signals for the character font flash.
However, the color signal for the character background can be controlled by bit 3 of the OSD control register (refer to Figure 64). The
flash cycle bases on the VSYNC count.
· VSYNC cycle 5 48 ; 800 ms (at flash ON)
· VSYNC cycle 5 16 ; 267 ms (at flash OFF)
3 Italic
The italic is made by slanting the font stored in OSD ROM to the right
only in the CC mode. The italic is controlled by bit 7 of color code 1.
The display example of the italic and underline is shown in Figure 85.
In this case, “R” is displayed.
Notes 1: When setting both the italic and the flash, the italic character flashes.
2: When the pre-divide ratio = 1, the italic character with slant
of 1 dot 5 5 steps is displayed (refer to Figure 84 (c)). When
the pre-divide ratio = 2, the italic character with slant of 1/2
dot 5 10 steps is displayed (refer to Figure 84 (d)).
3: The boundary of character color is displayed in italic. However, the boundary of character background color is not affected by the italic (refer to Figure 85).
4: The adjacent character (one side or both side) to an italic
character is displayed in italic even when the character is
not specified to display in italic (refer to Figure 85).
5: When displaying the italic character in the block with the
pre-divide ratio = 1, set the OSD clock frequency to 11 MHz
to 14 MHz.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Color code 1
Color code 1
Bit 6
Bit 7
Bit 6
Bit 7
0
0
1
0
(a) Ordinary
(b) Underline
Color code 1
Color code 1
Bit 6
Bit 7
Bit 6
Bit 7
0
1
0
1
(c) Italic (pre-divide ratio = 1)
(d) Italic (pre-divide ratio = 2)
Fig. 84. Example of Attribute Display (in CC mode)
Italic on one side
Bit 7 of color
code 1
1
0
0
Note : The wavy-lined is the boundary of character color
Fig. 85. Example of Italic Display
88
Italic on both sides
1
1
0
1
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Extra font
There are 16 kinds of the extra fonts configured with 16 ✕ 26 dots in
OSD ROM. This 16 kinds fonts can be displayed by ORed with the
character font by a character unit (refer to Figure 62). In only the
EXOSD mode, the extra font is controlled the following : bits 7 to 5 of
the color code 1 and bit 3 of the color code 2.
The extra font color for each screen is specified by the extra color
register. When the character font overlaps with the extra font, the
color of the area becomes the ORed color of both fonts.
Notes 1 : When using the extra font, set bits 7 and 6 of the OSD
control register to “0” (refer to Figure 64).
2 : Extra fonts are always displayed by ORed with the character font. Accordingly, when displaying only a extra font,
set a blank for a character font and OR with it.
Extra Font Color Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Extra font color register (EC) [Address 021916]
B
0
Name
Extra font color R
control bit (EC0)
1
2
Functions
After reset
R W
0 : No output
1 : Output
0
R W
Extra font color G
control bit (EC1)
0 : No output
1 : Output
0
R W
Extra font color B
control bit (EC2)
0 : No output
1 : Output
0
R W
0
R W
0
R —
3, 4 Fix these bits to “0.”
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
5
to
7
Fig. 86. Extra Font Color Register
16 dots
16 dots
Blank character font
26 dots
20 dots
+
(OR)
26 dots
16 dots
Extra font specified by EX0 to EX3
Fig. 87. Display Example of Only Extra Font
89
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Border
The border is output in the OSD mode and the EXOSD mode. The all
bordered (bordering around of character font) and the shadow bordered (bordering right and bottom sides of character font) are selected (refer to Figure 88) by bit 2 of the OSD control register (refer to
Figure 64). The border ON/OFF is controlled by bit 2 of the block
control register (refer to Figure 65).
The OUT1 signal is used for border output. The border color for each
screen is specified by the border color register.
The horizontal size (x) of border is 1TC (OSD clock cycle divided in
the pre-divide circuit) regardless of the character font dot size. However, only when the pre-divide ratio = 2 and character size = 1.5TC,
the horizontal size is 1.5TC. The vertical size (y) different depending
on the screen scan mode and the vertical dot size of character font.
Notes 1 : There is no border for the extra font.
2 : The border dot area is the shaded area as shown in Figure
90. In the EXOSD mode, top and bottom of character font
display area is not bordered.
3 : When the border dot overlaps on the next character
font, the character font has priority (refer to Figure 91 A).
When the border dot overlaps on the next character back
ground, the border has priority (refer to Figure 91 B).
4 : The border is not displayed at right side of the most right
dot in the display area of the 40th character (the character
located at the most right of the block).
However, note that MASK version cannot display the border for the right edge dots of the 36th’s character area.
All bordered
Shadow bordered
Fig. 88. Example of Border Display
y
x
Scan mode
Border
dot size
Vertical dot size of
character font
Normal scan mode
1/2H
Fig. 89. Horizontal and Vertical Size of Border
90
1/2H, 1H, 2H, 3H
1TC (OSD clock cycle divided in pre-divide circuit)
1.5TC when selecting 1.5T C for character size.
Horizontal size (x)
Vertical size (y)
1H, 2H, 3H
Bi-scan mode
1/2H
1H
1H
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
OSD mode
EXOSD mode
16 dots
16 dots
Character
font area
20 dots
20 dots
Character
font area
1 dot width of border
1 dot width of border
1 dot width of border
1 dot width of border
Fig. 90. Border Area
Character boundary
B
Character boundary
A
Character boundary
B
Fig. 91. Border Priority
91
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Border Color Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Border color register (FC) [Address 021B 16]
B
0
Name
Border color R
control bit (FC0)
1
2
Functions
After reset
R W
0 : No output
1 : Output
0
R W
Border color G
control bit (FC1)
0 : No output
1 : Output
0
R W
Border color B
control bit (FC2)
0 : No output
1 : Output
0
R W
0
R W
0
R —
3, 4 Fix these bits to “0.”
5
to
7
Fig. 92. Border Color Register
92
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(11) Multiline Display
The M37274EFSP can ordinarily display 16 lines on the CRT screen
by displaying 16 blocks at different vertical positions. In addition, it
can display up to 16 lines by using OSD interrupts.
An OSD interrupt request occurs at the point at which display of each
block has been completed. In other words, when a scanning line
reaches the point of the display position (specified by the vertical
position registers) of a certain block, the character display of that
block starts, and an interrupt occurs at the point at which the scanning line exceeds the block. The mode in which an OSD interrupt
occurs is different depending on the setting of the raster color register (refer to Figure 99).
· When bit 7 of the raster color register is “0”
An OSD interrupt occurs at the end of block display in the OSD
and the EXOSD mode.
· When bit 7 of the raster color register is “1”
An OSD interrupt occurs at the end of block display in the CC mode.
Notes 1: An OSD interrupt does not occur at the end of display when
the block is not displayed. In other words, if a block is set to
off display by the display control bit of the block control register (addresses 00D016 to 00DB16), an OSD interrupt request does not occur (refer to Figure 93 (A)).
2: When another block display appeares while one block is
displayed, an OSD interrupt request occurs only once at
the end of the another block display (refer to Figure 93 (B)).
3: On the screen setting window, an OSD interrupt occurs
even at the end of the CC mode block (off display) out of
window (refer to Figure 93 (C)).
Block 1 (on display)
“OSD interrupt request”
Block 1 (on display)
“OSD interrupt request”
Block 2 (on display)
“OSD interrupt request”
Block 2 (on display)
“OSD interrupt request”
Block 3 (off display)
No
“OSD interrupt request”
No
“OSD interrupt request”
Block 3 (on display)
“OSD interrupt request”
Block 4 (on display)
“OSD interrupt request”
On display (OSD interrupt request occurs
at the end of block display)
Block 4 (off display)
Off display (OSD interrupt request does
not occur at the end of block display)
(A)
Block 1
“OSD interrupt request”
Block 1
Block 2
No
“OSD interrupt request”
Block 2
“OSD interrupt request”
“OSD interrupt request”
Block 3
“OSD interrupt request”
Window
In CC mode
(B)
(C)
Fig. 93. Note on Occurence of OSD Interrupt
93
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(12) Automatic Solid Space Function
Note : When using this function, set “0916” to the character below :
· The 1st character
· The 34th character and the following character.
This function generates automatically the solid space (OUT1 or OUT2
blank output) of the character area in the CC mode.
The solid space is output in the following area :
· the character area except character code “0916 ”
· the character area on the left and right sides
This function is turned on and off by bit 4 of the OSD control register
(refer to Figure 64).
Table 17. Setting for Automatic Solid Space
Bit 4 of OSD control register
0
Bit 7 of block control register
1
0
1
0
1
Bit 4 of color code 1
0
1
OUT1 output signal
Character
Character
Character
Solid
Character
font part
display
font part
space
font part
0
1
0
1
0
1
area
OUT2 output signal
OFF
OFF
Character
OFF
Solid
display
space
area
When setting the character code “05 16” as the character A, “06 16” as the character B.
Character to be displayed
(OSD RAM)
09 05 09 09 09 06 06
16
16
16
16
16
16
• • •
16
06 09 09
16
16
• • •
16
09
16
(Display screen)
• • •
1st
2nd
3rd
character character character
No blank output
(See note 1)
Fig. 94. Display Screen Example of Automatic Solid Space
94
• • •
34th
character
(See note 1)
35th
character
40 th
character
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(13) Scan Mode
M37274EFSP has the bi-scan mode for corresponding to HSYNC of
double speed frequency. In the bi-scan mode, the vertical start display position and the vertical size is two times as compared with the
normal scan mode. The scan mode is selected by bit 1 of the OSD
control register (refer to Figure 64).
Table 18. Setting for Scan Mode
Parameter
Bit 1 of OSD control register
Scan Mode
Bi-Scan
Normal Scan
Vertical display start position
0
1
Value of vertical position register ✕ 1H
Value of vertical position register ✕ 2H
1TC ✕ 1/2H
1TC ✕ 1H
1TC ✕ 1H
1TC ✕ 2H
2TC ✕ 2H
2TC ✕ 4H
3TC ✕ 3H
3TC ✕ 6H
Vertical dot size
(14) Window Function
This function sets the top and bottom boundary of display limit on a
screen. The window function is valid only in the CC mode. The top
boundary is set by window H registers 1 and 2. The bottom boundary is set by window L registers 1 and 2. This function is turned on
and off by bit 5 of the OSD control register (refer to Figure 64).
The window H registers 1 and 2 is shown in Figures 96 and 97, of
window L registers 1 and 2 is shown in Figures 98 and 99.
Notes 1: Set values except “0016” and “0116” to the window H register 1 when the window H register 2 is “0016.”
2: Set the register value fit for the following condition :
(WH1 + WH2) < (WL1 + WL2)
A B C D E
EXOSD mode
F
CC mode
G H
K L
I
J
M N O
P Q R S T
U V W X Y
CC mode
Top
boundary
of window
Window
CC mode
OSD mode
Bottom
boundary
of window
Screen
Fig. 95. Example of Window Function
95
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Window H Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Window H register 1 (WH1) [Address 021C16]
B
Name
Functions
0 Control bits of window
to top boundary
7 (WN10 to WN17)
(See note 1)
After reset
R W
Top boundary position (low-order 8 bits)
Indeterminate R W
TH ✕
(setting value of low-order 2 bits of WH2 ✕ 162
+ setting value of high-order 4 bits of WH1 ✕ 161
+ setting value of low-order 4 bits of WH1 ✕ 160)
Notes 1: Set values except “00 16” to the WH1 when WH2 is “00 16.”
2: TH is cycle of H SYNC.
3: WH2: Window H register 2
Fig. 96. Window H Register 1
Window H Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Window H register 2 (WH2) [Address 021E16]
B
Name
0, 1 Control bits of window
top boundary
(WN20 ,WN21)
(See note 1)
Functions
After reset
R W
Top boundary position (high-order 2 bits)
Indeterminate R W
TH ✕
(setting value of low-order 2 bits of WH2 ✕ 162
+ setting value of high-order 4 bits of WH1 ✕ 161
+ setting value of low-order 4 bits of WH1 ✕ 160)
2 Nothing is assigned. These bits are write disable bits.
Indeterminate R —
to When these bits are read out, the values are indeterminate.
7
Notes 1: Set values except “00 16” to the WH1 when WH2 is “00 16.”
2: TH is cycle of H SYNC.
3: WH1: Window H register 1
Fig. 97. Window H Register 2
96
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Window L Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Window L register 1 (WL1) [Address 021D16]
B
Name
0 Control bits of window
to top boundary
7 (WL10 to WL17)
(See note 1)
Functions
After reset
R W
Indeterminate R W
Top boundary position (low-order 8 bits)
TH ✕
(setting value of low-order 2 bits of WL2 ✕ 162
+ setting value of high-order 4 bits of WL1 ✕ 161
+ setting value of low-order 4 bits of WL1 ✕ 160)
Notes 1: Set values fit for the following condition: (WH1+WH2 ✕162)<(WL1+WL2✕
162)
2: T H is cycle of H SYNC.
3: WL2: Window L register 2
Fig. 98. Window L Register 1
Window L Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Window L register 2 (WL2) [Address 021F16]
B
Name
0, 1 Control bits of window
top boundary
(WL20, WL21)
(See note 1)
Functions
After reset
R W
Top boundary position (high-order 2 bits)
Indeterminate R W
TH ✕
(setting value of low-order 2 bits of WL2 ✕ 162
+ setting value of high-order 4 bits of WL1 ✕ 161
+ setting value of low-order 4 bits of WL1 ✕ 160)
2 Nothing is assigned. These bits are write disable bits.
Indeterminate R —
to When these bits are read out, the values are indeterminate.
7
Notes 1: Set values fit for the following condition: (WH1+WH2 ✕162)<(WL1+WL2✕
162)
2: TH is cycle of H SYNC.
3: WL1: Window L register 1
Fig. 99. Window L Register 2
97
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(15) OSD Output Pin Control
The OSD output pins R, G, B, and OUT1 can also function as ports
P52, P53, P54 and P55. Set the corresponding bit of the OSD port
control register (address 00CB16) to “0” to specify these pins as OSD
output pins, or set it to “1” to specify it as a general-purpose port P5
pins. The OUT2 can also function as port P10. Set the corresponding
bit of the port P1 direction register (address 00C316) to “1” (output
mode). After that, switch between the OSD output function and the
port function by the OSD port control register. Set the corresponding
bit to “1” to specify the pin as OSD output pin, or set it to “0” to specify
as port P1 pin.
The input polarity of the HSYNC, VSYNC and output polarity of signals
R, G, B, OUT1 and OUT2 can be specified with the I/O polarity control register (address 021716) . Set a bit to “0” to specify positive
polarity; set it to “1” to specify negative polarity (refer to Figure 78).
The OSD port control register is shown in Figure 100.
OSD Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
OSD port control register (PF) [Address 00CB16]
B
Name
Functions
0, 1, Fix these bits to “0.”
7
After reset R W
0
R W
2
Port P5 2 output signal
selection bit (R)
0 : R signal output
1 : Port P52 output
0
R W
3
Port P5 3 output signal
selection bit (G)
0 : G signal output
1 : Port P53 output
0
R W
4
Port P5 4 output signal
selection bit (B)
0 : B signal output
1 : Port P54 output
0
R W
5
Port P5 5 output signal
selection bit (OUT1)
0 : OUT1 signal output
1 : Port P55 output
0
R W
6
Port P1 0 output signal
selection bit (OUT2)
0 : Port P10 output
1 : OUT2 signal output (Note)
0
R W
Note. Set bit 0 of Port P1 direction register (address 00C3 16) to "1" (output mode).
Fig. 100. OSD Port Control Register
98
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(16) Raster Coloring Function
An entire screen (raster) can be colored by setting the bits 6 to 0 of
the raster color register. Since each of the R, G, B, OUT1, and OUT2
pins can be switched to raster coloring output, 7 raster colors can be
obtained.
If the OUT1 pin has been set to raster coloring output, a raster coloring signal is always output during 1 horizontal scanning period. This
setting is necessary for erasing a background TV image.
If the R, G, and B pins have been set to output, a raster coloring
signal is output in the part except a no-raster colored character (in
Figure 102, a character “1”) and the character background output
during 1 horizontal scanning period. This ensures that the character
color/the character background color is not mixed with the raster color.
The structure of the raster color register is shown in Figure 101, the
example of raster coloring is shown in Figure 102.
Raster Color Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Raster color register (RC) [Address 021816]
B
0
1
2
Name
Raster color R
control bit (RC0)
Raster color G
control bit (RC1)
Raster color B
control bit (RC2)
Functions
0 : No output
1 : Output
0 : No output
1 : Output
0 : No output
1 : Output
3, 4 Fix these bits to “0.”
After reset R W
0
R W
0
R W
0
R W
0
R —
Raster color OUT1
control bit (RC5)
0 : No output
1 : Output
0
R W
6 Raster color OUT2
control bit (RC6)
0 : No output
1 : Output
0
R W
7 OSD interrupt source
selection bit (RC7)
0 : Interrupt occurs at end of
OSD or EXOSD block
display
1 : Interrupt occurs at end of
CC mode block display
0
R W
5
Fig. 101. Raster Color Register
99
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
: Character color “RED” (R)
: Border color “GREEN” (G)
: Background color “MAGENTA” (R and B)
: Raster color “BLUE” (B and OUT1)
A
A'
HSYNC
OUT1
R
G
B
Fig. 102. Example of Raster Coloring
100
Signals
across
A-A'
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
ROM CORRECTION FUNCTION
This can correct program data in ROM. Up to 2 addresses (2 blocks)
can be corrected, a program for correction is stored in the ROM correction memory in RAM. The ROM memory for correction is 32 bytes
✕ 2 blocks.
Block 1 : addresses 02C016 to 02DF16
Block 2 : addresses 02E016 to 02FF16
Set the address of the ROM data to be corrected into the ROM correction address register. When the value of the counter matches the
ROM data address in the ROM correction address, the main program branches to the correction program stored in the ROM memory
for correction. To return from the correction program to the main program, the op code and operand of the JMP instruction (total of 3
bytes) are necessary at the end of the correction program. When the
blocks 1 and 2 are used in series, the above instruction is not needed
at the end of the block 1.
The ROM correction function is controlled by the ROM correction
enable register.
Notes 1 : Specify the first address (op code address) of each
instruction as the ROM correction address.
2 : Use the JMP instruction (total of 3 bytes) to return from
the main program to the correction program.
3 : Do not set the same ROM correction address to blocks
1 and 2.
ROM correction address 1 (high-order)
0242 16
ROM correction address 1 (low-order)
0243 16
ROM correction address 2 (high-order)
0244 16
ROM correction address 2 (low-order)
0245 16
Fig. 103. ROM Correction Address Registers
ROM Correction Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
0
ROM correction enable register (RCR) [Address 024616]
0
B
Name
Functions
0
Block 1 enable bit (RC0)
0: Disabled
1: Enabled
0
R W
1
Block 2 enable bit (RC1)
0: Disabled
1: Enabled
0
R W
0
R W
0
R —
2, 3 Fix these bits to “0.”
4
to
7
Nothing is assigned. These bits are write disable bits. When
these bits are read out, the values are “0.”
After reset R W
Fig. 104. ROM Correction Enable Register
101
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
RESET CIRCUIT
When the oscillation of a quartz-crystal oscillator or a ceramic resonator is stable and the power source voltage is 5 V ± 10 %, hold the
______
RESET pin at LOW for 2 µs or more, then return is to HIGH. Then, as
shown in Figure 106, reset is released and the program starts form
the address formed by using the content of address FFFF16 as the
high-order address and the content of the address FFFE16 as the
low-order address. The internal state of microcomputer at reset are
shown in Figures 5 to 9.
An example of the reset circuit is shown in Figure 105.
The reset input voltage must be kept 0.9 V or less until the power
source voltage surpasses 4.5 V.
Poweron
4.5 V
Power source voltage 0 V
0.9 V
Reset input voltage 0 V
27
Vcc
1
5
30
M51953AL
RESET
4
3
0.1 µF
26
Vss
M37274EFSP
Fig. 105. Example of Reset Circuit
XIN
φ
RESET
Internal RESET
SYNC
Address
?
01, S
?
01, S-1 01, S-2
FFFE
FFFF
AD H,
AD L
Reset address from the vector table
?
Data
32768 count of X IN
clock cycle (Note 3)
Fig. 106. Reset Sequence
102
?
?
?
?
AD L
ADH
Notes 1 : f(XIN) and f(φ ) are in the relation : f(XIN) = 2·f (φ).
2 : A question mark (?) indicates an undefined state that
depends on the previous state.
3 : Immediately after a reset, timer 3 and timer 4 are
connected by hardware. At this time, “FF 16” is set
in timer 3 and “07 16” is set to timer 4. Timer 3 counts down
with f(XIN)/16, and reset state is released by the timer 4
overflow signal.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
CLOCK GENERATING CIRCUIT
(3) Low-Speed Mode
The M37274EFSP has 2 built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance with
the resonator manufacturer’s recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor
exists on-chip. However, an external feed-back resistor is needed
between XCIN and XCOUT. When using XCIN-XCOUT as sub-clock,
clear bits 5 and 4 of the clock source control register to “0.” To supply
a clock signal externally, input it to the XIN (XCIN) pin and make the
XOUT (XCOUT) pin open. When not using XCIN clock, connect the
XCIN to VSS and make the XCOUT pin open.
After reset has completed, the internal clock φ is half the frequency of
XIN. Immediately after poweron, both the XIN and XCIN clock start
oscillating. To set the internal clock φ to low-speed operation mode,
set bit 7 of the CPU mode register (address 00FB16) to “1.”
If the internal clock is generated from the sub-clock (XCIN), a low
power consumption operation can be realized by stopping only the
main clock XIN. To stop the main clock, set bit 6 (CM6) of the CPU
mode register (00FB16) to “1.” When the main clock XIN is restarted,
the program must allow enough time to for oscillation to stabilize.
Note that in low-power-consumption mode the XCIN-XCOUT drivability
can be reduced, allowing even lower power consumption. To reduce
the XCIN-XCOUT drivability, clear bit 5 (CM5) of the CPU mode register (00FB16) to “0.” At reset, this bit is set to “1” and strong drivability
is selected to help the oscillation to start. When an STP instruction is
executed, set this bit to “1” by software before executing.
M37274EFSP
Oscillation Control
(1) Stop mode
The built-in clock generating circuit is shown in Figure 95. When the
STP instruction is executed, the internal clock φ stops at HIGH. At
the same time, timers 3 and 4 are connected by hardware and “FF16”
is set in timer 3 and “0716” is set in timer 4. Select f(XIN)/16 or f(XCIN)/
16 as the timer 3 count source (set both bit 0 of the timer mode
register 2 and bit 6 at address 00C716 to “0” before the execution of
the STP instruction). Moreover, set the timer 3 and timer 4 interrupt
enable bits to disabled (“0”) before execution of the STP instruction.
The oscillator restarts when external interrupt is accepted. However,
the internal clock φ keeps its “H” level until timer 4 overflows, allowing time for oscillation stabilization when a ceramic resonator or a
quartz-crystal oscillator is used.
X CIN
Rf
X IN
XOUT
Rd
CCIN
CCOUT
CIN
COUT
Fig. 107. Ceramic Resonator Circuit Example
M37274EFSP
(2) Wait mode
When the WIT instruction is executed, the internal clock φ stops in
the “H” level but the oscillator continues running. This wait state is
released at reset or when an interrupt is accepted (Note). Since the
oscillator does not stop, the next instruction can be executed at once.
Note: In the wait mode, the following interrupts are invalid.
(1) VSYNC interrupt
(2) OSD interrupt
(3) Timers 1 and 2 interrupts using TIM2 pin input as count
source
(4) Timer 3 interrupt using TIM3 pin input as count source
(5) Data slicer interrupt
(6) Multi-master I2C-BUS interface interrupt
(7) f(XIN)/4096 interrupt
(8) All timer interrupts using f(XIN)/2 or f(XCIN)/2 as count source
(9) All timer interrupts using f(XIN)/4096 or f(XCIN)/4096 as
count source
(10) A-D conversion interrupt
X COUT
X CIN
XCOUT XIN
Open
External oscillation
circuit or external
pulse
Vcc
Vss
XOUT
Open
External oscillation
circuit
Vcc
Vss
Fig. 108. External Clock Input Circuit Example
103
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XCIN
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
XCOUT
OSC1 oscillating
mode selection bits
(Notes 1, 4)
XOUT
XIN
“1”
Timer 3 count
stop bit (Notes 1, 2)
Timer 4 count
stop bit (Notes 1, 2)
Timer 3
Timer 4
“1”
1/8
1/2
“0”
Internal system clock
selection bit (Notes 1, 3)
“0”
Timer 3
count source selection bit (Notes 1, 2)
Timing
(Internal clock)
Main clock (X IN–XOUT) stop bit (Notes 1, 3)
Internal system clock
selection bit (Notes 1, 3)
Q
S
R
S
STP instruction
WIT
instruction
Q
Q
R
S
R
Reset
Interrupt disable flag I
Interrupt request
Notes 1 : The value at reset is “0.”
2 : Refer to the structure of timer mode register 2.
3 : Refer to the structure of CPU mode register (next page).
4 : Refer to the structure of clock source control register.
Fig. 109. Clock Generating Circuit Block Diagram
104
Reset
STP instruction
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
High-speed operation
start mode
Reset
WIT instruction
8MHz oscillating
32kHz oscillating
φ is stopped (HIGH)
Timer operating
STP instruction
8MHz oscillating
32kHz oscillating
f(φ) = 4MHz
Interrupt
8MHz stopped
32kHz stopped
φ is stopped (HIGH)
Interrupt (Note 1)
External INT,
timer interrupt,
or SI/O interrupt
External INT
CM7 = 0
CM7 = 1
WIT instruction
8MHz oscillating
32kHz oscillating
φ is stopped (HIGH)
Timer operating
(Note 3)
STP instruction
8MHz oscillating
32kHz oscillating
f(φ) = 16kHz
Interrupt
8MHz stopped
32kHz stopped
φ is stopped (HIGH)
Interrupt (Note 2)
CM6 = 0
The program must
allow time for 8MHz
oscillation to stabilize
CM6 = 1
8MHz stopped
32kHz oscillating
φ is stopped (HIGH)
Timer operating
(Note 3)
STP instruction
WIT instruction
8MHz stopped
32kHz stopped
φ = stopped (HIGH )
8MHz stopped
32kHz oscillating
f(φ) = 16kHz
Interrupt
Interrupt (Note 2)
CPU mode register
(Address : 00FB 16)
CM6 : Main clock (X IN–XOUT) stop bit
0 : Oscillating
1 : Stopped
CM7 : Internal system clock selection bit
0 : X IN-XOUT selected (high-speed mode)
1 : X CIN-XCOUT selected (low-speed mode)
The example assumes that 8 MHz is being applied to the X
IN
pin and 32 kHz to the X CIN pin. The φ indicates the internal clock.
Notes 1: When the STP state is ended, a delay of approximately 8ms is automatically generated by timer 3 and timer 4.
2: The delay after the STP state ends is approximately 2s.
3: When the internal clock φ divided by 8 is used as the timer count source, the frequency of the count source is 2kHz.
Fig. 110. State Transitions of System Clock
105
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
DISPLAY OSCILLATION CIRCUIT
ADDRESSING MODE
The OSD oscillation circuit has a built-in clock oscillation circuits, so
that a clock for OSD can be obtained simply by connecting an LC, a
ceramic resonator, or a quartz-crystal oscillator across the pins OSC1
and OSC2. Which of the sub-clock or the OSD oscillation circuit is
selected by setting bits 5 and 4 of the clock source control register
(address 021616).
The memory access is reinforced with 17 kinds of addressing modes.
Refer to SERIES 740 <Software> User’s Manual for details.
MACHINE INSTRUCTIONS
There are 71 machine instructions. Refer to SERIES 740 <Soft- ware>
User’s Manual for details.
PROGRAMMING NOTES
OSC1
(1) The divide ratio of the timer is 1/(n+1).
(2) Even though the BBC and BBS instructions are executed immediately after the interrupt request bits are modified (by the program), those instructions are only valid for the contents before
the modification. At least one instruction cycle is needed (such as
an NOP) between the modification of the interrupt request bits
and the execution of the BBC and BBS instructions.
(3) After the ADC and SBC instructions are executed (in the decimal
mode), one instruction cycle (such as an NOP) is needed before
the SEC, CLC, or CLD instruction is executed.
(4) An NOP instruction is needed immediately after the execution of
a PLP instruction.
(5) In order to avoid noise and latch-up, connect a bypass capacitor
(≈ 0.1 mF) directly between the VCC pin–VSS pin, AVCC pin–VSS
pin, and the VCC pin–CNVSS pin, using a thick wire.
OSC2
L
C1
C2
Fig. 111. Display Oscillation Circuit
AUTO-CLEAR CIRCUIT
When a power source is supplied, the auto-clear
function will oper______
ate by connecting the following circuit to the RESET pin.
Circuit example 1
Vcc
RESET
Vss
Circuit example 2
RESET
Vcc
Vss
Note : Make the level change from “L” to “H” at the point at
which the power source voltage exceeds the specified
voltage.
Fig. 112. Auto-clear Circuit Example
106
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
PROM Programming Method
The built-in PROM of the One Time PROM version (blank) and the
built-in EPROM version can be read or programmed with a generalpurpose PROM programmer using a special programming adapter.
Product
M37274EFSP
Name of Programming Adapter
PCA7400
The PROM of the One Time PROM version (blank) is not tested or
screened in the assembly process nor any following processes. To
ensure proper operation after programming, the procedure shown in
Figure 97 is recommended to verify programming.
Programming with
PROM programmer
Screening (Caution)
(150°C for 40 hours)
Verification with
PROM programmer
Functional check in target device
Caution : The screening temperature is far higher
than the storage temperature. Never
expose to 150°C exceeding 100 hours.
Fig. 113. Programming and testing of One Time PROM version
107
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
ABSOLUTE MAXIMUM RATINGS
Conditions
Ratings
Unit
All voltages are based
on VSS.
Output transistors are
cut off.
–0.3 to 6
V
Parameter
Symbol
VCC, AVCC
Power source voltage VCC, AVCC
VI
Input voltage
CNVSS
VI
Input voltage
VO
Output voltage
P00–P07, P10–P17, P20–P27,
P30, P31, P40–P46, P64, P63,
P7
0–P72, XIN, HSYNC, VSYNC,
______
RESET
P03, P10–P17, P20–P27, P30,
P31, P52–P55, SOUT, SCLK, XOUT,
OSC2
–0.3 to 6
V
–0.3 to VCC + 0.3
V
–0.3 to VCC + 0.3
V
VO
Output voltage
P00–P02, P04–P07
–0.3 to 13
V
IOH
Circuit current
P52–P55, P10, P03, P15–P17,
P20–P27, P30, P31
0 to 1 (Note 1)
mA
IOL1
Circuit current
P52–P55, P10, , P03, P15–P17,
P20–P27, SOUT, SCLK
0 to 2 (Note 2)
mA
IOL2
Circuit current
P11–P14
0 to 6 (Note 2)
mA
IOL3
IOL4
Circuit current
Circuit current
P00–P02, P04–P07
P30, P31
0 to 1 (Note 2)
0 to 10 (Note 3)
mA
mA
Pd
Topr
Power dissipation
Operating temperature
Tstg
Storage temperature
Ta = 25 °C
550
mW
–10 to 70
°C
–40 to 125
°C
RECOMMENDED OPERATING CONDITIONS (Ta = –10 °C to 70 °C, VCC = 5 V ± 10 %, unless otherwise noted)
Symbol
VCC, AVCC
VCC, AVCC
VSS
VIH1
Parameter
IOL2
Power source voltage (Note 4), During CPU, OSD, data slicer operation
RAM hold voltage (when clock is stopped)
Power source voltage
HIGH input voltage
P00–P07, P10–P17, P20–P27, P30, P31,
P40–P46, P64, P70–P72, HSYNC, VSYNC,
______
RESET, XIN, P63
HIGH input voltage
SCL1, SCL2, SDA1, SDA2
LOW input voltage
P00–P07, P10–P17, P20–P27, P30, P31,
P40–P46, P63, P64, P70–P72
LOW input voltage
SCL1, SCL2, SDA1, SDA2
______
LOW input voltage (Note 6)
RESET, XIN, OSC1, HSYNC, VSYNC,
INT1, INT2, INT3, TIM2, TIM3, SCLK, SIN
HIGH average output current (Note 1) P52–P55, P10, P03, P15–P17, P20–P27,
P30, P31
LOW average output current (Note 2) P52–P55, P10, P03, P15–P17, P20–P27,
SOUT, SCLK
LOW average output current (Note 2) P11–P14
IOL3
LOW average output current (Note 2) P00–P02, P04–P07
IOL4
LOW average output current (Note 3) P30, P31
f(XIN)
Oscillation frequency (for CPU operation) (Note 5)
Oscillation frequency (for sub-clock operation)
VIH2
VIL1
VIL2
VIL3
IOH
IOL1
f(XCIN)
fOSC
fhs1
fhs2
fhs3
fhs4
VI
108
Oscillation frequency (for OSD)
Input frequency
Input frequency
Input frequency
Input frequency
Input amplitude video signal
OSC1
XIN
XCIN
LC oscillating mode
Ceramic oscillating mode
TIM2, TIM3, INT1, INT2, INT3
SCLK
SCL1, SCL2
Horizontal sync. signal of video signal
CVIN
Min.
4.5
2.0
0
0.8VCC
Limits
Typ.
5.0
0
Max.
5.5
5.5
0
VCC
Unit
V
V
V
V
0.7VCC
0
VCC
0.4 VCC
V
V
0
0
0.3 VCC
0.2 VCC
V
V
7.9
29
8.0
32
11.0
26.5
27.0
15.262
1.5
15.734
2.0
1
mA
2
mA
6
mA
1
mA
10
mA
8.1
MHz
35
27.0
27.5
100
1
400
16.206
2.5
kHz
MHz
kHz
MHz
kHz
kHz
V
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
ELECTRIC CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted)
Parameter
Symbol
ICC
Power source current
System operation
Wait mode
Stop mode
Test conditions
Limits
Min.
Typ.
Max.
VCC = 5.5 V, CRT OFF
f(XIN) = 8 MHz Data slicer OFF
15
30
CRT ON
Data slicer ON
30
50
VCC = 5.5 V, f(XIN) = 0,
f(XCIN) = 32kHz,
OSD OFF, Data slicer OFF,
Low-power dissipation
mode set (CM5 = “0”,
CM6 = “1”)
60
200
mA
µA
VCC = 5.5 V, f(XIN) = 8 MHz
2
4
VCC = 5.5 V, f(XIN) = 0,
f(XCIN) = 32kHz,
Low-power dissipation
mode set (CM5 = “0”,
CM6 = “1”)
25
100
VCC = 5.5 V, f(XIN) = 0,
f(XCIN) = 0
1
10
HIGH output voltage P52–P55, P10, P03, P15–P17,
P20–P27, P30, P31
VCC = 4.5 V
IOH = –0.5 mA
VOL
LOW output voltage P52–P55, P10, SOUT, SCLK,
P00–P07, P15–P17, P20–P27
VCC = 4.5 V
IOL = 0.5 mA
0.4
LOW output voltage P30, P31
VCC = 4.5 V
IOL = 10.0 mA
VCC = 4.5 V IOL = 3 mA
IOL = 6 mA
3.0
VT+–VT–
IIZH
mA
µA
VOH
LOW output voltage P11–P14
Unit
2.4
V
V
0.4
0.6
______
Hysteresis (Note 6) RESET, HSYNC, VSYNC, INT1,
INT2, INT3, TIM2, TIM3, SIN, SCLK,
SCL1, SCL2, SDA1, SDA2
______
HIGH input leak current RESET, P03, P10–P17, P20–P27,
P30, P31, P40–P46, P63, P64,
P70–P72, HSYNC, VSYNC
HIGH input leak current
P00–P02, P04–P07
VCC = 5.0 V
0.5
1.3
V
VCC = 5.5 V
VI = 5.5 V
5
VCC = 5.5 V
VI = 12 V
10
RESET, P00–P07, P10–P17, P20– VCC = 5.5 V
VI = 0 V
P27, P30, P31, P40–P46, P63,
P64, P70–P72, HSYNC, VSYNC
5
µA
130
Ω
µA
______
IIZL
LOW input leak current
RBS
I2C-BUS·BUS switch connection resistor
(between SCL1 and SCL2, SDA1 and SDA2)
Notes 1:
2:
3:
4:
5:
6:
7:
8:
VCC = 4.5 V
The total current that flows out of the IC must be 20 or less.
The total input current to IC (IOL1 + IOL2 + IOL3) must be 20 mA or less.
The total average input current for ports P30, P31 to IC must be 10 mA or less.
Connect 0.1 µF or more capacitor externally between the power source pins VCC–VSS and AVCC–VSS so as to reduce power source
noise.
Also connect 0.1 µF or more capacitor externally between the pins VCC–CNVSS.
Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. When using the data slicer, use 8 MHz.
P16, P41–P44 have the hysteresis when these pins are used as interrupt input pins or timer input pins. P11–P14 have the hysteresis
when these pins are used as multi-master I2C-BUS interface ports. P17 and P46 have the hysteresis when these pins are used as
serial I/O pins.
When using the sub-clock, set fCLK < fCPU/3.
Pin names in each parameter is described as below.
(1) Dedicated pins: dedicated pin names.
(2) Duble-/triple-function ports
• When the same limits: I/O port name.
• When the limits of functins except ports are different from I/O port limits: function pin name.
109
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
A-D CONVERTER CHARACTERISTICS
(VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted)
Symbol
—
Resolution
—
Non-linearity error
—
Differential non-linearity error
Limits
Test conditions
Parameter
VOT
Zero transition error
VCC = 5.12V
IOL (SUM) = 0mA
VFST
Full-scale transition error
VCC = 5.12V
TCONV
Conversion time
VREF
Reference voltage
RLADDER
Ladder resistor
VIA
Analog input current
Min.
Max.
Typ.
Unit
8
bits
0
±2
LSB
0
±0.9
LSB
0
2
LSB
4
LSB
0
12.25
12.5
VCC
25
µs
V
k
0
VREF
V
MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS
Symbol
Standard clock mode High-speed clock mode
Parameter
Min.
Max.
Max.
Min.
Unit
tBUF
Bus free time
4.7
1.3
µs
tHD:STA
Hold time for START condition
4.0
0.6
µs
tLOW
LOW period of SCL clock
4.7
1.3
1000
µs
tR
20+0.1Cb
300
Rising time of both SCL and SDA signals
tHD:DAT
Data hold time
0
0
0.9
tHIGH
HIGH period of SCL clock
µs
4.0
0.6
tF
Falling time of both SCL and SDA signals
300
ns
tSU:DAT
Data set-up time
250
100
ns
tSU:STA
Set-up time for repeated START condition
4.7
0.6
µs
tSU:STO
Set-up time for STOP condition
4.0
0.6
µs
300
µs
20+0.1Cb
Note: Cb = total capacitance of 1 bus line
SDA
tHD:STA
tBUF
tLOW
P
tR
tSU:STO
tF
Sr
S
P
SCL
tHD:STA
tHD:DAT
tHIGH
tSU:DAT
Fig. 114. Definition Diagram of Timing on Multi-master I2C-BUS
110
tSU:STA
S : Start condition
Sr : Restart condition
P : Stop condition
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MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
PACKAGE OUTLINE
111
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MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
52P4B (52-PIN SHRINK DIP) MARK SPECIFICATION FORM
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
APPENDIX
Pin Configuration (TOP VIEW)
1
52
P52/R
VSYNC
2
51
P40/AD4
3
50
P53/G
P54/B
P41/INT2
4
49
P55/OUT1
P42/TIM2
5
48
P04/PWM0
P43/TIM3
6
47
P05/PWM1
P24/AD3
7
46
P06/PWM2
P25/AD2
8
45
P26/AD1
9
44
P07/PWM3
P20
P27/AD5
P00/PWM4
10
43
P21
42
P22
P01/PWM5
12
41
P02/PWM6
P17/SIN
P44/INT1
P45/SOUT
13
38
P23
P10/OUT2
P11/SCL1
P12/SCL2
16
37
P13/SDA1
P46/SCLK
AVCC
17
36
18
35
P14/SDA2
P15
HLF/AD6
19
34
P72/RVCO
20
33
P71/VHOLD
21
32
P70/CVIN
CNV SS
XIN
22
31
P30
P31
23
30
RESET
24
29
XOUT
VSS
25
28
P64/OSC2/XCOUT
P63/OSC1/XCIN
26
27
VCC
11
14
15
M37274EFSP
HSYNC
40
39
P16/INT3
P03/DA
Outline 52P4B
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Memory Map
000016
10000 16
Not used
10800 16
RAM
(1024 bytes)
00C0 16
00FF16
010016
Zero page
SFR1 area
020016
024816
SFR2 area
155FF 16
Not used
02C0 16
02FF16
030016
Not used
ROM correction memory
Block 1 : addresses 02C0 16 to 02DF 16
Block 2 : addresses 02E0 16 to 02FF 16
18000 16
ROM for OSD
(11072 bytes)
053F16
Not used
RAM for OSD (Note)
(1920 bytes)
080016
0FF716
Not used
100016
ROM
(60 K bytes)
1E41F 16
Not used
FF0016
FFDE16
FFFF16
114
1FFFF 16
Interrupt vector area
Special page
Note : Refer to Table 13. Contents of OSD RAM.
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Memory Map of Special Function Register
(SFR)
■SFR1 area (addresses C016 to DF16)
< Bit allocation >
:
Name
< State immediately after reset >
0 : “0” immediately after reset
Function bit
:
1 : “1” immediately after reset
: No function bit
? : Indeterminate immediately
after reset
0 : Fix to this bit to “0”
(do not write to “1”)
1 : Fix to this bit to “1”
(do not write to “0”)
Address
Register
Bit allocation
State immediately after reset
b7
C016
C116
C216
C316
C416
C516
C616
C716
C816
C916
CA16
CB16
CC16
CD16
CE16
CF16
D016
D116
D216
D316
D416
D516
D616
D716
D816
D916
DA16
DB16
DC16
DD16
DE16
DF16
b0 b7
b0
Port P0 (P0)
Port P0 direction register (D0)
Port P1 (P1)
Port P1 direction register (D1)
Port P2 (P2)
Port P2 direction register (D2)
Port P3 (P3)
Port P3 direction register (D3)
P6IM T3SC
Port P4 (P4)
Port P4 direction register (D4)
0
P46D P45D
Port P5 (P5)
OSD port control register (PF)
Port P6 (P6)
Port P7 (P7)
OSD control register (OC)
0
OUT2 OUT1
B
G
R
0
0
0
OC7 OC6 OC5 OC4 OC3 OC2 OC1 OC0
Horizontal position register (HP) HP7 HP6 HP5 HP4 HP3
Block control register 1 (BC1)
BC17 BC16 BC 15 BC14 BC 13
Block control register 2 (BC2)
BC27 BC26 BC 25 BC24 BC 23
Block control register 3 (BC3)
BC37 BC36 BC 35 BC34 BC 33
HP2 HP1 HP0
BC12 BC 11 BC10
BC22 BC 21 BC20
BC32 BC 31 BC30
Block control register 4 (BC4)
BC47 BC46 BC 45 BC44 BC 43 BC42 BC 41 BC40
Block control register 5 (BC5)
BC57 BC56 BC 55 BC54 BC 53 BC52 BC 51 BC50
Block control register 6 (BC6)
BC67 BC66 BC 65 BC64 BC 63 BC62 BC 61 BC60
Block control register 7 (BC7)
BC77 BC76 BC 75 BC74 BC 73 BC72 BC 71 BC70
Block control register 8 (BC8)
BC87 BC86 BC 85 BC84 BC 83 BC82 BC 81 BC80
Block control register 9 (BC9)
BC97 BC96 BC 95 BC94 BC 93 BC92 BC 91 BC90
Block control register 10 (BC10)
BC107 BC106 BC105 BC104 BC103 BC102 BC101 BC100
Block control register 11 (BC11)
BC117 BC116 BC115 BC114 BC113 BC112 BC111 BC110
Block control register 12 (BC12)
Block control register 13 (BC13)
Block control register 14 (BC14)
Block control register 15 (BC15)
Block control register 16 (BC16)
BC127 BC126 BC125 BC124 BC123 BC122 BC121 BC120
BC137 BC136 BC135 BC134 BC133 BC132 BC131 BC 130
BC147 BC146 BC145 BC144 BC143 BC142 BC141 BC140
BC157 BC156 BC155 BC154 BC153 BC152 BC151 BC150
BC167 BC166 BC165 BC164 BC163 BC162 BC161 BC160
0
0
?
0016
?
0016
?
0016
?
0016
?
0016
?
0016
?
0 0
0016
0016
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
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M37274EFSP
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
■SFR1 area (addresses E016 to FF16)
< Bit allocation >
:
Name
< State immediately after reset >
0 : “0” immediately after reset
Function bit
:
1 : “1” immediately after reset
: No function bit
? : Indeterminate immediately
after reset
0 : Fix to this bit to “0”
(do not write to “1”)
1 : Fix to this bit to “1”
(do not write to “0”)
Address
Register
Bit allocation
b7
E016
E116
E216
E316
E416
E516
E616
E716
E816
E916
EA16
EB16
EC16
ED16
EE16
EF16
F016
F116
F216
F316
F416
F516
F616
F716
F816
F916
FA16
FB16
FC16
FD16
FE16
FF16
116
Caption position register (CP)
Start bit position register (SP)
Window register (WN)
Sync slice register (SSL)
1
0
State immediately after reset
b0 b7
0 CP4 CP3 CP2 CP1 CP0
b0
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
0
SSL7
0 WN5 WN4 WN3 WN2 WN1 WN0
0 0 0 0 1 0 1
Caption data register 1 (CD1)
Caption data register 2 (CD2)
Clock run-in register 1 (CR1)
Clock run-in register 2 (CR2)
Clock run-in detect register 1 (CRD1)
0
1
1
0
0
0
1
1
CR13 CR12 CR11 CR10
1
1
CR21
1
CRD17 CRD15 CRD15 CRD15 CRD15
Clock run-in detect register 2 (CRD2)
CRD27 CRD25 CRD25 CRD25 CRD25 CRD22 CRD21 CRD20
Data slicer control register 1 (DSC1)
Data slicer control register 2 (DSC2)
DSC17
DSC27
0
0
DSC15
DSC25
0
0
0
0
DSC22 DSC21 DSC20
?
?
0
0
?
?
ADIN2 ADIN1 ADIN0
0
?
0
0
0
0
0
0
1
DSC12 DSC11 DSC10
Caption data register 3 (CD3)
Caption data register 4 (CD4)
A-D conversion register (AD)
A-D control register (ADCON)
Timer 1 (TM1)
Timer 2 (TM2)
Timer 3 (TM3)
Timer 4 (TM4)
Timer mode register 1 (TM1)
Timer mode register 2 (TM2)
I2C data shift register (S0)
I2C address register (S0D)
I2C status register (S1)
I2C control register (S1D)
I2C clock control register (S2)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
0
0
ADVREF ADSTR
TM17 TM16 TM15 TM14 TM13 TM12 TM11 TM10
TM27 TM26 TM25 TM24 TM23 TM22 TM21 TM20
D7
D6
D5
D4
D3
D2
D1
D0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
MST TRX BB
PIN
AL AAS AD0 LRB
BSEL1 BSEL0 10 BIT ALS ES0 BC2 BC1 BC0
SAD
ACK FAST
ACK BIT
CCR4 CCR3 CCR2 CCR1 CCR0
MODE
CM7 CM6 CM5
1
1
CM2
0
0
ADR VSCR CRTR TM4R TM3R TM2R TM1R
0
T56R IICR INT2R
CK01MSR SIOR DSR INT1R
ADE VSCE CRTE TM4E TM3E TM2E TM1E
T56S T56E IICE INT2E 1MSE SIOE DSE INT1E
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0 0
0 0
0016
0016
?
0 1
FF16
0716
FF16
0716
0016
0016
?
0016
1 0
0016
0016
1 1
0016
0016
0016
0016
0
?
0
0
0
0
0
0
0
0
0
?
1
0
0
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M37274EFSP
L
PRE
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
■SFR2 area (addresses 20016 to 21F16)
< Bit allocation >
:
Name
< State immediately after reset >
0 : “0” immediately after reset
Function bit
:
1 : “1” immediately after reset
: No function bit
? : Indeterminate immediately
after reset
0 : Fix to this bit to “0”
(do not write to “1”)
1 : Fix to this bit to “1”
(do not write to “0”)
Address
Register
Bit allocation
State immediately after reset
b7
20016
20116
20216
20316
20416
20516
20616
20716
20816
20916
20A16
20B16
20C16
20D16
20E16
20F16
21016
21116
21216
21316
21416
21516
21616
21716
21816
21916
21A16
21B16
21C16
21D16
21E16
21F16
b0 b7
b0
PWM0 register (PWM0)
PWM1 register (PWM1)
PWM2 register (PWM2)
PWM3 register (PWM3)
PWM4 register (PWM4)
PWM5 register (PWM5)
PWM6 register (PWM6)
Clock run-in detect register 3 (CRD3) CRD35 CRD34 CRD33 CRD32 CRD31
CR36 CR35 CR34 CR33 CR32 CR31 CR30
Clock run-in register (CR3)
PWM mode register 1 (PN)
PWM mode register 2 (PW)
PN3 PN2 PN1 PN0
0 PW6 PW5 PW4 PW3 PW2 PW1 PW0
?
?
?
1
0
0
Timer 5 (TM5)
Timer 6 (TM6)
0016
Sync pulse counter register (SYC)
SYC5 SYC4 SYC3 SYC2 SYC1 SYC0
Data slicer control register 3 (DSC3)
DSC37 DSC36 DSC35 DSC34 DSC33 DSC32 DSC31 DSC30
Interrupt input polarity register (IP)
AD/INT3 INT3
SEL
POL
Serial I/O mode register (SM)
0
0
0
INT2 INT1
RE3
POL POL
0
0
0
RE5 SM4 SM3
SM5
RE3 SM2
RE2 SM1
RE1 SM0
Serial I/O register (SIO)
Clock source control register (CS)
I/O polarity control register (PC)
Raster color register (RC)
Extra font color register (EC)
Border color register (FC)
Window H register 1 (WH1)
Window L register 1 (WL1)
Window H register 2 (WH2)
Window L register 2 (WL2)
INT3
0
RE5
RE3 RE2 RE1
CS6
POL CS5 CS4 CS3 CS2 CS1 CS0
AD/INT3
PC7
SEL
AD/INT3
RC7
SEL
PC6
RE5
PC5 PC4 RE3
RE2 PC1
RE1 PC0
0 PC2
POL
INT3
INT3
RC6
RC5
POL RE5
RE5
0
0
0
0
0
0
0
0
RE2
RC2 RC1
RE1 RC0
RE2
EC2 RE1
EC1 EC0
0
0
0
FC2 FC1 FC0
WH17 WH16 WH15 WH14 WH13 WH12 WH11 WH10
WL17 WL16 WL15 WL14 WL13 WL12 WL21 WL20
WH21 WH20
WL21 WL20
?
?
?
?
?
?
?
?
0016
?
? 0
0016
0716
FF16
0016
0016
0016
?
0016
0016
?
?
0016
0 0
0016
0016
0016
0016
?
?
?
?
0
0
0
0
0
0
117
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M37274EFSP
L
PRE
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
■ SFR2 area (addresses 22016 to 24816)
< State immediately after reset >
< Bit allocation >
:
Name
0 : “0” immediately after reset
Function bit
:
1 : “1” immediately after reset
: No function bit
? : Indeterminate immediately
after reset
0 : Fix to this bit to “0”
(do not write to “1”)
1 : Fix to this bit to “1”
(do not write to “0”)
Address
22016
22116
22216
22316
22416
22516
22616
22716
22816
22916
22A16
22B16
22C16
22D16
22E16
22F16
23016
23116
23216
23316
23416
23516
23616
23716
23816
23916
23A16
23B16
23C16
23D16
23E16
23F16
24016
24116
24216
24316
24416
24516
24616
24716
24816
118
Register
b7
Bit allocation
b0 b7
Vertical position register 11 (VP11)
VP117 VP116 VP1 15 VP114 VP1 13 VP112 VP1 11 VP1 10
Vertical position register 12 (VP12)
VP127 VP126 VP1 25 VP124 VP1 23 VP122 VP1 21 VP1 20
Vertical position register 13 (VP13)
Vertical position register 14 (VP14)
VP137 VP136 VP1 35 VP134 VP1 33 VP132 VP1 31 VP1 30
Vertical position register 15 (VP15)
Vertical position register 16 (VP16)
VP157 VP156 VP1 55 VP154 VP1 53 VP152 VP1 51 VP1 50
Vertical position register 17 (VP17)
VP177 VP176 VP1 75 VP174 VP1 73 VP172 VP1 71 VP1 70
Vertical position register 18 (VP18)
Vertical position register 19 (VP19)
VP187 VP186 VP1 85 VP184 VP1 83 VP182 VP1 81 VP1 80
Vertical position register 110 (VP110)
VP1107 VP1106 VP1 105 VP1104 VP1103 VP1102 VP1101 VP1100
Vertical position register 111 (VP111)
Vertical position register 112 (VP112)
VP1117 VP1116 VP1 115 VP1114 VP1113 VP1112 VP1111 VP1110
Vertical position register 113 (VP113)
Vertical position register 114 (VP114)
VP1137 VP1136 VP1 135 VP1134 VP1133 VP1132 VP1131 VP1130
Vertical position register 115 (VP115)
Vertical position register 116 (VP116)
Vertical position register 21 (VP21)
VP1157 VP1156 VP1 155 VP1154 VP1153 VP1152 VP1151 VP1150
b0
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
VP147 VP146 VP1 45 VP144 VP1 43 VP142 VP1 41 VP1 40
VP167 VP166 VP1 65 VP164 VP1 63 VP162 VP1 61 VP1 60
VP197 VP196 VP1 95 VP194 VP1 93 VP192 VP1 91 VP1 90
VP1127 VP1126 VP1 125 VP1124 VP1123 VP1122 VP1121 VP1120
VP1147 VP1146 VP1 145 VP1144 VP1143 VP1142 VP1141 VP1140
VP1167 VP1166 VP1 165 VP1164 VP1163 VP1162 VP1161 VP1160
VP211 VP210
Vertical position register 22 (VP22)
VP221 VP220
Vertical position register 23 (VP23)
VP231 VP230
Vertical position register 24 (VP24)
VP241 VP240
Vertical position register 25 (VP25)
Vertical position register 26 (VP26)
VP251 VP250
Vertical position register 27 (VP27)
VP271 VP270
Vertical position register 28 (VP28)
Vertical position register 29 (VP29)
VP281 VP280
Vertical position register 210 (VP210)
VP2101 VP2100
Vertical position register 211 (VP211)
Vertical position register 212 (VP212)
VP2111 VP2110
Vertical position register 213 (VP213)
VP2131 VP2130
Vertical position register 214 (VP214)
VP2141 VP2140
Vertical position register 215 (VP215)
Vertical position register 216 (VP216)
DA-H register (DA-H)
VP2151 VP2150
VP261 VP260
VP291 VP290
VP2121 VP2120
VP2161 VP2160
0
DA-L register (DA-L)
ROM correction address 1 (high-order)
ROM correction address 1 (low-order)
ROM correction address 2 (high-order)
ROM correction address 2 (low-order)
ROM correction enable register (RCR)
State immediately after reset
0
0016
0
0
RCR1 RCR0
0
0
0
?
? ?
0016
0016
0016
0016
0016
0016
0016
?
?
?
MITSUBISHI MICROCOMPUTERS
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not
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Not e para
Som
M37274EFSP
L
PRE
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Internal State of Processor Status Register and
Program Counter at Reset
< State immediately after reset >
< Bit allocation >
:
Name
0 : “0” immediately after reset
Function bit
:
1 : “1” immediately after reset
: No function bit
? : Indeterminate immediately
after reset
0 : Fix to this bit to “0”
(do not write to “1”)
1 : Fix to this bit to “1”
(do not write to “0”)
Register
Bit allocation
State immediately after reset
b0 b7
b7
Processor status register (PS)
Program counter (PCH)
Program counter (PCL)
N
V
T
B
D
I
Z
C
b0
?
? ? ? ? 1 ? ?
Contents of address FFFF 16
Contents of address FFFE 16
119
MITSUBISHI MICROCOMPUTERS
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M37274EFSP
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Structure of Register
The figure of each register structure describes its functions, contents
at reset, and attributes as follows:
Note : The following registers are the EPROM version’s registers.
They are different from the MASK version’s.
Bit attributes (Note 2)
Bits
Values immediately after reset release (Note 1)
CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
1 1
0 0
CPU mode register (CPUM) (CM) [Address FB 16]
B
Name
Processor
mode bits
0, 1
(CM0, CM1)
2
Stack page selection
bit (Note) (CM2)
Functions
b1 b0
0
0
1
1
After reset R W
0
RW
0
RW
1
RW
0: Single-chip mode
1:
0:
Not available
1:
0: 0 page
1: 1 page
3, 4 Fix these bits to “1.”
Nothing is assigned.1This bit is write disable bit.
When this bit is read out, the value is “0.”
b7 b6
6, 7 Clock switch bits
(CM6, CM7)
0 0: f(X IN) = 8 MHz
0 1: f(X IN) = 12 MHz
1 0: f(X IN) = 16 MHz
1 1: Do not set
RW
5
0
RW
: Bit in which nothing is assigned
Notes 1: Values immediately after reset release
0••••••“0” after reset release
1••••••“1” after reset release
?••••••Indeterminate after reset release
2: Bit attributes••••••The attributes of control register bits are classified into 3 types : read-only, write-only
and read and write. In the figure, these attributes are represented as follows :
W••••••Write
R••••••Read
••••••Write enabled
••••••Read enabled
✕ ••••••Read disabled
✕ ••••••Write disabled
✽ ••••••“0” can be set by software, but “1”
cannot be set.
120
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M37274EFSP
L
PRE
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Port Pi Direction Register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (Di) (i=0,1,2) [Addresses 00C116, 00C316, 00C516]
B
0
Name
Functions
After reset R W
0 : Port Pi0 input mode
1 : Port Pi0 output mode
0
R W
1
0 : Port Pi1 input mode
1 : Port Pi1 output mode
0
R W
2
0 : Port Pi2 input mode
1 : Port Pi2 output mode
0
R W
3
0 : Port Pi3 input mode
1 : Port Pi3 output mode
0
R W
4
0 : Port Pi4 input mode
1 : Port Pi4 output mode
0
R W
5
0 : Port Pi5 input mode
1 : Port Pi5 output mode
0
R W
6
0 : Port Pi6 input mode
1 : Port Pi6 output mode
0
R W
7
0 : Port Pi7 input mode
1 : Port Pi7 output mode
0
R W
Port Pi direction register
Port Pi Direction Register
Addresses 00C116, 00C316, 00C516
Port P3 Direction Register
b7 b6 b5 b4 b3 b2 b1 b0
Port P3 direction register (D3) [Address 00C716]
B
0
Name
Port P3 direction register
1
Functions
After reset R W
0 : Port P30 input mode
1 : Port P30 output mode
0
R W
0 : Port P31 input mode
1 : Port P31 output mode
0
R W
0
R —
2
to
5
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
6
Timer 3 count source
selection bit (T3SC)
Refer to Timer mode register 2
(address 00F5 16).
0
R W
7
Ports P63 , P64 selection
bit (P6IM)
Refer to clock source control
register (address 0216 16 ).
0
R W
Port P3 Direction Register
Address 00C716
121
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Port P4 Direction Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Port P4 direction register (D4) [Address 00C9 16]
B
Name
0
Fix this bit to “0.”
Functions
1 to 4, Nothing is assigned. These bits are write disable bits.
7 When these bits are read out, the values are “0.”
After reset R W
0
R W
0
R —
5
Port P45 selection bit
0: SOUT pin
1: Input port P45
0
R W
6
Port P46 selection bit
0: SCLK pin
1: Input port P46
0
R W
Port P4 Direction Register
Address 00C916
OSD Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
OSD port control register (PF) [Address 00CB16]
B
Name
Functions
0, 1, Fix these bits to “0.”
7
After reset R W
0
R W
2
Port P5 2 output signal
selection bit (R)
0 : R signal output
1 : Port P52 output
0
R W
3
Port P5 3 output signal
selection bit (G)
0 : G signal output
1 : Port P53 output
0
R W
4
Port P5 4 output signal
selection bit (B)
0 : B signal output
1 : Port P54 output
0
R W
5
Port P5 5 output signal
selection bit (OUT1)
0 : OUT1 signal output
1 : Port P55 output
0
R W
6
Port P1 0 output signal
selection bit (OUT2)
0 : Port P10 output
1 : OUT2 signal output (Note)
0
R W
Note. Set bit 0 of Port P1 direction register (address 00C3 16) to "1" (output mode).
OSD Port Control Register
122
Address 00CB16
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
OSD Control Register
b7 b6 b5 b4 b3 b2 b1 b0
OSD control register (OC) [Address 00CE16]
B
Functions
Name
After reset R W
0 : All-blocks display off
0 OSD control bit
(OC0) (See note 1) 1 : All-blocks display on
1 Scan mode selection 0 : Normal scnan mode
1 : Bi-scan mode
bit (OC1)
2 Border type selection 0 : All bordered
bit (OC2)
1 : Shadow bordered (See note 2)
Flash mode selection 0 : Color signal of character background
bit (OC3)
part does not flash
1 : Color signal of character background
part flashes
3
0
R W
0
R W
0
R W
0
R W
4 Automatic solid space
control bit (OC4)
0 : OFF
1 : ON
0
R W
5 Window control bit
(OC5)
0 : OFF
1 : ON
0
R W
0
R W
6, 7 Layer mixing control
bits (OC6, OC7)
(See note 3)
b7 b6
0 0: Logic sum (OR) of layer 1’s
color and layer 2’s color
0 1: Layer 1’s color has priority
1 0: Layer 2’s color has priority
1 1: Do not set.
Notes 1 : Even this bit is switched during display, the display screen
remains unchanged until a rising (falling) of the next V SYNC.
2 : Shadow border is output at right and bottom side of the font.
3 : Set “00” during displaying extra fonts.
OSD Control Register
Address 00CE16
Horizontal Position Register
b7 b6 b5 b4 b3 b2 b1 b0
Horizontal position register (HP) [Address 00CF16 ]
B
Name
0 Control bits of horizontal
to display start positions
7 (HP0 to HP7)
Functions
Horizontal display start positions
4TOSC ✕
(setting value of high-order 4 bits ✕ 161 +
setting value of low-order 4 bits ✕ 160 )
After reset R W
0
R W
Notes 1. The setting value synchronizes with the V SYNC.
2. TOSC = OSD oscillation period.
Horizontal Position Register
Address 00CF16
123
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PRE
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Block Control register i
b7 b6 b5 b4 b3 b2 b1 b0
Block control register i (BCi) (i=1 to 16) [Addresses 00D016 to 00DF 16](See note 1)
B
Name
0, 1 Display mode
selection bits
(BCi0, BCi1)
2
Border control bit
(BCi2)
3, 4 Dot size selection
bits (BCi3, BCi4)
5, 6 Pre-divide ratio •
layer selection bit
(BCi5, BCi6)
7
OUT2 output control bit
(BCi7) (See note 2)
Functions
b1
0
0
1
1
After reset
b0
Indeterminate R W
0: Display OFF
1: OSD mode
0: CC mode
1: EXOSD mode
0: Border OFF
1: Border ON
b6
R W
b5
0
0
0
1
1
0
1
1
1
1
b4
0
0
1
1
0
0
1
1
0
0
1
1
—
—
0
0
1
1
b3 CS6 Pre-divide
ratio
0
0
1 —
✕1
1
0
1
✕2
0 —
1
0
1
✕3
0 —
1
✕1
0
1 0
0
✕2
1 1
0
1
Indeterminate R W
Dot size
Display
layer
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
Layer1
3Tc ✕ 3H
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
1Tc ✕ 1/2H
1Tc ✕ 1H
1Tc ✕ 1/2H Layer2
1Tc ✕ 1H
1.5Tc ✕ 1/2H
1.5Tc ✕ 1H
BC17: Window top boundary
BC27: Window bottom boundary
Indeterminate R W
Indeterminate R W
Indeterminate R W
Notes 1: Note that MASK version the block control registers at addresses 00D016 to 00DB 16
when programming.
2: Bit 4 of the color code 1 controls OUT1 output when bit 7 is "0".
Bit 4 of the color code 1 controls OUT2 output when bit 7 is "1".
3: CS6 : Bit 6 of the clock control register (address 0216 16)
4: Tc : Pre-devided clock period for OSD
5: H : Hsync
Block Control Register i
124
Addresses 00D016 to 00DB16
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M37274EFSP
L
PRE
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Caption Position Register
b7 b6 b5 b4 b3 b2 b1 b0
1
0
0
Caption Position Register (CP) [Address 00E0 16]
Name
B
Functions
0 Specification main data
to slice line (CP0 to CP4)
4
5, 6 Fix these bits to “0.”
7
Fix this bit to “0.”
After reset
R W
0
R W
0
R W
0
R W
Caption Position Register
Address 00E016
Start Bit Position Register
b7 b6 b5 b4 b3 b2 b1 b0
Start bit position register (SP) [Address 00E116]
After reset
R W
0
to
6
Start bit generating time Time from a falling of the horizontal
(SP0 to SP6)
synchronous signal to occurrence
of a start bit =
4 ✕ set value (“00 16” to “7F16”) ✕
reference clock period
0
R W
7
DSC1 bit 7 control bit
(SP7)
0
R W
B
Name
Functions
0 : Generation of 16 pulses
1 : Generation of 16 pulses and
detection of clock run-in
pulse (4 to 6 pulses)
Start Bit Position Register
Address 00E116
Window Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Window register (WN) [Address 00E2 16]
B
0
to
5
Name
Window start time
(WN0 to WN5)
6, 7 Fix these bits to “0.”
Window Register
Functions
Time from a falling of the horizontal
synchronous signal to start of the
window =
4 ✕ set value (“00 16” to “3F16”) ✕
reference clock period
After reset
R W
0
R W
0
R W
Address 00E216
125
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Sync Slice Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
1
0
1
Sync slice register (SSL) [Address 00E3 16]
After reset
R W
Fix these bits to “1.”
0
R W
1, Fix these bits to “0.”
3 to 6
0
R W
0
R W
B
0, 2
7
Name
Vertical synchronous
signal (V sep) generating
method selection bit
(SSL7)
Functions
0: Method 1
1: Method 2
Sync Slice Register
Address 00E316
Clock Run-in Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
1
0
1
Clock run-in register 1 (CR1) [Address 00E6 16]
B
Name
Functions
After reset
R W
0
to
3
Clock run-in count value
of main-data slice line
(CR10 to CR13)
0
R W
4, 6
Fix these bits to “1.”
0
R W
5, 7
Fix these bits to “0.”
0
R W
Clock Run-in Register 1
Address 00E616
Clock Run-in Register 2
b7 b6 b5 b4 b3 b2 b1 b0
1
0
0
1
1
1
1
Clock run-in register 2 (CR2) [Address 00E716]
B
Name
Functions
0,
Fix these bits to “1.”
2 to 4,
7
Clock Run-in Register 2
126
1
Start bit detecting
method selection bit
(CR21)
5, 6
Fix these bits to “0.”
0: Method 1
1: Method 2
After reset
R W
0
R W
0
R W
0
R W
Address 00E716
MITSUBISHI MICROCOMPUTERS
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M37274EFSP
L
PRE
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Clock Run-in Detect Register i
b7 b6 b5 b4 b3 b2 b1 b0
Clock run-in detect register i (CRDi) (i=1, 3) [Addresses 00E8 16, 020816]
After reset
R W
0
to
2
Test bits
Read-only
0
R W
3
to
7
Clock run-in detection bits
(CRDi3 to CRDi7)
Number of reference clock s
to be counted one clock runin pulse period
0
R —
B
Name
Functions
Clock Run-in detect Register i
Addresses 00E816, 020816
Clock Run-in Detect Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Clock run-in detect register 2 (CRD2) [Address 00E916]
B
Functions
After reset
R W
b0
0 : Not available
1 : 1st pulse
0 : 2nd pulse
1 : 3rd pulse
0 : 4th pulse
1 : 5th pulse
0 : 6th pulse
1 : 7th pulse
0
R W
Time from detection of a start
bit to occurrence of a data clock
= (13 + set value) ✕
reference clock period
0
R W
Name
0
to
2
Clock run-in pulses for
sampling
(CRD20 to CRD22)
b2
0
0
0
0
1
1
1
1
3
to
7
Data clock generating
time
(CRD23 to CRD27)
b1
0
0
1
1
0
0
1
1
Clock Run-in detect Register 2
Address 00E916
127
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Data Slicer Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
Data slicer control register 1(DSC1) [Address 00EA16]
B
0
Bit
Data slicer control bit
(DSC10)
1, 2 Field to be sliced data
selection bit
(DSC11, DSC12)
After reset
R W
0: Data slicer stopped
1: Data slicer operating
Functions
0
R W
Field of main
b1 data slice line
0
F2
1
F1
0
F1 and F2
1
F1 and F2
0
R W
0
R W
b2
0
0
1
1
Field for setting
refernce voltage
F2
F1
F2
F1
3, 4, Fix these bits to “0.”
6
5
Field determination
flag
(DSC15)
Indeterminate R —
0 : Hsep
Vsep
1 : Hsep
Vsep
7
Data latch completion
flag for caption data in
main data slice line
(DSC17)
0: Data is not yet latched
1: Data is latched
Indeterminate R W
Definition of fields 1 (F1) and 2 (F2)
F1 : Hsep
VSYNC
Vsep
F2 : Hsep
VSYNC
Vsep
Data Slicer Control Register 1
128
Address 00EA16
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M37274EFSP
L
PRE
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Data slicer Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
Data slicer Control register 2 (DSC2) [Address 00EB16]
B
After reset
R W
0
Timing signal generating
circuit control bit (DSC20)
Name
0: Stopped
1: Operating
Functions
0
R W
1
Reference clock source
selection bit (DSC21)
0: Video signal
1: HSYNC signal
0
R W
Indeterminate R —
Read-only
2, 7 Test bit
0
3, 4, Fix these bits to “0.”
6
V-pulse shape determination 0: Match
flag (DSC25)
1: Mis match
5
R W
Indeterminate R —
Data Slicer Control Register 2
Address 00EB16
A-D Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
A-D control register (ADCON) [Address 00EF 16]
B
Name
0
to
2
Analog input pin selection
bits
(ADIN0 to ADIN2)
b2
0
0
0
0
1
1
1
1
3
A-D conversion completion
bit (ADSTR)
4
VCC connection selection bit
(ADVREF)
6
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is indeterminate.
5, 7 Fix these bits to “0.”
A-D Control Register
Functions
b1
0
0
1
1
0
0
1
1
b0
0 : AD1
1 : AD2
0 : AD3
1 : AD4
0 : AD5
1 : AD6
0:
Do not set.
1:
After reset R W
0
R W
0: Conversion in progress
1: Convertion completed
Indeterminate
R W
0: OFF
1: ON
Indeterminate
R W
Indeterminate
R —
0
R —
Address 00EF16
129
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Timer Mode Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer mode register 1 (TM1) [Address 00F4 16]
B
Name
0 Timer 1 count source
selection bit 1 (TM10)
Functions
After reset R W
0: f(XIN)/16 or f(X CIN)/16 (Note)
0
R W
1: Count source selected by bit 5 of TM1
1
Timer 2 count source
selection bit 1 (TM11)
0: Count source selected by bit 4 of TM1
1: External clock from TIM2 pin
0
R W
2
Timer 1 count
stop bit (TM12)
Timer 2 count stop
bit (TM13)
0: Count start
1: Count stop
0: Count start
1: Count stop
0
R W
0
R W
4
Timer 2 count source
selection bit 2
(TM14)
0: f(XIN)/16 or f(X CIN)/16 (See note)
1: Timer 1 overflow
0
R W
5
Timer 1 count source
selection bit 2 (TM15)
0: f(XIN)/4096 or f(X CIN)/4096 (See note)
1: External clock from TIM2 pin
0
R W
6
Timer 5 count source
selection bit 2 (TM16)
0: Timer 2 overflow
1: Timer 4 overflow
0
R W
7
Timer 6 internal count
source selection bit
(TM17)
0: f(XIN)/16 or f(X CIN)/16 (See note)
1: Timer 5 overflow
0
R W
3
Note: Either f(X IN) or f(X CIN) is selected by bit 7 of the CPU mode register.
Timer Mode Register 1
130
Address 00F416
MITSUBISHI MICROCOMPUTERS
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M37274EFSP
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Not e para
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L
PRE
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Timer Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer mode register 2 (TM2) [Address 00F516]
B
Name
0 Timer 3 count source
selection bit (TM20)
1, 4 Timer 4 count source
selection bits
(TM21, TM24)
Functions
(b6 at address 00C7 16)
b0
0 0 : f(X IN)/16 or f(XCIN)/16 (See note)
0 1 : f(X CIN)
1 0:
External clock from TIM3 pin
1 1:
b4
0
0
1
1
After reset R W
0
R W
b1
0 : Timer 3 overflow signal
1 : f(X IN)/16 or f(XCIN)/16 (See note)
0 : f(X IN)/2 or f(XCIN)/2 (See note)
1 : f(X CIN)
0
R W
2
Timer 3 count
stop bit (TM22)
0: Count start
1: Count stop
0
R W
3
Timer 4 count stop bit
(TM23)
0: Count start
1: Count stop
0
R W
5
Timer 5 count stop bit
(TM25)
0: Count start
1: Count stop
0
R W
6
Timer 6 count stop bit
(TM26)
0: Count start
1: Count stop
0
R W
7
Timer 5 count source
selection bit 1
(TM27)
0: f(XIN)/16 or f(X CIN)/16 (See note)
1: Count source selected by bit 6
of TM1
0
R W
Note: Either f(X IN) or f(X CIN) is selected by bit 7 of the CPU mode register.
Timer Mode Register 2
Address 00F516
I2C Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0
2
I C data shift register1(S0) [Address 00F6 16]
B
0
to
7
Name
Functions
D0 to D7
This is an 8-bit shift register to store
receive data and write transmit data.
After reset
R W
Indeterminate R W
Note: To write data into the I2C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
I2C Data Shift Register
Address 00F616
131
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
I2C Address Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C address register (S0D) [Address 00F716]
B
Name
Functions
After reset R W
0
Read/write bit
(RBW)
0: Read
1: Write
0
R —
1
to
7
Slave address
(SAD0 to SAD6)
The address data transmitted from
the master is compared with the
contents of these bits.
0
R W
I2C Address Register
Address 00F716
I2C Status Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C status register (S1) [Address 00F816]
B
Name
Functions
0
Last receive bit (LRB)
(See note)
0 : Last bit = “0 ”
1 : Last bit = “1 ”
1
General call detecting flag
(AD0) (See note)
2
After reset R W
Indeterminate
R —
0 : No general call detected
1 : General call detected
0
R —
Slave address comparison
flag (AAS) (See note)
0 : Address mismatch
1 : Address match
0
R —
3
Arbitration lost detecting flag
(AL) (See note)
0 : Not detected
1 : Detected
0
R —
4
I2C-BUS interface interrupt
request bit (PIN)
0 : Interrupt request issued
1 : No interrupt request issued
0
R —
5
Bus busy flag (BB)
0 : Bus free
1 : Bus busy
0
R W
b7
0
0
1
1
0
R W
6, 7 Communication mode
specification bits
(TRX, MST)
b6
0 : Slave recieve mode
1 : Slave transmit mode
0 : Master recieve mode
1 : Master transmit mode
Note : These bits and flags can be read out, but cannnot be written.
I2C Status Register
132
Address 00F816
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M37274EFSP
L
PRE
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
I2C Control Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C control register (S1D : address 00F9 16)
B
Name
Functions
0
to
2
Bit counter
(Number of transmit/recieve
bits)
(BC0 to BC2)
b2
0
0
0
0
1
1
1
1
3
I2 C-BUS interface use
enable bit (ESO)
4
5
b0
0:
1:
0:
1:
0:
1:
0:
1:
After reset R W
0
R W
0 : Disabled
1 : Enabled
0
R W
Data format selection bit
(ALS)
0 : Addressing mode
1 : Free data format
0
R W
Addressing format selection
bit (10BIT SAD)
0 : 7-bit addressing format
1 : 10-bit addressing format
0
R W
b7 b6 Connection port (See note)
0 0 : None
0 1 : SCL1, SDA1
1 0 : SCL2, SDA2
1 1 : SCL1, SDA1
SCL2, SDA2
0
R W
6, 7 Connection control bits
between I2C-BUS interface
and ports
b1
0
0
1
1
0
0
1
1
8
7
6
5
4
3
2
1
Note: When using ports P1 1 -P14 as I2C-BUS interface, the output structure changes
automatically from CMOS output to N-channel open-drain output.
I2C Control Register
Address 00F916
I2C Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0
I2 C clock control register (S2 : address 00FA 16)
B
0
to
4
Name
Functions
SCL frequency control bits Setup value of Standard clock
(CCR0 to CCR4)
CCR4–CCR0
mode
00 to 02
After reset R W
High speed
clock mode
0
R W
Setup disabled Setup disabled
03
Setup disabled
04
Setup disabled
333
250
05
100
400 (See note)
06
83.3
166
...
500/CCR value
1000/CCR value
1D
17.2
34.5
1E
16.6
33.3
1F
16.1
32.3
(at φ = 4 MHz, unit : kHz)
5
SCL mode
specification bit
(FAST MODE)
0 : Standard clock mode
1 : High-speed clock mode
0
R W
6
ACK bit
(ACK BIT)
0 : ACK is returned.
1 : ACK is not returned.
0
R W
7
ACK clock bit
(ACK)
0 : No ACK clock
1 : ACK clock
0
R W
Note: At 4000kHz in the high-speed clock mode, the duty is as below .
“0” period : “1” period = 3 : 2
In the other cases, the duty is as below.
“0” period : “1” period = 1 : 1
I2C Clock Control Register
Address 00FA16
133
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
1 1
0 0
CPU mode register (CPUM) (CM) [Address FB16]
B
Name
0, 1 Processor mode bits
(CM0, CM1)
Stack page selection
bit (CM2) (See note)
2
Functions
After reset R W
0
RW
1
RW
1
RW
0: LOW drive
1: HIGH drive
1
RW
0: Oscillating
1: Stopped
0
RW
0: X IN–XOUT selected
(high-speed mode)
1: X CIN–XCOUT selected
(high-speed mode)
0
RW
b1 b0
0
0
1
1
0: Single-chip mode
1:
0:
Not available
1:
0: 0 page
1: 1 page
3, 4 Fix these bits to “1.”
5 XCOUT drivability
selection bit (CM5)
6 Main Clock (X IN–XOUT)
stop bit
(CM6)
Internal system clock
selection bit
(CM7)
7
Note: This bit is set to “1” after the reset release.
CPU Mode Register
Address 00FB16
Interrupt Request Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address 00FC16]
B
0
1
2
3
4
5
6
7
Name
Functions
0 : No interrupt request issued
Timer 1 interrupt
1 : Interrupt request issued
request bit (TM1R)
Timer 2 interrupt
0 : No interrupt request issued
request bit (TM2R)
1 : Interrupt request issued
0 : No interrupt request issued
Timer 3 interrupt
1 : Interrupt request issued
request bit (TM3R)
0 : No interrupt request issued
Timer 4 interrupt
1 : Interrupt request issued
request bit (TM4R)
OSD interrupt request 0 : No interrupt request issued
1 : Interrupt request issued
bit (CRTR)
0 : No interrupt request issued
V SYNC interrupt
request bit (VSCR) 1 : Interrupt request issued
A-D conversion • INT3
0 : No interrupt request issued
interrupt request bit (ADR) 1 : Interrupt request issued
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
After reset R W
0
R ✽
0
R ✽
0
R ✽
0
R ✽
0
R ✽
0
R ✽
0
R ✽
0
R —
✽: “0” can be set by software, but “1” cannot be set.
Interrupt Request Register 1
134
Address 00FC16
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M37274EFSP
L
PRE
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Interrupt Request Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt request register 2 (IREQ2) [Address 00FD16]
B
Name
Functions
After reset R W
INT1 interrupt
request bit (INT1R)
1 Data slicer interrupt
request bit (DSR)
2 Serial I/O interrupt
request bit (SIOR)
3 f(XIN)/4096 interrupt
request bit (1MSR)
4 INT2 interrupt
request bit (INT2R)
5 Multi-master I 2C-BUS
interrupt request bit (IICR)
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
R ✽
0
R ✽
0
R ✽
0
R ✽
0
R ✽
0
R ✽
6
Timer 5 • 6 interrupt
request bit (T56R)
0 : No interrupt request issued
1 : Interrupt request issued
0
R ✽
7
Fix this bit to “0.”
0
R W
0
✽: “0” can be set by software, but “1” cannot be set.
Interrupt Request Register 2
Address 00FD16
Interrupt Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address 00FE16]
B
0
1
2
3
4
5
6
7
Interrupt Control Register 1
Name
Timer 1 interrupt
enable bit (TM1E)
Timer 2 interrupt
enable bit (TM2E)
Timer 3 interrupt
enable bit (TM3E)
Timer 4 interrupt
enable bit (TM4E)
OSD interrupt enable bit
(CRTE)
VSYNC interrupt enable
bit (VSCR)
A-D conversion • INT3
interrupt enable bit (ADE)
Functions
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Nothing is assigned. This bit is a write disable
bit. When this bit is read out, the value is “0.”
After reset R W
0
R W
0
R W
0
R W
0
R W
0
R W
0
R W
0
R W
0
R —
Address 00FE16
135
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Interrupt Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2 (ICON2) [Address 00FF16]
B
Name
0
INT1 interrupt
enable bit (INT1E)
Data slicer interrupt
enable bit (DSR)
Serial I/O interrupt
enable bit (SIOE)
f(XIN)/4096 interrupt
enable bit (1MSE)
INT2 interrupt enable
bit (INT2E)
Functions
After reset R W
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
R W
0
R W
0
R W
0
R W
0
R W
5
Multi-master I 2C-BUS interface 0 : Interrupt disabled
interrupt enable bit (IICE)
1 : Interrupt enabled
0
R W
6
Timer 5 • 6 interrupt
enable bit (T56E)
0 : Interrupt disabled
1 : Interrupt enabled
0
R W
7
Timer 5 • 6 interrupt
switch bit (TM56S)
0 : Timer 5
1 : Timer 6
0
R W
1
2
3
4
Interrupt Control Register 2
Address 00FF16
Clock Run-in Register 3
b7 b6 b5 b4 b3 b2 b1 b0
Clock run-in register 3 (CR3) [Address 020916]
Clock Run-in Register 3
136
B
Name
0
to
3
4
Clock run-in count value of
sub-data slice line (CR30
to CR33)
Data latch completion flag
for caption data in subdata slice line (CR34)
5
Functions
After reset
R W
0
R W
0: Data is not latched yet
1: Data is latched
Indeterminate R W
Data slice line selection bit
for interrupt request
(CR35)
0: Main data slice line
1: Sub- data slice line
Indeterminate R W
6
Interrupt mode selection bit
(CR36)
0: Interrupt occurs at end
of data slice line
1: Interrupt occurs at
completion of caption
data latch
Indeterminate R W
7
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
Indeterminate R —
Address 020916
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M37274EFSP
L
PRE
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
PWM Mode Register 1
b7 b6 b5 b4 b3 b2 b1 b0
PWM mode register 1 (PN) [Address 020A 16]
B
0
Name
PWM counts source
selection bit (PN0)
1
Functions
After reset
R W
0 : Count source supply
1 : Count source stop
0
R W
DA/P03 output
selection bit (PN1)
0 : P03 output
1 : DA output
0
R W
2
DA output polarity
selection bit (PN2)
0 : Positive polarity
1 : Negative polarity
0
R W
3
PWM output polarity
selection bit (PN3)
0 : Positive polarity
1 : Negative polarity
0
R W
4
to
7
Nothing is assigned. These bits are write disable bits. Indeterminate R —
When these bits are read out, the values are “0.”
PWM Mode Register 1
Address 020A16
PWM Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
PWM Mode Register 2
PWM mode register 2 (PW) [Address 020B 16]
B
Name
0 P04/PWM0 output
selection bit (PW0)
Functions
0 : P0 4 output
1 : PWM0 output
After reset R W
0
R W
1
P05/PWM1 output
selection bit (PW1)
0 : P0 5 output
1 : PWM1 output
0
R W
2
P06/PWM2 output
selection bit (PW2)
0 : P0 6 output
1 : PWM2 output
0
R W
3
P07/PWM3 output
selection bit (PW3)
0 : P0 7 output
1 : PWM3 output
0
R W
4
P00/PWM4 output
selection bit (PW4)
0 : P0 0 output
1 : PWM4 output
0
R W
5
P01/PWM5 output
selection bit (PW5)
0: P01 output
1: PWM5 output
0
R W
6
P02/PWM6 output
selection bit (PW6)
0: P02 output
1: PWM6 output
0
R W
7
Fix this bit to “0.”
0
R W
Address 020B16
137
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Sync Pulse Counter Register
b7 b6 b5 b4 b3 b2 b1 b0
Sync pulse counter register (SYC) [Address 020F16]
B
Name
Functions
0
to
4
Count value
(SYC0 to SYC4)
5
Count source (SYC5)
0: HSYNC signal
1: Composite sync signal
6, 7 Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
After reset
R W
0
R —
0
R W
0
R —
Sync Pulse Counter Register
Address 020F16
Data Slicer Control Register 3
b7 b6 b5 b4 b3 b2 b1 b0
Data slicer control register 3 (DSC3) [Address 021016]
B
0
Bit
Line selection bit for
slice voltage (DSC30)
1, 2 Field to be sliced data
selection bit
(DSC31, DSC32)
3
to
7
Functions
0: Main data slice line
1: Sub-data slice line
b2
0
0
1
1
Setting bit of sub-data
slice line
(DSC33 to DSC37)
Field of subb1 data slice line
0
F2
1
F1
0
F1 and F2
1
F1 and F2
Field for setting
refernce voltage
After reset
R W
0
R W
0
R W
0
R W
F2
F1
F2
F1
Definition of fields 1 (F1) and 2 (F2)
F1 : Hsep
VSYNC
Vsep
F2 : Hsep
VSYNC
Vsep
Data Slicer Control Register 3
138
Address 021016
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Not e para
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L
PRE
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Interrupt Input Polarity Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
Interrupt input polarity register (IP) [Address 0212 16]
B
Name
Functions
0 to 2, Fix these bits to “0.”
5
After reset
R W
0
R W
3
INT1 polarity switch bit
(INT1POL)
0 : Positive polarity
1 : Negative polarity
0
R W
4
INT2 polarity switch bit
(INT2POL)
0 : Positive polarity
1 : Negative polarity
0
R W
6
INT3 polarity switch bit
(INT3POL)
0 : Positive polarity
1 : Negative polarity
0
R W
7
A-D conversion • INT3
interrupt source selection
bit (RE7)
0 : Positive polarity
1 : Negative polarity
0
R W
Interrupt Input Polarity Register
Address 021216
Serial I/O Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Serial I/O mode register (SM) [Address 0213 16]
B
Name
0, 1 Internal synchronous
clock selection bits
(SM0, SM1)
b0
0: f(X IN)/4 or f(X CIN)/4
1: f(X IN)/16 or f(X CIN)/16
0: f(X IN)/32 or f(X CIN)/32
1: f(X IN)/64 or f(X CIN)/64
After reset R W
R W
0
2
Synchronous clock
selection bit (SM2)
0: External clock
1: Internal clock
0
R W
3
Port function
selection bit (SM3)
0: P1 1, P1 3
1: SCL1, SDA1
0
R W
4
Port function
selection bit (SM4)
0: P1 2, P1 4
1: SCL2, SDA2
0
R W
5
Transfer direction
selection bit (SM5)
0: LSB first
1: MSB first
0
R W
0
R W
6, 7 Fix these bits to “0.”
Serial I/O Mode Register
Functions
b1
0
0
1
1
Address 021316
139
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M37274EFSP
L
PRE
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Clock Source Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Clock source control register (CS) [Address 0216 16 ]
B
0
Name
CC mode clock
selection bit (CS0)
1, 2 OSD mode clock selection
bits (CS1, CS2)
3
EXOSD mode clock
selection bit (CS3)
4, 5 OSD oscillating mode
selection bits (CS4, CS5)
6
Pre-divide ratio of layer 2
selection bit (CS6)
7
Test bit
(See note 3)
Functions
After reset R W
0: Data slicer clock
1: OSC1 clock
0
R W
b2
0
R W
0
R W
0
R W
0
R W
0
R W
0
0
1
1
b1
0: Data slicer clock
1: OSC1 clock
0: Main clock (See note 1)
1: Do not set
0: Data slicer clock
1: OSC1 clock
b5
b4
0 0: 32 kHz oscillating mode
0 1: Input ports P6 3, P64
(See note 2)
1 0: LC oscillating mode
1 1: Ceramic • quartz-crystal
oscillating mode
0: ✕ 1
1: ✕ 2
Notes 1: When setting “10 2,” main clock is set as a clock in the CC mode and
EXOSD mode regardless of bits 0, 3.
2: When selecting input ports P6 3 and P64 , set bit 7 at address 00C7 16
to “0.”
3: Be sure to set bit 7 to “0” for program of the mask and the EPROM
versions. For the emulator MCU version (M37274ERSS), be sure to set
bit 7 to “1” when using the data slicer clock for software debugging.
Clock Source Control Register
140
Address 021616
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L
PRE
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
I/O Polarity Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
I/O polarity control register (PC) [Address 021716]
B
Name
Functions
After reset R W
0
HSYNC input polarity
switch bit (PC0)
0 : Positive polarity input
1 : Negative polarity input
0
R W
1
VSYNC input polarity
switch bit (PC1)
0 : Positive polarity input
1 : Negative polarity input
0
R W
2
R, G, B output polarity
switch bit (PC2)
0 : Positive polarity output
1 : Negative polarity output
0
R W
3
Fix this bit to "0".
0
R —
4
OUT1 output polarity
switch bit (PC4)
0 : Positive polarity output
1 : Negative polarity output
0
R W
5
OUT2 output polarity
switch bit (PC5)
0 : Positive polarity output
1 : Negative polarity output
0
R W
6
Display dot line selection
bit (PC6) (See note)
0:“
0
R W
1
R —
“
1:“
“
7
Field determination flag
(PC7)
” at even field
” at odd field
” at even field
” at odd field
0 : Even field
1 : Odd field
Note: Refer to Figure 79.
I/O Polarity Control Register
Address 021716
Raster Color Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Raster color register (RC) [Address 021816]
B
0
1
2
Name
Raster color R
control bit (RC0)
Raster color G
control bit (RC1)
Raster color B
control bit (RC2)
Functions
0 : No output
1 : Output
0 : No output
1 : Output
0 : No output
1 : Output
3, 4 Fix these bits to “0.”
0
R W
0
R W
0
R W
0
R —
Raster color OUT1
control bit (RC5)
0 : No output
1 : Output
0
R W
6 Raster color OUT2
control bit (RC6)
0 : No output
1 : Output
0
R W
7 OSD interrupt source
selection bit (RC7)
0 : Interrupt occurs at end of
OSD or EXOSD block
display
1 : Interrupt occurs at end of
CC mode block display
0
R W
5
Raster Color Register
After reset R W
Address 021816
141
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Extra Font Color Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Extra font color register (EC) [Address 0219 16]
B
0
Name
Extra font color R
control bit (EC0)
After reset
R W
0 : No output
1 : Output
Functions
0
R W
1
Extra font color G
control bit (EC1)
0 : No output
1 : Output
0
R W
2
Extra font color B
control bit (EC2)
0 : No output
1 : Output
0
R W
0
R W
0
R —
3, 4 Fix these bits to “0.”
5
to
7
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
Extra Font Color Register
Address 021916
Border Color Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Border color register (FC) [Address 021B 16]
B
0
Name
Border color R
control bit (FC0)
After reset
R W
0 : No output
1 : Output
Functions
0
R W
1
Border color G
control bit (FC1)
0 : No output
1 : Output
0
R W
2
Border color B
control bit (FC2)
0 : No output
1 : Output
0
R W
0
R W
0
R —
3, 4 Fix these bits to “0.”
5
to
7
Border Color Register
142
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
Address 021B16
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Window H Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Window H register 1 (WH1) [Address 021C16]
B
Name
0 Control bits of window
to top boundary
7 (WN10 to WN17)
(See note 1)
Functions
After reset
R W
Top boundary position (low-order 8 bits)
Indeterminate R W
TH ✕
(setting value of low-order 2 bits of WH2 ✕ 162
+ setting value of high-order 4 bits of WH1 ✕ 161
+ setting value of low-order 4 bits of WH1 ✕ 160)
Notes 1: Set values except “00 16” to the WH1 when WH2 is “00 16.”
2: TH is cycle of H SYNC.
3: WH2: Window H register 2
Window H Register 1
Address 021C16
Window L Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Window L register 1 (WL1) [Address 021D16]
B
Name
0 Control bits of window
to top boundary
7 (WL10 to WL17)
(See note 1)
Functions
After reset
R W
Indeterminate R W
Top boundary position (low-order 8 bits)
TH ✕
(setting value of low-order 2 bits of WL2 ✕ 162
+ setting value of high-order 4 bits of WL1 ✕ 161
+ setting value of low-order 4 bits of WL1 ✕ 160)
Notes 1: Set values fit for the following condition: (WH1+WH2 ✕162)<(WL1+WL2✕
162)
2: T H is cycle of H SYNC.
3: WL2: Window L register 2
Window L Register 1
Address 021D16
Window H Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Window H register 2 (WH2) [Address 021E16]
B
Name
0, 1 Control bits of window
top boundary
(WN20 ,WN21)
(See note 1)
Functions
After reset
R W
Top boundary position (high-order 2 bits)
Indeterminate R W
TH ✕
(setting value of low-order 2 bits of WH2 ✕ 162
+ setting value of high-order 4 bits of WH1 ✕ 161
+ setting value of low-order 4 bits of WH1 ✕ 160)
2 Nothing is assigned. These bits are write disable bits.
Indeterminate R —
to When these bits are read out, the values are indeterminate.
7
Notes 1: Set values except “00 16” to the WH1 when WH2 is “00 16.”
2: TH is cycle of H SYNC.
3: WH1: Window H register 1
Window H Register 2
Address 021E16
143
MITSUBISHI MICROCOMPUTERS
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M37274EFSP
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Not e para
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PRE
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Window L Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Window L register 2 (WL2) [Address 021F16]
B
Name
0, 1 Control bits of window
top boundary
(WL20, WL21)
(See note 1)
Functions
After reset
R W
Top boundary position (high-order 2 bits)
Indeterminate R W
TH ✕
(setting value of low-order 2 bits of WL2 ✕ 162
+ setting value of high-order 4 bits of WL1 ✕ 161
+ setting value of low-order 4 bits of WL1 ✕ 160)
2 Nothing is assigned. These bits are write disable bits.
Indeterminate R —
to When these bits are read out, the values are indeterminate.
7
Notes 1: Set values fit for the following condition: (WH1+WH2 ✕162)<(WL1+WL2✕
162)
2: TH is cycle of H SYNC.
3: WL1: Window L register 1
Window L Register 2
Address 021F16
Vertical Position Register 1i
b7 b6 b5 b4 b3 b2 b1 b0
Vertical position register 1i (VP1i) (i = 1 to 16) [Addresses 0220 16 to 022F 16]
B
Name
Functions
After reset R W
0 Control bits of vertical Vertical display start positions
Indeterminate R W
to display start positions (low-order 8 bits)
7 (VP1i0 to VP1i7)
TH ✕
(See note 1)
(setting value of low-order 2 bits of VP2i ✕ 162
+ setting value of low-order 4 bits of VP1i ✕ 161
+ setting value of low-order 4 bits of VP1i ✕ 160)
Notes 1: Set values except “00 16” “0116” to VP1i when VP2i is “00 16.”
2: T H is cycle of H SYNC.
Vertical Position Register 1i
Addresses 022016 to 022B16
Vertical Position Register 2i
b7 b6 b5 b4 b3 b2 b1 b0
Vertical position register 2i (VP2i) (i = 1 to 16) [Addresses 0230 16 to 023F 16]
B
Name
Functions
After reset
R W
0, 1 Control bits of vertical Vertical display start positions
Indeterminate R W
display start positions (high-order 2 bits)
TH ✕
(VP1i0, VP1i1)
(See note 1)
(setting value of low-order 2 bits of VP2i ✕ 162
+ setting value of low-order 4 bits of VP1i ✕ 161
+ setting value of low-order 4 bits of VP1i ✕ 160)
2 Nothing is assigned. These bits are write disable bits.
to
When these bits are read out, the values are indeterminate.
7
Indeterminate R —
Notes 1: Set values except “00 16” “01 16” to VP1i when VP2i is “00 16.”
2: T H is cycle of H SYNC.
Vertical Position Register 2i
144
Addresses 023016 to 023B16
MITSUBISHI MICROCOMPUTERS
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M37274EFSP
L
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
ROM Correction Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
ROM correction enable register (RCR) [Address 024616]
B
Name
Functions
0
Block 1 enable bit (RC0)
0: Disabled
1: Enabled
0
R W
1
Block 2 enable bit (RC1)
0: Disabled
1: Enabled
0
R W
0
R W
0
R —
2, 3 Fix these bits to “0.”
4
to
7
ROM Correction Enable Register
Nothing is assigned. These bits are write disable bits. When
these bits are read out, the values are “0.”
After reset R W
Address 024616
145
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples
contained in these materials.
All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
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Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Notes regarding these materials
•
•
•
•
•
•
© 1997 MITSUBISHI ELECTRIC CORP.
New publication, effective Nov. 1997.
Specifications subject to change without notice.
M37274EFSP DATA SHEET
REVISION DESCRIPTION LIST
Rev.
No.
1.0
Revision Description
Rev.
date
971130
First Edition
(1/1)