HD74HCT688 8-bit Magnitude Comparator REJ03D0673–0200 (Previous ADE-205-563) Rev.2.00 Mar 30, 2006 Description The HD74HCT688 compares bit for bit two 8-bit words and indicates whether or not they are equal. The P=Q output indicates equality when it is low. A single active low enable is provided to facilitate cascading of several packages and enable comparison of words greater than 8-bits. This device is useful in memory block decoding applications, where memory block enable signals must be generated from computer address information. Features • • • • • • • LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (Data to P=Q) = 18 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74HCT688P DILP-20 pin (JEDEC) PRDP0020AC-B (DP-20NEV) P — HD74HCT688FPEL SOP-20 pin (JEITA) PRSP0020DD-B (FP-20DAV) FP EL (2,000 pcs/reel) HD74HCT688RPEL SOP-20 pin (JEDEC) PRSP0020DC-A (FP-20DBV) RP EL (1,000 pcs/reel) Function Table Input H : L : X : Data P, Q P=Q P>Q P<Q X high level low level irrelevant Rev.2.00, Mar 30, 2006 page 1 of 7 Enable G L L L H Output P=Q L H H H HD74HCT688 Pin Arrangement G 1 20 VCC P0 2 19 P=Q Q0 3 18 Q7 P1 4 17 P7 Q1 5 16 Q6 P2 6 15 P6 Q2 7 14 Q5 P3 8 13 P5 Q3 9 12 Q4 GND 10 11 P4 (Top view) Rev.2.00, Mar 30, 2006 page 2 of 7 HD74HCT688 Logic Diagram P0 Q0 P1 Q1 P2 Q2 P3 Q3 P4 P=Q Q4 P5 Q5 P6 Q6 P7 Q7 G Absolute Maximum Ratings Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC VIN, VOUT IIK, IOK IOUT ICC or IGND PT Tstg Ratings –0.5 to 7.0 –0.5 to VCC +0.5 ±20 ±25 ±50 500 –65 to +150 Unit V V mA mA mA mW °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Rev.2.00, Mar 30, 2006 page 3 of 7 HD74HCT688 Recommended Operating Conditions Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time*1 Symbol VCC VIN, VOUT Ta tr, tf Ratings 4.5 to 5.5 0 to VCC –40 to 85 0 to 500 Unit V V °C ns Conditions VCC = 4.5 V Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Electrical Characteristics Item Input voltage Output voltage Symbol VCC (V) Min VIH 4.5 to 5.5 2.0 4.5 to 5.5 — VIL VOH 4.5 4.4 4.5 4.18 VOL 4.5 — 4.5 — Ta = 25°C Typ Max — — — 0.8 — — — — — 0.1 — 0.26 Ta = –40 to+85°C Min Max 2.0 — — 0.8 4.4 — 4.13 — — 0.1 — 0.33 Unit Test Conditions V V V Vin = VIH or VIL IOH = –20 µA IOH = –4 mA V Vin = VIH or VIL IOL = 20 µA IOL = 4 mA Input current Iin 5.5 — — ±0.1 — ±1.0 µA Vin = VCC or GND Quiescent current ICC 5.5 — — 4.0 — 40 µA Vin = VCC or GND, Iout = 0 µA Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Item Propagation delay time Symbol VCC (V) tPLH tPHL tPLH tPHL Output rise/fall time Input capacitance tTLH tTHL Cin 4.5 4.5 4.5 4.5 Ta = 25°C Ta = –40 to +85°C Unit Min Typ Max Min Max Test Conditions — 17 42 — 53 ns Por Q to output — 19 42 — 53 — 9 24 — 30 ns Enable to output — 12 24 — 30 4.5 — 5 15 — 19 ns — — 5 10 — 10 pF Test Circuit Input Pulse Generator Zout = 50 Ω VCC See Function Table VCC G Output P1 P7 P=Q Q0 Q7 Note : 1. CL includes probe and jig capacitance. Rev.2.00, Mar 30, 2006 page 4 of 7 CL = 50 pF HD74HCT688 Waveforms • Waveform – 1 tr tf 90% 1.3V 10% P or Q VCC 90% 1.3V 10% 0V tw tPHL tPLH 90% 1.3V P=Q 1.3V 10% G tr tf 90% 1.3V VCC 90% 1.3V 10% 10% tPHL 0V tPLH 90% P=Q VOL tTHL tTLH • Waveform – 2 VOH 90% 90% 1.3V 10% tTHL 1.3V 10% tTLH Notes : 1. Input waveform : PRR ≤ 1 MHz, duty cycle 50%, tr ≤ 6 ns, tf ≤ 6 ns Rev.2.00, Mar 30, 2006 page 5 of 7 VOH VOL HD74HCT688 Package Dimensions JEITA Package Code P-DIP20-6.3x24.5-2.54 RENESAS Code PRDP0020AC-B Previous Code DP-20NEV MASS[Typ.] 1.26g D 11 E 20 1 10 b3 0.89 A1 A Z Reference Symbol L e1 D E A A1 bp b3 c θ e Z L θ bp e c e1 ( Ni/Pd/Au plating ) JEITA Package Code P-SOP20-7.5x12.8-1.27 RENESAS Code PRSP0020DC-A *1 Previous Code FP-20DBV Dimension in Millimeters Min Nom Max 7.62 24.50 25.40 6.30 7.00 5.08 0.51 0.40 0.48 0.56 1.30 0.19 0.25 0.31 0° 15° 2.29 2.54 2.79 1.27 2.54 MASS[Typ.] 0.52g D F 20 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" @ DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT @ INCLUDE TRIM OFFSET. 11 HE c *2 E bp Index mark Terminal cross section ( Ni/Pd/Au plating ) 1 e *3 bp x M L1 A Z Reference Dimension in Millimeters Symbol 10 A1 θ L y Detail F Rev.2.00, Mar 30, 2006 page 6 of 7 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 12.80 13.2 7.50 0.10 0.20 0.30 2.65 0.34 0.40 0.46 0.20 0.25 0.30 0° 8° 10.00 10.40 10.65 1.27 0.12 0.15 0.935 0.40 0.70 1.27 1.45 HD74HCT688 JEITA Package Code P-SOP20-5.5x12.6-1.27 RENESAS Code PRSP0020DD-B *1 Previous Code FP-20DAV MASS[Typ.] 0.31g D NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 20 11 c HE *2 E bp Index mark Terminal cross section ( Ni/Pd/Au plating ) 1 Z 10 e *3 bp x Reference Dimension in Millimeters Symbol M A L1 A1 θ y L Detail F Rev.2.00, Mar 30, 2006 page 7 of 7 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 12.60 13.0 5.50 0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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