HD74HC75 Quad. Bistable Latches REJ03D0550-0200 (Previous ADE-205-422) Rev.2.00 Oct 06, 2005 Description This latch is ideally suited for use as temporary storage for binary information processing, input/output, and indicator units. Information present at the data (D) input is transferred to the Q output when the latch enable (LE) is high. The Q output will follow the data input as long as the enable remains high. When the enable goes low, the information that was present at the data input at the time the transition occurred is retained at the Q output unit the enable is permitted to go high again. Features • • • • • • High Speed Operation: tpd (D to Q) = 12.5 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C) Ordering Information Part Name Package Code (Previous Code) PRDP0016AE-B (DP-16FV) Package Type HD74HC75P DILP-16 pin HD74HC75FPEL SOP-16 pin (JEITA) HD74HC75RPEL SOP-16 pin (JEDEC) PRSP0016DH-B (FP-16DAV) PRSP0016DG-A (FP-16DNV) Package Abbreviation Taping Abbreviation (Quantity) P — FP EL (2,000 pcs/reel) RP EL (2,500 pcs/reel) Note: Please consult the sales office for the above package availability. Function Table Inputs Outputs Data Latch Enable Q Q H L H L H H H L X L Q0 Q0 H: High level L: Low level X: Irrelevant Q0, Q0 : Output level before the indicated steady state input conditions were established. Rev.2.00, Oct 06, 2005 page 1 of 7 HD74HC75 Pin Arrangement Q0a 1 16 Q0a D0a 2 15 Q1a D1a 3 14 Q1a LEb 4 13 LEa VCC 5 12 GND D0b 6 11 Q0b D1b 7 10 Q0b Q1b 8 9 Q1b (Top view) Logic Diagram (1/4) Data Q Q Latch Enable Absolute Maximum Ratings Item Supply voltage range Symbol VCC Ratings –0.5 to 7.0 Unit V Input / Output voltage Input / Output diode current Vin, Vout IIK, IOK –0.5 to VCC +0.5 ±20 V mA Output current VCC, GND current IO ICC or IGND ±25 ±50 mA mA PT Tstg 500 –65 to +150 mW °C Power dissipation Storage temperature Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Rev.2.00, Oct 06, 2005 page 2 of 7 HD74HC75 Recommended Operating Conditions Symbol Ratings Unit Supply voltage Input / Output voltage Item VCC VIN, VOUT 2 to 6 0 to VCC V V Operating temperature Ta –40 to 85 0 to 1000 °C 0 to 500 0 to 400 ns Input rise / fall time Note: *1 tr , tf Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Electrical Characteristics Ta = 25°C Item Input voltage Symbol VCC (V) VIH VIL Output voltage VOH VOL Ta = –40 to+85°C 2.0 Min 1.5 Typ — Max — Min 1.5 Max — 4.5 6.0 3.15 4.2 — — — — 3.15 4.2 — — 2.0 4.5 — — — — 0.5 1.35 — — 0.5 1.35 6.0 2.0 — 1.9 — 2.0 1.8 — — 1.9 1.8 — 4.5 6.0 4.4 5.9 4.5 6.0 — — 4.4 5.9 — — 4.5 6.0 4.18 5.68 — — — — 4.13 5.63 — — 2.0 4.5 — — 0.0 0.0 0.1 0.1 — — 0.1 0.1 6.0 4.5 — — 0.0 — 0.1 0.26 — — 0.1 0.33 Unit Test Conditions V V V Vin = VIH or VIL IOH = –20 µA IOH = –4 mA IOH = –5.2 mA V Vin = VIH or VIL IOL = 20 µA IOL = 4 mA Input current Iin 6.0 6.0 — — — — 0.26 ±0.1 — — 0.33 ±1.0 IOL = 5.2 mA µA Vin = VCC or GND Quiescent supply current ICC 6.0 — — 2.0 — 20 µA Vin = VCC or GND, Iout = 0 µA Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Item Propagation delay time Symbol VCC (V) tPLH, tPHL Min Ta = 25°C Ta = –40 to +85°C Unit Typ Max Min Max 2.0 4.5 — — — 12 125 25 — — 155 31 6.0 2.0 — — — — 21 110 — — 26 140 4.5 6.0 — — 13 — 22 19 — — 28 24 2.0 4.5 — — — 12 145 29 — — 180 36 6.0 2.0 — — — — 25 125 — — 31 155 4.5 6.0 — — 13 — 25 21 — — 31 26 Rev.2.00, Oct 06, 2005 page 3 of 7 Test Conditions ns Data to Q ns Data to Q ns Latch Enable to Q ns Latch Enable to Q HD74HC75 Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Ta = 25°C Item Setup time Symbol VCC (V) tsu Hold time th Pulse width tw Output rise/fall time Input capacitance tTLH, tTHL Cin Ta = –40 to +85°C 2.0 Min 100 Typ — Max — Min 125 Max — 4.5 6.0 20 17 4 — — — 25 21 — — 2.0 4.5 5 5 — 0 — — 5 5 — — 6.0 2.0 5 80 — — — — 5 100 — — 4.5 6.0 16 14 5 — — — 20 17 — — 2.0 4.5 — — — 5 75 15 — — 95 19 6.0 — — — — 5 13 10 — — 16 10 Unit Test Conditions ns Data to Latch Enable ns Latch Enable to Data ns Latch Enable ns pF Test Circuit VCC VCC Pulse generator Zout = 50 Ω Input Pulse generator Zout = 50 Ω See Function Table Output Input Latch Enable Q CL = 50 pF Output Data Q Note: C L includes the probe and jig capacitance. Rev.2.00, Oct 06, 2005 page 4 of 7 CL = 50 pF HD74HC75 Waveforms • Waveform − 1 tr tf tw tw 90 % D VCC 90 % 50 % 50 % 50 % 10 % 10 % t su th tr tw VCC 50 % tw t PLH 50 % 0V t PHL t PHL t PLH 90 % Q th tf 90 % 90 % 50 % 50 % 10 % 10 % Latch Enable 0V t su VOH 90 % 50 % 10 % 50 % 10 % t TLH t PHL t PLH t PLH t PHL 90 % 90 % Q 50 % 10 % t THL 50 % 10 % t TLH Note: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns Rev.2.00, Oct 06, 2005 page 5 of 7 VOL t THL VOH VOL HD74HC75 Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g D 9 E 16 1 8 b3 0.89 Z A1 A Reference Symbol L e Nom c e1 D 19.2 E 6.3 JEITA Package Code P-SOP16-3.95x9.9-1.27 RENESAS Code PRSP0016DG-A *1 Previous Code FP-16DNV 7.4 A1 0.51 b p 0.40 b 3 0.48 0.56 1.30 c 0.19 θ 0° e 2.29 0.25 0.31 2.54 2.79 15° 1.12 L 2.54 MASS[Typ.] 0.15g D NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 16 20.32 5.06 Z ( Ni/Pd/Au plating ) Max 7.62 1 A θ bp e Dimension in Millimeters Min 9 c *2 Index mark HE E bp Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) Dimension in Millimeters Min Nom Max D 9.90 10.30 E 3.95 A2 1 Z 8 e *3 bp x A1 0.10 0.14 0.25 0.34 0.40 0.46 0.15 0.20 0.25 6.10 6.20 1.75 A M L1 bp b1 c A c A1 θ L y Detail F 1 θ 0° HE 5.80 1.27 e x 0.25 y 0.15 Z 0.635 0.40 L L Rev.2.00, Oct 06, 2005 page 6 of 7 8° 1 0.60 1.08 1.27 HD74HC75 JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV MASS[Typ.] 0.24g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. D F 16 9 c HE *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) 1 Z *3 bp Nom D 10.06 E 5.50 Max 10.5 A2 8 e Dimension in Millimeters Min x A1 M 0.00 0.10 0.20 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 2.20 A L1 bp b1 c A c A1 θ y L Detail F 1 θ 0° HE 7.50 1.27 e x 0.12 y 0.15 Z 0.80 0.50 L L Rev.2.00, Oct 06, 2005 page 7 of 7 8° 1 0.70 1.15 0.90 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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