HT66F007

Small Package A/D Flash 8-bit MCU
HT66F007
Revision: V1.00
Date: ����������������
October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
Table of Contents
Features............................................................................................................. 6
CPU Features.......................................................................................................................... 6
Peripheral Features.................................................................................................................. 6
General Description ......................................................................................... 7
Block Diagram................................................................................................... 7
Pin Assignment................................................................................................. 8
Pin Descriptions............................................................................................... 8
Absolute Maximum Ratings............................................................................. 9
D.C. Characteristics........................................................................................ 10
A.C. Characteristics........................................................................................ 12
DC Electrical Characteristics ........................................................................ 13
Comparator Electrical Characteristics......................................................... 14
Power on Reset Electrical Characteristics................................................... 14
System Architecture....................................................................................... 15
Clocking and Pipelining.......................................................................................................... 15
Program Counter.................................................................................................................... 16
Stack...................................................................................................................................... 17
Arithmetic and Logic Unit – ALU............................................................................................ 17
Flash Program Memory.................................................................................. 18
Structure................................................................................................................................. 18
Special Vectors...................................................................................................................... 18
Look-up Table......................................................................................................................... 18
Table Program Example......................................................................................................... 19
In Circuit Programming.......................................................................................................... 20
On-Chip Debug Support – OCDS.......................................................................................... 21
RAM Data Memory.......................................................................................... 21
Structure................................................................................................................................. 21
Special Function Register Description......................................................... 23
Indirect Addressing Registers – IAR0, IAR1.......................................................................... 23
Memory Pointers – MP0, MP1............................................................................................... 23
Bank Pointer – BP.................................................................................................................. 24
Accumulator – ACC................................................................................................................ 24
Program Counter Low Register – PCL................................................................................... 24
Look-up Table Registers – TBLP, TBHP, TBLH...................................................................... 24
Status Register – STATUS..................................................................................................... 25
EEPROM Data Memory................................................................................... 27
EEPROM Data Memory Structure......................................................................................... 27
EEPROM Registers............................................................................................................... 27
Reading Data from the EEPROM ......................................................................................... 29
Rev. 1.00
2
October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
Writing Data to the EEPROM................................................................................................. 29
Write Protection...................................................................................................................... 29
EEPROM Interrupt................................................................................................................. 29
Programming Considerations................................................................................................. 30
Programming Examples......................................................................................................... 30
Oscillator......................................................................................................... 31
Oscillator Overview................................................................................................................ 31
System Clock Configurations................................................................................................. 31
External Crystal/Ceramic Oscillator – HXT............................................................................ 32
Internal RC Oscillator – HIRC................................................................................................ 33
Internal 32kHz Oscillator – LIRC............................................................................................ 33
Supplementary Oscillator....................................................................................................... 33
Operating Modes and System Clocks.......................................................... 34
System Clocks....................................................................................................................... 34
System Operation Modes....................................................................................................... 36
Control Register..................................................................................................................... 37
Fast Wake-up......................................................................................................................... 38
Operating Mode Switching .................................................................................................... 39
NORMAL Mode to SLOW Mode Switching............................................................................ 40
SLOW Mode to NORMAL Mode Switching ........................................................................... 41
Entering the SLEEP0 Mode................................................................................................... 42
Entering the SLEEP1 Mode................................................................................................... 42
Entering the IDLE0 Mode....................................................................................................... 42
Entering the IDLE1 Mode....................................................................................................... 43
Standby Current Considerations............................................................................................ 43
Wake-up................................................................................................................................. 44
Programming Considerations................................................................................................. 44
Watchdog Timer.............................................................................................. 45
Watchdog Timer Clock Source............................................................................................... 45
Watchdog Timer Control Register.......................................................................................... 45
Watchdog Timer Operation.................................................................................................... 46
Reset and Initialisation................................................................................... 47
Reset Functions..................................................................................................................... 47
Reset Initial Conditions.......................................................................................................... 50
Input/Output Ports.......................................................................................... 52
Pull-high Resistors................................................................................................................. 52
Port A Wake-up...................................................................................................................... 53
I/O Port Control Registers...................................................................................................... 53
Special Pin Control................................................................................................................. 54
Pin-remapping Functions....................................................................................................... 54
I/O Pin Structures................................................................................................................... 56
Programming Considerations................................................................................................. 57
Rev. 1.00
3
October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
Timer Modules – TM....................................................................................... 58
Introduction............................................................................................................................ 58
TM Operation......................................................................................................................... 58
TM Clock Source.................................................................................................................... 59
TM Interrupts.......................................................................................................................... 59
TM External Pins.................................................................................................................... 59
TM Input/Output Pin Control Register.................................................................................... 60
Compact Type TM – CTM............................................................................... 63
Compact TM Operation.......................................................................................................... 63
Compact Type TM Register Description................................................................................ 64
Compact Type TM Operating Modes..................................................................................... 69
Compare Match Output Mode................................................................................................ 69
Timer/Counter Mode.............................................................................................................. 72
PWM Output Mode................................................................................................................. 72
Standard Type TM – STM............................................................................... 75
Standard TM Operation.......................................................................................................... 75
Standard Type TM Register Description................................................................................ 76
Standard Type TM Operating Modes..................................................................................... 80
Compare Output Mode........................................................................................................... 80
Timer/Counter Mode.............................................................................................................. 83
PWM Output Mode................................................................................................................. 83
Single Pulse Mode................................................................................................................. 86
Capture Input Mode............................................................................................................... 88
Analog to Digital Converter........................................................................... 90
A/D Overview......................................................................................................................... 90
A/D Converter Register Description....................................................................................... 90
A/D Converter Data Registers – ADRL, ADRH...................................................................... 91
A/D Converter Control Registers – ADCR0, ADCR1, ACER.................................................. 91
A/D Operation........................................................................................................................ 94
A/D Input Pins........................................................................................................................ 95
Summary of A/D Conversion Steps........................................................................................ 96
Programming Considerations................................................................................................. 97
A/D Transfer Function............................................................................................................ 97
A/D Programming Examples.................................................................................................. 98
Comparator................................................................................................... 100
Comparator Operation......................................................................................................... 100
Comparator Interrupt............................................................................................................ 101
Programming Considerations............................................................................................... 101
Interrupts....................................................................................................... 102
Interrupt Registers................................................................................................................ 102
Interrupt Operation............................................................................................................... 106
External Interrupt.................................................................................................................. 108
Comparator Interrupt............................................................................................................ 108
Rev. 1.00
4
October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
Multi-function Interrupt......................................................................................................... 108
A/D Converter Interrupt........................................................................................................ 109
Time Base Interrupts............................................................................................................ 109
EEPROM Interrupt................................................................................................................111
TM Interrupts.........................................................................................................................111
Interrupt Wake-up Function...................................................................................................111
Programming Considerations................................................................................................112
Configuration Options...................................................................................113
Application Circuits.......................................................................................113
Instruction Set................................................................................................114
Instruction..............................................................................................................................114
Instruction Timing..................................................................................................................114
Moving and Transferring Data...............................................................................................114
Arithmetic Operations............................................................................................................114
Logical and Rotate Operations..............................................................................................115
Branches and Control Transfer.............................................................................................115
Bit Operations.......................................................................................................................115
Table Read Operations.........................................................................................................115
Other Operations...................................................................................................................115
Instruction Set Summary..............................................................................116
Table Conventions.................................................................................................................116
Instruction Definition.....................................................................................118
Package Information.................................................................................... 127
10-pin MSOP Outline Dimensions....................................................................................... 128
Rev. 1.00
5
October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
Features
CPU Features
• Operating Voltage:
♦♦
fSYS=8MHz: 2.2V~5.5V
♦♦
fSYS=12MHz: 2.7V~5.5V
♦♦
fSYS=20MHz: 4.5V~5.5V
• Up to 0.2μs instruction cycle with 20MHz system clock at VDD=5V
• Power down and wake-up functions to reduce power consumption
• Three Oscillators:
♦♦
External Crystal -- HXT
♦♦
Internal RC -- HIRC
♦♦
Internal 32kHz -- LIRC
• Fully intergrated internal 4MHz, 8MHz, 12MHz oscillator requires no external components
• Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP
• All instructions executed in one or two instruction cycles
• Table read instructions
• 63 powerful instructions
• 8-level subroutine nesting
• Bit manipulation instruction
Peripheral Features
• Flash Program Memory: 2K×16
• RAM Data Memory: 160×8
• EEPROM Memory: 512×8
• Watchdog Timer function
• 8 bidirectional I/O lines
• One pin-shared external interrupt
• Multiple Timer Module for time measure, input capture, compare match output, PWM output
function or single pulse output function
• Dual Time-Base functions for generation of fixed time interrupt signals
• 5-channel 12-bit resolution A/D converter
• Single Comparator Function
• Low voltage reset function
• Package: 10-pin MSOP
Rev. 1.00
6
October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
General Description
The device is a Flash Memory type 8-bit high performance RISC architecture microcontroller.
Offering users the convenience of Flash Memory multi-programming features, this device also
includes a wide range of functions and features. Other memory includes an area of RAM Data
Memory as well as an area of EEPROM memory for storage of non-volatile data such as serial
numbers, calibration data etc.
Analog features include a multi-channel 12-bit A/D converter and a comparator functions. Multiple
and extremely flexible Timer Modules provide timing, pulse generation and PWM generation
functions. Protective features such as an internal Watchdog Timer, Low Voltage Reset coupled with
excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile
electrical environments.
A full choice of HXT, HIRC and LIRC oscillator functions are provided including a fully integrated
system oscillator which requires no external components for its implementation. The ability to
operate and switch dynamically between a range of operating modes using different clock sources
gives users the ability to optimise microcontroller operation and minimize power consumption.
The inclusion of flexible I/O programming features, Time-Base functions along with many other
features ensure that the device will find excellent use in applications such as electronic metering,
environmental monitoring, handheld instruments, household appliances, electronically controlled
tools, motor driving in addition to many others.
Block Diagram
Rev. 1.00
7
October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
Pin Assignment
1
2
P A 1 /[T P 0 _ 1 ]/A N 1 /V R E F /C N /IC P C K
3
P A 0 /T P 0 _ 0 /A N 0 /C P /IC P D A
4
1 0
P A 3 /[IN T ]/A N 3
P A 2 /[IN T ]/T C K 1 /T P 2 _ 0 /A N 2 /C X
V S S & A V S S
P A 4 /[T C K 1 ]/T P 1 _ 1
9
P A 5 /IN T /T P 0 _ 1 /O S C 2 /A N 4
8
P A 6 /[T C K 0 ]/T P 1 _ 0 /O S C 1
7
6
5
P A 7 /[IN T ]/T C K 0 /[T C K 1 ]/[T P 1 _ 0 ]
V D D
& A V D D
HT66F007 10MSOP
1
1 6
2
1 5
3
1 4
4
1 3
5
1 2
6
1 1
7
1 0
8
9
V D D & A V D D
P A 6 /[T C K 0 ]/T P 1 _ 0 /O S C 1
P A 5 /IN T /T P 0 _ 1 /O S C 2 /A N 4
P A 7 /[IN T ]/T C K 0 /[T C K 1 ]/[T P 1 _ 0 ]
P A 4 /[T C K 1 ]/T P 1 _ 1
N C
N C
O C D S C K
V S S & A V S S
P A 0 /T P 0 _ 0 /A N 0 /C P /IC P D A
P A 1 /[T P 0 _ 1 ]/A N 1 /V R E F /C N /IC P C K
P A 2 /[IN T ]/T C K 1 /T P 2 _ 0 /A N 2 /C X
P A 3 /[IN T ]/A N 3
N C
N C
O C D S D A
HT66V007 16NSOP
Note: 1. Bracketed pin names indicate non-default pinout remapping locations.
2. If the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the
“/” sign can be used for higher priority.
3. AVDD&VDD means the VDD and AVDD are the double bonding. VSS&AVSS means the VSS and
AVSS are the double bonding.
Pin Descriptions
With the exception of the power pins and some relevant transformer control pins, all pins on these
devices can be referenced by their Port name, e.g. PA0, PA1 etc, which refer to the digital I/O
function of the pins. However these Port pins are also shared with other function such as the Analog
to Digital Converter, Timer Module pins etc. The function of each pin is listed in the following table,
however the details behind how each pin is configured is contained in other sections of the datasheet.
Rev. 1.00
8
October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
Pin Name
Function
PA0~PA7
General purpose I/O port A
AN0~AN4
A/D Converter input 0~4
VREF
A/D Converter reference voltage input
INT
OP
I/T
O/T
Pin-Shared Mapping
PAPU
PAWU
ST
CMOS
—
ACER
AN
—
ADCR1
AN
—
PA1
External interrupt
PRM
ST
—
PA5 or PA2 or PA3 or PA7
TCK0
TM0 input
PRM
ST
—
PA7 or PA6
TCK1
TM1 input
PRM
ST
—
PA2 or PA4 or PA7
TP0_0
TM0 I/O
PRM
ST
CMOS PA0
TP0_1
TM0 I/O
PRM
ST
CMOS PA5 or PA1
TP1_0
TM1 I/O
PRM
ST
CMOS PA6 or PA7
TP1_1
TM1 I/O
PRM
ST
CMOS PA4
TP2_0
TM2 I/O
PRM
ST
CMOS PA2
OSC1
HXT pin
CO
HXT
—
PA6
OSC2
HXT pin
CO
—
HXT
PA5
AN
—
PA0
CPC
AN
—
PA1
CP
Comparator positive input
CN
Comparator negative input
CX
Comparator output
ICPCK
ICP clock input
—
ST
—
ICPDA
ICP data input/output
—
ST
PA0~PA3, PA5
CMOS PA2
—
PA1
CMOS PA0
VDD
Positive power supply*
—
PWR
—
—
AVDD
A/D Converter power supply*
—
PWR
—
—
VSS
Negative power supply, ground**
—
PWR
—
—
AVSS
A/D Converter ground**
—
PWR
—
—
The following pins are only for the HT66V007
OCDSCK
On-chip debug support clock pin
—
ST
—
—
OCDSDA
On-chip debug support data/address pin
—
ST
CMOS
—
Note : I/T: Input type;
O/T: Output type
OP: Optional by configuration option (CO) or register option
PWR: Power;
CO: Configuration option; ST: Schmitt Trigger input
CMOS: CMOS output; AN: Analog input pin
HXT: High frequency ctystal oscillator
*: VDD is the device power supply while AVDD is the ADC power supply. The AVDD pin is bonded
together internally with VDD.
**: VSS is the device ground pin while AVSS is the ADC ground pin. The AVSS pin is bonded together
internally with VSS.
Absolute Maximum Ratings
Supply Voltage.................................................................................................VSS−0.3V to VSS+6.0V
Input Voltage...................................................................................................VSS−0.3V to VDD+0.3V
Storage Temperature.....................................................................................................-50˚C to 125˚C
Operating Temperature...................................................................................................-40˚C to 85˚C
IOH Total...................................................................................................................................-100mA
IOL Total.................................................................................................................................... 100mA
Total Power Dissipation ......................................................................................................... 500mW
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum
Ratings" may cause substantial damage to these devices. Functional operation of these devices at
other conditions beyond those listed in the specification is not implied and prolonged exposure to
extreme conditions may affect devices reliability.
Rev. 1.00
9
October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
D.C. Characteristics
Ta=25°C
Symbol
VDD
Parameter
Operating Voltage
(HXT, HIRC)
Test Conditions
—
3V
5V
3V
IDD1
Operating Current,
Normal Mode, fSYS=fH
(HXT)
5V
3V
5V
3V
5V
5V
3V
IDD2
Operating Current,
Normal Mode, fSYS=fH
(HIRC)
5V
3V
5V
3V
5V
3V
5V
3V
5V
IDD3
Operating Current,
Normal Mode, fH=12MHz
(HIRC)
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
IDD4
Operating Current,
Normal Mode, fH=12MHz
(HXT)
3V
5V
3V
5V
3V
5V
3V
5V
IDD5
Rev. 1.00
Operating Current,
Slow Mode, fSYS=fL=LIRC,
fSUB=LIRC
Min.
Typ.
Max.
Unit
fSYS=8MHz
2.2
—
5.5
V
fSYS=12MHz
2.7
—
5.5
V
fSYS=20MHz
4.5
—
5.5
V
VDD
3V
5V
Conditions
No load, fH=4MHz, ADC off, WDT enable
No load, fH=8MHz, ADC off, WDT enable
No load, fH=12MHz, ADC off, WDT enable
No load, fH=16MHz, ADC off, WDT enable
No load, fH=20MHz, ADC off, WDT enable
No load, fH=4MHz, ADC off, WDT enable
No load, fH=8MHz, ADC off, WDT enable
No load, fH=12MHz, ADC off, WDT enable
No load, fSYS=fH/2, ADC off, WDT enable
No load, fSYS=fH/4, ADC off, WDT enable
No load, fSYS=fH/8, ADC off, WDT enable
No load, fSYS=fH/16, ADC off, WDT enable
No load, fSYS=fH/32, ADC off, WDT enable
No load, fSYS=fH/64, ADC off, WDT enable
No load, fSYS=fH/2, ADC off, WDT enable
No load, fSYS=fH/4, ADC off, WDT enable
No load, fSYS=fH/8, ADC off, WDT enable
No load, fSYS=fH/16, ADC off, WDT enable
No load, fSYS=fH/32, ADC off, WDT enable
No load, fSYS=fH/64, ADC off, WDT enable
No load, fSYS=LIRC, ADC off, WDT enable,
LVR disable
10
—
0.6
0.9
mA
—
1.8
2.7
mA
—
1.1
1.7
mA
—
2.9
4.4
mA
—
1.6
2.5
mA
—
4.1
6.2
mA
—
2.0
3.0
mA
—
5.2
7.8
mA
—
6.4
9.6
mA
—
0.6
0.9
mA
—
1.8
2.7
mA
—
1.1
1.7
mA
—
2.9
4.4
mA
—
1.6
2.5
mA
—
4.1
6.2
mA
—
1.7
2.4
mA
—
2.6
4.4
mA
—
1.6
2.4
mA
—
2.4
4.0
mA
—
1.5
2.2
mA
—
2.2
3.6
mA
—
1.4
2.0
mA
—
2.0
3.2
mA
—
1.3
1.8
mA
—
1.8
2.8
mA
—
1.2
1.6
mA
mA
—
1.6
2.4
—
0.90
1.50
mA
—
2.50
3.75
mA
—
0.7
1.0
mA
—
2.0
3.0
mA
—
0.6
0.9
mA
—
1.6
2.4
mA
—
0.50
0.75
mA
—
1.50
2.25
mA
—
0.49
0.74
mA
—
1.45
2.18
mA
—
0.47
0.71
mA
—
1.40
2.10
mA
—
10
20
μA
—
30
50
μA
October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
Symbol
Parameter
Test Conditions
VDD
Conditions
No load, fSYS=LIRC, ADC off, WDT enable,
LVR enable
IDD5A
Operating Current,
Slow Mode, fSYS=fL=LIRC,
fSUB=LIRC
3V
IIDLE01
IDLE0 Mode Standby
Current (LIRC on)
3V
IIDLE11
IDLE1 Mode Standby
Current (HXT)
IIDLE11A
IDLE1 Mode Standby
Current (HIRC)
IIDLE12
IDLE1 Mode Standby
Current (HXT)
IIDLE12A
IDLE1 Mode Standby
Current (HIRC)
IIDLE13
IDLE1 Mode Standby
Current (HXT)
5V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
IIDLE13A
IDLE1 Mode Standby
Current (HIRC)
5V
IIDLE14
IDLE1 Mode Standby
Current (HXT)
5V
IIDLE15
IDLE1 Mode Standby
Current (HXT)
ISLEEP0
SLEEP0 Mode Standby
Current (LIRC off)
3V
ISLEEP1
SLEEP1 Mode Standby
Current (LIRC on)
3V
VIL1
Input Low Voltage for I/O
Ports or Input Pins
5V
—
VIH1
Input High Voltage for I/O
Ports or Input Pins
5V
—
VIL2
TTL Input Low Voltage for
PA2, PA5, PA6 PA7
5V
VIH2
TTL Input High Voltage for
PA2, PA5, PA6 PA7
5V
3V
5V
5V
5V
No load, ADC off, WDT enable
No load, ADC off, WDT enable,
fSYS=4MHz on
No load, ADC off, WDT enable,
fSYS=4MHz on
Min.
Typ.
Max.
Unit
—
40
60
μA
—
90
135
μA
—
1.3
3.0
μA
—
2.2
5.0
μA
mA
—
0.4
0.8
—
0.8
1.6
mA
—
0.4
0.8
mA
—
0.8
1.6
mA
No load, ADC off, WDT enable,
fSYS=8MHz on
—
0.5
1.0
mA
—
1.0
2.0
mA
No load, ADC off, WDT enable,
fSYS=8MHz on
—
0.8
1.6
mA
—
1.0
2.0
mA
—
0.6
1.2
mA
—
1.2
2.4
mA
No load, ADC off, WDT enable,
fSYS=12MHz on
—
0.6
1.2
mA
—
1.2
2.4
mA
No load, ADC off, WDT enable,
fSYS=16MHz on
—
1.0
2.0
mA
—
2.0
4.0
mA
—
2.5
5.0
mA
No load, ADC off, WDT enable,
fSYS=12MHz on
No load, ADC off, WDT enable,
fSYS=20MHz on
No load, ADC off, WDT disable,
LVR disable
—
0.1
1.0
μA
—
0.3
2.0
μA
—
1.3
5.0
μA
—
2.2
10
μA
—
0
—
1.5
V
—
0
—
0.2VDD
V
—
3.5
—
5.0
V
—
0.8VDD
—
VDD
V
5V±10%
0.0
—
0.8
V
5V±10%
2.0
—
VDD
V
No load, ADC off, WDT enable,
LVR disable
LVR enable, 2.1V option
VLVR
Low Voltage Reset Voltage
—
LVR enable, 2.55V option
LVR enable, 3.15V option
-5%×
Typ.
LVR enable, 3.8V option
ILVR
Additional Power
Consumption if LVR is used
IOL
I/O Port Sink Current
IOH
I/O Port Source Current
RPH
Pull-high Resistance for I/O
Ports
IOCDS
Operating Current, Normal
Mode, fSYS=fH (HIRC)
(for OCDS EV testing,
connect to an e-Link)
Rev. 1.00
3V
5V
LVR disable → LVR enable
2.1
V
2.55 +5%×
3.15 Typ.
V
3.8
V
V
—
30
45
μA
—
60
90
μA
3V
VOL=0.1VDD
8
16
—
mA
5V
VOL=0.1VDD
16
32
—
mA
3V
VOH=0.9VDD
-3.75
-7.5
—
mA
5V
VOH=0.9VDD
-7.5
-15
—
mA
3V
—
20
60
100
kΩ
5V
—
10
30
50
kΩ
3V
No load, fH=4MHz, ADC off, WDT enable
—
0.7
1.0
mA
11
October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
A.C. Characteristics
Ta=25°C
Symbol
Test Conditions
Parameter
Min.
Typ.
Max.
Unit
DC
DC
─
8
MHz
─
12
4.5V~5.5V
MHz
DC
─
20
2.2V~5.5V
MHz
0.4
─
8
MHz
0.4
─
12
MHz
4.5V~5.5V
0.4
─
20
MHz
3V/5V
-2%
4
+2%
MHz
-2%
8
+2%
MHz
3V/5V
-2%
12
+2%
MHz
3V/5V
-4%
4
+3%
MHz
-4%
8
+3%
MHz
-4%
12
+3%
MHz
-7%
4
+7%
MHz
-7%
8
+7%
MHz
3V/5V
-7%
12
+7%
MHz
2.2V~4.0V
-9%
4
+6%
MHz
-5%
4
+12% MHz
VDD
Conditions
2.2V~5.5V
fCPU
fSYS
Operating Clock
System clock (HXT)
2.7V~5.5V
2.7V~5.5V
3V/5V
3V/5V
─
─
Ta=25°C
Ta=0°C~70°C
3V/5V
3V/5V
3V/5V
3.0V~5.5V
fHIRC
System Clock (HIRC)
2.2V~4.0V
Ta=-40°C~85°C
Ta=0°C~70°C
-9%
8
+5%
-5%
8
+11% MHz
-10%
12
+10% MHz
3.0V~5.5V Ta=0°C~70°C
-10%
12
+10% MHz
2.2V~4.0V Ta=-40°C~85°C
-12%
4
+6%
3.0V~5.5V Ta=-40°C~85°C
-8%
4
+12% MHz
2.2V~4.0V Ta=-40°C~85°C
-12%
8
+6%
3.0V~5.5V Ta=-40°C~85°C
-8%
8
+12% MHz
2.7V~4.0V Ta=-40°C~85°C
-13%
12
+13% MHz
3.0V~5.5V Ta=-40°C~85°C
-13%
12
+13% MHz
2.2V~5.5V
-15%
4
+15% MHz
2.2V~5.5V Ta=-40°C~85°C
-15%
8
+15% MHz
2.7V~5.5V
-15%
12
+15% MHz
-10%
32
+10%
kHz
-50%
32
+60%
kHz
3.0V~5.5V
Ta=0°C~70°C
2.7V~4.0V Ta=0°C~70°C
5V
Ta=25°C
MHz
MHz
MHz
fLIRC
System Clock (LIRC)
tTIMER
TCKn Input Pulse Width
─
─
0.3
─
─
μs
tINT
Interrupt Pulse Width
─
─
10
─
─
μs
tLVR
Low Voltage Width to Reset
─
─
120
240
480
μs
tSRESET
Software Reset Width to Reset
─
─
45
90
120
μs
tEERD
EEPROM Read Time
─
─
─
2
4
tSYS
tEEWR
EEPROM Write Time
─
─
─
2
4
ms
─
fSYS=HXT
─
1024
─
tSYS
tSST
Rev. 1.00
2.2V~5.5V Ta=-40°C~85°C
System Start-up Timer Period
(Wake-up from HALT)
12
─
fSYS=HIRC
─
15~16
─
tSYS
─
fSYS=LIRC
─
1~2
─
tSYS
October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
Symbol
tRSTD
Test Conditions
Parameter
Min.
Typ.
Max.
Unit
─
25
50
100
ms
─
8.3
16.7
33.3
ms
VDD
Conditions
System Reset Delay Time
(Power On Reset, LVR reset, LVR S/W
reset(LVRC), WDT S/W reset(WDTC))
─
System Reset Delay Time
(WDT normal reset)
─
Note: 1. tSYS=1/fSYS
2. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1μF decoupling capacitor should
be connected between VDD and VSS and located as close to the device as possible.
DC Electrical Characteristics
Ta=25°C
Symbol
Parameter
Test Conditions
VDD
Conditions
Min.
Typ.
Max. Unit
AVDD
A/D Converter Operating Voltage
─
─
2.7
─
5.5
V
VADI
A/D Converter Input Voltage
─
─
0
─
VREF
V
VREF
A/D Converter Reference Voltage
─
─
2
─
AVDD
V
VBG
Reference Voltage with Buffer Voltage
─
─
-3%
1.25
+3%
V
VREF=AVDD=VDD
tADCK=0.5μs
-2
─
+2
LSB
VREF=AVDD=VDD
tADCK=0.5μs
-4
─
+4
LSB
3V
No load (tADCK=0.5μs )
─
0.9
1.35
mA
5V
No load (tADCK=0.5μs )
─
1.2
1.8
mA
2.7V
DNL
Differential Non-linearity
3V
5V
2.7V
INL
Integral Non-linearity
3V
5V
IADC
Additional Power Consumption if A/D
Converter is used
IBG
Additional Power Consumption if VBG
Reference with Buffer is used
─
─
─
200
300
μA
tADCK
A/D Converter Clock Period
─
─
0.5
─
10
μs
tADC
A/D Conversion Time
(Include Sample and Hold Time)
─
─
16
─
tADCK
tADS
A/D Converter Sampling Time
─
─
─
4
─
tADCK
tON2ST
A/D Converter On-to-Start Time
─
─
2
─
─
μs
tBGS
VBG Turn on Stable Time
─
─
200
─
─
μs
Rev. 1.00
13
12-bit ADC
October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
Comparator Electrical Characteristics
Symbol
—
Test Conditions
Parameter
Comparator operating voltage
VDD
Conditions
—
—
3V
ICM
Comparator operating current
VCMPOS
Comparator input offset voltage
5V
—
5V
—
Min.
Typ.
Max.
Unit
2.2
—
5.5
V
—
50
75
μA
—
85
130
μA
-10
—
+10
mV
mV
VHYS
Hysteresis width
5V
—
20
40
60
VCM
Comparator common mode voltage range
—
—
VSS
—
VDD-1.4
V
AOL
Comparator open loop gain
—
—
60
80
—
dB
tPD
Comparator response time
— With 100mV overdrive (Note)
—
300
600
ns
Note: Measured with comparator one input pin at VCM=(VDD-1.4)/2 while the other pin input transition from VSS to
(VCM +100mV) or from VDD to (VCM -100mV).
Power on Reset Electrical Characteristics
Ta=25°C
Symbol
Test Conditions
Parameter
VDD
Conditions
Min.
Typ. Max.
Unit
VPOR
VDD Start Voltage to Ensure Power-on Reset
─
─
─
─
100
mV
RRVDD
VDD Rising Rate to Ensure Power-on Reset
─
─
0.035
─
─
V/ms
tPOR
Minimum Time for VDD Stays at VPOR to Ensure
Power-on Reset
─
─
1
─
─
ms
Rev. 1.00
14
October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed
to their internal system architecture. The device takes advantage of the usual features found within
RISC microcontrollers providing increased speed of operation and Periodic performance. The
pipelining scheme is implemented in such a way that instruction fetching and instruction execution
are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch
or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which
carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions,
etc. The internal data path is simplified by moving data through the Accumulator and the ALU.
Certain internal registers are implemented in the Data Memory and can be directly or indirectly
addressed. The simple addressing methods of these registers along with additional architectural
features ensure that a minimum of external components is required to provide a functional I/O and
A/D control system with maximum reliability and flexibility. This makes the device suitable for
low-cost, high-volume production for controller applications.
Clocking and Pipelining
The main system clock, derived from either a HXT, HIRC or LIRC oscillator is subdivided into
four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at
the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4
clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms
one instruction cycle. Although the fetching and execution of instructions takes place in consecutive
instruction cycles, the pipelining structure of the microcontroller ensures that instructions are
effectively executed in one instruction cycle. The exception to this are instructions where the
contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the
instruction will take one more instruction cycle to execute.


   
   
System Clock and Pipelining
Rev. 1.00
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HT66F007
Small Package A/D Flash 8-bit MCU
For instructions involving branches, such as jump or call instructions, two machine cycles are
required to complete instruction execution. An extra cycle is required as the program takes one
cycle to first obtain the actual jump or call address and then another cycle to actually execute the
branch. The requirement for this extra cycle should be taken into account by programmers in timing
sensitive applications.
  
    
 Instruction Fetching
Program Counter
During program execution, the Program Counter is used to keep track of the address of the next
instruction to be executed. It is automatically incremented by one each time an instruction is
executed except for instructions, such as “JMP” or “CALL” that demand a jump to a non-consecutive
Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are
directly addressable by the application program.
When executing instructions requiring jumps to non-consecutive addresses such as a jump
instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control
by loading the required address into the Program Counter. For conditional skip instructions, once
the condition has been met, the next instruction, which has already been fetched during the present
instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is
obtained.
Program Counter
Program Counter High byte
PCL Register
PC10~PC8
PCL7~PCL0
The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is
available for program control and is a readable and writeable register. By transferring data directly
into this register, a short program jump can be executed directly, however, as only this low byte
is available for manipulation, the jumps are limited to the present page of memory, that is 256
locations. When such program jumps are executed it should also be noted that a dummy cycle
will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is
needed to pre-fetch.
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HT66F007
Small Package A/D Flash 8-bit MCU
Stack
This is a special part of the memory which is used to save the contents of the Program Counter
only. The stack is neither part of the data nor part of the program space, and is neither readable nor
writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed
onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction,
RET or RETI, the Program Counter is restored to its previous value from the stack. After a device
reset, the Stack Pointer will point to the top of the stack.
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded
but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or
RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer
to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can
still be executed which will result in a stack overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program branching. If the stack is overflow, the first Program
Counter save in the stack will be lost.
P ro g ra m
T o p o f S ta c k
S ta c k L e v e l 1
S ta c k L e v e l 2
S ta c k
P o in te r
B o tto m
C o u n te r
S ta c k L e v e l 3
o f S ta c k
P ro g ra m
M e m o ry
S ta c k L e v e l 8
Arithmetic and Logic Unit – ALU
The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic
and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU
receives related instruction codes and performs the required arithmetic or logical operations after
which the result will be placed in the specified register. As these ALU calculation or operations may
result in carry, borrow or other status changes, the status register will be correspondingly updated to
reflect these changes. The ALU supports the following functions:
• Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA
• Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA
• Rotation: RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC
• Increment and Decrement: INCA, INC, DECA, DEC
• Branch decision: JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI
Rev. 1.00
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HT66F007
Small Package A/D Flash 8-bit MCU
Flash Program Memory
The Program Memory is the location where the user code or program is stored. For this device the
Program Memory is Flash type, which means it can be programmed and re-programmed a large
number of times, allowing the user the convenience of code modification on the same device.
By using the appropriate programming tools, this Flash device offers users the flexibility to
conveniently debug and develop their applications while also offering a means of field programming
and updating.
Structure
The Program Memory has a capacity of 2K×16 bits. The Program Memory is addressed by the
Program Counter and also contains data, table information and interrupt entries. Table data, which
can be setup in any location within the Program Memory, is addressed by a separate table pointer
register.
Special Vectors
Within the Program Memory, certain locations are reserved for the reset and interrupts. The location
000H is reserved for use by the device reset for program initialisation. After a device reset is
initiated, the program will jump to this location and begin execution.
Program Memory Structure
Look-up Table
Any location within the Program Memory can be defined as a look-up table where programmers can
store fixed data. To use the look-up table, the table pointer must first be setup by placing the address
of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers
define the total address of the look-up table.
After setting up the table pointer, the table data can be retrieved from the Program Memory using
the “TABRD [m]” or “TABRDL [m]” instructions, respectively. When the instruction is executed,
the lower order table byte from the Program Memory will be transferred to the user defined
Data Memory register [m] as specified in the instruction. The higher order table data byte from
the Program Memory will be transferred to the TBLH special register. Any unused bits in this
transferred higher order byte will be read as “0”.
The accompanying diagram illustrates the addressing data flow of the look-up table.
Rev. 1.00
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October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
Instruction
Table Location Bits
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
TABRD [m]
@10
@9
@8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: b10~b0: Table location bits
@7~@0: Table pointer (TBLP) bits
@10~@8: Table pointer (TBHP) bits
Table Program Example
The following example shows how the table pointer and table data is defined and retrieved from the
microcontroller. This example uses raw table data located in the Program Memory which is stored
there using the ORG statement. The value at this ORG statement is “700H” which refers to the start
address of the last page within the 2K words Program Memory of the device. The table pointer is setup
here to have an initial value of “06H”. This will ensure that the first data read from the data table will
be at the Program Memory address “706H” or 6 locations after the start of the last page. Note that the
value for the table pointer is referenced to the first address of the present page if the “TABRD [m]”
instruction is being used. The high byte of the table data which in this case is equal to zero will be
transferred to the TBLH register automatically when the “TABRD [m]” instruction is executed.
Because the TBLH register is a read-only register and cannot be restored, care should be taken
to ensure its protection if both the main routine and Interrupt Service Routine use table read
instructions. If using the table read instructions, the Interrupt Service Routines may change the
value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is
recommended that simultaneous use of the table read instructions should be avoided. However, in
situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the
execution of any main routine table-read instructions. Note that all table related instructions require
two instruction cycles to complete their operation.
Table Read Program Example
tempreg1 db ? ; temporary register #1
tempreg2 db ? ; temporary register #2
:
:
mov a,06h ; initialise low table pointer - note that this address is referenced
mov tblp,a ; to the last page or present page
mov a,07h ; initialise high table pointer
mov tbhp,a
:
:
tabrd tempreg1 ; transfers value in table referenced by table pointer data at program
; memory address “706H” transferred to tempreg1 and TBLH
dec tblp ; reduce value of table pointer by one
tabrd tempreg2 ; transfers value in table referenced by table pointer data at program
; memory address “705H” transferred to tempreg2 and TBLH in this
; example the data “1AH” is transferred to tempreg1 and data “0FH” to
; register tempreg2
:
:
org 700h; sets initial address of program memory
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
Rev. 1.00
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October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
In Circuit Programming
The provision of Flash type Program Memory provides the user with a means of convenient and easy
upgrades and modifications to their programs on the same device. As an additional convenience,
Holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface.
This provides manufacturers with the possibility of manufacturing their circuit boards complete with
a programmed or un-programmed microcontroller, and then programming or upgrading the program
at a later stage. This enables product manufacturers to easily keep their manufactured products
supplied with the latest program releases without removal and re-insertion of the device.
The Holtek Flash MCU to Writer Programming Pin correspondence table is as follows:
Holtek Write Pins
MCU Programming Pins
Function
ICPDA
PA0
Programming Serial Data
ICPCK
PA1
Programming Serial Clock
VDD
VDD
Power Supply
VSS
VSS
Ground
The Program Memory and EEPROM data memory can both be programmed serially in-circuit using
this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional
line for the clock. Two additional lines are required for the power supply and ground. The technical
details regarding the in-circuit programming of the device are beyond the scope of this document
and will be supplied in supplementary literature.
W r ite r C o n n e c to r
S ig n a ls
M C U
W r ite r _ V D D
V D D
IC P D A
P A 0
IC P C K
P A 1
W r ite r _ V S S
V S S
*
P r o g r a m m in g
P in s
*
T o o th e r C ir c u it
Note: * may be resistor or capacitor. The resistance of * must be greater than 1k or the capacitance
of * must be less than 1nF.
Rev. 1.00
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October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
On-Chip Debug Support – OCDS
There is an EV chip which is used to emulate the HT66F00x device series. This EV chip device also
provides an “On-Chip Debug” function to debug the device during the development process. The
EV chip and the actual MCU devices are almost functionally compatible except for the “On-Chip
Debug” function. Users can use the EV chip device to emulate the real chip device behavior
by connecting the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The
OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS
clock input pin. When users use the EV chip for debugging, other functions which are shared with
the OCDSDA and OCDSCK pins in the actual MCU device will have no effect in the EV chip.
However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as
the Flash Memory programming pins for ICP. For a more detailed OCDS description, refer to the
corresponding document named “Holtek e-Link for 8-bit MCU OCDS User’s Guide”.
Holtek e-Link Pins
EV Chip Pins
Pin Description
OCDSDA
OCDSDA
On-chip Debug Support Data/Address input/output
OCDSCK
OCDSCK
On-chip Debug Support Clock input
VDD
VDD
Power Supply
GND
VSS
Ground
RAM Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where
temporary information is stored.
Structure
Divided into two sections, the first of these is an area of RAM, known as the Special Function Data
Memory. Here are located registers which are necessary for correct operation of the device. Many
of these registers can be read from and written to directly under program control, however, some
remain protected from user manipulation. The second area of Data Memory is known as the General
Purpose Data Memory, which is reserved for general purpose use. All locations within this area are
read and write accessible under program control.
The overall Data Memory is subdivided into two banks. The Special Purpose Data Memory registers
are accessible in all banks, with the exception of the EEC register at address 40H, which is only
accessible in Bank 1. Switching between the different Data Memory banks is achieved by setting the
Bank Pointer to the correct value. The start address of the Data Memory for the device is the address
00H.
Rev. 1.00
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HT66F007
Small Package A/D Flash 8-bit MCU
Special Purpose Data Memory Structure
Rev. 1.00
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October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
Special Function Register Description
Most of the Special Function Register details will be described in the relevant functional section,
however several registers require a separate description in this section.
Indirect Addressing Registers – IAR0, IAR1
The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM
register space, do not actually physically exist as normal registers. The method of indirect addressing
for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in
contrast to direct memory addressing, where the actual memory address is specified. Actions on the
IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather
to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a
pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can
access data from any bank. As the Indirect Addressing Registers are not physically implemented,
reading the Indirect Addressing Registers indirectly will return a result of “00H” and writing to the
registers indirectly will result in no operation.
Memory Pointers – MP0, MP1
Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are
physically implemented in the Data Memory and can be manipulated in the same way as normal
registers providing a convenient way with which to address and track data. When any operation to
the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller
is directed to is the address specified by the related Memory Pointer. MP0, together with Indirect
Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to
access data from all banks according to BP register. Direct Addressing can only be used with Bank 0,
all other Banks must be addressed indirectly using MP1 and IAR1.
The following example shows how to clear a section of four Data Memory locations already defined
as locations adres1 to adres4.
Indirect Addressing Program Example
data .section ´data´
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block db ?
code .section at 0 ´code´
org 00h
start:
mov a,04h ;
mov block,a
mov a,offset adres1 ;
mov mp0,a ;
loop:
clr IAR0 ;
inc mp0;
sdz block ;
jmp loop
continue:
setup size of block
Accumulator loaded with first RAM address
setup memory pointer with first RAM address
clear the data at address defined by mp0
increment memory pointer
check if last memory location has been cleared
The important point to note here is that in the example shown above, no reference is made to specific
Data Memory addresses.
Rev. 1.00
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HT66F007
Small Package A/D Flash 8-bit MCU
Bank Pointer – BP
For this device, the Data Memory is divided into two banks, Bank0 and Bank1. Selecting the
required Data Memory area is achieved using the Bank Pointer. Bit 0 of the Bank Pointer is used to
select Data Memory Banks 0~1.
The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power
Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the
Special Function Data Memory is not affected by the bank selection, which means that the Special
Function Registers can be accessed from within any bank. Directly addressing the Data Memory
will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing
data from Bank1 must be implemented using Indirect Addressing.
BP Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
—
DMBP0
R/W
—
—
—
—
—
—
—
R/W
POR
—
—
—
—
—
—
—
0
Bit 7~1
Unimplemented, read as “0”
Bit 0DMBP0: Select Data Memory Banks
0: Bank 0
1: Bank 1
Accumulator – ACC
The Accumulator is central to the operation of any microcontroller and is closely related with
operations carried out by the ALU. The Accumulator is the place where all intermediate results
from the ALU are stored. Without the Accumulator it would be necessary to write the result of
each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads. Data transfer operations usually involve
the temporary storage function of the Accumulator; for example, when transferring data between
one user-defined register and another, it is necessary to do this by passing the data through the
Accumulator as no direct transfer between two registers is permitted.
Program Counter Low Register – PCL
To provide additional program control functions, the low byte of the Program Counter is made
accessible to programmers by locating it within the Special Purpose area of the Data Memory. By
manipulating this register, direct jumps to other program locations are easily implemented. Loading
a value directly into this PCL register will cause a jump to the specified Program Memory location,
however, as the register is only 8-bit wide, only jumps within the current Program Memory page are
permitted. When such operations are used, note that a dummy cycle will be inserted.
Look-up Table Registers – TBLP, TBHP, TBLH
These three special function registers are used to control operation of the look-up table which is
stored in the Program Memory. TBLP and TBHP are the table pointers and indicate the location
where the table data is located. Their value must be setup before any table read commands are
executed. Their value can be changed, for example using the “INC” or “DEC” instructions, allowing
for easy table data pointing and reading. TBLH is the location where the high order byte of the table
data is stored after a table read data instruction has been executed. Note that the lower order table
data byte is transferred to a user defined location.
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Small Package A/D Flash 8-bit MCU
Status Register – STATUS
This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation
and system management flags are used to record the status and operation of the microcontroller.
With the exception of the TO and PDF flags, bits in the status register can be altered by instructions
like most other registers. Any data written into the status register will not change the TO or PDF flag.
In addition, operations related to the status register may give different results due to the different
instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or
by executing the “CLR WDT” or “HALT” instruction. The PDF flag is affected only by executing
the “HALT” or “CLR WDT” instruction or during a system power-up.
The Z, OV, AC and C flags generally reflect the status of the latest operations.
• C is set if an operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through
carry instruction.
• AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
• Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
• OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
• PDF is cleared by a system power-up or executing the “CLR WDT” instruction. PDF is set by
executing the “HALT” instruction.
• TO is cleared by a system power-up or executing the “CLR WDT” or “HALT” instruction. TO is
set by a WDT time-out.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will
not be pushed onto the stack automatically. If the contents of the status registers are important and if
the subroutine can corrupt the status register, precautions must be taken to correctly save it.
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STATUS Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
TO
PDF
OV
Z
AC
C
R/W
R/W
—
—
R
R
R/W
R/W
R/W
POR
—
—
0
0
×
×
×
×
"×" unknown
Bit 7~6
Unimplemented, read as “0”
Bit 5TO: Watchdog Time-Out flag
0: After power up or executing the “CLR WDT” or “HALT” instruction
1: A watchdog time-out occurred.
Bit 4PDF: Power down flag
0: After power up or executing the “CLR WDT” instruction
1: By executing the “HALT” instruction
Bit 3OV: Overflow flag
0: No overflow
1: An operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit or vice versa.
Bit 2Z: Zero flag
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero
Bit 1AC: Auxiliary flag
0: No auxiliary carry
1: An operation results in a carry out of the low nibbles in addition, or no borrow
from the high nibble into the low nibble in subtraction
Bit 0C: Carry flag
0: No carry-out
1: An operation results in a carry during an addition operation or if a borrow does
not take place during a subtraction operation
C is also affected by a rotate through carry instruction.
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Small Package A/D Flash 8-bit MCU
EEPROM Data Memory
One of the special features in the device is its internal EEPROM Data Memory. EEPROM, which
stands for Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile
form of memory, with data retention even when its power supply is removed. By incorporating
this kind of data memory, a whole new host of application possibilities are made available to the
designer. The availability of EEPROM storage allows information such as product identification
numbers, calibration values, specific user data, system setup data or other product information to
be stored directly within the product microcontroller. The process of reading and writing data to the
EEPROM memory has been reduced to a very trivial affair.
EEPROM Data Memory Structure
The EEPROM Data Memory capacity is up to 512×8 bits. Unlike the Program Memory and
RAM Data Memory, the EEPROM Data Memory is not directly mapped and is therefore not
directly accessible in the same way as the other types of memory. Read and Write operations to the
EEPROM are carried out in single byte operations using an address and data register in Bank 0 and
a single control register in Bank 1.
EEPROM Registers
Four registers control the overall operation of the internal EEPROM Data Memory. These are the
address registers, EEA and EEAH, the data register, EED and a single control register, EEC. As all
the EEA, EEAH and EED registers are located in Bank 0, they can be directly accessed in the same
way as any other Special Function Register. The EEC register however, being located in Bank1,
cannot be directly addressed directly and can only be read from or written to indirectly using the
MP1 Memory Pointer and Indirect Addressing Register, IAR1. Because the EEC control register is
located at address 40H in Bank 1, the MP1 Memory Pointer must first be set to the value 40H and
the Bank Pointer register, BP, set to the value, 01H, before any operations on the EEC register are
executed.
EEPROM Control Registers List
Name
EEA
Bit
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
D8
EEAH
—
—
—
—
—
—
—
EED
D7
D6
D5
D4
D3
D2
D1
D0
EEC
—
—
—
—
WREN
WR
RDEN
RD
EEA Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.00
Data EEPROM address
Data EEPROM address bit 7~bit 0
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EEAH Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
—
D8
R/W
—
—
—
—
—
—
—
R/W
POR
—
—
—
—
—
—
—
0
4
3
2
1
0
Bit 7~1
Unimplemented, read as “0”
Bit 0
Data EEPROM address
Data EEPROM address bit 8
EED Register
Bit
7
6
5
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
4
3
2
1
0
Bit 7~0
Data EEPROM data
Data EEPROM data bit 7~bit 0
EEC Register
Bit
7
6
5
Name
—
—
—
—
WREN
WR
RDEN
RD
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
Bit 7~4
Unimplemented, read as “0”
Bit 3WREN: Data EEPROM Write Enable
0: Disable
1: Enable
This is the Data EEPROM Write Enable Bit which must be set high before Data
EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM write operations.
Bit 2WR: EEPROM Write Control
0: Write cycle has finished
1: Activate a write cycle
This is the Data EEPROM Write Control Bit and when set high by the application
program will activate a write cycle. This bit will be automatically reset to zero by the
hardware after the write cycle has finished. Setting this bit high will have no effect if
the WREN has not first been set high.
Bit 1RDEN: Data EEPROM Read Enable
0: Disable
1: Enable
This is the Data EEPROM Read Enable Bit which must be set high before Data
EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM read operations.
Bit 0RD: EEPROM Read Control
0: Read cycle has finished
1: Activate a read cycle
This is the Data EEPROM Read Control Bit and when set high by the application
program will activate a read cycle. This bit will be automatically reset to zero by the
hardware after the read cycle has finished. Setting this bit high will have no effect if
the RDEN has not first been set high.
Note: The WREN, WR, RDEN and RD can not be set to “1” at the same time in one instruction. The
WR and RD can not be set to “1” at the same time.
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Small Package A/D Flash 8-bit MCU
Reading Data from the EEPROM
To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set
high to enable the read function. The EEPROM address of the data to be read must then be placed
in the EEA and EEAH registers. If the RD bit in the EEC register is now set high, a read cycle will
be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been
set. When the read cycle terminates, the RD bit will be automatically cleared to zero, after which the
data can be read from the EED register. The data will remain in the EED register until another read
or write operation is executed. The application program can poll the RD bit to determine when the
data is valid for reading.
Writing Data to the EEPROM
The EEPROM address of the data to be written must then be placed in the EEA and EEAH registers
and the data placed in the EED register. To write data to the EEPROM, the write enable bit, WREN,
in the EEC register must first be set high to enable the write function. After this, the WR bit in
the EEC register must be immediately set high to initiate a write cycle. These two instructions
must be executed consecutively. The global interrupt bit EMI should also first be cleared before
implementing any write operations, and then set again after the write cycle has started. Note that
setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the
EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to
microcontroller system clock, a certain time will elapse before the data will have been written into
the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the
WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates,
the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the
data has been written to the EEPROM. The application program can therefore poll the WR bit to
determine when the write cycle has ended.
Write Protection
Protection against inadvertent write operation is provided in several ways. After the device is
powered-on the Write Enable bit in the control register will be cleared preventing any write
operations. Also at power-on the Bank Pointer, BP, will be reset to zero, which means that Data
Memory Bank 0 will be selected. As the EEPROM control register is located in Bank 1, this adds a
further measure of protection against spurious write operations. During normal program operation,
ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect
write operations.
EEPROM Interrupt
The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM
interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. When an
EEPROM write cycle ends, the DEF request flag will be set. If the global and EEPROM interrupts
are enabled and the stack is not full, a jump to the associated Interrupt vector will take place. When
the interrupt is serviced the EEPROM interrupt flag will be automatically reset. More details can be
obtained in the Interrupt section.
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Programming Considerations
Care must be taken that data is not inadvertently written to the EEPROM. Protection can be Periodic
by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Bank
Pointer could be normally cleared to zero as this would inhibit access to Bank 1where the EEPROM
control register exist. Although certainly not necessary, consideration might be given in the
application program to the checking of the validity of new write data by a simple read back process.
When writing data the WR bit must be set high immediately after the WREN bit has been set high,
to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared
before a write cycle is executed and then re-enabled after the write cycle starts.
Programming Examples
Reading data from the EEPROM – polling method
MOV A, EEPROM_ADRES
MOV EEA, A
MOV A, 040H MOV MP1, A MOV A, 01H MOV BP, A
SET IAR1.1 SET IAR1.0 BACK:
SZ IAR1.0 JMP BACK
CLR IAR1 CLR BP
MOV A, EED MOV READ_DATA, A
; user defined address
; setup memory pointer MP1
; MP1 points to EEC register
; setup Bank Pointer
; set RDEN bit, enable read operations
; start Read Cycle - set RD bit
; check for read cycle end
; disable EEPROM read/write
; move read data to register
Writing Data to the EEPROM – polling method
MOV A, EEPROM_ADRES
MOV EEA, A
MOV A, EEPROM_DATA
MOV EED, A
MOV A, 040H MOV MP1, A MOV A, 01H MOV BP, A
CLR EMI
SET IAR1.3 SET IAR1.2 SET EMI
BACK:
SZ IAR1.2 JMP BACK
CLR IAR1 CLR BP
Rev. 1.00
; user defined address
; user defined data
; setup memory pointer MP1
; MP1 points to EEC register
; setup Bank Pointer
; set WREN bit, enable write operations
; start Write Cycle - set WR bit
; check for write cycle end
; disable EEPROM read/write
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Small Package A/D Flash 8-bit MCU
Oscillator
Various oscillator options offer the user a wide range of functions according to their various
application requirements. The flexible features of the oscillator functions ensure that the best
optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation
are selected through a combination of configuration options and registers.
Oscillator Overview
In addition to being the source of the main system clock the oscillators also provide clock sources
for the Watchdog Timer and Time Base Interrupts. An external oscillator requiring some external
components as well as fully integrated internal oscillators, requiring no external components,
are provided to form a wide range of both fast and slow system oscillators. All oscillator options
are selected throuth the configuration options. The higher frequency oscillators provide higher
performance but carry with it the disadvantage of higher power requirements, while the opposite
is of course true for the lower frequency oscillators. With the capability of dynamically switching
between fast and slow system clock, the device has the flexibility to optimize the performance/power
ratio, a feature especially important in power sensitive portable applications.
Name
Freq.
Pins
External Crystal
Type
HXT
400kHz~20MHz
OSC1/OSC2
Internal High Speed RC
HIRC
4, 8, 12MHz
—
Internal Low Speed RC
LIRC
32kHz
—
Oscillator Types
System Clock Configurations
There are three methods of generating the system clock, two high speed oscillators and a low speed
oscillator. The high speed oscillators are the external crystal/ceramic oscillator and the internal
4MHz, 8MHz, 12MHz RC oscillator. The low speed oscillator is the internal 32kHz RC oscillator.
Selecting whether the low or high speed oscillator is used as the system oscillator is implemented
using the HLCLK bit and CKS2~CKS0 bits in the SMOD register and as the system clock can be
dynamically selected.
The actual source clock used for each of the high speed and the low speed oscillators is chosen
via configuration options. The frequency of the slow speed or high speed system clock is also
determined using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. Note that two
oscillator selections must be made namely one high speed and one low speed system oscillators. It is
not possible to choose a no-oscillator selection for either the high or low speed oscillator. The OSC1
and OSC2 pins are used to connect the external components for the external crystal.
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Small Package A/D Flash 8-bit MCU
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System Clock Configurations
External Crystal/Ceramic Oscillator – HXT
The External Crystal/Ceramic System Oscillator is one of the high frequency oscillator choices,
which is selected via configuration option. For most crystal oscillator configurations, the simple
connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for
oscillation, without requiring external capacitors. However, for some crystal types and frequencies,
to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a
ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as
shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the
crystal or resonator manufacturer’s specification.
     Crystal/Resonator Oscillator – HXT
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Small Package A/D Flash 8-bit MCU
Crystal Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
12MHz
0pF
0pF
8MHz
0pF
0pF
4MHz
0pF
0pF
1MHz
100pF
100pF
Note: C1 and C2 values are for guidance only.
Crystal Recommended Capacitor Values
Internal RC Oscillator – HIRC
The internal RC oscillator is a fully integrated system oscillator requiring no external components.
The internal RC oscillator has three fixed frequencies of either 4MHz, 8MHz or 12MHz. Device
trimming during the manufacturing process and the inclusion of internal frequency compensation
circuits are used to ensure that the influence of the power supply voltage, temperature and process
variations on the oscillation frequency are minimised. As a result, at a power supply of 5V and
at temperature of -40˚C~85˚C degrees, the fixed oscillation frequency of the HIRC will have a
tolerance within 2%. Note that if this internal system clock option is selected, as it requires no
external pins for its operation, I/O pins PA6 and PA5 are free for use as normal I/O pins.
Internal 32kHz Oscillator – LIRC
The Internal 32kHz System Oscillator is the low frequency oscillator. It is a fully integrated
RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its
implementation. Device trimming during the manufacturing process and the inclusion of internal
frequency compensation circuits are used to ensure that the influence of the power supply voltage,
temperature and process variations on the oscillation frequency are minimised. As a result, at a
power supply of 5V and at a temperature of 25˚C degrees, the fixed oscillation frequency of 32kHz
will have a tolerance within 10%.
Supplementary Oscillator
The low speed oscillator, in addition to providing a system clock source is also used to provide
a clock source to two other device functions. These are the Watchdog Timer and the Time Base
Interrupts.
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Small Package A/D Flash 8-bit MCU
Operating Modes and System Clocks
Present day applications require that their microcontrollers have high performance but often still
demand that they consume as little power as possible, conflicting requirements that are especially
true in battery powered portable applications. The fast clocks required for high performance will
by their nature increase current consumption and of course vice-versa, lower speed clocks reduce
current consumption. As Holtek has provided this device with both high and low speed clock
sources and the means to switch between them dynamically, the user can optimise the operation of
their microcontroller to achieve the best performance/power ratio.
System Clocks
The device has many different clock sources for both the CPU and peripheral function operation.
By providing the user with a wide range of clock options using configuration options and register
programming, a clock system can be configured to obtain maximum application performance.
The main system clock, can come from either a high frequency, fH, or a low frequency, fL, and is
selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system
clock can be sourced from either an HXT or HIRC oscillator, selected via a configuration option.
The low speed system clock source can be sourced from the internal clock fL. If fL is selected then
it can be sourced from the LIRC oscillator. The other choice, which is a divided version of the high
speed system oscillator has a range of fH/2~fH/64.
There are two additional internal clocks for the peripheral circuits, the substitute clock, fSUB, and
the Time Base clock, fTBC. Each of these internal clocks is sourced by the LIRC oscillator. The fSUB
clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred
to enable faster wake-up times.
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Small Package A/D Flash 8-bit MCU
System Clock Configurations
Note: When the system clock source fSYS is switched to fL from fH, the high speed oscillation will stop to conserve
the power. Thus there is no fH~fH/64 for peripheral circuit to use.
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System Operation Modes
There are six different modes of operation for the microcontroller, each one with its own
special characteristics and which can be chosen according to the specific performance and
power requirements of the application. There are two modes allowing normal operation of the
microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP0,
SLEEP1, IDLE0 and IDLE1 Modes are used when the microcontroller CPU is switched off to
conserve power.
Operating Mode
Description
CPU
fSYS
fLIRC/fSUB
fTBC
NORMAL mode
On
fH~fH/64
On
On
SLOW mode
On
fL
On
On
ILDE0 mode
Off
Off
On
On
IDLE1 mode
Off
On
On
On
SLEEP0 mode
Off
Off
Off
Off
SLEEP1 mode
Off
Off
On
Off
NORMAL Mode
As the name suggests this is one of the main operating modes where the microcontroller has all of
its functions operational and where the system clock is provided by one of the high speed oscillators.
This mode operates allowing the microcontroller to operate normally with a clock source will come
from one of the high speed oscillators, HXT or HIRC. The high speed oscillator will however first
be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0
and HLCLK bits in the SMOD register. Although a high speed oscillator is used, running the
microcontroller at a divided clock ratio reduces the operating current.
SLOW Mode
This is also a mode where the microcontroller operates normally although now with a slower
speed clock source. The clock source used will be from the low speed oscillator LIRC. Running
the microcontroller in this mode allows it to run with much lower operating currents. In the SLOW
Mode, the fH is off.
SLEEP0 Mode
The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the
SMOD register is low. In the SLEEP0 mode the CPU will be stopped, and the fLIRC clock will be
stopped too, and the Watchdog Timer function is disabled.
SLEEP1 Mode
The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the
SMOD register is low. In the SLEEP1 mode the CPU will be stopped. However the fLIRC clocks will
continue to operate if the Watchdog Timer function is enabled.
IDLE0 Mode
The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the
SMOD register is high and the FSYSON bit in the CTRL register is low. In the IDLE0 Mode the
system oscillator will be inhibited from driving the CPU but some peripheral functions will remain
operational such as the Watchdog Timer and TMs. In the IDLE0 Mode, the system oscillator will be
stopped.
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IDLE1 Mode
The IDLE1 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the
SMOD register is high and the FSYSON bit in the CTRL register is high. In the IDLE1 Mode the
system oscillator will be inhibited from driving the CPU but may continue to provide a clock source
to keep some peripheral functions operational such as the Watchdog Timer and TMs. In the IDLE1
Mode, the system oscillator will continue to run, and this system oscillator may be high speed or low
speed system oscillator. In the IDLE1 Mode the Watchdog Timer clock, fLIRC, will be on.
Control Register
A single register, SMOD, is used for overall control of the internal clocks within the device.
SMOD Register
Bit
7
6
5
4
3
2
1
0
Name
CKS2
CKS1
CKS0
FSTEN
LTO
HTO
IDLEN
HLCLK
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
POR
0
0
0
0
0
0
1
1
Bit 7~5CKS2~CKS0: The system clock selection when HLCLK is “0”
000: fL (fLIRC)
001: fL (fLIRC)
010: fH/64
011: fH/32
100: fH/16
101: fH/8
110: fH/4
111: fH/2
These three bits are used to select which clock is used as the system clock source. In
addition to the system clock source, which can be the LIRC, a divided version of the
high speed system oscillator can also be chosen as the system clock source.
Bit 4FSTEN: Fast Wake-up Control (only for HXT)
0: Disable
1: Enable
This is the Fast Wake-up Control bit which determines if the fSUB clock source is
initially used after the device wakes up. When the bit is high, the fSUB clock source can
be used as a temporary system clock to provide a faster wake up time as the fSUB clock
is available.
Bit 3LTO: Low speed system oscillator ready flag
0: Not ready
1: Ready
This is the low speed system oscillator ready flag which indicates when the low speed
system oscillator is stable after power on reset or a wake-up has occurred. The flag
will be low when in the SLEEP0 mode, but after a wake-up has occurred the flag will
change to a high level after 1~2 cycles if the LIRC oscillator is used.
Bit 2HTO: High speed system oscillator ready flag
0: Not ready
1: Ready
This is the high speed system oscillator ready flag which indicates when the high speed
system oscillator is stable. This flag is cleared to “0” by hardware when the device is
powered on and then changes to a high level after the high speed system oscillator is
stable. Therefore this flag will always be read as “1” by the application program after
device power-on. The flag will be low when in the SLEEP or IDLE0 Mode, but after
power on reset or a wake-up has occurred, the flag will change to a high level after
1024 clock cycles if the HXT oscillator is used and after 15~16 clock cycles if the
HIRC oscillator is used.
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Bit 1IDLEN: IDLE Mode Control
0: Disable
1: Enable
This is the IDLE Mode Control bit and determines what happens when the HALT
instruction is executed. If this bit is high, when a HALT instruction is executed the
device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running
but the system clock will continue to keep the peripheral functions operational, if
FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop
in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT
instruction is executed.
Bit 0HLCLK: System Clock Selection
0: fH/2~fH/64 or fL
1: fH
This bit is used to select if the fH clock or the fH/2~fH/64 or fL clock is used as the
system clock. When the bit is high the f H clock will be selected and if low the
fH/2~fH/64 or fL clock will be selected. When system clock switches from the fH clock
to the fL clock and the fH clock will be automatically switched off to conserve power.
Fast Wake-up
To minimise power consumption the device can enter the SLEEP or IDLE0 Mode, where the system
clock source to the device will be stopped. However when the device is woken up again, it can take
a considerable time for the original system oscillator to restart, stabilise and allow normal operation
to resume. To ensure the device is up and running as fast as possible a Fast Wake-up function is
provided, which allows fSUB, namely the LIRC oscillator, to act as a temporary clock to first drive the
system until the original system oscillator has stabilised. As the clock source for the Fast Wake-up
function is fSUB, the Fast Wake-up function is only available in the SLEEP1 and IDLE0 modes.
When the device is woken up from the SLEEP0 mode, the Fast Wake-up function has no effect
because the fSUB clock is stopped. The Fast Wake-up enable/disable function is controlled using the
FSTEN bit in the SMOD register.
If the HXT oscillator is selected as the NORMAL Mode system clock, and if the Fast Wake-up
function is enabled, then it will take one to two tSUB clock cycles of the LIRC oscillator for the
system to wake-up. The system will then initially run under the fSUB clock source until 1024 HXT
clock cycles have elapsed, at which point the HTO flag will switch high and the system will switch
over to operating from the HXT oscillator.
If the HIRC oscillators or LIRC oscillator is used as the system oscillator then it will take 15~16
clock cycles of the HIRC or 1~2 cycles of the LIRC to wake up the system from the SLEEP or
IDLE0 Mode. The Fast Wake-up bit, FSTEN will have no effect in these cases.
System FSTEN
Oscillator
Bit
0
HXT
1
HIRC
×
LIRC
×
Wake-up Time
(SLEEP0 Mode)
Wake-up Time
(SLEEP1 Mode)
Wake-up Time
(IDLE0 Mode, FSYSON=0)
Wake-up Time (IDLE1
Mode, FSYSON=1)
1024 HXT cycles
1024 HXT cycles
1~2 HXT cycles
1024 HXT cycles
1~2 fSUB cycles
(System runs with fSUB first for 1024 HXT cycles
and then switches over to run with the HXT clock)
1~2 HXT cycles
15~16 HIRC cycles 15~16 HIRC cycles
1~2 LIRC cycles
1~2 LIRC cycles
1~2 HIRC cycles
1~2 LIRC cycles
Note that if the Watchdog Timer is disabled, which means that the LIRC is off, then there will be no
Fast Wake-up function available when the device wakes-up from the SLEEP0 Mode.
Rev. 1.00
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HT66F007
Small Package A/D Flash 8-bit MCU

­ 
   

­   Operating Mode Switching
The device can switch between operating modes dynamically allowing the user to select the best
performance/power ratio for the present task in hand. In this way microcontroller operations that
do not require high performance can be executed using slower clocks thus requiring less operating
current and prolonging battery life in portable applications.
In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed
using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the
NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When
a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is
determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the CTRL
register.
When the HLCLK bit switches to a low level, which implies that clock source is switched from the
high speed clock source, fH, to the clock source, fH/2~fH/64 or fL. If the clock is from the fL, the high
speed clock source will stop running to conserve power. When this happens it must be noted that the
fH/16 and fH/64 internal clock sources will also stop running, which may affect the operation of other
internal functions such as the TMs. The accompanying flowchart shows what happens when the
device moves between the various operating modes.
Rev. 1.00
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HT66F007
Small Package A/D Flash 8-bit MCU
NORMAL Mode to SLOW Mode Switching
When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore
consumes more power, the system clock can switch to run in the SLOW Mode by setting the
HLCLK bit to “0” and setting the CKS2~CKS0 bits to “000” or “001” in the SMOD register.This
will then use the low speed system oscillator which will consume less power. Users may decide to
do this for certain operations which do not require high performance and can subsequently reduce
power consumption.
The SLOW Mode is sourced from the LIRC oscillator and therefore requires this oscillator to be
stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register.
         
          ­           ­          Rev. 1.00
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October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
SLOW Mode to NORMAL Mode Switching
In SLOW Mode the system uses LIRC low speed system oscillator. To switch back to the NORMAL
Mode, where the high speed system oscillator is used, the HLCLK bit should be set to “1” or
HLCLK bit is “0”, but CKS2~CKS0 is set to “010”, “011”, “100”, “101”, “110” or “111”. As a
certain amount of time will be required for the high frequency clock to stabilise, the status of the
HTO bit is checked. The amount of time required for high speed system oscillator stabilization
depends upon which high speed system oscillator type is used.

          
          ­           ­           Rev. 1.00
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October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
Entering the SLEEP0 Mode
There is only one way for the device to enter the SLEEP0 Mode and that is to execute the “HALT”
instruction in the application program with the IDLEN bit in SMOD register equal to “0” and the
WDT off. When this instruction is executed under the conditions described above, the following will
occur:
• The system clock, WDT clock and Time Base clock will be stopped and the application program
will stop at the “HALT” instruction.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and stopped.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Entering the SLEEP1 Mode
There is only one way for the device to enter the SLEEP1 Mode and that is to execute the “HALT”
instruction in the application program with the IDLEN bit in SMOD register equal to “0” and the
WDT on. When this instruction is executed under the conditions described above, the following will
occur:
• The system clock and Time Base clock will be stopped and the application program will stop at
the “HALT” instruction, but the WDT will remain with the clock source coming from the fLIRC
clock.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting as the WDT is enabled.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Entering the IDLE0 Mode
There is only one way for the device to enter the IDLE0 Mode and that is to execute the “HALT”
instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the
FSYSON bit in CTRL register equal to “0”. When this instruction is executed under the conditions
described above, the following will occur:
• The system clock will be stopped and the application program will stop at the “HALT” instruction,
but the Time Base clock fTBC and the fSUB clock will be on.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting if the WDT is enabled.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
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October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
Entering the IDLE1 Mode
There is only one way for the device to enter the IDLE1 Mode and that is to execute the “HALT”
instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the
FSYSON bit in CTRL register equal to “1”. When this instruction is executed under the conditions
described above, the following will occur:
• The system clock and Time Base clock and fSUB will be on and the application program will stop
at the “HALT” instruction.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting if the WDT is enabled.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Standby Current Considerations
As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the
device to as low a value as possible, perhaps only in the order of several micro-amps except in the
IDLE1 Mode, there are other considerations which must also be taken into account by the circuit
designer if the power consumption is to be minimised. Special attention must be made to the I/O pins
on the device. All high-impedance input pins must be connected to either a fixed high or low level as
any floating input pins could create internal oscillations and result in increased current consumption.
This also applies to devices which have different package types, as there may be unbonbed pins.
These must either be setup as outputs or if setup as inputs must have pull-high resistors connected.
Care must also be taken with the loads, which are connected to I/O pins, which are setup as
outputs. These should be placed in a condition in which minimum current is drawn or connected
only to external circuits that do not draw current, such as other CMOS inputs. In the IDLE1 Mode
the system oscillator is on, if the system oscillator is from the high speed system oscillator, the
additional standby current will also be perhaps in the order of several hundred micro-amps.
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HT66F007
Small Package A/D Flash 8-bit MCU
Wake-up
After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources
listed as follows:
• An external falling edge on Port A
• A system interrupt
• A WDT overflow
If the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although
both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can
be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or
executing the clear Watchdog Timer instructions and is set when executing the “HALT” instruction.
The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program
Counter and Stack Pointer, the other flags remain in their original status.
Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin
to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at
the instruction following the “HALT” instruction. If the system is woken up by an interrupt, then
two possible situations may occur. The first is where the related interrupt is disabled or the interrupt
is enabled but the stack is full, in which case the program will resume execution at the instruction
following the “HALT” instruction. In this situation, the interrupt which woke-up the device will not
be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled
or when a stack level becomes free. The other situation is where the related interrupt is enabled and
the stack is not full, in which case the regular interrupt response takes place. If an interrupt request
flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related
interrupt will be disabled.
Programming Considerations
The high speed and low speed oscillators both use the same SST counter. For example, if the system
is woken up from the SLEEP0 Mode and the HIRC oscillators need to start-up from an off state.
• If the device is woken up from the SLEEP0 Mode to the NORMAL Mode, the high speed system
oscillator needs an SST period. The device will execute first instruction after HTO is “1”.
• If the device is woken up from the SLEEP1 Mode to NORMAL Mode, and the system clock
source is from HXT oscillator and FSTEN is “1”, the system clock can be switched to the LIRC
oscillator after wake up.
• There are peripheral functions, such as TMs, for which the fSYS is used. If the system clock source
is switched from fH to fL, the clock source to the peripheral functions mentioned above will
change accordingly.
• The on/off condition of fSUB depends upon whether the WDT is enabled or disabled as the WDT
clock source is sourced from fLIRC.
Rev. 1.00
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HT66F007
Small Package A/D Flash 8-bit MCU
Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to
unknown locations, due to certain uncontrollable external events such as electrical noise.
Watchdog Timer Clock Source
The Watchdog Timer clock source is provided by the internal fLIRC clock which is supplied by the
LIRC oscillator. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 218 to give
longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. The
LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V. However, it
should be noted that this specified internal clock period can vary with VDD, temperature and process
variations. The WDT can be enabled/disabled using the WDTC register.
Watchdog Timer Control Register
A single register, WDTC, controls the required timeout period as well as the enable/disable
operation. The WRF software reset flag will be indicated in the CTRL register. This register controls
the overall operation of the Watchdog Timer.
WDTC Register
Bit
7
6
5
4
3
2
1
0
Name
WE4
WE3
WE2
WE1
WE0
WS2
WS1
WS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
0
1
1
Bit 7~3WE4~WE0: WDT function software control
10101: WDT disable
01010: WDT enable
Other values: Reset MCU
When these bits are changed to any other values by the environmental noise to reset
the microcontroller, the reset operation will be activated after 2~3 LIRC clock cycles
and the WRF bit in the CTRL register will be set to 1to indicate the reset source.
Bit 2~0WS2~WS0: WDT Time-out period selection
000: 28/fLIRC
001: 210/fLIRC
010: 212/fLIRC
011: 214/fLIRC
100: 215/fLIRC
101: 216/fLIRC
110: 217/fLIRC
111: 218/fLIRC
These three bits determine the division ratio of the Watchdog Timer sourece clock,
which in turn determines the timeout period.
Rev. 1.00
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HT66F007
Small Package A/D Flash 8-bit MCU
CTRL Register
Bit
7
6
5
4
3
2
1
0
Name
FSYSON
—
—
—
—
LVRF
LRF
WRF
R/W
R/W
—
—
—
—
R/W
R/W
R/W
POR
0
—
—
—
—
×
0
0
Bit 7
FSYSON: fSYS Control IDLE Mode
Describe elsewhere
Bit 6~3
Unimplemented, read as “0”
Bit 2LVRF: LVR function reset flag
Describe elsewhere
Bit 1LRF: LVRC register software reset flag
Describe elsewhere
Bit 0WRF: WDTC register software reset flag
0: Not occur
1: Occurred
This bit is set to 1 by the WDT Control register software reset and cleared by the
application program. Note that this bit can only be cleared to 0 by the application
program.
Watchdog Timer Operation
The Watchdog Timer operates by providing a device reset when its timer overflows. This means
that in the application program and during normal operation the user has to strategically clear the
Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is
done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps
to an unknown location, or enters an endless loop, the clear WDT instructions will not be executed
in the correct manner, in which case the Watchdog Timer will overflow and reset the device. With
regard to the Watchdog Timer enable/disable function, there are five bits, WE4~WE0, in the WDTC
register to additional enable/disable and reset control of the Watchdog Timer.
WE4~WE0 Bits
WDT Function
10101B
Disable
01010B
Enable
Any other value
Reset MCU
Watchdog Timer Enable/Disable Control
Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set
the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer
time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack
Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer.
The first is a WDT reset, which means a value other than 01010B and 10101B is written into the
WE4~WE0 bit locations, the second is using the Watchdog Timer software clear instructions and the
third is via a HALT instruction. There is only one method of using software instruction to clear the
Watchdog Timer. That is to use the single “CLR WDT” instruction to clear the WDT.
The maximum time-out period is when the 218 division ratio is selected. As an example, with a
32kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8
seconds for the 218 division ratio, and a minimum timeout of 7.8ms for the 28 division ration.
Rev. 1.00
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October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
WDTC Register
WE4~WE0 bits
Reset MCU
CLR
“CLR WDT”Instruction
LIRC
fLIRC
8-stage Divider
fLIRC/28
WDT Prescaler
WS2~WS0
(fLIRC/28 ~ fLIRC/218)
8-to-1 MUX
WDT Time-out
(28/fLIRC ~ 218/fLIRC)
Watchdog Timer
Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set
to some predetermined condition irrespective of outside parameters. The most important reset
condition is after power is first applied to the microcontroller. In this case, internal circuitry will
ensure that the microcontroller, after a short delay, will be in a well defined state and ready to
execute the first program instruction. After this power-on reset, certain important internal registers
will be set to defined states before the program commences. One of these registers is the Program
Counter, which will be reset to zero forcing the microcontroller to begin program execution from the
lowest Program Memory address.
Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All
types of reset operations result in different register conditions being setup. Another reset exists in the
form of a Low Voltage Reset, LVR, where a full reset is implemented in situations where the power
supply voltage falls below a certain threshold.
Reset Functions
There are several ways in which a microcontroller reset can occur, through events occurring both
internally and externally:
• Power-on Reset
The most fundamental and unavoidable reset is the one that occurs after power is first applied to
the microcontroller. As well as ensuring that the Program Memory begins execution from the first
memory address, a power-on reset also ensures that certain other registers are preset to known
conditions. All the I/O port and port control registers will power up in a high condition ensuring
that all pins will be first set to inputs.
VDD
Powe�-on
Reset
tRSTD
SST Time-out
Note: tRSTD is power-on delay, typical time=50ms
Power-On Reset Timing Chart
Rev. 1.00
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HT66F007
Small Package A/D Flash 8-bit MCU
• Low Voltage Reset – LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage
of the device, which is selected via the LVRC register. If the supply voltage of the device drops
to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will
automatically reset the device internally and the LVRF bit in the CTRL register will also be set
to1. For a valid LVR signal, a low voltage, i.e., a voltage in the range between 0.9V~VLVR must
exist for greater than the value tLVR specified in the A.C. characteristics. If the low voltage state
does not exceed this value, the LVR will ignore the low supply voltage and will not perform
a reset function. The actual VLVR can be selected by the LVS bits in the LVRC register. If the
LVS7~LVS0 bits are changed to some certain values by the environmental noise, the LVR will
reset the device after 2~3 LIRC clock cycles. When this happens, the LRF bit in the CTRL
register will be set to 1. After power on the register will have the value of 01010101B. Note that
the LVR function will be automatically disabled when the device enters the power down mode.
Note:tRSTD is power-on delay, typical time=50ms
Low Voltage Reset Timing Chart
• LVRC Register
Bit
7
6
5
4
3
2
1
0
Name
LVS7
LVS6
LVS5
LVS4
LVS3
LVS2
LVS1
LVS0
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
POR
0
1
0
1
0
1
0
1
Bit 7~0LVS7~LVS0: LVR Voltage Select control
01010101: 2.1V
00110011: 2.55V
10011001: 3.15V
10101010: 3.8V
Any other value: Generates MCU reset – register is reset to POR value
When an actual low voltage condition occurs, as specified by one of the four defined
LVR voltage values above, an MCU reset will be generated. The reset operation will
be activated after 2~3 LIRC clock cycles. In this situation this register contents will
remain the same after such a reset occurs.
Any register value, other than the four defined values above, will also result in the
generation of an MCU reset. The reset operation will be activated after 2~3 LIRC
clock cycles. However in this situation this register contents will be reset to the POR
value.
Rev. 1.00
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Small Package A/D Flash 8-bit MCU
• CTRL Register
Bit
7
6
5
4
3
2
1
0
Name
FSYSON
—
—
—
—
LVRF
LRF
WRF
R/W
R/W
—
—
—
—
R/W
R/W
R/W
POR
0
—
—
—
—
×
0
0
Bit 7
FSYSON: fSYS Control IDLE Mode
Describe elsewhere
Bit 6~3
Unimplemented, read as “0”
Bit 2LVRF: LVR function reset flag
0: Not occur
1: Occurred
This bit is set to 1 when a specific Low Voltage Reset situation condition occurs. This
bit can only be cleared to 0 by the application program.
Bit 1LRF: LVRC register software reset flag
0: Not occur
1: Occurred
This bit is set to 1 if the LVRC register contains any non defined LVR voltage register
values. This in effect acts like a software reset function. This bit can only be cleared to
0 by the application program.
Bit 0WRF: WDTC register software reset flag
Describe elsewhere
• Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as an LVR reset except that
the Watchdog time-out flag TO will be set to “1”.
Note: tRSTD is power-on delay, typical time=16.7ms
WDT Time-out Reset during Normal Operation Timing Chart
• Watchdog Time-out Reset during SLEEP or IDLE Mode
The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds
of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack
Pointer will be cleared to “0” and the TO flag will be set to “1”. Refer to the A.C. Characteristics
for tSST details.
Note: The tSST is 15~16 clock cycles if the system clock source is provided by the HIRC.
The tSST is 1024 clocks for HXT. The tSST is 1~2 clock for the LIRC.
WDT Time-out Reset during SLEEP or IDLE Timing Chart
Rev. 1.00
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HT66F007
Small Package A/D Flash 8-bit MCU
Reset Initial Conditions
The different types of reset described affect the reset flags in different ways. These flags, known
as PDF and TO are located in the status register and are controlled by various microcontroller
operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are
shown in the table:
TO
PDF
0
0
Power-on reset
RESET Conditions
u
u
LVR reset during NORMAL or SLOW Mode operation
1
u
WDT time-out reset during NORMAL or SLOW Mode operation
1
1
WDT time-out reset during IDLE or SLEEP Mode operation
Note: “u” stands for unchanged
The following table indicates the way in which the various components of the microcontroller are
affected after a power-on reset occurs.
Item
Condition After RESET
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins counting
Timer Modules
Timer Modules will be turned off
Input/Output Ports
I/O ports will be setup as inputs and AN0~AN4 as A/D input pins
Stack Pointer
Stack Pointer will point to the top of the stack
The different kinds of resets all affect the internal registers of the microcontroller in different ways.
To ensure reliable continuation of normal program execution after a reset occurs, it is important to
know what condition the microcontroller is in after a particular reset occurs. The following table
describes how each type of reset affects each of the microcontroller internal registers. Note that
where more than one package type exists the table will reflect the situation for the larger package
type.
Reset
(Power On)
WDT Time-out
(Normal Operation)
LVR Reset
WDT Time-out
(HALT)*
IAR0
0000 0000
0000 0000
0000 0000
uuuu uuuu
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
IAR1
0000 0000
0000 0000
0000 0000
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
BP
---- ---0
---- ---0
---- ---0
---- ---u
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
0000 0000
0000 0000
0000 0000
0000 0000
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBHP
---- --xx
---- --uu
---- --uu
---- --uu
Register
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
- - 11 u u u u
SMOD
0 0 0 0 0 0 11
0 0 0 0 0 0 11
0 0 0 0 0 0 11
uuuu uuuu
INTEG
---- --00
---- --00
---- --00
---- --uu
INTC0
-000 0000
-000 0000
-000 0000
-uuu uuuu
INTC1
0000 0000
0000 0000
0000 0000
uuuu uuuu
INTC2
--00 --00
--00 --00
--00 --00
--uu --uu
MFI0
--00 --00
--00 --00
--00 --00
--uu --uu
MFI1
--00 --00
--00 --00
--00 --00
--uu --uu
MFI2
--00 --00
--00 --00
--00 --00
--uu --uu
PA
1111 1111
1111 1111
1111 1111
uuuu uuuu
Rev. 1.00
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October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
Reset
(Power On)
WDT Time-out
(Normal Operation)
LVR Reset
WDT Time-out
(HALT)*
PAC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAPU
0000 0000
0000 0000
0000 0000
uuuu uuuu
PAWU
0000 0000
0000 0000
0000 0000
uuuu uuuu
PRM
0000 0-00
0000 0-00
0000 0-00
uuuu u-uu
LVRC
0101 0101
0101 0101
0101 0101
uuuu uuuu
WDTC
0 1 0 1 0 0 11
0 1 0 1 0 0 11
0 1 0 1 0 0 11
uuuu uuuu
TBC
0 0 11 - 111
0 0 11 - 111
0 0 11 - 111
uuuu -uuu
CTRL
0--- -x00
0--- -yyy
0--- -yyy
u--- -uuu
EEAH
---- ---0
---- ---0
---- ---0
---- ---u
EEA
0000 0000
0000 0000
0000 0000
uuuu uuuu
EED
0000 0000
0000 0000
0000 0000
uuuu uuuu
ADRL(ADRFS=0)
xxxx ----
xxxx ----
xxxx ----
uuuu ----
ADRL(ADRFS=1)
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADRH(ADRFS=0)
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADRH(ADRFS=1)
---- xxxx
---- xxxx
---- xxxx
---- uuuu
ADCR0
0 11 0 - 0 0 0
0 11 0 - 0 0 0
0 11 0 - 0 0 0
uuu- -uuu
ADCR1
00-0 -000
00-0 -000
00-0 -000
uuuu uuuu
ACER
- - - 1 1111
- - - 1 1111
- - - 1 1111
---u uuuu
CPC
1000 0001
1000 0001
1000 0001
uuuu uuuu
TMPC
---0 0101
---0 0101
---0 0101
---u uuuu
TM0C0
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0C1
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0DL
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0DH
---- --00
---- --00
---- --00
---- --uu
TM0AL
0000 0000
0000 0000
0000 0000
uuuu uuuu
Register
TM0AH
---- --00
---- --00
---- --00
---- --uu
TM1C0
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1C1
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1DL
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1DH
---- --00
---- --00
---- --00
---- --uu
TM1AL
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1AH
---- --00
---- --00
---- --00
---- --uu
TM2C0
0000 0---
0000 0---
0000 0---
uuuu u---
TM2C1
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM2DL
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM2DH
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM2AL
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM2AH
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM2RP
0000 0000
0000 0000
0000 0000
uuuu uuuu
SPC
---- 0000
---- 0000
---- 0000
---- uuuu
EEC
---- 0000
---- 0000
---- 0000
---- uuuu
Note: "*" stands for warm reset
"-" not implement
"u" stands for "unchanged"
"x" stands for "unknown"
"y" stands for "by register bit function"
Rev. 1.00
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Small Package A/D Flash 8-bit MCU
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output
designation of every pin fully under user program control, pull-high selections for all ports and
wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a
wide range of application possibilities.
The device provides bidirectional input/output lines labeled with port names PA. These I/O ports
are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose
Data Memory table. All of these I/O ports can be used for input and output operations. For input
operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge
of instruction “MOV A, [m]”, where m denotes the port address. For output operation, all the data is
latched and remains unchanged until the output latch is rewritten.
I/O Control Register List
Bit
Register
Name
7
6
5
4
3
2
1
0
PA
D7
D6
D5
D4
D3
D2
D1
D0
PAC
D7
D6
D5
D4
D3
D2
D1
D0
PAPU
D7
D6
D5
D4
D3
D2
D1
D0
PAWU
D7
D6
D5
D4
D3
D2
D1
D0
TP10PS
TP01PS
—
INTPS1
INTPS0
—
SPC3
SPC2
SPC1
SPC0
PRM
TCK1PS1 TCK1PS0 TCK0PS
SPC
—
—
—
Pull-high Resistors
Many product applications require pull-high resistors for their switch inputs usually requiring the
use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when
configured as an input have the capability of being connected to an internal pull-high resistor.
These pull-high resistors are selected using register PAPU, and are implemented using weak PMOS
transistors.
PAPU Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.00
I/O Port A bit7~bit 0 Pull-High Control
0: Disable
1: Enable
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Small Package A/D Flash 8-bit MCU
Port A Wake-up
The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves
power, a feature that is important for battery and other low-power applications. Various methods
exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port
A pins from high to low. This function is especially suitable for applications that can be woken up
via external switches. Each pin on Port A can be selected individually to have this wake-up feature
using the PAWU register.
PAWU Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
I/O Port A bit 7~bit 0 Wake Up Control
0: Disable
1: Enable
I/O Port Control Registers
Each I/O port has its own control register known as PAC, to control the input/output configuration.
With this control register, each CMOS output or input can be reconfigured dynamically under
software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control
register. For the I/O pin to function as an input, the corresponding bit of the control register must
be written as a “1”. This will then allow the logic state of the input pin to be directly read by
instructions. When the corresponding bit of the control register is written as a “0”, the I/O pin will
be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used
to read the output register. However, it should be noted that the program will in fact only read the
status of the output data latch and not the actual logic status of the output pin.
PAC Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
1
1
1
1
1
1
Bit 7~0
Rev. 1.00
I/O Port A bit 7~bit 0 Input/Output Control
0: Output
1: Input
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October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
Special Pin Control
There are four pins, named PA2, PA5, PA6 and PA7, can be set to TTL or CMOS input for special
applications.
SPC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
SPC3
SPC2
SPC1
SPC0
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
Bit 7~4
Unimplemented, read as “0”
Bit 3SPC3: PA7 Special pin control
0: CMOS input
1: TTL input
Bit 2SPC2: PA6 Special pin control
0: CMOS input
1: TTL input
Bit 1SPC1: PA5 Special pin control
0: CMOS input
1: TTL input
Bit 0SPC0: PA2 Special pin control
0: CMOS input
1: TTL input
Pin-remapping Functions
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more
than one function. Limited numbers of pins can force serious design constraints on designers but
by supplying pins with multi-functions, many of these difficulties can be overcome. The way in
which the pin function of each pin is selected is different for each function and a priority order is
established where more than one pin function is selected simultaneously. Additionally there is a
PRM register to establish certain pin functions. Generally speaking, the analog function has higher
priority than the digital function. However, if more than two analog functions are enabled and the
analog signal input comes from the same external pin, the analog input will be internally connected
to all of these active analog functional modules.
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Small Package A/D Flash 8-bit MCU
Pin-remapping Registers
The limited number of supplied pins in a package can impose restrictions on the amount of functions
a certain device can contain. However by allowing the same pins to share several different functions
and providing a means of function selection, a wide range of different functions can be incorporated
into even relatively small package sizes.
• PRM Register
Bit
Name
7
6
5
3
2
1
0
TP10PS
TP01PS
—
INTPS1
INTPS0
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
POR
0
0
0
0
0
—
0
0
Bit 7~6
TCK1PS1 TCK1PS0 TCK0PS
4
TCK1PS1, TCK1PS0: TCK1 pin-remapping function selection bit
00: TCK1 on PA2
01: TCK1 on PA7
10: Undefined
11: TCK1 on PA4
Bit 5TCK0PS: TCK0 pin-remapping function selection bit
0: TCK0 on PA7
1: TCK0 on PA6
Bit 4TP10PS: TP1_0 pin-remapping function selection bit
0: TP1_0 on PA6
1: TP1_0 on PA7
Bit 3TP01PS: TP0_1 pin-remapping function selection bit
0: TP0_1 on PA5
1: TP0_1 on PA1
Rev. 1.00
Bit 2
Unimplemented, read as “0”
Bit 1~0
INTPS1, INTPS0: INT pin-remapping function selection bit
00: INT on PA5
01: INT on PA2
10: INT on PA3
11: INT on PA7
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October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
I/O Pin Structures
The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As
the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a
guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared
structures does not permit all types to be shown.
Generic Input/Output Structure
 €  
 ­
­
   
A/D Input/Output Structure
Rev. 1.00
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HT66F007
Small Package A/D Flash 8-bit MCU
Programming Considerations
Within the user program, one of the first things to consider is port initialisation. After a reset, all of
the I/O data and port control registers will be set high. This means that all I/O pins will default to
an input state, the level of which depends on the other connected circuitry and whether pull-high
selections have been chosen. If the port control register, PAC, is then programmed to setup some
pins as outputs, these output pins will have an initial high output value unless the associated port
data register, PA, is first programmed. Selecting which pins are inputs and which are outputs can
be achieved byte-wide by loading the correct values into the appropriate port control register or
by programming individual bits in the port control register using the “SET [m].i” and “CLR [m].i”
instructions. Note that when using these bit control instructions, a read-modify-write operation takes
place. The microcontroller must first read in the data on the entire port, modify it to the required new
bit values and then rewrite this data back to the output ports.
The power-on reset condition of the A/D converter control registers ensures that any A/D input
pins which are always shared with other I/O functions will be setup as analog inputs after a reset.
Although these pins will be configurated as A/D inputs after a reset, the A/D converter will not be
switched on. It is therefore important to note that if it is required to use these pins as I/O digital
input pins or as other functions, the A/D converter control registers must be correctly programmed
to remove the A/D function. Note also that as the A/D channel is enabled, any internal pull-high
registor connections will be removed.
Port A has the additional capability of providing wake-up functions. When the device is in the
SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high
to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this
function.
Rev. 1.00
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HT66F007
Small Package A/D Flash 8-bit MCU
Timer Modules – TM
One of the most fundamental functions in any microcontroller device is the ability to control and
measure time. To implement time related functions the device includes several Timer Modules,
abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide
operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output
as well as being the functional unit for the generation of PWM signals. Each of the TMs has two
individual interrupts. The addition of input and output pins for each TM ensures that users are
provided with timing units with a wide and flexible range of features.
The common features of the different TM types are described here with more detailed information
provided in the individual Compact and Standard TM sections.
Introduction
The device contains two 10-bit Compact TMs and a 16-bit Standard TM, the 10-bit CTMs are
named to TM0 and TM1, the 16-bit STM is named to TM2. Although similar in nature, the different
TM types vary in their feature complexity. The common features to the Compact and Standard
TMs will be described in this section and the detailed operation will be described in corresponding
sections. The main features and differences between the two types of TMs are summarised in the
accompanying table.
CTM
STM
Timer/Counter
Function
√
√
I/P Capture
—
√
Compare Match Output
√
√
PWM Channels
1
1
Single Pulse Output
—
1
Edge
Edge
Duty or Period
Duty or Period
PWM Alignment
PWM Adjustment Period & Duty
TM Function Summary
TM0
10-bit CTM
TM1
TM2
10-bit CTM
16-bit STM
TM Name/Type Reference
TM Operation
The two different types of TMs offer a diverse range of functions, from simple timing operations
to PWM signal generation. The key to understanding how the TM operates is to see it in terms of
a free running counter whose value is then compared with the value of pre-programmed internal
comparators. When the free running counter has the same value as the pre-programmed comparator,
known as a compare match situation, a TM interrupt signal will be generated which can clear the
counter and perhaps also change the condition of the TM output pin. The internal TM counter is
driven by a user selectable clock source, which can be an internal clock or an external pin.
Rev. 1.00
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Small Package A/D Flash 8-bit MCU
TM Clock Source
The clock source which drives the main counter in each TM can originate from various sources.
The selection of the required clock source is implemented using the TnCK2~TnCK0 bits in the TM
control registers. The clock source can be a ratio of either the system clock fSYS or the internal high
clock fH, the fTBC clock source or the external TCKn pin. Note that setting these bits to the value 101
will select a reserved clock input, in effect disconnecting the TM clock source. The TCKn pin clock
source is used to allow an external signal to drive the TM as an external clock source or for event
counting.
TM Interrupts
The Compact and Standard type TMs each has two internal interrupts, the internal comparator A
or comparator P, which generate a TM interrupt when a compare match condition occurs. When a
TM interrupt is generated, it can be used to clear the counter and also to change the state of the TM
output pin. TM External Pins
Each of the TMs, irrespective of what type, has one TM input pin, with the label TCKn. The TM
input pin, is essentially a clock source for the TM and is selected using the TnCK2~TnCK0 bits in
the TMnC0 register. This external TM input pin allows an external clock source to drive the internal
TM. This external TM input pin is shared with other functions but will be connected to the internal
TM if selected using the TnCK2~TnCK0 bits. The TM input pin can be chosen to have either a
rising or falling active edge.
The TMs each have one or more output pins. When the TM is in the Compare Match Output Mode,
these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare
match situation occurs. The external TPn output pin is also the pin where the TM generates the
PWM output waveform. As the TM output pins are pin-shared with other function, the TM output
function must first be setup using registers. A single bit in one of the registers determines if its
associated pin is to be used as an external TM output pin or if it is to have another function. The
number of output pins for each TM type is different, the details are provided in the accompanying
table.
Both CTM and STM output pin names have an “_n” suffix. Pin names that include a “_0” or “_1”
suffix indicate that they are from a TM with multiple output pins. This allows the TM to generate a
complimentary output pair, selected using the I/O register data bits.
TM0
TM1
TM2
TP0_0, TP0_1
TP1_0, TP1_1
TP2_0
TM Output Pins
Note: The TP2_1 pin of STM is not bonded to the external TM output pin.
Rev. 1.00
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October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
TM Input/Output Pin Control Register
Selecting to have a TM input/output or whether to retain its other shared function is implemented
using one register, with a single bit in each register corresponding to a TM input/output pin. Setting
the bit high will setup the corresponding pin as a TM input/output, if reset to zero the pin will retain
its original other function.
TM0 Function Pin Control Block Diagram
TM1 Function Pin Control Block Diagram
Rev. 1.00
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October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
TM2 Function Pin Control Block Diagram
Note: 1. The I/O register data bits shown are used for TM output inversion control.
2. For the TM2, the TP2_1 pin is not bonded to the external pin.
3. The above diagrams do not enclude the Pin-remapping function, refer to the PRM register
for the Pin-remapping function.
TMPC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
T2CP0
T1CP1
T1CP0
T0CP1
T0CP0
R/W
—
—
—
R/W
R/W
R/W
R/W
R/W
POR
—
—
—
0
0
1
0
1
Bit 7~5 Unimplemented, read as “0”
Bit 4T2CP0: TP2_0 pin control
0: Disable
1: Enable
Bit 3T1CP1: TP1_1 pin Control
0: Disabled
1: Enabled
Bit 2T1CP0: TP1_0 pin control
0: Disabled
1: Enabled
Bit 1T0CP1: TP0_1 pin Control
0: Disabled
1: Enabled
Bit 0T0CP0: TP0_0 pin Control
0: Disabled
1: Enabled
Rev. 1.00
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October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
Programming Considerations
The TM Counter Registers and the Capture/Compare CCRA register, being either 10-bit or 16-bit,
all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes
can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be
carried out in a specific way. The important point to note is that data transfer to and from the 8-bit
buffer and its related low byte only takes place when a write or read operation to its corresponding
high byte is executed.
TM Counte� Registe� (Read only)
TMxDL
TMxDH
�-�it
Buffe�
TMxAL
TMxAH
TM CCRA Registe� (Read/W�ite)
Data
Bus
As the CCRA register is implemented in the way shown in the following diagram and accessing
this register is carried out in a specific way described above, it is recommended to use the “MOV”
instruction to access the CCRA low byte register, named TMxAL, in the following access
procedures. Accessing the CCRA low byte register without following these access procedures will
result in unpredictable values.
The following steps show the read and write procedures:
• Writing Data to CCRA
♦♦
Step 1. Write data to Low Byte TMxAL
––note that here data is only written to the 8-bit buffer.
♦♦
Step 2. Write data to High Byte TMxAH
––here data is written directly to the high byte registers and simultaneously data is latched
from the 8-bit buffer to the Low Byte registers.
• Reading Data from the Counter Registers and CCRA
Rev. 1.00
♦♦
Step 1. Read data from the High Byte TMxDH, TMxAH
––here data is read directly from the High Byte registers and simultaneously data is latched
from the Low Byte register into the 8-bit buffer.
♦♦
Step 2. Read data from the Low Byte TMxDL, TMxAL
––this step reads data from the 8-bit buffer.
62
October 18, 2013
HT66F007
Small Package A/D Flash 8-bit MCU
Compact Type TM – CTM
Although the simplest form of the two TM types, the Compact TM type still contains three operating
modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The
Compact TM can also be controlled with an external input pin and can drive one or two external
output pins. These two external output pins can be the same signal or the inverse signal.
€‚
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„…
ƒ ‚
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€† „‡ …
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­ ­     Compact Type TM Block Diagram (n=0, 1)
Compact TM Operation
At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock
source. There are also two internal comparators with the names, Comparator A and Comparator
P. These comparators will compare the value in the counter with CCRP and CCRA registers. The
CCRP is three bits wide whose value is compared with the highest three bits in the counter while the
CCRA is the ten bits and therefore compares with all counter bits.
The only way of changing the value of the 10-bit counter using the application program, is to
clear the counter by changing the TnON bit from low to high. The counter will also be cleared
automatically by a counter overflow or a compare match with one of its associated comparators.
When these conditions occur, a TM interrupt signal will also usually be generated. The Compact
Type TM can operate in a number of different operational modes, can be driven by different clock
sources including an input pin and can also control two output pins. All operating setup conditions
are selected using relevant internal registers.
Rev. 1.00
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Small Package A/D Flash 8-bit MCU
Compact Type TM Register Description
Overall operation of each Compact TM is controlled using several registers. A read only register
pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store
the internal 10-bit CCRA value. The remaining two registers are control registers which setup the
different operating and control modes as well as the three CCRP bits.
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TMPC
—
—
—
T2CP0
T1CP1
T1CP0
T0CP1
T0CP0
TMnC0
TnPAU
TnCK2
TnCK1
TnCK0
TnON
TnRP2
TnRP1
TnRP0
TMnC1
TnM1
TnM0
TnIO1
TnIO0
TnOC
TnPOL
TnDPX
TnCCLR
D0
TMnDL
D7
D6
D5
D4
D3
D2
D1
TMnDH
—
—
—
—
—
—
D9
D8
TMnAL
D7
D6
D5
D4
D3
D2
D1
D0
TMnAH
—
—
—
—
—
—
D9
D8
Compact TM Register List (n=0, 1)
TMnC0 Register
Bit
7
6
5
4
3
2
1
0
Name
TnPAU
TnCK2
TnCK1
TnCK0
TnON
TnRP2
TnRP1
TnRP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7TnPAU: TMn Counter Pause Control
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the TM will remain powered up
and continue to consume power. The counter will retain its residual value when this bit
changes from low to high and resume counting from this value when the bit changes
to a low value again.
Bit 6~4TnCK2~TnCK0: Select TMn Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fTBC
101: fTBC
110: TCKn rising edge clock
111: TCKn falling edge clock
These three bits are used to select the clock source for the TM. The external pin clock
source can be chosen to be active on the rising or falling edge. The clock source fSYS is
the system clock, while fH and fTBC are other internal clocks, the details of which can
be found in the oscillator section.
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Bit 3TnON: TMn Counter On/Off Control
0: Off
1: On
This bit controls the overall on/off function of the TM. Setting the bit high enables the
counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the
counter from counting and turn off the TM which will reduce its power consumption.
When the bit changes state from low to high the internal counter value will be reset to
zero, however when the bit changes from high to low, the internal counter will retain
its residual value until the bit returns high again.
If the TM is in the Compare Match Output Mode then the TM output pin will be reset
to its initial condition, as specified by the TnOC bit, when the TnON bit changes from
low to high.
Bit 2~0TnRP2~TNRP0: TMn CCRP 3-bit register, compared with the TMn Counter bit 9~bit 7
Comparator P Match Period
000: 1024 TMn clocks
001: 128 TMn clocks
010: 256 TMn clocks
011: 384 TMn clocks
100: 512 TMn clocks
101: 640 TMn clocks
110: 768 TMn clocks
111: 896 TMn clocks
These three bits are used to setup the value on the internal CCRP 3-bit register, which
are then compared with the internal counter’s highest three bits. The result of this
comparison can be selected to clear the internal counter if the TnCCLR bit is set to
zero. Setting the TnCCLR bit to zero ensures that a compare match with the CCRP
values will reset the internal counter. As the CCRP bits are only compared with the
highest three counter bits, the compare values exist in 128 clock cycle multiples.
Clearing all three bits to zero is in effect allowing the counter to overflow at its
maximum value.
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Small Package A/D Flash 8-bit MCU
TMnC1 Register
Bit
7
6
5
4
3
2
1
0
Name
TnM1
TnM0
TnIO1
TnIO0
TnOC
TnPOL
TnDPX
TnCCLR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6TnM1~TnM0: Select TMn Operating Mode
00: Compare Match Output Mode
01: Undefined
10: PWM Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the TM. To ensure reliable operation the
TM should be switched off before any changes are made to the bits. In the Timer/Counter
Mode, the TM output pin control must be disabled.
Bit 5~4TnIO1~TnIO0: Select TMn output function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Mode
00: PWM output inactive state
01: PWM output active state
10: PWM output
11: Undefined
Timer/counter Mode
Unused
These two bits are used to determine how the TM output pin changes state when a
certain condition is reached. The function that these bits select depends upon in which
mode the TM is running.
In the Compare Match Output Mode, the TnIO1~TnIO0 bits determine how the TM
output pin changes state when a compare match occurs from the Comparator A. The
TM output pin can be setup to switch high, switch low or to toggle its present state
when a compare match occurs from the Comparator A. When the TnIO1~TnIO0 bits
are both zero, then no change will take place on the output. The initial value of the TM
output pin should be setup using the TnOC bit. Note that the output level requested by
the TnIO1~TnIO0 bits must be different from the initial value setup using the TnOC
bit otherwise no change will occur on the TM output pin when a compare match
occurs. After the TM output pin changes state it can be reset to its initial level by
changing the level of the TnON bit from low to high.
In the PWM Mode, the TnIO1 and TnIO0 bits determine how the TM output pin
changes state when a certain compare match condition occurs. The PWM output
function is modified by changing these two bits. It is necessary to change the values
of the TnIO1 and TnIO0 bits only after the TM has been switched off. Unpredictable
PWM outputs will occur if the TnIO1 and TnIO0 bits are changed when the TM is
running.
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Small Package A/D Flash 8-bit MCU
Bit 3TnOC: TMn Output control bit
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Mode
0: Active low
1: Active high
This is the output control bit for the TM output pin. Its operation depends upon
whether TM is being used in the Compare Match Output Mode or in the PWM Mode.
It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output
Mode it determines the logic level of the TM output pin before a compare match
occurs. In the PWM Mode it determines if the PWM signal is active high or active
low.
Bit 2TnPOL: TMn Output polarity Control
0: Non-invert
1: Invert
This bit controls the polarity of the TM output pin. When the bit is set high the TM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the
TM is in the Timer/Counter Mode.
Bit 1TnDPX: TMn PWM period/duty Control
0: CCRP - period; CCRA - duty
1: CCRP - duty; CCRA - period
This bit, determines which of the CCRA and CCRP registers are used for period and
duty control of the PWM waveform.
Bit 0TnCCLR: Select TMn Counter clear condition
0: TMn Comparatror P match
1: TMn Comparatror A match
This bit is used to select the method which clears the counter. Remember that the
Compact TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the TnCCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The TnCCLR bit is not
used in the PWM Mode.
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Small Package A/D Flash 8-bit MCU
TMnDL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0TMnDL: TMn Counter Low Byte Register bit 7~bit 0
TMn 10-bit Counter bit 7~bit 0
TMnDH Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
D9
D8
R/W
—
—
—
—
—
—
R
R
POR
—
—
—
—
—
—
0
0
2
1
0
Bit 7~2
Unimplemented, read as “0”
Bit 1~0TMnDH: TMn Counter High Byte Register bit 1~bit 0
TMn 10-bit Counter bit 9~bit 8
TMnAL Register
Bit
7
6
5
4
3
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0TMnAL: TMn CCRA Low Byte Register bit 7~bit 0
TMn 10-bit CCRA bit 7~bit 0
TMnAH Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
D9
D8
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as “0”
Bit 1~0TMnAH: TMn CCRA High Byte Register bit 1~bit 0
TMn 10-bit CCRA bit 9~bit 8
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Small Package A/D Flash 8-bit MCU
Compact Type TM Operating Modes
The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode,
PWM Output Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and
TnM0 bits in the TMnC1 register.
Compare Match Output Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00 respectively.
In this mode once the counter is enabled and running it can be cleared by three methods. These are
a counter overflow, a compare match from Comparator A and a compare match from Comparator P.
When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when
a compare match from Comparator P, the other is when the CCRP bits are all zero which allows
the counter to overflow. Here both TnAF and TnPF interrupt request flags for Comparator A and
Comparator P respectively, will both be generated.
If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the TnAF interrupt request flag will be
generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when
TnCCLR is high no TnPF interrupt request flag will be generated. If the CCRA bits are all zero, the
counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the TnAF
interrupt request flag will not be generated.
As the name of the mode suggests, after a comparison is made, the TM output pin, will change
state. The TM output pin condition however only changes state when a TnAF interrupt request flag
is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag,
generated from a compare match occurs from Comparator P, will have no effect on the TM output
pin. The way in which the TM output pin changes state are determined by the condition of the
TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1
and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match
occurs from Comparator A. The initial condition of the TM output pin, which is setup after the
TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0
bits are zero then no pin change will take place.
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Small Package A/D Flash 8-bit MCU
Counte� Value
Counte� ove�flow
CCRP=0
0x�FF
TnCCLR = 0; TnM [1:0] = 00
CCRP > 0
Counte� �lea�ed �y CCRP value
CCRP > 0
Counte�
Resta�t
Resume
CCRP
Pause
CCRA
Stop
Time
Tn�N
TnPAU
TnP�L
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TM �/P Pin
�utput pin set to
initial Level Low
if Tn�C=0
�utput not affe�ted �y TnAF
flag. Remains High until �eset
�y Tn�N �it
�utput Toggle with
TnAF flag
He�e TnI� [1:0] = 11
Toggle �utput sele�t
Note TnI� [1:0] = 10
A�tive High �utput sele�t
�utput Inve�ts
when TnP�L is high
�utput Pin
Reset to Initial value
�utput �ont�olled �y
othe� pin-sha�ed fun�tion
Compare Match Output Mode – TnCCLR=0
Note: 1. With TnCCLR=0, a Comparator P match will clear the counter
2. The TM output pin controlled only by the TnAF flag
3. The output pin reset to initial state by a TnON bit rising edge
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Small Package A/D Flash 8-bit MCU
Counter Value
TnCCLR = 1; TnM [1:0] = 00
CCRA = 0
Counter overflow
CCRA > 0 Counter cleared by CCRA value
0x3FF
CCRA=0
Resume
CCRA
Pause
Stop
Counter Restart
CCRP
Time
TnON
TnPAU
TnPOL
No TnAF flag
generated on
CCRA overflow
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TnPF not
generated
Output does
not change
TM O/P Pin
Output pin set to
initial Level Low
if TnOC=0
Output not affected by
TnAF flag. Remains High
until reset by TnON bit
Output Toggle with
TnAF flag
Here TnIO [1:0] = 11
Toggle Output select
Note TnIO [1:0] = 10
Active High Output select
Output Inverts
when TnPOL is high
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode – TnCCLR=1
Note: 1. With TnCCLR=1, a Comparator A match will clear the counter
2. The TM output pin controlled only by the TnAF flag
3. The output pin reset to initial state by a TnON rising edge
4. The TnPF flags is not generated when TnCCLR=1
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Small Package A/D Flash 8-bit MCU
Timer/Counter Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively.
The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode
generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output
pin is not used. Therefore the above description and Timing Diagrams for the Compare Match
Output Mode can be used to understand its function. As the TM output pin is not used in this mode,
the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively.
The PWM function within the TM is useful for applications which require functions such as motor
control, heating control, illumination control etc. By providing a signal of fixed frequency but
of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with
varying equivalent DC RMS values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect as the PWM
period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register
is used to clear the internal counter and thus control the PWM waveform frequency, while the other
one is used to control the duty cycle. Which register is used to control either frequency or duty cycle
is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and duty
cycle can therefore be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The TnOC bit In the TMnC1 register is used to
select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to
enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is
used to reverse the polarity of the PWM output waveform.
CTM, PWM Mode, Edge-aligned Mode, TnDPX=0
CCRP
001b
010b
011b
100b
101b
110b
111b
000b
Period
128
256
384
512
640
768
896
1024
Duty
CCRA
If fSYS=16MHz, TM clock source is fSYS/4, CCRP=100b, CCRA=128,
The CTM PWM output frequency=(fSYS/4)/512=fSYS/2048=7.8125kHz, duty=128/512=25%.
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
CTM, PWM Mode, Edge-aligned Mode, TnDPX=1
CCRP
001b
010b
011b
Period
Duty
100b
101b
110b
111b
000b
768
896
1024
CCRA
128
256
384
512
640
The PWM output period is determined by the CCRA register value together with the TM clock
while the PWM duty cycle is defined by the CCRP register value.
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Small Package A/D Flash 8-bit MCU
Counter Value
TnDPX = 0; TnM [1:0] = 10
Counter cleared
by CCRP
Counter Reset when
TnON returns high
CCRP
Pause Resume
CCRA
Counter Stop if
TnON bit low
Time
TnON
TnPAU
TnPOL
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0)
PWM Duty Cycle
set by CCRA
PWM Period
set by CCRP
PWM resumes
operation
Output controlled by
Output Inverts
other pin-shared function
when TnPOL = 1
PWM Mode – TnDPX=0
Note: 1. Here TnDPX=0 - Counter cleared by CCRP
2. A counter clear sets PWM Period
3. The internal PWM function continues running even when TnIO[1:0]=00 or 01
4. The TnCCLR bit has no influence on PWM operation
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Small Package A/D Flash 8-bit MCU
Counter Value
TnDPX = 1; TnM [1:0] = 10
Counter cleared
by CCRA
Counter Reset when
TnON returns high
CCRA
Pause Resume
CCRP
Counter Stop if
TnON bit low
Time
TnON
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0)
PWM Duty Cycle
set by CCRP
PWM Period
set by CCRA
PWM resumes
operation
Output controlled by
Output Inverts
other pin-shared function
when TnPOL = 1
PWM Mode – TnDPX=1
Note: 1. Here TnDPX=1 - Counter cleared by CCRA
2. A counter clear sets PWM Period
3. The internal PWM function continues even when TnIO[1:0]=00 or 01
4. The TnCCLR bit has no influence on PWM operation
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Small Package A/D Flash 8-bit MCU
Standard Type TM – STM
The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/Event
Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can drive one
external output pin.
Note: TPn_1 (n=2) pin is not connected to the external pin.
Standard Type TM Block Diagram (n=2)
Standard TM Operation
At its core is a 16-bit count-up counter which is driven by a user selectable internal clock source.
There are also two internal comparators with the names, Comparator A and Comparator P. These
comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is 8-bit
wide whose value is compared with the highest 8 bits in the counter while the CCRA is the sixteen
bits and therefore compares with all counter bits.
The only way of changing the value of the 16-bit counter using the application program, is to
clear the counter by changing the T2ON bit from low to high. The counter will also be cleared
automatically by a counter overflow or a compare match with one of its associated comparators.
When these conditions occur, a TM interrupt signal will also usually be generated. The Standard
Type TM can operate in a number of different operational modes, can be driven by different clock
sources and can also control an output pin. All operating setup conditions are selected using relevant
internal registers.
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Small Package A/D Flash 8-bit MCU
Standard Type TM Register Description
Overall operation of the Standard TM is controlled using series of registers. A read only register
pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store
the internal 16-bit CCRA value. The remaining two registers are control registers which setup the
different operating and control modes as well as eight CCRP bits.
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TM2C0
T2PAU
T2CK2
T2CK1
T2CK0
T2ON
—
—
—
TM2C1
T2M1
T2M0
T2IO1
T2IO0
T2OC
T2POL
T2DPX
T2CCLR
TM2DL
D7
D6
D5
D4
D3
D2
D1
D0
TM2DH
D15
D14
D13
D12
D11
D10
D9
D8
TM2AL
D7
D6
D5
D4
D3
D2
D1
D0
TM2AH
D15
D14
D13
D12
D11
D10
D9
D8
TM2RP
D7
D6
D5
D4
D3
D2
D1
D0
16-bit Standard TM Register List
TM2C0 Register
Bit
7
6
5
4
3
2
1
0
Name
T2PAU
T2CK2
T2CK1
T2CK0
T2ON
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
POR
0
0
0
0
0
—
—
—
Bit 7T2PAU: TM2 Counter Pause Control
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the TM will remain powered up
and continue to consume power. The counter will retain its residual value when this bit
changes from low to high and resume counting from this value when the bit changes
to a low value again.
Bit 6~4T2CK2~T2CK0: Select TM2 Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fTBC
101: Reserved
110: Reserved
111: Reserved
These three bits are used to select the clock source for the TM. Selecting the Reserved
clock input will effectively disable the internal counter. The clock source fSYS is the
system clock, while fH and fTBC are other internal clocks, the details of which can be
found in the oscillator section.
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Bit 3T2ON: TM2 Counter On/Off Control
0: Off
1: On
This bit controls the overall on/off function of the TM. Setting the bit high enables the
counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the
counter from counting and turn off the TM which will reduce its power consumption.
When the bit changes state from low to high the internal counter value will be reset to
zero, however when the bit changes from high to low, the internal counter will retain
its residual value until the bit returns high again.
If the TM is in the Compare Match Output Mode then the TM output pin will be reset
to its initial condition, as specified by the T2OC bit, when the T2ON bit changes from
low to high.
Bit 2~0
Unimplemented, read as "0"
TM2C1 Register
Bit
7
6
5
4
3
2
1
0
Name
T2M1
T2M0
T2IO1
T2IO0
T2OC
T2POL
T2DPX
T2CCLR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6T2M1~T2M0: Select TM2 Operating Mode
00: Compare Match Output Mode
01: Capture Input Mode
10: PWM Mode or Single Pulse Output Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the TM. To ensure reliable operation
the TM should be switched off before any changes are made to the bits. In the Timer/
Counter Mode, the TM output pin control must be disabled.
Bit 5~4T2IO1~T2IO0: Select TM2 output function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Mode/Single Pulse Output Mode
00: PWM output inactive state
01: PWM output active state
10: PWM output
11: Single pulse output
Capture Input Mode
00: Input capture at rising edge of TP2_0, TP2_1
01: Input capture at falling edge of TP2_0, TP2_1
10: Input capture at falling/rising edge of TP2_0, TP2_1
11: Input capture disabled
Timer/counter Mode
Unused
These two bits are used to determine how the TM output pin changes state when a
certain condition is reached. The function that these bits select depends upon in which
mode the TM is running.
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Small Package A/D Flash 8-bit MCU
In the Compare Match Output Mode, the T2IO1~T2IO0 bits determine how the TM
output pin changes state when a compare match occurs from the Comparator A. The
TM output pin can be setup to switch high, switch low or to toggle its present state
when a compare match occurs from the Comparator A. When the T2IO1~T2IO0 bits
are both zero, then no change will take place on the output. The initial value of the TM
output pin should be setup using the T2OC bit. Note that the output level requested by
the T2IO1~T2IO0 bits must be different from the initial value setup using the T2OC
bit otherwise no change will occur on the TM output pin when a compare match
occurs. After the TM output pin changes state it can be reset to its initial level by
changing the level of the T2ON bit from low to high.
In the PWM Mode, the T2IO1 and T2IO0 bits determine how the TM output pin
changes state when a certain compare match condition occurs. The PWM output
function is modified by changing these two bits. It is necessary to change the values
of the T2IO1 and T2IO0 bits only after the TM has been switched off. Unpredictable
PWM outputs will occur if the T2IO1 and T2IO0 bits are changed when the TM is
running.
Bit 3T2OC: TM2 Output control bit
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Mode/Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the TM output pin. Its operation depends upon
whether TM is being used in the Compare Match Output Mode or in the PWM Mode/
Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In
the Compare Match Output Mode it determines the logic level of the TM output pin
before a compare match occurs. In the PWM Mode it determines if the PWM signal is
active high or active low.
Bit 2T2POL: TM2 Output polarity Control
0: Non-invert
1: Invert
This bit controls the polarity of the TM output pin. When the bit is set high the TM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the
TM is in the Timer/Counter Mode.
Bit 1T2DPX: TM2 PWM period/duty Control
0: CCRP - period; CCRA - duty
1: CCRP - duty; CCRA - period
This bit, determines which of the CCRA and CCRP registers are used for period and
duty control of the PWM waveform.
Bit 0T2CCLR: Select TM2 Counter clear condition
0: TM Comparatror P match
1: TM Comparatror A match
This bit is used to select the method which clears the counter. Remember that the
Standard TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the T2CCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The T2CCLR bit is not
used in the PWM, Single Pulse or Input Capture Mode.
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TM2DL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0TM2DL: TM2 Counter Low Byte Register bit 7~bit 0
TM2 16-bit Counter bit 7~bit 0
TM2DH Register
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0TM2DH: TM2 Counter High Byte Register bit 7~bit 0
TM2 16-bit Counter bit 15~bit 8
TM2AL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0TM2AL: TM2 CCRA Low Byte Register bit 7~bit 0
TM2 16-bit CCRA bit 7~bit 0
TM2AH Register
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0TM2AH: TM2 CCRA High Byte Register bit 7~bit 0
TM2 16-bit CCRA bit 15~bit 8
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TM2RP Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0TM2RP: TM2 CCRP High Byte Register bit 7~bit 0
TM2 CCRP 8-bit register, compared with the TM2 Counter bit 15~bit 8. Comparator P
Match Period
0: 65536 TM2 clocks
1~255: 256 × (1~255) TM2 clocks
These eight bits are used to setup the value on the internal CCRP 8-bit register, which
are then compared with the internal counter’s highest eight bits. The result of this
comparison can be selected to clear the internal counter if the T2CCLR bit is set to
zero. Setting the T2CCLR bit to zero ensures that a compare match with the CCRP
values will reset the internal counter. As the CCRP bits are only compared with the
highest eight counter bits, the compare values exist in 256 clock cycle multiples.
Clearing all eight bits to zero is in effect allowing the counter to overflow at its
maximum value.
Standard Type TM Operating Modes
The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode,
PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The
operating mode is selected using the T2M1 and T2M0 bits in the TM2C1 register.
Compare Output Mode
To select this mode, bits T2M1 and T2M0 in the TM2C1 register, should be set to 00 respectively.
In this mode once the counter is enabled and running it can be cleared by three methods. These are
a counter overflow, a compare match from Comparator A and a compare match from Comparator P.
When the T2CCLR bit is low, there are two ways in which the counter can be cleared. One is when
a compare match from Comparator P, the other is when the CCRP bits are all zero which allows
the counter to overflow. Here both T2AF and T2PF interrupt request flags for Comparator A and
Comparator P respectively, will both be generated.
If the T2CCLR bit in the TM2C1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the T2AF interrupt request flag will be
generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when
T2CCLR is high no T2PF interrupt request flag will be generated. In the Compare Match Output
Mode, the CCRA can not be set to “0”.
As the name of the mode suggests, after a comparison is made, the TM output pin, will change
state. The TM output pin condition however only changes state when a T2AF interrupt request flag
is generated after a compare match occurs from Comparator A. The T2PF interrupt request flag,
generated from a compare match occurs from Comparator P, will have no effect on the TM output
pin. The way in which the TM output pin changes state are determined by the condition of the
T2IO1 and T2IO0 bits in the TM2C1 register. The TM output pin can be selected using the T2IO1
and T2IO0 bits to go high, to go low or to toggle from its present condition when a compare match
occurs from Comparator A. The initial condition of the TM output pin, which is setup after the
T2ON bit changes from low to high, is setup using the T2OC bit. Note that if the T2IO1 and T2IO0
bits are zero then no pin change will take place.
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Counter Value
CCRP = 0
TnCCLR = 0; TnM[1:0] = 00
Counter
overflow
0xFFFF
CCRP > 0
Counter cleared by CCRP value
CCRP > 0
CCRP
Pause
Resume
CCRA
Stop
Counter
Reset
Time
TnON
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TM O/P Pin
Output Pin set
to Initial Level
Low if TnOC = 0
Output Toggle
with TnAF flag
Now TnIO1, TnIO0 = 10
Active High Output
Select
Output not affected by
TnAF flag. Remains High
until reset by TnON bit
Here TnIO1, TnIO0 = 11
Toggle Output Select
Output inverts
when TnPOL is high
Output Pin
Reset to initial value
Output controlled
by other pin-shared function
Compare Match Output Mode – TnCCLR=0
Note: 1. With TnCCLR=0 a Comparator P match will clear the counter
2. The TM output pin controlled only by the TnAF flag
3. The output pin reset to initial state by a TnON bit rising edge
4. n=2
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TnCCLR = 1; TnM[1:0] = 00
Counter Value
CCRA = 0
Counter overflows
CCRA > 0 Counter cleared by CCRA value
0xFFFF
CCRA = 0
CCRA
Pause
Resume
Stop
CCRP
Counter
Reset
Time
TnON
TnPAU
TnPOL
No TnAF flag
generated on
CCRA overflow
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TM O/P Pin
Output does
not change
TnPF not
generated
Output Pin set
to Initial Level
Low if TnOC = 0
Output not affected by
TnAF flag remains High
until reset by TnON bit
Output Toggle
with TnAF flag
Now TnIO1, TnIO0 = 10
Active High Output
Select
Output controlled by
other pin-shared function
Output inverts
when TnPOL is high
Output Pin
Reset to initial value
Here TnIO1, TnIO0 = 11
Toggle Output Select
Compare Match Output Mode – TnCCLR=1
Note: 1. With TnCCLR=1 a Comparator A match will clear the counter
2. The TM output pin controlled only by the TnAF flag
3. The output pin reset to initial state by a TnON rising edge
4. The TnPF flags is not generated when TnCCLR=1
5. n=2
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Timer/Counter Mode
To select this mode, bits T2M1 and T2M0 in the TM2C1 register should be set to 11 respectively.
The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode
generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output
pin is not used. Therefore the above description and Timing Diagrams for the Compare Match
Output Mode can be used to understand its function. As the TM output pin is not used in this mode,
the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode
To select this mode, bits T2M1 and T2M0 in the TM2C1 register should be set to 10 respectively
and also the T2IO1 and T2IO0 bits should be set to 10 respectively. The PWM function within
the TM is useful for applications which require functions such as motor control, heating control,
illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the
TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS
values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM mode, the T2CCLR bit has no effect as the PWM
period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register
is used to clear the internal counter and thus control the PWM waveform frequency, while the other
one is used to control the duty cycle. Which register is used to control either frequency or duty cycle
is determined using the T2DPX bit in the TM2C1 register.
The PWM waveform frequency and duty cycle can therefore be controlled by the values in the
CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be
generated when a compare match occurs from either Comparator A or Comparator P. The T2OC bit
In the TM2C1 register is used to select the required polarity of the PWM waveform while the two
T2IO1 and T2IO0 bits are used to enable the PWM output or to force the TM output pin to a fixed
high or low level. The T2POL bit is used to reverse the polarity of the PWM output waveform.
16-bit STM, PWM Mode, Edge-aligned Mode, T2DPX=0
CCRP
1~255
0
Period
CCRP×256
65536
Duty
CCRA
If fSYS=16MHz, TM clock source is fSYS/4, CCRP=2 and CCRA=128,
The STM PWM output frequency=(fSYS/4)/512=fSYS/2048=7.8125kHz, duty=128/512=25%.
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
16-bit STM, PWM Mode, Edge-aligned Mode, T2DPX=1
CCRP
1~255
Period
Duty
0
CCRA
CCRP×256
65536
The PWM output period is determined by the CCRA register value together with the TM clock
while the PWM duty cycle is defined by the (CCRP×256) except when the CCRP value is equal to 0.
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Counter Value
TnDPX = 0; TnM [1:0] = 10
Counter cleared
by CCRP
Counter Reset when
TnON returns high
CCRP
Pause Resume
CCRA
Counter Stop if
TnON bit low
Time
TnON
TnPAU
TnPOL
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0)
PWM Duty Cycle
set by CCRA
PWM Period
set by CCRP
PWM resumes
operation
Output controlled by
Output Inverts
other pin-shared function
when TnPOL = 1
PWM Mode – TnDPX=0
Note: 1. Here TnDPX=0 - Counter cleared by CCRP
2. A counter clear sets PWM Period
3. The internal PWM function continues running even when TnIO[1:0]=00 or 01
4. The TnCCLR bit has no influence on PWM operation
5. n=2
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Counter Value
TnDPX = 1; TnM [1:0] = 10
Counter cleared
by CCRA
Counter Reset when
TnON returns high
CCRA
Pause Resume
CCRP
Counter Stop if
TnON bit low
Time
TnON
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0)
PWM Duty Cycle
set by CCRP
PWM Period
set by CCRA
PWM resumes
operation
Output controlled by
Output Inverts
other pin-shared function
when TnPOL = 1
PWM Mode – TnDPX=1
Note: 1. Here TnDPX=1 - Counter cleared by CCRA
2. A counter clear sets PWM Period
3. The internal PWM function continues even when TnIO[1:0]=00 or 01
4. The TnCCLR bit has no influence on PWM operation
5. n=2
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Single Pulse Mode
To select this mode, bits T2M1 and T2M0 in the TM2C1 register should be set to 10 respectively
and also the T2IO1 and T2IO0 bits should be set to 11 respectively. The Single Pulse Output Mode,
as the name suggests, will generate a single shot pulse on the TM output pin.
The trigger for the pulse output leading edge is a low to high transition of the T2ON bit, which can
be implemented using the application program. When the T2ON bit transitions to a high level, the
counter will start running and the pulse leading edge will be generated. The T2ON bit should remain
high when the pulse is in its active state. The generated pulse trailing edge will be generated when
the T2ON bit is cleared to zero, which can be implemented using the application program or when a
compare match occurs from Comparator A.
Single Pulse Generation (n=2)
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Single Pulse Mode
Note: 1. Counter stopped by CCRA match
2. CCRP is not used
3. The pulse is triggered by setting the TnON bit high
4. In the Single Pulse Mode, TnIO [1:0] must be set to “11” and can not be changed.
5. n=2
However a compare match from Comparator A will also automatically clear the T2ON bit and thus
generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control
the pulse width. A compare match from Comparator A will also generate a TM interrupt. The counter
can only be reset back to zero when the T2ON bit changes from low to high when the counter
restarts. In the Single Pulse Mode CCRP is not used. The T2CCLR and T2DPX bits are not used in
this Mode.
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Capture Input Mode
To select this mode bits T2M1 and T2M0 in the TM2C1 register should be set to 01 respectively.
This mode enables external signals to capture and store the present value of the internal counter
and can therefore be used for applications such as pulse width measurements. The external signal is
supplied on the TP2_0 or TP2_1 pin, whose active edge can be either a rising edge, a falling edge or
both rising and falling edges; the active edge transition type is selected using the T2IO1 and T2IO0
bits in the TM2C1 register. The counter is started when the T2ON bit changes from low to high
which is initiated using the application program.
When the required edge transition appears on the TP2_0 or TP2_1 pin the present value in the
counter will be latched into the CCRA registers and a TM interrupt generated. Irrespective of what
events occur on the TP2_0 or TP2_1 pin the counter will continue to free run until the T2ON bit
changes from high to low. When a CCRP compare match occurs the counter will reset back to zero;
in this way the CCRP value can be used to control the maximum counter value. When a CCRP
compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the
number of overflow interrupt signals from the CCRP can be a useful method in measuring long
pulse widths. The T2IO1 and T2IO0 bits can select the active trigger edge on the TP2_0 or TP2_1
pin to be a rising edge, falling edge or both edge types. If the T2IO1 and T2IO0 bits are both set
high, then no capture operation will take place irrespective of what happens on the TP2_0 or TP2_1
pin, however it must be noted that the counter will continue to run.
As the TP2_0 pin is pin shared with other functions, care must be taken if the TM is in the Input
Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may
cause an input capture operation to be executed. The T2CCLR and T2DPX bits are not used in this
Mode.
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Counter Value
TnM [1:0] = 01
Counter cleared
by CCRP
Counter Counter
Stop
Reset
CCRP
YY
Pause
Resume
XX
Time
TnON
TnPAU
TM capture
pin TPn_x
Active
edge
Active
edge
Active edge
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
CCRA
Value
TnIO [1:0]
Value
XX
00 – Rising edge
YY
01 – Falling edge
XX
10 – Both edges
YY
11 – Disable Capture
Capture Input Mode
Note: 1. TnM[1:0]=01 and active edge set by the TnIO[1:0] bits
2. A TM Capture input pin active edge transfers the counter value to CCRA
3. The TnCCLR bit is not used
4. No output function - TnOC and TnPOL bits are not used
5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero
6. n=2
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Analog to Digital Converter
The need to interface to real world analog signals is a common requirement for many electronic
systems. However, to properly process these signals by a microcontroller, they must first be
converted into digital signals by A/D converters. By integrating the A/D conversion electronic
circuitry into the microcontroller, the need for external components is reduced significantly with the
corresponding follow-on benefits of lower costs and reduced component space requirements.
A/D Overview
The device contains a multi-channel analog to digital converter which can directly interface to
external analog signals, such as that from sensors or other control signals and convert these signals
directly into a 12-bit digital value.
Input Channels
A/D Channel Select Bits
Input Pins
5
ACS4, ACS2~ACS0
AN0~AN4
The accompanying block diagram shows the overall internal structure of the A/D converter, together
with its associated registers.
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A/D Converter Structure
A/D Converter Register Description
Overall operation of the A/D converter is controlled using five registers. A read only register pair
exists to store the ADC data 12-bit value. The remaining three registers are control registers which
setup the operating and control function of the A/D converter.
Name
Bit
7
6
5
4
3
2
1
0
ADRL(ADRFS=0)
D3
D2
D1
D0
—
—
—
—
ADRL(ADRFS=1)
D7
D6
D5
D4
D3
D2
D1
D0
ADRH(ADRFS=0)
D11
D10
D9
D8
D7
D6
D5
D4
ADRH(ADRFS=1)
—
—
—
—
D11
D10
D9
D8
ADCR0
START
EOCB
ADOFF
ADRFS
—
ACS2
ACS1
ACS0
ADCR1
ACS4
VBGEN
—
VREFS
—
ADCK2
ADCK1
ADCK0
—
—
—
ACE4
ACE3
ACE2
ACE1
ACE0
ACER
A/D Converter Register List
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Small Package A/D Flash 8-bit MCU
A/D Converter Data Registers – ADRL, ADRH
As the device contains an internal 12-bit A/D converter, it requires two data registers to store the
converted value. These are a high byte register, known as ADRH, and a low byte register, known
as ADRL. After the conversion process takes place, these registers can be directly read by the
microcontroller to obtain the digitised conversion value. As only 12 bits of the 16-bit register space
is utilised, the format in which the data is stored is controlled by the ADRFS bit in the ADCR0
register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits. Any
unused bits will be read as zero.
ADRFS
0
1
ADRH
7
6
D11 D10
0
0
ADRL
5
4
3
2
1
0
7
6
5
4
3
2
1
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A/D Data Registers
A/D Converter Control Registers – ADCR0, ADCR1, ACER
To control the function and operation of the A/D converter, three control registers known as ADCR0,
ADCR1, ACER are provided. These 8-bit registers define functions such as the selection of which
analog channel is connected to the internal A/D converter, the digitised data format, the A/D clock
source as well as controlling the start function and monitoring the A/D converter end of conversion
status. The ACS2~ACS0 bits in the ADCR0 register and ACS4 bit is the ADCR1 register define
the ADC input channel number. As the device contains only one actual analog to digital converter
hardware circuit, each of the individual 5 analog inputs must be routed to the converter. It is the
function of the ACS4, ACS2~ACS0 bits to determine which analog channel input signals or internal
1.25V is actually connected to the internal A/D converter.
The ACER control register contains the ACE4~ACE0 bits which determine which pins on Port A
are used as analog inputs for the A/D converter input and which pins are not to be used as the A/D
converter input. Setting the corresponding bit high will select the A/D input function, clearing the
bit to zero will select either the I/O or other pin-shared function. When the pin is selected to be an
A/D input, its original function whether it is an I/O or other pin-shared function will be removed. In
addition, any internal pull-high resistors connected to these pins will be automatically removed if the
pin is selected to be an A/D input.
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ADCR0 Register
Bit
7
6
5
4
3
2
1
0
Name
START
EOCB
ADOFF
ADRFS
—
ACS2
ACS1
ACS0
R/W
R/W
R
R/W
R/W
—
R/W
R/W
R/W
POR
0
1
1
0
—
0
0
0
Bit 7START: Start the A/D conversion
0→1→0: start
0→1: reset the A/D converter and set EOCB to “1”
This bit is used to initiate an A/D conversion process. The bit is normally low but if set
high and then cleared low again, the A/D converter will initiate a conversion process.
When the bit is set high the A/D converter will be reset.
Bit 6EOCB: End of A/D conversion flag
0: A/D conversion ended
1: A/D conversion in progress
This read only flag is used to indicate when an A/D conversion process has completed.
When the conversion process is running the bit will be high.
Bit 5ADOFF : ADC module power on/off control bit
0: ADC module power on
1: ADC module power off
This bit controls the power to the A/D internal function. This bit should be cleared
to zero to enable the A/D converter. If the bit is set high then the A/D converter will
be switched off reducing the device power consumption. As the A/D converter will
consume a limited amount of power, even when not executing a conversion, this may
be an important consideration in power sensitive battery powered applications.
Note: 1. it is recommended to set ADOFF=1 before entering IDLE/SLEEP Mode for
saving power.
2. ADOFF=1 will power down the ADC module.
Bit 4ADRFS: ADC Data Format Control
0: ADC Data MSB is ADRH bit 7, LSB is ADRL bit 4
1: ADC Data MSB is ADRH bit 3, LSB is ADRL bit 0
This bit controls the format of the 12-bit converted A/D value in the two A/D data
registers. Details are provided in the A/D data register section.
Bit 3
Unimplemented, read as “0”
Bit 2~0ACS2~ACS0: Select A/D channel (when ACS4 is “0”)
000: AN0
001: AN1
010: AN2
011: AN3
Others: AN4
These are the A/D channel select control bits. As there is only one internal hardware
A/D converter each of the eight A/D inputs must be routed to the internal converter
using these bits. If bit ACS4 in the ADCR1 register is set high then the internal 1.25V
will be routed to the A/D Converter.
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ADCR1 Register
Bit
7
6
5
4
3
2
1
0
Name
ACS4
VBGEN
—
VREFS
—
ADCK2
ADCK1
ADCK0
R/W
R/W
R/W
—
R/W
—
R/W
R/W
R/W
POR
0
0
—
0
—
0
0
0
Bit 7ACS4: Selecte Internal 1.25V as ADC input Control
0: Disable
1: Enable
This bit enables 1.25V to be connected to the A/D converter. The VBGEN bit must
first have been set to enable the bandgap circuit 1.25V voltage to be used by the A/D
converter. When the ACS4 bit is set high, the bandgap 1.25V voltage will be routed to
the A/D converter and the other A/D input channels disconnected.
Bit 6VBGEN: Internal 1.25V Control
0: Disable
1: Enable
This bit controls the internal Bandgap circuit on/off function to the A/D converter.
When the bit is set high the bandgap 1.25V voltage can be used by the A/D converter.
If 1.25V is not used by the A/D converter and the LVR function is disabled then the
bandgap reference circuit will be automatically switched off to conserve power. When
1.25V is switched on for use by the A/D converter, a time tBG should be allowed for
the bandgap circuit to stabilise before implementing an A/D conversion.
Bit 5
Unimplemented, read as “0”
Bit 4VREFS: Selecte ADC reference voltage
0: Internal ADC power
1: VREF pin
This bit is used to select the reference voltage for the A/D converter. If the bit is high
then the A/D converter reference voltage is supplied on the external VREF pin. If the
pin is low then the internal reference is used which is taken from the power supply pin
VDD. When the A/D converter reference voltage is supplied on the external VREF pin
which is pin-shared with other functions, all of the pin-shared functions except VREF
on this pin are disabled.
Bit 3
Unimplemented, read as “0”
Bit 2~0ADCK2~ADCK0: Select ADC clock source
000: fSYS
001: fSYS/2
010: fSYS/4
011: fSYS/8
100: fSYS/16
101: fSYS/32
110: fSYS/64
111: Undefined
These three bits are used to select the clock source for the A/D converter.
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ACER Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
ACE4
ACE3
ACE2
ACE1
ACE0
R/W
—
—
—
R/W
R/W
R/W
R/W
R/W
POR
—
—
—
1
1
1
1
1
Bit 7~5
Unimplemented, read as “0”
Bit 4ACE4: Define PA5 is A/D input or not
0: Not A/D input
1: A/D input, AN4
Bit 3ACE3: Define PA3 is A/D input or not
0: Not A/D input
1: A/D input, AN3
Bit 2ACE2: Define PA2 is A/D input or not
0: Not A/D input
1: A/D input, AN2
Bit 1ACE1: Define PA1 is A/D input or not
0: Not A/D input
1: A/D input, AN1
Bit 0ACE0: Define PA0 is A/D input or not
0: Not A/D input
1: A/D input, AN0
A/D Operation
The START bit in the ADCR0 register is used to start and reset the A/D converter. When the
microcontroller sets this bit from low to high and then low again, an analog to digital conversion
cycle will be initiated. When the START bit is brought from low to high but not low again, the
EOCB bit in the ADCR0 register will be set high and the analog to digital converter will be reset.
It is the START bit that is used to control the overall start operation of the internal analog to digital
converter.
The EOCB bit in the ADCR0 register is used to indicate when the analog to digital conversion
process is complete. This bit will be automatically set to “0” by the microcontroller after a
conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set
in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt
signal will be generated. This A/D internal interrupt signal will direct the program flow to the
associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled,
the microcontroller can be used to poll the EOCB bit in the ADCR0 register to check whether it has
been cleared as an alternative method of detecting the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen
to be either fSYS or a subdivided version of fSYS. The division ratio value is determined by the
ADCK2~ADCK0 bits in the ADCR1 register.
Although the A/D clock source is determined by the system clock fSYS, and by bits ADCK2~ADCK0,
there are some limitations on the maximum A/D clock source speed that can be selected. As the
recommended range of permissible A/D clock period, tADCK, is from 0.5μs to 10μs, care must be
taken for system clock frequencies. For example, if the system clock operates at a frequency of
4MHz, the ADCK2~ADCK0 bits should not be set to 000B or 110B. Doing so will give A/D clock
periods that are less than the minimum A/D clock period or greater than the maximum A/D clock
period which may result in inaccurate A/D conversion values.
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Refer to the following table for examples, where values marked with an asterisk * show where,
depending upon the device, special care must be taken, as the values may be less than the specified
minimum A/D Clock Period.
A/D Clock Period (tADCK)
ADCK2,
ADCK1,
ADCK0
=000
(fSYS)
ADCK2,
ADCK1,
ADCK0
=001
(fSYS/2)
ADCK2,
ADCK1,
ADCK0
=010
(fSYS/4)
ADCK2,
ADCK1,
ADCK0
=011
(fSYS/8)
ADCK2,
ADCK1,
ADCK0
=100
(fSYS/16)
ADCK2,
ADCK1,
ADCK0
=101
(fSYS/32)
ADCK2,
ADCK1,
ADCK0
=110
(fSYS/64)
ADCK2,
ADCK1,
ADCK0
=111
1MHz
1μs
2μs
4μs
8μs
16μs*
32μs*
64μs*
Undefined
2MHz
500ns
1μs
2μs
4μs
8μs
16μs*
32μs*
Undefined
4MHz
250ns*
500ns
1μs
2μs
4μs
8μs
16μs*
Undefined
8MHz
125ns*
250ns*
500ns
1μs
2μs
4μs
8μs
Undefined
12MHz
83ns*
167ns*
333ns*
667ns
1.33μs
2.67μs
5.33μs
Undefined
fSYS
A/D Clock Period Examples
Controlling the power on/off function of the A/D converter circuitry is implemented using the
ADOFF bit in the ADCR0 register. This bit must be zero to power on the A/D converter. When the
ADOFF bit is cleared to zero to power on the A/D converter internal circuitry a certain delay, as
indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if no
pins are selected for use as A/D inputs by clearing the ACE4~ACE0 bits in the ACER registers, if
the ADOFF bit is zero then some power will still be consumed. In power conscious applications it
is therefore recommended that the ADOFF is set high to reduce power consumption when the A/D
converter function is not being used.
The reference voltage supply to the A/D Converter can be supplied from either the positive power
supply pin, VDD, or from an external reference sources supplied on pin VREF. The desired selection
is made using the VREFS bit. As the VREF pin is pin-shared with other functions, when the VREFS
bit is set high, the VREF pin function will be selected and the other pin functions will be disabled
automatically.
A/D Input Pins
All of the A/D analog input pins are pin-shared with the I/O pins on Port A as well as other
functions. The ACE4~ACE0 bits in the ACER registers, determine whether the input pins are setup
as A/D converter analog inputs or whether they have other functions. If the ACE4~ACE0 bits for its
corresponding pin is set high then the pin will be setup to be an A/D converter input and the original
pin functions disabled. In this way, pins can be changed under program control to change their
function between A/D inputs and other functions. All pull-high resistors, which are setup through
register programming, will be automatically disconnected if the pins are setup as A/D inputs. Note
that it is not necessary to first setup the A/D pin as an input in the PAC port control register to enable
the A/D input as when the ACE4~ACE0 bits enable an A/D input, the status of the port control
register will be overridden.
The A/D converter has its own reference voltage pin, VREF, however the reference voltage can
also be supplied from the power supply pin, a choice which is made through the VREFS bit in the
ADCR1 register. The analog input values must not be allowed to exceed the value of VREF.
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A/D Input Structure
Summary of A/D Conversion Steps
The following summarises the individual steps that should be executed in order to implement an A/D
conversion process.
• Step 1
Select the required A/D conversion clock by correctly programming bits ADCK2~ADCK0 in the
ADCR1 register.
• Step 2
Enable the A/D by clearing the ADOFF bit in the ADCR0 register to zero.
• Step 3
Select which channel is to be connected to the internal A/D converter by correctly programming
the ACS4, ACS2~ACS0 bits which are also contained in the ADCR1 and ADCR0 register.
• Step 4
Select which pins are to be used as A/D inputs and configure them by correctly programming the
ACE4~ACE0 bits in the ACER register.
• Step 5
If the interrupts are to be used, the interrupt control registers must be correctly configured to
ensure the A/D converter interrupt function is active. The master interrupt control bit, EMI, and
the A/D converter interrupt bit, ADE, must both be set high to do this.
• Step 6
The analog to digital conversion process can now be initialised by setting the START bit in
the ADCR0 register from low to high and then low again. Note that this bit should have been
originally cleared to zero.
• Step 7
To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR0
register can be polled. The conversion process is complete when this bit goes low. When this
occurs the A/D data registers ADRL and ADRH can be read to obtain the conversion value. As an
alternative method, if the interrupts are enabled and the stack is not full, the program can wait for
an A/D interrupt to occur.
Note: When checking for the end of the conversion process, if the method of polling the EOCB bit
in the ADCR0 register is used, the interrupt enable step above can be omitted.
The accompanying diagram shows graphically the various stages involved in an analog to digital
conversion process and its associated timing. After an A/D conversion process has been initiated
by the application program, the microcontroller internal hardware will begin to carry out the
conversion, during which time the program can continue with other functions. The time taken for the
A/D conversion is 16 tADCK where tADCK is equal to the A/D clock period.
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‚ ‚
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                  ­      A/D Conversion Timing
Programming Considerations
During microcontroller operations where the A/D converter is not being used, the A/D internal
circuitry can be switched off to reduce power consumption, by setting bit ADOFF high in the
ADCR0 register. When this happens, the internal A/D converter circuits will not consume power
irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are
used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then
this may lead to some increase in power consumption.
A/D Transfer Function
As the device contains a 12-bit A/D converter, its full-scale converted digitised value is equal to
FFFH. Since the full-scale analog input value is equal to the VDD or VREF voltage, this gives a single
bit analog input value of VDD or VREF divided by 4096.
1 LSB=(VDD or VREF)/4096
The A/D Converter input voltage value can be calculated using the following equation:
A/D input voltage=A/D output digital value × (VDD or VREF)/4096
The diagram shows the ideal transfer function between the analog input value and the digitised
output value for the A/D converter. Except for the digitised zero value, the subsequent digitised
values will change at a point 0.5 LSB below where they would change without the offset, and the
last full scale digitised value will change at a point 1.5 LSB below the VDD or VREF level.
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    
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      Ideal A/D Transfer Function
A/D Programming Examples
The following two programming examples illustrate how to setup and implement an A/D conversion.
In the first example, the method of polling the EOCB bit in the ADCR0 register is used to detect
when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to
determine when the conversion is complete.
Example: using an EOCB polling method to detect the end of conversion
clr
ADE;
mova,03H
mov ADCR1,a ;
clr ADOFF
mov a,0Fh ;
mov ACER,a
mova,01h
mov ADCR0,a ;
:
start_conversion:
clr START ;
set START ;
clr START ;
polling_EOC:
sz EOCB ;
jmp polling_EOC ;
mov a,ADRL ;
mov ADRL_buffer,a ;
mov a,ADRH ;
mov ADRH_buffer,a ;
:
:
jmp start_conversion ;
Rev. 1.00
disable ADC interrupt
select fSYS/8 as A/D clock and switch off 1.25V
setup ACER to configure pins AN0~AN3
enable and connect AN0 channel to A/D converter
high pulse on start bit to initiate conversion
reset A/D
start A/D
poll the ADCR0 register EOCB bit to detect end of A/D conversion
continue polling
read low byte conversion result value
save result to user defined register
read high byte conversion result value
save result to user defined register
start next A/D conversion
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Example: using the interrupt method to detect the end of conversion
clr ADE ;
mova,03H
mov ADCR1,a ;
Clr ADOFF
mova,0Fh;
mov ACER,a
mova,01h
mov ADCR0,a;
Start_conversion:
clr START ;
set START ;
clr START ;
clrADF
;
set ADE;
set EMI;
:
:
;
ADC_ISR:
mov acc_stack,a ;
mov a,STATUS
mov status_stack,a ;
:
:
mov a,ADRL ;
mov adrl_buffer,a ;
mov a,ADRH ;
mov adrh_buffer,a ;
:
:
EXIT_INT_ISR:
mov a,status_stack
mov STATUS,a ;
mov a,acc_stack ;
reti
Rev. 1.00
disable ADC interrupt
select fSYS/8 as A/D clock and switch off 1.25V
setup ACER to configure pins AN0~AN3
enable and connect AN0 channel to A/D converter
high pulse on START bit to initiate conversion
reset A/D
start A/D
clear ADC interrupt request flag
enable ADC interrupt
enable global interrupt
ADC interrupt service routine
save ACC to user defined memory
save STATUS to user defined memory
read
save
read
save
low byte conversion result value
result to user defined register
high byte conversion result value
result to user defined register
restore STATUS from user defined memory
restore ACC from user defined memory
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Comparator
One independent analog comparator is contained within the device. This function offers flexibility
via its register controlled features such as power-down, polarity select, hysteresis etc. In sharing its
pins with normal I/O pins the comparator does not waste precious I/O pins if there functions are
otherwise unused.
Comparator Operation
The device contains one comparator which is used to compare two analog voltages and provide
an output based on their difference. Full control over the internal comparator is provided via the
control register, CPC. The comparator output is recorded via a bit in the control register, but can also
be transferred out onto a shared I/O pin. Additional comparator functions include, output polarity,
hysteresis functions and power down control.
Any pull-high resistors connected to the shared comparator input pins will be automatically
disconnected when the comparator is enabled. As the comparator inputs approach their switching
level, some spurious output signals may be generated on the comparator output due to the slow
rising or falling nature of the input signals. This can be minimised by selecting the hysteresis
function will apply a small amount of positive feedback to the comparator. Ideally the comparator
should switch at the point where the positive and negative inputs signals are at the same voltage
level, however, unavoidable input offsets introduce some uncertainties here. The hysteresis function,
if enabled, also increases the switching offset value.
Comparator Register
There is one register for overall comparator operation.
CPC Register
Bit
7
6
5
4
3
2
1
0
Name
CSEL
CEN
CPOL
COUT
COS
CINTE1
CINTE0
CHYEN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
0
0
0
0
0
0
1
Bit 7CSEL: Select Comparator pins or I/O pins
0: I/O pins select
1: Comparator input pins CP and CN selected
This is the Comparator pin or I/O pin select bit. If the bit is high the comparator will
be selected and the comparator input pins will be enabled. As a result, these two pins
will lose their I/O pin functions. Any pull-high configuration options associated with
the comparator shared pins will also be automatically disconnected.
Bit 6CEN: Comparator On/Off control
0: Off
1: On
This is the Comparator on/off control bit. If the bit is zero the comparator will be
switched off and no power consumed even if analog voltages are applied to its inputs.
For power sensitive applications this bit should be cleared to zero if the comparator is
not used or before the device enters the SLEEP or IDLE mode.
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Bit 5CPOL: Comparator output polarity
0: Output not inverted
1: Output inverted
This is the comparator polarity bit. If the bit is zero then the COUT bit will reflect
the non-inverted output condition of the comparator. If the bit is high the comparator
COUT bit will be inverted.
Bit 4COUT: Comparator output bit
CPOL=0
0: CP < CN
1: CP > CN
CPOL=1
0: CP > CN
1: CP < CN
This bit stores the comparator output bit. The polarity of the bit is determined by the
voltages on the comparator inputs and by the condition of the CPOL bit.
Bit 3COS: Comparator output path select
0: CX pin
1: Internal use
This is the comparator output path select control bit. If the bit is set to “0” and the
CSEL bit is “1” the comparator output is connected to an external CX pin. If the bit is
set to “1” or the CSEL bit is “0” the comparator output signal is only used internally
by the device allowing the shared comparator output pin to retain its normal I/O
operation.
Bit 2~1
CINTE1, CINTE0: Comparator Interrupt edge control
00: Rising edge
01: Falling edge
1x: Rising edge and falling edge
Bit 0CHYEN: Hysteresis Control
0: Off
1: On
This is the hysteresis control bit and if set high will apply a limited amount of
hysteresis to the comparator, as specified in the Comparator Electrical Characteristics
table. The positive feedback induced by hysteresis reduces the effect of spurious
switching near the comparator threshold.
Comparator Interrupt
The comparator possesses its own interrupt function. When the comparator changes state, its
relevant interrupt flag will be set, and if the corresponding interrupt enable bit is set, then a jump
to its relevant interrupt vector will be executed. Note that it is the changing state of the COUT bit
and not the output pin which generates an interrupt. If the microcontroller is in the SLEEP or IDLE
Mode and the comparator is enabled, then if the external input lines cause the comparator output bit
to change state, the resulting generated interrupt flag will also generate a wake-up. If it is required to
disable a wake-up from occurring, then the interrupt function should be disabled before entering the
SLEEP or IDLE Mode.
Programming Considerations
If the comparator is enabled, it will remain active when the microcontroller enters the SLEEP or
IDLE Mode, however as it will consume a certain amount of power, the user may wish to consider
disabling it before the SLEEP or IDLE Mode is entered.
As comparator pins are shared with normal I/O pins the I/O registers for these pins will be read as
zero (port control register is “1”) or read as port data register value (port control register is “0”) if
the comparator function is enabled.
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Interrupts
Interrupts are an important part of any microcontroller system. When an external event or an
internal function such as a Timer Module or an A/D converter requires microcontroller attention,
their corresponding interrupt will enforce a temporary suspension of the main program allowing the
microcontroller to direct attention to their respective needs. The device contains an external interrupt
and internal interrupts functions. The external interrupt is generated by the action of the external
INT pin, while the internal interrupts are generated by various internal functions such as the TMs,
Comparator, Time Base, EEPROM and the A/D converter.
Interrupt Registers
Overall interrupt control, which basically means the setting of request flags when certain
microcontroller conditions occur and the setting of interrupt enable bits by the application program,
is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the
accompanying table. The number of registers depends upon the device chosen but fall into three
categories. The first is the INTC0~INTC2 registers which setup the primary interrupts, the second
is the MFI0~MFI2 registers which setup the Multi-function interrupts. Finally there is an INTEG
register to setup the external interrupt trigger edge type.
Each register contains a number of enable bits to enable or disable individual registers as well as
interrupt flags to indicate the presence of an interrupt request. The naming convention of these
follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of
that interrupt followed by either an “E” for enable/disable bit or “F” for request flag.
Function
Enable Bit
Request Flag
Notes
—
Global
EMI
—
INT Pin
INTE
INTF
—
A/D Converter
ADE
ADF
—
Multi-function
MFnE
MFnF
Comparator
CPE
CPF
Time Base
TBnE
TBnF
EEPROM
TM
DEE
DEF
TnPE
TnPF
TnAE
TnAF
n=0~2
—
n=0 or 1
—
n=0~2
Interrupt Register Bit Naming Conventions
Interrupt Register Contents
Name
Rev. 1.00
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
INTS0
INTEG
—
—
—
—
—
—
INTS1
INTC0
—
MF0F
TB0F
INTF
MF0E
TB0E
INTE
EMI
INTC1
TB1F
ADF
DEF
MF1F
TB1E
ADE
DEE
MF1E
INTC2
—
—
MF2F
CPF
—
—
MF2E
CPE
MFI0
—
—
T0AF
T0PF
—
—
T0AE
T0PE
MFI1
—
—
T1AF
T1PF
—
—
T1AE
T1PE
MFI2
—
—
T2AF
T2PF
—
—
T2AE
T2PE
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INTEG Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
INTS1
INTS0
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2 Unimplemented, read as “0”
Bit 1~0
INTS1, INTS0: Defines INT interrupt active edge
00: Disabled Interrupt
01: Rising Edge Interrupt
10: Falling Edge Interrupt
11: Dual Edge Interrupt
INTC0 Register
Bit
7
6
5
4
3
2
1
0
Name
—
MF0F
TB0F
INTF
MF0E
TB0E
INTE
EMI
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit 7
Unimplemented, read as “0”
Bit 6MF0F: Multi-function 0 Interrupt Request Flag
0: No request
1: Interrupt request
Bit 5TB0F: Time Base 0 Interrupt Request Flag
0: No request
1: Interrupt request
Bit 4INTF: INT Interrupt Request Flag
0: No request
1: Interrupt request
Bit 3 MF0E: Multi-function 0 Interrupt Control
0: Disable
1: Enable
Bit 2TB0E: Time Base 0 Interrupt Control
0: Disable
1: Enable
Bit 1INTE: INT Interrupt Control
0: Disable
1: Enable
Bit 0EMI: Global Interrupt Control
0: Disable
1: Enable
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INTC1 Register
Bit
7
6
5
4
3
2
1
0
Name
TB1F
ADF
DEF
MF1F
TB1E
ADE
DEE
MF1E
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7TB1F : Time Base 1 Interrupt Request Flag
0: No request
1: Interrupt request
Bit 6ADF: A/D Converter Interrupt Request Flag
0: No request
1: Interrupt request
Bit 5DEF: Data EEPROM Interrupt Request Flag
0: No request
1: Interrupt request
Bit 4MF1F: Multi-function 1 Interrupt Request Flag
0: No request
1: Interrupt request
Bit 3 TB1E : Time Base 1 Interrupt Control
0: Disable
1: Enable
Bit 2ADE: A/D Converter Interrupt Control
0: Disable
1: Enable
Bit 1DEE: Data EEPROM Interrupt Control
0: Disable
1: Enable
Bit 0MF1E: Multi-function 1 Interrupt Control
0: Disable
1: Enable
INTC2 Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
MF2F
CPF
—
—
MF2E
CPE
R/W
—
—
R/W
R/W
—
—
R/W
R/W
POR
—
—
0
0
—
—
0
0
Bit 7~6
Unimplemented, read as “0”
Bit 5MF2F: Multi-function 2 Interrupt Request Flag
0: No request
1: Interrupt request
Bit 4CPF: Comparator Interrupt Request Flag
0: No request
1: Interrupt request
Bit 3~2 Unimplemented, read as “0”
Bit 1MF2E: Multi-function 2 Interrupt Control
0: Disable
1: Enable
Bit 0CPE: Comparator Interrupt Control
0: Disable
1: Enable
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MFI0 Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
T0AF
T0PF
—
—
T0AE
T0PE
R/W
—
—
R/W
R/W
—
—
R/W
R/W
POR
—
—
0
0
—
—
0
0
Bit 7~6
Unimplemented, read as “0”
Bit 5T0AF: TM0 Comparator A match interrupt request flag
0: No request
1: Interrupt request
Bit 4T0PF: TM0 Comparator P match interrupt request flag
0: No request
1: Interrupt request
Bit 3~2
Unimplemented, read as “0”
Bit 1T0AE: TM0 Comparator A match interrupt control
0: Disable
1: Enable
Bit 0T0PE: TM0 Comparator P match interrupt control
0: Disable
1: Enable
MFI1 Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
T1AF
T1PF
—
—
T1AE
T1PE
R/W
—
—
R/W
R/W
—
—
R/W
R/W
POR
—
—
0
0
—
—
0
0
Bit 7~6
Unimplemented, read as “0”
Bit 5T1AF: TM1 Comparator A match interrupt request flag
0: No request
1: Interrupt request
Bit 4T1PF: TM1 Comparator P match interrupt request flag
0: No request
1: Interrupt request
Bit 3~2 Unimplemented, read as “0”
Bit 1T1AE: TM1 Comparator A match interrupt control
0: Disable
1: Enable
Bit 0T1PE: TM1 Comparator P match interrupt control
0: Disable
1: Enable
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MFI2 Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
T2AF
T2PF
—
—
T2AE
T2PE
R/W
—
—
R/W
R/W
—
—
R/W
R/W
POR
—
—
0
0
—
—
0
0
Bit 7~6
Unimplemented, read as “0”
Bit 5T2AF: TM2 Comparator A match interrupt request flag
0: No request
1: Interrupt request
Bit 4T2PF: TM2 Comparator P match interrupt request flag
0: No request
1: Interrupt request
Bit 3~2
Unimplemented, read as “0”
Bit 1T2AE: TM2 Comparator A match interrupt control
0: Disable
1: Enable
Bit 0T2PE: TM2 Comparator P match interrupt control
0: Disable
1: Enable
Interrupt Operation
When the conditions for an interrupt event occur, such as a TM Comparator P or Comparator A
match or A/D conversion completion etc, the relevant interrupt request flag will be set. Whether
the request flag actually generates a program jump to the relevant interrupt vector is determined by
the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to
its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual
interrupt will not be generated and the program will not jump to the relevant interrupt vector. The
global interrupt enable bit, if cleared to zero, will disable all interrupts.
When an interrupt is generated, the Program Counter, which stores the address of the next instruction
to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a
new address which will be the value of the corresponding interrupt vector. The microcontroller will
then fetch its next instruction from this interrupt vector. The instruction at this vector will usually
be a “JMP” which will jump to another section of program which is known as the interrupt service
routine. Here is located the code to control the appropriate interrupt. The interrupt service routine
must be terminated with a “RETI”, which retrieves the original Program Counter address from
the stack and allows the microcontroller to continue with normal execution at the point where the
interrupt occurred.
The various interrupt enable bits, together with their associated request flags, are shown in the
accompanying diagrams with their order of priority. Some interrupt sources have their own
individual vector while others share the same multi-function interrupt vector. Once an interrupt
subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit,
EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring.
However, if other interrupt requests occur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be recorded.
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If an interrupt requires immediate servicing while the program is already in another interrupt service
routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack
is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until
the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from
becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that
is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or
IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set
before the device is in SLEEP or IDLE Mode.
Legend
EMI auto disabled in ISR
xxF Request Flag – no auto reset in ISR
xxF Request Flag – auto reset in ISR
Interrupt
Name
Request
Flags
Enable
Bits
Master
Enable
Vector
xxE Enable Bit
INT Pin
INTF
INTE
EMI
04H
Enable
Bits
Time Base 0 TB0F
TB0E
EMI
08H
M. Funct. 0
MF0F
MF0E
EMI
0CH
M. Funct. 1
MF1F
MF1E
EMI
10H
EEPROM
DEF
DEE
EMI
14H
A/D
ADF
ADE
EMI
18H
Time Base 1 TB1F
TB1E
EMI
1CH
Interrupt
Name
Request
Flags
TM0 P
T0PF
T0PE
TM0 A
T0AF
T0AE
TM1 P
T1PF
T1PE
TM1 A
T1AF
T1AE
TM2 P
T2PF
T2PE
TM2 A
T2AF
T2AE
Comparator
CPF
CPE
EMI
20H
M. Funct. 2
MF2F
MF2E
EMI
24H
Priority
High
Interrupts contained within
Multi-Function Interrupts
Low
Interrupt Structure
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External Interrupt
The external interrupt is controlled by signal transitions on the pins INT. An external interrupt
request will take place when the external interrupt request flag, INTF, is set, which will occur when
a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. To
allow the program to branch to the interrupt vector address, the global interrupt enable bit, EMI, and
the external interrupt enable bit, INTE, must first be set. Additionally the correct interrupt edge type
must be selected using the INTEG register to enable the external interrupt function and to choose
the trigger edge type. As the external interrupt pin is pin-shared with an I/O pin, it can only be
configured as external interrupt pin if its external interrupt enable bit in the corresponding interrupt
register has been set. The pin must also be setup as an input by setting the corresponding bit in the
port control register. When the interrupt is enabled, the stack is not full and the correct transition
type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take
place. When the interrupt is serviced, the external interrupt request flag, INTF, will be automatically
reset and the EMI bit will be automatically cleared to disable other interrupts. Note that the pull-high
resistor selection on the external interrupt pin will remain valid even if the pin is used as an external
interrupt input.
The INTEG register is used to select the type of active edge that will trigger the external interrupt.
A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt.
Note that the INTEG register can also be used to disable the external interrupt function.
Comparator Interrupt
The comparator interrupt is controlled by the internal comparator. A comparator interrupt request
will take place when the comparator interrupt request flag, CPF, is set, a situation that will occur
when the comparator output bit changes state. To allow the program to branch to its respective
interrupt vector address, the global interrupt enable bit, EMI, and comparator interrupt enable
bit, CPE, must first be set. When the interrupt is enabled, the stack is not full and the comparator
inputs generate a comparator output transition, a subroutine call to the comparator interrupt vector,
will take place. When the interrupt is serviced, the comparator interrupt request flag, will be
automatically reset and the EMI bit will be automatically cleared to disable other interrupts.
Multi-function Interrupt
Within this device there are up to three Multi-function interrupts. Unlike the other independent
interrupts, these interrupts have no independent source, but rather are formed from other existing
interrupt sources, namely the TM Interrupts.
A Multi-function interrupt request will take place when any of the Multi-function interrupt request
flags, MF0F~MF2F are set. The Multi-function interrupt flags will be set when any of their included
functions generate an interrupt request flag. To allow the program to branch to its respective interrupt
vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one
of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of
the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related MultiFunction request flag, will be automatically reset and the EMI bit will be automatically cleared to
disable other interrupts.
However, it must be noted that, although the Multi-function Interrupt flags will be automatically
reset when the interrupt is serviced, the request flags from the original source of the Multi-function
interrupts, namely the TM Interrupts, will not be automatically reset and must be manually reset by
the application program.
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A/D Converter Interrupt
The device contains an A/D converter which has its own independent interrupt. The A/D Converter
Interrupt is controlled by the termination of an A/D conversion process. An A/D Converter Interrupt
request will take place when the A/D Converter Interrupt request flag, ADF, is set, which occurs
when the A/D conversion process finishes. To allow the program to branch to its respective interrupt
vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit, ADE, must first be
set. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a
subroutine call to the A/D Converter Interrupt vector, will take place. When the interrupt is serviced,
the A/D Converter Interrupt flag, ADF, will be automatically cleared. The EMI bit will also be
automatically cleared to disable other interrupts.
Time Base Interrupts
The function of the Time Base Interrupts is to provide regular time signal in the form of an internal
interrupt. They are controlled by the overflow signals from their respective timer functions. When
these happens their respective interrupt request flags, TB0F or TB1F will be set. To allow the
program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI
and Time Base enable bits, TB0E or TB1E, must first be set. When the interrupt is enabled, the stack
is not full and the Time Base overflows, a subroutine call to their respective vector locations will
take place. When the interrupt is serviced, the respective interrupt request flag, TB0F or TB1F, will
be automatically reset and the EMI bit will be cleared to disable other interrupts.
The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Their
clock sources originate from the internal clock source fTB. This fTB input clock passes through a
divider, the division ratio of which is selected by programming the appropriate bits in the TBC
register to obtain longer interrupt periods whose value ranges. The clock source that generates fTB,
which in turn controls the Time Base interrupt period, can originate from several different sources,
as shown in the System Operating Mode section.
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TBC Register
Bit
7
6
5
4
3
2
1
0
Name
TBON
TBCK
TB11
TB10
—
TB02
TB01
TB00
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
POR
0
0
1
1
—
1
1
1
Bit 7TBON: TB0 and TB1 Control bit
0: Disable
1: Enable
Bit 6TBCK: Select fTB Clock
0: fTBC
1: fSYS/4
Bit 5~4TB11~TB10: Select Time Base 1 Time-out Period
00: 4096/fTB
01: 8192/fTB
10: 16384/fTB
11: 32768/fTB
Bit 3
Unimplemented, read as “0”
Bit 2~0TB02~TB00: Select Time Base 0 Time-out Period
000: 256/fTB
001: 512/fTB
010: 1024/fTB
011: 2048/fTB
100: 4096/fTB
101: 8192/fTB
110: 16384/fTB
111: 32768/fTB
 Time Base Interrupt
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EEPROM Interrupt
An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set,
which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective
interrupt vector address, the global interrupt enable bit, EMI, and EEPROM Interrupt enable bit,
DEE, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write
cycle ends, a subroutine call to the respective EEPROM Interrupt vector, will take place. When the
EEPROM Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts,
and the EEPROM interrupt request flag, DEF, will also be automatically cleared.
TM Interrupts
The Compact and Standard Type TMs each has two interrupts. All of the TM interrupts are contained
within the Multi-function Interrupts. For each of the Compact and Standard Type TMs there are two
interrupt request flags TnPF and TnAF and two enable bits TnPE and TnAE. A TM interrupt request
will take place when any of the TM request flags are set, a situation which occurs when a TM
comparator P or comparator A match situation happens.
To allow the program to branch to its respective interrupt vector address, the global interrupt enable
bit, EMI, and the respective TM Interrupt enable bit, and associated Multi-function interrupt enable
bit, MFnF, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator
match situation occurs, a subroutine call to the relevant TM Interrupt vector locations, will take
place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other
interrupts, however only the related MFnF flag will be automatically cleared. As the TM interrupt
request flags will not be automatically cleared, they have to be cleared by the application program.
Interrupt Wake-up Function
Each of the interrupt functions has the capability of waking up the microcontroller when in the
SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to
high and is independent of whether the interrupt is enabled or not. Therefore, even though the device
is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge
transitions on the external interrupt pin, a low power supply voltage or comparator input change may
cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must
therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function
is to be disabled then the corresponding interrupt request flag should be set high before the device
enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up
function.
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Programming Considerations
By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being
serviced, however, once an interrupt request flag is set, it will remain in this condition in the
interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by
the application program.
Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt
service routine is executed, as only the Multi-function interrupt request flags, MF0F~MF2F, will
be automatically cleared, the individual request flag for the function needs to be cleared by the
application program.
It is recommended that programs do not use the “CALL” instruction within the interrupt service
subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately.
If only one stack is left and the interrupt is not well controlled, the original control sequence will be
damaged once a CALL subroutine is executed in the interrupt subroutine.
Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE
Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is
required to prevent a certain interrupt from waking up the microcontroller then its respective request
flag should be first set high before enter SLEEP or IDLE Mode.
As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the
contents of the accumulator, status register or other registers are altered by the interrupt service
program, their contents should be saved to the memory at the beginning of the interrupt service
routine.
To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI
instruction in addition to executing a return to the main program also automatically sets the EMI
bit high to allow further interrupts. The RET instruction however only executes a return to the main
program leaving the EMI bit in its present zero state and therefore disabling the execution of further
interrupts.
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Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the device
during the programming process. During the development process, these options are selected using
the HT-IDE software development tools. As these options are programmed into the device using
the hardware programming tools, once they are selected they cannot be changed later using the
application program. All options must be defined for proper system function, the details of which are
shown in the table.
No.
Options
Oscillator Option
1
High Speed/Low Speed System Oscillator Selection – fOSC:
1. HIRC+LIRC
2. HXT+LIRC
2
HIRC Frequency Selection:
1. 4MHz
2. 8MHZ
3. 12MHz
Application Circuits
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Instruction Set
Instruction
Central to the successful operation of any microcontroller is its instruction set, which is a set of
program instruction codes that directs the microcontroller to perform certain operations. In the case
of Holtekmicrocontrollers, a comprehensive and flexible set of over 60 instructions is provided to
enable programmers to implement their application with the minimum of programming overheads.
For easier understanding of the various instruction codes, they have been subdivided into several
functional groupings
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch,
call, or table read instructions where two instruction cycles are required. One instruction cycle is
equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions
would be implemented within 0.5μs and branch or call instructions would be implemented within
1μs. Although instructions which require one more cycle to implement are generally limited to
the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other
instructions which involve manipulation of the Program Counter Low register or PCL will also take
one more cycle to implement. As instructions which change the contents of the PCL will imply a
direct jump to that new address, one more cycle will be required. Examples of such instructions
would be “CLR PCL” or “MOV PCL, A”. For the case of skip instructions, it must be noted that if
the result of the comparison involves a skip operation then this will also take one more cycle, if no
skip is involved then only one cycle is required.
Moving and Transferring Data
The transfer of data within the microcontroller program is one of the most frequently used
operations. Making use of three kinds of MOV instructions, data can be transferred from registers to
the Accumulator and vice-versa as well as being able to move specific immediate data directly into
the Accumulator. One of the most important data transfer applications is to receive data from the
input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and data manipulation is a necessary feature of
most microcontroller applications. Within the Holtek microcontroller instruction set are a range of
add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care
must be taken to ensure correct handling of carry and borrow data when results exceed 255 for
addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC
and DECA provide a simple means of increasing or decreasing by a value of one of the values in the
destination specified.
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Logical and Rotate Operations
The standard logical operations such as AND, OR, XOR and CPL all have their own instruction
within the Holtek microcontroller instruction set. As with the case of most instructions involving
data manipulation, data must pass through the Accumulator which may involve additional
programming steps. In all logical data operations, the zero flag may be set if the result of the
operation is zero. Another form of logical data manipulation comes from the rotate instructions such
as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different
rotate instructions exist depending on program requirements. Rotate instructions are useful for serial
port programming applications where data can be rotated from an internal register into the Carry
bit from where it can be examined and the necessary serial bit set high or low. Another application
where rotate data operations are used is to implement multiplication and division calculations.
Branches and Control Transfer
Program branching takes the form of either jumps to specified locations using the JMP instruction or
to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine
call, the program must return to the instruction immediately when the subroutine has been carried
out. This is done by placing a return instruction RET in the subroutine which will cause the program
to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is no requirement to jump back to the original
jumping off point as in the case of the CALL instruction. One special and extremely useful set
of branch instructions are the conditional branches. Here a decision is first made regarding the
condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and jump to the following instruction. These
instructions are the key to decision making and branching within the program perhaps determined
by the condition of certain input switches or by the condition of internal data bits.
Bit Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all
Holtek microcontrollers. This feature is especially useful for output port bit programming where
individual bits or port pins can be directly set high or low using either the “SET [m].i” or “CLR [m].i”
instructions respectively. The feature removes the need for programmers to first read the 8-bit output
port, manipulate the input data to ensure that other bits are not changed and then output the port with
the correct new data. This read-modify-write process is taken care of automatically when these bit
operation instructions are used.
Table Read Operations
Data storage is normally implemented by using registers. However, when working with large
amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in
the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program
Memory to be setup as a table where data can be directly stored. A set of easy to use instructions
provides the means by which this fixed data can be referenced and retrieved from the Program
Memory.
Other Operations
In addition to the above functional instructions, a range of other instructions also exist such as
the “HALT” instruction for Power-down operations and instructions to control the operation of
the Watchdog Timer for reliable program operations under extreme electric or electromagnetic
environments. For their relevant operations, refer to the functional related sections.
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Instruction Set Summary
The following table depicts a summary of the instruction set categorised according to function and
can be consulted as a basic instruction reference using the following listed conventions.
Table Conventions
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Mnemonic
Description
Cycles
Flag Affected
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
1
1Note
1
1Note
Z
Z
Z
Z
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
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Mnemonic
Description
Cycles
Flag Affected
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1Note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRD [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no
skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the “CLR WDT1” and “CLR WDT2” instructions the TO and PDF flags may be affected by the
execution status. The TO and PDF flags are cleared after both “CLR WDT1” and “CLR WDT2”
instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
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HT66F007
Small Package A/D Flash 8-bit MCU
Instruction Definition
ADC A,[m]
Description
Operation
Affected flag(s)
Add Data Memory to ACC with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the Accumulator.
ACC ← ACC + [m] + C
OV, Z, AC, C
ADCM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m] + C
OV, Z, AC, C
Add Data Memory to ACC
ADD A,[m]
Description
The contents of the specified Data Memory and the Accumulator are added.
The result is stored in the Accumulator.
Operation
Affected flag(s)
ACC ← ACC + [m]
OV, Z, AC, C
ADD A,x
Description
Operation
Affected flag(s)
Add immediate data to ACC
The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator.
ACC ← ACC + x
OV, Z, AC, C
ADDM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory
The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m]
OV, Z, AC, C
AND A,[m]
Description
Operation
Affected flag(s)
Logical AND Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ [m]
Z
AND A,x
Description
Operation
Affected flag(s)
Logical AND immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ x
Z
ANDM A,[m]
Description
Operation
Affected flag(s)
Logical AND ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND
operation. The result is stored in the Data Memory.
[m] ← ACC ″AND″ [m]
Z
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HT66F007
Small Package A/D Flash 8-bit MCU
CALL addr
Description
Operation
Affected flag(s)
Subroutine call
Unconditionally calls a subroutine at the specified address. The Program Counter then
increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Stack ← Program Counter + 1
Program Counter ← addr
None
CLR [m]
Description
Operation
Affected flag(s)
Clear Data Memory
Each bit of the specified Data Memory is cleared to 0.
[m] ← 00H
None
CLR [m].i
Description
Operation
Affected flag(s)
Clear bit of Data Memory
Bit i of the specified Data Memory is cleared to 0.
[m].i ← 0
None
CLR WDT
Description
Operation
Affected flag(s)
Clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CLR WDT1
Description
Operation
Affected flag(s)
Pre-clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in
conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have
effect. Repetitively executing this instruction without alternately executing CLR WDT2 will
have no effect.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CLR WDT2
Description
Operation
Affected flag(s)
Pre-clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction
with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect.
Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CPL [m]
Description
Operation
Affected flag(s)
Complement Data Memory
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa.
[m] ← [m]
Z
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HT66F007
Small Package A/D Flash 8-bit MCU
CPLA [m]
Description
Operation
Affected flag(s)
Complement Data Memory with result in ACC
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
ACC ← [m]
Z
DAA [m]
Description
Operation
Affected flag(s)
Decimal-Adjust ACC for addition with result in Data Memory
Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value
resulting from the previous addition of two BCD variables. If the low nibble is greater than 9
or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6
will be added to the high nibble. Essentially, the decimal conversion is performed by adding
00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag
may be affected by this instruction which indicates that if the original BCD sum is greater than
100, it allows multiple precision decimal addition.
[m] ← ACC + 00H or
[m] ← ACC + 06H or [m] ← ACC + 60H or
[m] ← ACC + 66H
C
DEC [m]
Description
Operation
Affected flag(s)
Decrement Data Memory
Data in the specified Data Memory is decremented by 1.
[m] ← [m] − 1
Z
DECA [m]
Description
Operation
Affected flag(s)
Decrement Data Memory with result in ACC
Data in the specified Data Memory is decremented by 1. The result is stored in the
Accumulator. The contents of the Data Memory remain unchanged.
ACC ← [m] − 1
Z
HALT
Description
Operation
Affected flag(s)
Enter power down mode
This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power
down flag PDF is set and the WDT time-out flag TO is cleared.
TO ← 0
PDF ← 1
TO, PDF
INC [m]
Description
Operation
Affected flag(s)
Increment Data Memory
Data in the specified Data Memory is incremented by 1.
[m] ← [m] + 1
Z
INCA [m]
Description
Operation
Affected flag(s)
Increment Data Memory with result in ACC
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator.
The contents of the Data Memory remain unchanged.
ACC ← [m] + 1
Z
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Small Package A/D Flash 8-bit MCU
JMP addr
Description
Operation
Affected flag(s)
Jump unconditionally
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Program Counter ← addr
None
MOV A,[m]
Description
Operation
Affected flag(s)
Move Data Memory to ACC
The contents of the specified Data Memory are copied to the Accumulator.
ACC ← [m]
None
MOV A,x
Description
Operation
Affected flag(s)
Move immediate data to ACC
The immediate data specified is loaded into the Accumulator.
ACC ← x
None
MOV [m],A
Description
Operation
Affected flag(s)
Move ACC to Data Memory
The contents of the Accumulator are copied to the specified Data Memory.
[m] ← ACC
None
NOP
Description
Operation
Affected flag(s)
No operation
No operation is performed. Execution continues with the next instruction.
No operation
None
OR A,[m]
Description
Operation
Affected flag(s)
Logical OR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise
logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ [m]
Z
OR A,x
Description
Operation
Affected flag(s)
Logical OR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ x
Z
ORM A,[m]
Description
Operation
Affected flag(s)
Logical OR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
[m] ← ACC ″OR″ [m]
Z
RET
Description
Operation
Affected flag(s)
Return from subroutine
The Program Counter is restored from the stack. Program execution continues at the restored
address.
Program Counter ← Stack
None
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Small Package A/D Flash 8-bit MCU
RET A,x
Description
Operation
Affected flag(s)
Return from subroutine and load immediate data to ACC
The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address.
Program Counter ← Stack
ACC ← x
None
RETI
Description
Operation
Affected flag(s)
Return from interrupt
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the
EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Program Counter ← Stack
EMI ← 1
None
RL [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← [m].7
None
RLA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left with result in ACC
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
The rotated result is stored in the Accumulator and the contents of the Data Memory remain
unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← [m].7
None
RLC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← C
C ← [m].7
C
RLCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the
Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← C
C ← [m].7
C
RR [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← [m].0
None
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Small Package A/D Flash 8-bit MCU
RRA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0
rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the
Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← [m].0
None
RRC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← C
C ← [m].0
C
RRCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← C
C ← [m].0
C
SBC A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
ACC ← ACC − [m] − C
OV, Z, AC, C
SBCM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry and result in Data Memory
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m] − C
OV, Z, AC, C
SDZ [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is 0
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
[m] ← [m] − 1
Skip if [m]=0
None
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Small Package A/D Flash 8-bit MCU
SDZA [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is zero with result in ACC
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0,
the program proceeds with the following instruction.
ACC ← [m] − 1
Skip if ACC=0
None
SET [m]
Description
Operation
Affected flag(s)
Set Data Memory
Each bit of the specified Data Memory is set to 1.
[m] ← FFH
None
SET [m].i
Description
Operation
Affected flag(s)
Set bit of Data Memory
Bit i of the specified Data Memory is set to 1.
[m].i ← 1
None
SIZ [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is 0
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
[m] ← [m] + 1
Skip if [m]=0
None
SIZA [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is zero with result in ACC
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
ACC ← [m] + 1
Skip if ACC=0
None
SNZ [m].i
Description
Operation
Affected flag(s)
Skip if bit i of Data Memory is not 0
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this
requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m].i ≠ 0
None
SUB A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − [m]
OV, Z, AC, C
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Small Package A/D Flash 8-bit MCU
SUBM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with result in Data Memory
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m]
OV, Z, AC, C
SUB A,x
Description
Operation
Affected flag(s)
Subtract immediate data from ACC
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − x
OV, Z, AC, C
SWAP [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory
The low-order and high-order nibbles of the specified Data Memory are interchanged.
[m].3~[m].0 ↔ [m].7~[m].4
None
SWAPA [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory with result in ACC
The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
ACC.3~ACC.0 ← [m].7~[m].4
ACC.7~ACC.4 ← [m].3~[m].0
None
SZ [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0
If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Skip if [m]=0
None
SZA [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0 with data movement to ACC
The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
ACC ← [m]
Skip if [m]=0
None
SZ [m].i
Description
Operation
Affected flag(s)
Skip if bit i of Data Memory is 0
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires
the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle
instruction. If the result is not 0, the program proceeds with the following instruction.
Skip if [m].i=0
None
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Small Package A/D Flash 8-bit MCU
TABRD [m]
Description
Operation
Affected flag(s)
Read table (current page) to TBLH and Data Memory
The low byte of the program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
TABRDL [m]
Description
Operation
Affected flag(s)
Read table (last page) to TBLH and Data Memory
The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
XOR A,[m]
Description
Operation
Affected flag(s)
Logical XOR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ [m]
Z
XORM A,[m]
Description
Operation
Affected flag(s)
Logical XOR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
[m] ← ACC ″XOR″ [m]
Z
XOR A,x
Description
Operation
Affected flag(s)
Logical XOR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ x
Z
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Small Package A/D Flash 8-bit MCU
Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website for
the latest version of the package information.
Additional supplementary information with regard to packaging is listed below. Click on the relevant
section to be transferred to the relevant website page.
• Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• Packing Meterials Information
• Carton information
• PB FREE Products
• Green Packages Products
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10-pin MSOP Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
—
—
0.043
A1
0.000
—
0.006
A2
0.030
0.033
0.037
B
0.007
—
0.013
C
0.003
—
0.009
D
—
0.118 BSC
—
E
—
0.193 BSC
—
E1
—
0.118 BSC
—
e
—
0.020 BSC
—
L
0.016
0.024
0.031
L1
—
0.037 BSC
—
y
—
0.004
—
θ
0°
—
8°
Symbol
Dimensions in mm
Min.
Nom.
A
—
—
Max.
1.10
A1
0.00
—
0.15
A2
0.75
0.85
0.95
B
0.17
—
0.33
C
0.08
—
0.23
D
—
3.00 BSC
—
E
—
4.90 BSC
—
E1
—
3.00 BSC
—
e
—
0.50 BSC
—
L
0.40
0.60
0.80
L1
—
0.95 BSC
—
y
—
0.10
—
θ
0°
—
8°
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Small Package A/D Flash 8-bit MCU
Copyright© 2013 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time
of publication. However, Holtek assumes no responsibility arising from the use of
the specifications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warranty or representation that
such applications will be suitable without further modification, nor recommends
the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical
components in life support devices or systems. Holtek reserves the right to alter
its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.tw.
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