HT82V48 6-Channel, 16-Bit, 120MSPS CIS Analog Signal Processor Features General Description • 3.3V operating voltage The HT82V48 is a fully integrated, dual high performance 16-bit 3-channel 60MSPS analog signal processor for high-speed double-sided scanner applications. • Up to 120MSPS for 6-channel inputs • 9-bit programmable gain amplifier • 8-bit programmable offset Each channel consist a Sample and Hold Amplifier, a 9-bit Programmable Gain Amplifier and an 8-bit offset correction Digital to Analog Converter. The PGA and offset DAC are programmed independently allowing unique values of gain and offset for the two 3-channel analog inputs. Each of the 3-channel signals are routed to a 60MHz high performance analog-todigital converter. • 4-bit programmable line-clamping bias • Internal voltage reference • 3-wire serial control interface • 48-pin LQFP-EP package Applications • Currency Scanner Double Sided Scanners For image sensor reference level stabilisation, the device also provide programmable line-clamping bias internally. The internal registers are programmed through a 3-wire serial interface, which provides timing control, gain, offset and operating mode adjustments. The device operates from a single 3.3V power supply with a typical power consumption of 925mW. Block Diagram AVDD1 AVSS1 REFT1 Clamp DAC VIR1 SHA VIG1 SHA VIB1 SHA DVDD1 ADCK AFE TG BIAS1 AFE #1 SH CLP 3:1 3:1 MUX 16-bit ADC SCK SCI PGA + DVSS1 PGA PGA + CML1 PGA1R[8:0] PGA1G[8:0] PGA1B[8:0] CDAC[3:0] + Bandgap Reference REFB1 SD SEB Offset DAC Clamp DAC Clamp DAC OS1R[7:0] OS1G[7:0] OS1B[7:0] CTL REG OEB VIR2 D[15:8] VIG2 3:1 3:1 MUX AFE #2 VIB2 MUX 16-bit ADC D[7:0] BIAS2 AVDD2 Rev. 1.00 AVSS2 REFT2 REFB2 1 CML2 DVDD2 DVSS2 January 26, 2015 HT82V48 Pin Assignment D4 D3 D2 D1 D0 DVSS2 DVSS1 DVDD1 AVSS1 CML1 REFB1 REFT1 AVDD1 AVSS1 BIAS1 VIR1 VIG1 VIB1 VIR2 VIG2 VIB2 BIAS2 AVSS2 AVDD2 36 35 34 33 32 31 30 29 28 27 26 25 24 37 23 38 22 39 21 40 HT82V48 20 41 19 42 48 LQFP-EP-A 18 43 44 17 Expose Pad 16 45 15 46 14 47 13 48 1 2 3 4 5 6 7 8 9 10 11 12 D5 D6 D7 DVSS2 ADCK SH DVDD2 D8 D9 D10 D11 D12 D13 D14 D15 OEB SEB SD SCK CLP AVSS2 CML2 REFB2 REFT2 Pin Description Pin Name I/O Description DVDD1 P AFE Digital Supply VSS1 P AFE Digital Ground DVDD2 P Data Bus Digital Supply VSS2 P Data Bus Digital Ground AVDD1 P AFE #1 Analog Supply AVSS1 P AFE #1 Analog Ground AVDD2 P AFE #2 Analog Supply AVSS2 P AFE #2 Analog Ground ADCK DI System Master Clock and ADC Sampling Clock SH DI Sample-Hold Clock CLP DI Clamping Interval SCK DI Serial Control Interface (SCI) Clock SD DI SCI Data SEB DI SCI Enable, Active Low VIR1 AI Analog Input , AFE #1 Channel R VIG1 AI Analog Input , AFE #1 Channel G VIB1 AI Analog Input , AFE #1 Channel B BIAS1 AO AFE #1 Bias Decoupling REFB1 AO AFE #1 ADC Bottom Reference Voltage Decoupling REFT1 AO AFE #1 ADC Top Reference Voltage Decoupling CML1 AO AFE #1 Internal Bias Level Decoupling VIR2 AI Analog Input , AFE #2 Channel R VIG2 AI Analog Input , AFE #2 Channel G VIB2 AI Analog Input , AFE #2 Channel B BIAS2 AO AFE #2 Bias Decoupling REFB2 AO AFE #2 ADC Bottom Reference Voltage Decoupling REFT2 AO AFE #2 ADC Top Reference Voltage Decoupling CML2 AO AFE #2 Internal Bias Level Decoupling Rev. 1.00 2 January 26, 2015 HT82V48 Pin Name I/O Description OEB DI Output Data Enable, Active Low D[15:8] DO Data Output D[7:0] DO Data Output Type: AI=Analog Input; AO=Analog Output; AIO=Analog In/out, DI=Digital Input; DO=Digital Output; P=Power Absolute Maximum Ratings Supply Voltage ..........................VSS-0.3V to VSS+4.3V Storage Temperature ............................-50°C to 125°C Operating Temperature..............................0°C to 70°C Digital supply power.................................3.0V to 3.6V Input Voltage .............................VSS-0.3V to VDD+0.3V Analogue Supply Power ...........................3.0V to 3.6V Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol Ta=25°C Parameter Test Conditions Min. Typ. Max. Unit Power Supply AVDD Analogue Supply Power — 3.0 3.3 3.6 V DVDD Digital Supply Power — 3.0 3.3 3.6 V V Digital Inputs VIH High level input voltage — 0.7×DVDD — — VIL LOR level input voltage — — — 0.2×DVDD V IIH High level input current — — — 1 μA IIL LOR level input current — — — 1 μA CI Input capacitance — — 5 — pF V Digital Outputs VOH High level output voltage IOH=1mA DVDD-0.5 — — VOL LOR level output voltage IOL=1mA — — 0.5 V IOZ High impedance output current — — 1 μA — AVDD=DVDD=3.3V, AVSS=DVSS=0V, Ta=25°C, ADCK=60MHz unless otherwise stated. Symbol Parameter Test Conditions Min. Typ. Max. Unit Overall system specification (including 16-bit ADC, PGA, Offset and SHA functions) Maximum Conversion rate Full-scale input voltage range VIN — — 60 — MSPS LOR=0; Max Gain — 0.33 — VP-P LOR=0; Min Gain — 3.03 — VP-P LOR=1; Max Gain — 0.20 — VP-P LOR=1; Min Gain — 1.82 — VP-P AVSS-0.3 — AVDD+0.3 Input signal limits — Full-scale transition error Gain=0dB — 30 — Zero-scale transition error Gain=0dB — 30 — mV mV DNL Differential non-linearity — — 2 — LSB INL Integral non-linearity — — 50 — LSB Rev. 1.00 3 January 26, 2015 HT82V48 Symbol Parameter Test Conditions Min. Typ. Max. — Channel to channel gain matching Total output noise Unit — 1.5 — % Min Gain — 30 — LSBrms Max Gain — 300 — LSBrms LOR=0 1.95 2.05 2.25 V LOR=1 — 1.85 — V LOR=0 0.95 1.05 1.25 V LOR=1 — 1.25 — V — 1.5 — V LOR=0 0.90 1.0 1.10 V LOR=1 — 0.6 — V bits References VRT Upper reference voltage VRB LORer reference voltage CML Input return bias voltage VRTB Differential reference voltage — Clamping(CLP) DAC Resolution VCSTEP Step size VCBOT Output voltage at code 0h — 4 — CRNG=0 — — 0.173 — CRNG=1 — 0.11 — — 0.4 — CRNG=0 — — 2.76 — CRNG=1 — 2.05 — V/step V VCTOP Output voltage at code Fh V DNL Differential non-linearity — -0.5 — +0.5 LSB INL Integral non-linearity — — +/-1 — LSB Resolution — — 8 — bits Step size — — 2.274 — mV/step Code 0x00 — -290 — mV Code 0xFF — +290 — mV 9 Offset DAC Output voltage Programmable Gain Amplifier Resolution — — — bits Gain equation — 0.67 + PGA[8:0] × 5.35/511 V/V GMAX Max gain, each channel — — 6.0 — V/V GMIN Min gain, each channel — — 0.65 — V/V Channel Matching — — 5 15 % Resolution — — 16 — bits Speed — — 60 — MSPS A/D Converter Full-scale input range LOR=0 — 2 — V LOR=1 — 1.2 — V V Digital Inputs VIH High level input voltage — 0.7×DVDD — — VIL LOR level input voltage — — — 0.2×DVDD V IIH High level input current — — — 1 μA IIL LOR level input current — — — 1 μA CI Input capacitance — — 5 — pF V Digital Outputs VOH High level output voltage IOH=1mA DVDD-0.5 — — VOL LOR level output voltage IOL=1mA — — 0.5 V IOZ High impedance output current — — 1 μA Rev. 1.00 — 4 January 26, 2015 HT82V48 Symbol Parameter Test Conditions Min. Typ. Max. Unit Digital I/O Pins VIH Applied high level input voltage — 0.7×DVDD — — V VIL Applied low level input voltage — — — 0.2×DVDD V VOH High level output voltage IOH=1mA DVDD-0.5 — VOL Low level output voltage IOL=1mA — — 0.5 V IIL Low level input current — — — 1 μA IIH High level input current — — — 1 μA IOZ High impedance output current — — — 1 μA Total supply current — — 290 — mA Analogue supply current — — 240 — mA Digital supply current — — 50 — mA Power down mode — — 400 — μA V Supply Currents A.C. Characteristics Symbol AVDD=DVDD=3.3V, AVSS=DVSS=0V, Ta=25°C, ADCK=60MHz unless otherwise stated. Parameter Test Conditions Min. Typ. Max. Unit ns Clock Parameter tADCK ADCK period — 16.67 — — DUTY ADCK duty — 45 50 55 % tSSH SH setup time — 0 — 4 ns tHSH SH hold time — 0 — 4 ns tSH SH width — — 1/2 — ADCK Serial Control Interface tSSCK SCK setup time — 10 — — ns tHSCK SCK hold time — 10 — — ns tSSD SD setup time — 10 — — ns tHSD SD hold time — 10 — — ns tTSD SD transition time; input/output alternated — 5 — — ns Data Output tVD 3-state to data valid — — 3 4 ns tZD Output enable high to 3-state — — 3 4 ns tDD Data output propagation delay — — 8 10 ns LAT Output latency (Pipeline delay) — — — 7 ADCK Note: Parameters are measured at 50% of the rising/falling edge. Rev. 1.00 5 January 26, 2015 HT82V48 Functional Description Bias and Clamping Introduction External Bias The S/H circuit reference levels are supplied by the BIAS1 and BIAS2 pins. The HT82V48 can sample up to two groups of three inputs, namely VIR1, VIG1, VIB1, VIR2, VIG2 and VIB2 simultaneously. After sampling the device then processes the sampled video signals with respect to an external reference level. Each processing channel consists of an input sampling block, a 4-bit programmable RLC DAC, an 8-bit programmable offset DAC and 9-bit Programmable Gain Amplifier. The ADC then converts each resulting analogue signal to a 16-bit digital word. The digital output from the ADC is then presented on an 8-bit or 16-bit wide bus. Internal control registers determine the configuration of the device, including the bias, offsets and gain applied on each channel. These registers are programmable via the devices’ Serial Control Interface. Internal Bias The S/H circuit reference level is supplied by the CLP DAC when CDACB=1. The level is programmed by the CDAC[3:0] bits. The operation is shown in Figure 1. Line Clamping In situations where the input video signal does not have a stable reference level it may be necessary to clamp only when those pixels which have a known state (e.g. the dummy, or black pixels at the start or end of a line of most image sensors). Use the CLP pin to identify the black pixels and enable the clamp at the same time as when the input is being sampled (i.e. when SH is high and CLP is high). This mode is enabled by setting CLPEN=1. The operation is shown in Figure 2. Internal Power-On-Reset Circuit The internal POR Circuit power is supplied on AVDD and is used to reset digital logic into a default state after power-up. The POR circuit is active from a voltage equal to 0.6VTyp. of AVDD and is released when the voltage reaches 1.2VTyp. of AVDD. (or 0.7VTyp. of DVDD if AVDD powers up before DVDD). When AVDD or DVDD returns to 0.6VTyp. the POR will again reactive. To ensure the control registers contents are at their default values before carrying out any other register writes it is recommended that a software reset is issued each time the power is cycled. Analog Input Signal Sampling There is only one S/H mode supported by the device. The ADCK:SH ratio is maintained at 3:1. For AFE #1, VIR1, VIG1 and VIB1 video inputs are sampled at the same time and converted by a highspeed A/D converter to multiplexed digital data. The AFE #2 video inputs, VIR2, VIG2 and VIB2 are also sampled at the same time. The reference timing diagram is shown in Figure 3. Power Management Output Formats After the device is powered up, the register bit, PDNB, allows the device to be fully powered down when cleared to zero. Individual blocks can be powered down using the bits in System Setup Register 1. The device output can be presented in several different formats under control of the ODFM[1:0] register bits as shown in Figure 3. The device supports 8-bit (ODFM[1:0]=[0,0]) resolution when AFE #1 and AFE #2 are operated at the same time during video signal processing. For DC level calibration, 16-bit resolution is enabled by setting ODFM[1:0] = [0, 1] or [1, 0] for AFE #1 or AFE #2. References The ADC reference voltages are derived from an internal bandgap reference and buffered to pins REFT and REFB, where they must be decoupled to ground. Pin CML is driven by a similar buffer and also requires decoupling. The output buffer from the CLP DAC also requires decoupling on pins BIAS1 and BIAS2. Offset Adjust and Programmable Gain An 8-bit Offset DAC is provided to compensate for offsets and then amplified by a 9-bit PGA. The gain and offset for each channel are independently programmable by control bits OSXY[7:0] and PGAXY[7:0]. S/H Processing The video level is processed with respect to the voltage on pins BIAS1 and BIAS2. BIAS1 and BIAS2 voltage are sampled at the same time as SH samples the video level. Rev. 1.00 6 January 26, 2015 HT82V48 ADC Input Black Level Adjust For a register write, an address A[4:0] is clocked in through SD, followed by 2 dummy clocks and a data word D[7:0]. Each bit is latched on the SCK rising edge. The dummy clocks are used for internal address data latch and decoding. The output from the PGA can be offset to match the full-scale range of the differential ADC(2×(VRT -VRB)). Serial Control Interface For a register read-back operation, the SD address and dummy clocks are the same as for the register write procedure. Here SD will change from an input to an output port and send out an output data word D[7:0] on the SCK falling edge after the end of a dummy clock. Then SD will change from an output to an input port after an SEB rising edge. SCK, SD and SEB are used both for register writing and reading. The R/WB bit for SD is used to determine whether the control is data write (R/WB=0) or data read (R/WB=1). The procedure is initiated on an SEB falling edge. SH Video Sample Capacitor VIXY BPCLP CLP Ref. Sample Capacitor BIASY X = R, G, B CDACPD (Initial : power-down) Y = 1, 2 Clamp DAC 4 CDAC[3:0] Figure 1 Bias and Clamping Configuration unstable Ref. level Analog Input Dummy or Black pixel ADCK SH CLP BPCLP Figure 2 Clamping Operation Rev. 1.00 7 January 26, 2015 HT82V48 tADCK ADCK Pixel (n) VIRx VIGx VIBx tSSH tSH tHSH SH tZD tVD OEB tDD ODFM[1:0] = (0,0) HB : B2H (n-4) LB : B1H (n-4) HB : R2H (n-3) LB : R1H (n-3) HB : G2H (n-3) LB : G1H (n-3) HB : B2H (n-3) LB : B1H (n-3) HB : R2H (n-2) LB : R1H (n-2) HB : R1H (n-3) LB : R1L (n-3) HB : G1H (n-3) LB : G1L (n-3) HB : B1H (n-3) LB : B1L (n-3) HB : R1H (n-2) LB : R1L (n-2) HB : R2H (n-3) LB : R2L (n-3) HB : G2H (n-3) LB : G2L (n-3) HB : B2H (n-3) LB : B2L (n-3) HB : R2H (n-2) LB : R2L (n-2) ODFM[1:0] = (0,1) D[15:8] D[7:0] HB : B1H (n-4) LB : B1L (n-4) ODFM[1:0] = (1,0) HB : B2H (n-4) LB : B2L (n-4) Where LB(or HB) denote low-byte(or high-byte), “R(or G, B)” denote channel R(or G, B), “1(or 2)” denote AFE #1(or #2), “L(or H)” denote low-byte (or high-byte) data and “n” denote pixel number. Figure 3 S/H and Data Output Control Timing SD R/ WB A4 Don ’ t Care A3 ~ A0 tSSD D7 ~ D1 tSSD tHSD 1 D0 tSSD 2 SCK tSSCK 2 Dummy Clocks tHSCK SEB R/WB = 0 / 1 : Data Write / Data Read Figure 4 Serial Control Interface Timing Rev. 1.00 8 January 26, 2015 HT82V48 Control Registers Register Mapping Here X denotse AFE #1 and AFE #2; Y denotse channel R, channel G and channel B Address Description POR D7 ODFM[1:0] 00h System Setup Register 1 07h 01h AFE Setup Register 1 00h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh AFE_1 CH_R PGA gain AFE_1 CH_G PGA gain AFE_1 CH_B PGA gain AFE_2 CH_R PGA gain AFE_2 CH_G PGA gain AFE_2 CH_B PGA gain D6 D5 D4 0 0 D3 60M CDAC[3:0] 00h D2 AFE2B AFE1B CLPEN CRNG CDACB D0 PDNB LOR PGA1R[7:0] 00h — 00h PGA1R[8] PGA1G[7:0] 00h — 00h PGA1G[8] PGA1B[7:0] 00h — 00h PGA1B[8] PGA2R[7:0] 00h — 00h PGA2R[8] PGA2G[7:0] 00h — 00h PGA2G[8] PGA2B[7:0] 00h — 0Eh AFE_1 CH_R Offset value 00h OS1R[7:0] 0Fh AFE_1 CH_G Offset value 00h OS1G[7:0] 10h AFE_1 CH_B Offset value 00h OS1B[7:0] 11h AFE_2 CH_R Offset value 00h OS2R[7:0] 12h AFE_2 CH_G Offset value 00h OS2G[7:0] 13h AFE_2 CH_B Offset value 00h OS2B[7:0] 14h Reserved 50h Rev. 1.00 D1 9 PGA2B[8] January 26, 2015 HT82V48 Register Description Register System Setup Register 1 Bit Name POR 0 PDNB 1 0=fully power down 1=fully active 1 AFE1B 1 0=AFE #1 power down 1=AFE #1 active 2 AFE2B 1 0=AFE #2 power down 1=AFE #2 active 3 60M 0 Maximum operating speed 0=50Msps 1=60Msps 4 Reserved 0 5 Reserved 0 7:6 AFE Setup Register 1 ODFM[1:0] Description — — 00b Output data format 0,0=D[15:8] : AFE #2 high-byte data; D[7:0] : AFE #1 high-byte data 0,1=D[15:8] : AFE #1 high-byte data; D[7:0] : AFE #1 low-byte data 1,0=D[15:8] : AFE #2 high-byte data; D[7:0] : AFE #2 low-byte data 1,1=D[15:6] : AFE #2 or AFE #1 high-10-bit data 0 LOR 0 Reduces the ADC reference range 2×(VRT - VRB), thus changing the max/min input voltages. 0=ADC reference range=2V 1=ADC reference range=1.2V 1 CDACB 0 0=CLP DAC power down 1=CLP DAC active 2 CRNG 0 Sets CLP DAC output range 0=CLP DAC ranges from 0 to AVDD 1=CLP DAC ranges from 0 to VRT 3 CLPEN 0 Enable clamping function. Clamping switch is controlled by CLP pin. 7:4 CDAC[3:0] 0 Controls CLP DAC driving BIAS1/BIAS2 pins to define voltage or clamping voltage. AFE #1 CH_R PGA gain 0 PGA1A[8] 0 7:0 PGA1A[7:0] 00h AFE #1 CH_G PGA gain 0 PGA1B[8] 0 7:0 PGA1B[7:0] 00h AFE #1 CH_B PGA gain 0 PGA1C[8] 0 7:0 PGA1C[7:0] 00h AFE #1 channel R PGA gain setting. 0.66 + PGA1A[8:0] × (7.34/511) AFE #1 channel G PGA gain setting. 0.66 + PGA1B[8:0] × (7.34/511) AFE #1 channel B PGA gain setting. 0.66 + PGA1C[8:0] × (7.34/511) AFE #2 CH_R PGA gain 0 PGA1A[8] 0 7:0 PGA2A[7:0] 00h AFE #2 CH_G PGA gain 0 PGA2B[8] 0 7:0 PGA2B[7:0] 00h AFE #2 CH_B PGA gain 0 PGA2C[8] 0 7:0 PGA2C[7:0] 00h AFE_1 CH_R Offset value 7:0 OS1A[7:0] 00h AFE #1 channel R offset DAC value. AFE_1 CH_G Offset value 7:0 OS1B[7:0] 00h AFE #1 channel G offset DAC value. AFE_1 CH_B Offset value 7:0 OS1C[7:0] 00h AFE #1 channel B offset DAC value. AFE_2 CH_R Offset value 7:0 OS2R[7:0] 00h AFE #2 channel R offset DAC value. AFE_2 CH_G Offset value 7:0 OS2G[7:0] 00h AFE #2 channel G offset DAC value. AFE_2 CH_B Offset value 7:0 OS2B[7:0] 00h AFE #2 channel B offset DAC value. Rev. 1.00 AFE #2 channel R PGA gain setting. 0.66 + PGA2A[8:0] × (7.34/511) AFE #2 channel G PGA gain setting. 0.66 + PGA2B[8:0] × (7.34/511) AFE #2 channel B PGA gain setting. 0.66 + PGA2C[8:0] × (7.34/511) 10 January 26, 2015 HT82V48 Register Bit Reserved Name POR Description 3:0 — — Reserved 5:4 TEST0[1:0] 01b Test Mode 7:6 TEST1[1:0] 01b Test Mode Application Circuits 0.1uF 0.1uF 0.1uF AVDD VDD Reservoir 1uF 10uF 0.01uF VDD AVSS1 D6 23 BIAS1 D7 22 VIR1 DVSS2 VIG1 ADCK VIB1 SH HT82V48 48 LQFP-EP-A DVDD2 10uF 21 20 19 18 D8 17 D9 16 BIAS2 D10 15 AVSS2 D11 14 AVDD2 D12 13 Expose Pad Reservoir 48 D4 0.1uF D3 47 25 24 VIB2 46 26 D5 VIG2 45 0.1uF D2 CIS2 Input 27 AVDD1 VIR2 44 28 D1 43 29 D0 42 30 DVSS2 41 CIS1 Input 31 DVSS1 0.1uF 40 32 DVDD1 39 33 AVSS1 38 34 CML1 37 0.1uF 35 REFB1 REFT1 CIS1 Vref AVDD AFE Data Output 0.1uF 36 Timing Control VDD 0.1uF AVDD 8 9 10 11 D13 7 D14 6 D15 CLP 5 OEB AVSS2 4 SEB CML2 3 SD REFB2 2 SCK REFT2 1 CIS2 Vref 12 0.01uF 1uF 0.1uF 0.1uF 0.1uF Serial Control I/F Notes: 1. All decoupling capacitors should be located as close as possible to the HT82V48 AFE. 2. AVSS and DVSS should be connected as close as possible to the HT82V48 AFE. 3. Any exposed pads should be connected to DVSS. Rev. 1.00 11 January 26, 2015 HT82V48 Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.00 12 January 26, 2015 HT82V48 48-pin LQFP-EP (Exposed Pads) (7mm × 7mm) Outline Dimensions Symbol Nom. Max. A — 0.354 BSC — B — 0.276 BSC — C — 0.354 BSC — D — 0.276 BSC — E — 0.020 BSC — D2 0.170 — 0.205 E2 0.079 — — F 0.007 0.009 0.011 G 0.053 0.055 0.057 H — — 0.063 I 0.002 — 0.006 J 0.018 0.024 0.030 K 0.004 — 0.008 α 0° — 7° Symbol Rev. 1.00 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. A — 9.00 BSC — B — 7.00 BSC — C — 9.00 BSC — D — 7.00 BSC — E — 0.50 BSC — D2 4.31 — 5.21 E2 2.00 — — F 0.17 0.22 0.27 G 1.35 1.40 1.45 H — — 1.60 I 0.05 — 0.15 J 0.45 0.60 0.75 K 0.09 — 0.20 α 0° — 7° 13 January 26, 2015 HT82V48 Copyright© 2015 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 14 January 26, 2015