HT82V42
Single-channel 16-Bit CCD/CIS Analog Signal Processor
Features
· 3.3V single power supply
· ±315mV 8-bit programmable offset
· Low power consumption: 188mW (Typ.)
· Programmable clamp voltage
· Power-down mode: 300uA (Typ.)
· Internal voltage reference
· 16-bit 15 MSPS A/D converter
· Programmable 4-wire serial interface
· Guaranteed won¢t miss codes
· 4-bit multiplexed nibble mode
· 8-bit programmable gain
· 20-pin SSOP/TSSOP package
· Correlated Double Sampling
Applications
· Flatbed document scanners
· Digital color copiers
· Film scanners
· Multifunction peripherals
General Description
The HT82V42 is a complete analog signal processor for
CCD imaging applications. It features a 1-channel architecture designed to sample and condition the outputs of
tri-linear color CCD arrays. The channel consists of an
input clamp, Correlated Double Sampler (CDS), offset
DAC and Programmable Gain Amplifier (PGA) and a
high performance 16-bit A/D converter. The CDS amplifiers may be disabled for use with sensors such as Con-
tact Image Sensors (CIS) and CMOS active pixel sensors, which do not require CDS. The 16-bit digital output
is available in 4-bit wide multiplexed format. The internal
registers are programmed through a 4-wire serial interface, which provides gain, offset and operating mode
adjustments. The HT82V42 operates from a single 3.3V
power supply and typically consumes 188mW of power.
Block Diagram
AVDD
AVSS
VRB
VRT
AVSS
VRX
DVDD1
DVDD2
DGND
RPGA
GPGA
BPGA
VIN
CDS
+
RDAC
GDAC
BDAC
3:1
MUX
3:1
MUX
BANDGAP
Reference
PGA
10-Bit
DAC
16-Bit
ADC
16
16 : 4
MUX
4
OD[0]
OD[1]
OD[2]
OD[3]/SDO
Configuration
Register
MUX
Register
RED
GREEN
BLUE
RED
GREEN
BLUE
VRLC/
BAIS
SCLK
SEN
SDI
Offset
Registers
Clamp
DAC
CDSCLK2
Rev. 1.20
Gain
Registers
Digital
Control
Interface
DCLK
1
RLC/ACYC
December 8, 2010
HT82V42
Pin Assignment
A G N D
1
2 0
V IN
D V D D 1
2
1 9
V R L C /V B IA S
A G N D
1
2 0
V R L C /V B IA S
V IN
2
1 9
C D S C L K 2
3
1 8
V R X
V R X
C D S C L K 2
3
1 8
D C L K
4
V R T
1 7
V R T
R L C /A C Y C
4
1 7
D G N D
V R B
5
1 6
V R B
D C L K
5
1 6
A G N D
S E N
6
1 5
A G N D
D G N D
6
1 5
A V D D
D V D D 2
7
1 4
A V D D
S E N
7
1 4
O D 3 /S D O
S D I
8
1 3
O D 3 /S D O
D V D D 2
8
1 3
O D 2
S C K
9
1 2
O D 2
S D I
9
1 2
O D 1
O D 0
1 0
1 1
O D 1
1 0
1 1
O D 0
S C K
H T 8 2 V 4 2
2 0 T S S O P -A
H T 8 2 V 4 2
2 0 S S O P -A
Pin Description
Pin Name
I/O
Description
AGND
P
Negative power supply for analog circuit
DVDD1
P
Digital Driver Power (3.3V).
CDSCLK2
DI
CDS Video Sample Clock Pulse Input
RLC/ACYC
DI
ACYC auto cycles between R, G, B inputs.
DCLK
DI
ADC Clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or any multiple of
2 thereafter depending on input sample mode).
DGND
P
Digital Driver Ground
SEN
DI
Serial Interface Enable Pulse (High Active)
DVDD2
P
Digital Driver Power(3.3V).
SDI
DI
Serial Data Input
SCK
DI
Clock Input for Serial Interface
Digital multiplexed output data bus.
ADC output data D[15:0] is available in two multiplexed formats as shown.
OD0~OD2
OD3/SDO
DO
A
B
C
D
D12
D8
D4
D0
D13
D9
D5
D1
D14
D10
D6
D2
D15
D11
D7
D3
When address bit4 = 1 and SEN has been pulsed high, this pin use as SDO for register data
read-back. Otherwise, this pin use as Digital Data Output.
AVDD
P
Analog Supply (3.3V).
VRB
AO
Reference Decoupling, this pin must be connected to AGND via a decoupling capacitor.
VRT
AO
Reference Decoupling, this pin must be connected to AGND via a decoupling capacitor.
VRX
AO
Reference Decoupling, this pin must be connected to AGND via a decoupling capacitor.
VRLC/VBIAS
AO
Selectable analog output voltage for RLC or single-ended bias reference. This pin would typically be connected to AGND via a decoupling capacitor. VRLC can be externally driven if programmed Hi-z.
VIN
AI
Analog Input
Note:
AI=Analog Input; AO=Analog Output; AIO=Analog Inout
DI=Digital Input; DO=Digital Output; P=Power
Rev. 1.20
2
December 8, 2010
HT82V42
Absolute Maximum Ratings
Supply Voltage ..........................VSS-0.3V to VSS+4.3V
Storage Temperature ...........................-50°C to 125°C
Input Voltage .............................VSS-0.3V to VCC+0.3V
Operating Temperature ..............................0°C to 70°C
Analogue Supply Power ...............................3.0V~3.6V
Digital supply power......................................3.0V~3.6V
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
AVDD=DVDD1=DVDD2=3.3V, AGND=DGND=0V, Ta=25°C, DCLK=30MHz unless otherwise stated.
Symbol
Parameter
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
Overall System Specification (including 16-bit ADC, PGA, Offset and CDS Functions)
VIN
¾
0.27
¾
VP-P
¾
3.0
¾
VP-P
AVDD
V
Full-scale Input Voltage Range
3.3V
(see Note 1)
¾
Input Signal Limits (see Note 2) 3.3V
¾
0
Full-scale Transition Error
3.3V
Gain = 0dB;
PGA[7:0] = 54(hex)
¾
50
¾
mV
Zero-scale Transition Error
3.3V
Gain = 0dB;
PGA[7:0] = 54(hex)
¾
50
¾
mV
DNL
Differential non-Linearity
3.3V
¾
¾
1.5
¾
LSB
INL
Integral non-Linearity
3.3V
¾
¾
50
¾
LSB
Min Gain
3.3V
¾
7
Total Output Noise
¾
Max Gain
¾
18
¾
LSB
rms
References
VRT
Upper Reference Voltage
¾
1.90
2.00
2.20
V
VRB
Lower Reference Voltage
¾
0.90
1.00
1.20
V
VRX
Input Return Bias Voltage
¾
¾
1.70
¾
V
VRTB
Diff. Reference Voltage
(VRT-VRB)
¾
0.9
1.0
1.1
V
¾
¾
4
¾
bits
¾
0.159
0.173
0.187
V/step
¾
0.096
0.11
0.124
V/step
¾
0.35
0.4
0.45
V
¾
0.35
0.40
0.45
V
Reset-Level Clamp (RLC) circuit/ Reference Level DAC
Reference RLCDAC Resolution
VRLCSTEP
Reference RLCDAC Step Size
RLCDACRNG=0
VRLCBOT
Reference RLCDAC Step Size
RLCDACRNG=1
VRLCBOT
Reference RLCDAC Output
Voltage at Code 0(hex),
RLCDACRNG=0
VRLCTOP
Reference RLCDAC Output
Voltage at Code 0(hex),
RLCDACRNG=1
Rev. 1.20
3.3V
3.3V
3
December 8, 2010
HT82V42
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
2.8
3.0
3.10
V
1.90
2.00
2.10
V
Resolution
¾
8
¾
bits
DNL
Differential Non-Linearity
¾
0.1
0.5
LSB
INL
Integral Non-Linearity
¾
0.25
1.00
LSB
Step Size
¾
2.46
¾
mV/step
¾
-315
¾
mV
¾
+315
¾
mV
¾
8
¾
bits
VRLCTOP
Parameter
Reference RLCLDAC Output
Voltage at Code F(hex),
RLCDACRNG=0
VDD
Conditions
3.3V
Reference RLCDAC Output
VRLCSTEP Voltage at Code F(hex),
RLCDACRNG=1
Offset DAC, Monotonicity Guaranteed
Output Voltage
Programmable Gain Amplifier
Resolution
Gain Equation
186/(278-PGA[7:0])
V/V
GMAX
Max Gain
6.50
8.00
8.40
V/V
GMIN
Min Gain
0.65
0.68
0.75
V/V
¾
2
¾
%
Resolution
¾
16
¾
bits
Speed
¾
¾
15
MSPS
Full-scale Input Range
(2*(VRT-VRB))
¾
2
¾
V
Gain Error
Analogue to Digital Converter
Digital Inputs
VIH
High Level Input Voltage
0.7VDD
¾
¾
V
VIL
Low Level Input Voltage
¾
¾
0.2VDD
V
IIH
High Level Input Current
¾
¾
1
mA
IIL
Low Level Input Current
¾
¾
1
mA
CI
Input Capacitance
¾
5
¾
pF
Digital Outputs
VOH
High Level Output Voltage
IOH=1mA
DVDD-0.5
¾
¾
V
VOL
Low Level Output Voltage
IOL=1mA
¾
¾
0.5
V
IOZ
High Impedance Output Current
¾
¾
1
mA
Supply Currents
Rev. 1.20
Total Supply Current - Active
(Signal Channel Mode)
LINEBYLINE=1
DCLK=30MHz
¾
57
¾
mA
Total Analog Supply Current Active (Signal Channel Mode)
LINEBYLINE=1
DCLK=30MHz
¾
36
¾
mA
Digital Supply Current - Active
(DVDD1)
DCLK=30MHz
¾
14
¾
mA
4
December 8, 2010
HT82V42
Symbol
Parameter
Test Conditions
VDD
Digital Supply Current - Active
(DVDD2)
Conditions
DCLK=30MHz
Supply Current - Full Power
Down Mode
Note:
Min.
Typ.
Max.
Unit
¾
7
¾
mA
¾
300
¾
mA
1. Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC
full-scale input range.
2. Input signal limits are the limits within which the full-scale input voltage signal must lie.
A.C. Characteristics
AVDD=DVDD1=DVDD2=3.3V, AGND=DGND=0V, Ta=25°C, DCLK=30MHz unless otherwise stated.
Symbol
Parameter
Conversion Rate
Test Conditions
VDD
Conditions
3.3V
¾
Min.
Typ.
Max.
Unit
¾
¾
15
MSPS
Input Video Timing
AVDD=DVDD1=DVDD2=3.3V, AGND=DGND=0V, Ta=25°C, DCLK=30MHz unless otherwise stated.
Symbol
Parameter
Min.
Typ.
Max.
Unit
tPER
DCLK period
33.3
¾
¾
ns
tDCLKH
DCLK high period
16.6
¾
¾
ns
tDCLKL
DCLK low period
16.6
¾
¾
ns
tVSMPSU
CDSCLK2 setup time
6
¾
¾
ns
tVSMPH
CDSCLK2 hold time
3
¾
¾
ns
tVSU
Video level setup time
10
¾
¾
ns
tVH
Video level hold time
3
¾
¾
ns
tRSU
Reset level setup time
10
¾
¾
ns
tRH
Reset level setup time
3
¾
¾
ns
Note : 1. tVSU and tRSU denote the setup time require after the input video signal has settled.
2. Parameters are measured at 50% of the rising/falling edge.
Rev. 1.20
5
December 8, 2010
HT82V42
Output Data Timing
Output Data Timing
AVDD=DVDD1=DVDD2=3.3V, AGND=DGND=0V, Ta=25°C, DCLK=30MHz unless otherwise stated.
Symbol
tPD
Parameter
Output propagation delay
Min.
Typ.
Max.
Unit
¾
¾
16
ns
Auto Cycle Timing
AVDD=DVDD1=DVDD2=3.3V, AGND=DGND=0V, Ta=25°C, DCLK=30MHz unless otherwise stated.
Symbol
Parameter
Min.
Typ.
Max.
Unit
tCYCSU
Auto cycle setup time
6
¾
¾
ns
tACYCH
Auto cycle hold time
3
¾
¾
ns
Rev. 1.20
6
December 8, 2010
HT82V42
Serial Interface
Serial Interface Timing
AVDD=DVDD1=DVDD2=3.3V, AGND=DGND=0V, Ta=25°C, DCLK=30MHz unless otherwise stated.
Symbol
Parameter
Min.
Typ.
Max.
Unit
tSPER
SCK period
37.6
¾
¾
ns
tSCKH
SCK high
18.8
¾
¾
ns
tSCKLz
SCK low
18.8
¾
¾
ns
tSSU
SDI setup time
6
¾
¾
ns
tSH
SDI hold time
6
¾
¾
ns
tSCE
SCK to SEN setup time
12
¾
¾
ns
tSEC
SEN to SCK setup time
12
¾
¾
ns
tSEW
SEN pulse width
25
¾
¾
ns
tSERD
SEN low to SDO = Register data
¾
¾
30
ns
tSCRD
SCK low to SDO = Register data
¾
¾
30
ns
tSCRDZ
SCK low to SDO = ADC data
¾
¾
30
ns
Note: Parameters are measured at 50% of the rising/falling edge.
Rev. 1.20
7
December 8, 2010
HT82V42
System Architecture
Introduction
· Colour Line-by-Line
A device block diagram showing the signal paths present is provided. The HT82V42 samples a single channel
input VIN. The device then processes the sampled video
signal with respect to the video reset level or an internally/externally generated reference level for signal processing. The processing channel consists of an Input
Sampling block with optional Reset Level Clamping
(RLC) and Correlated Double Sampling (CDS), an 8-bit
programmable offset DAC and an 8-bit Programmable
Gain Amplifier (PGA). The ADC then converts this analogue signal to a 16-bit digital word. The digital output
from the ADC is presented on a 4-bit wide bus. On-chip
control registers determine the configuration of the device, including the offsets and gains applied to R/G/B
signal. These registers are programmable via a serial
interface.
A single chosen input (Red, Green and Blue) is sampled and multiplexed into the analogue channel for
processing before being converted by the ADC. The
input selected can be switched in turn (Red ® Green
® Blue ® Red ¼) together with the PGA and Offset
DAC control registers by pulsing the RLC/ACYC pin.
This is known as auto-cycling. Alternatively, other
sampling sequences can be generated via the control
registers. Refer to the Line-by-Line Operation section
for more details.
Clamp Voltage
The device contains an integrated single 4-bit DAC
which is controlled by register setting for the clamp voltage. The internal clamp is sampled on the positive edge
of DCLK that occurs during each CDSCLK2 pulse. The
sampled level, high (or low) controls the presence (or
absence) of the internal CL pulse on the next reset level.
The position of CL can be adjusted by using control bits
CDSREF[1:0].
Input Sampling
The HT82V42 can sample and process the input analogue signals as follows:
· Monochrome
A single chosen input VIN is sampled, processed by
the corresponding channel, and converted by the
ADC. The choice of input can be changed via the control interface, e.g. on a line-by-line basis if required.
Reset Sample and Clamp Timing
Rev. 1.20
8
December 8, 2010
HT82V42
CDS/CIS Processing
of the PGA gain versus PGA register code. The coding
for the PGA registers is a straight binary number, with all
zero words corresponding to the minimum gain setting
(0.68x) and all one words corresponding to the maximum gain setting (8x).
For CCD type input signals, the time at which the reset
level is sampled, is adjustable by setting control bits
CDSREF[1:0] as shown in the previous figure.
For CIS type input signals, non-CDS processing is
used. During this case, the video level is processed with
the voltage level on VRLC/VBIAS, the pin VRLC/VBIAS
is generated internally or externally. The VRLC/VBIAS
is sampled by Rs at the same time as Vs samples the
video level in this mode.
The PGA has a gain range from 0.68x (-3.3dB) to 8x
(18dB), adjustable in 256 steps. The Figure shows the
PGA gain as a function of the PGA register code. Although the gain curve is approximately linear in dB, the
gain in V/V varies in nonlinear proportion with the register code, according to the following the equation:
PGA Gain Registers
Gain (V/V) = 186 / (278-PGA[7:0])
There are three PGA registers which are used to individually program the gain. Bits D7 through D0 control the
gain range in 256 increments. See the figure for a graph
Gain (dB) = 20LOG10 (186/(278-PGA[7:0]))
PGA Gain Register Settings
D7
D6
D5
D4
D3
D2
D1
D0
Gain(V/V) Gain (dB)
MSB
LSB
0
0
0
0
0
0
0
0
0.68
-3.3
0
1
0
1
1
1
0
1
1
0
0
0
0
0
0
1
0*
0
2.23
7
1
1
1
0
0
0
0
0
3.50
10.8
1
1
1
1
1
1
1
1
8
18
Note: * Power-on default value
Rev. 1.20
9
December 8, 2010
HT82V42
Offset Registers
There are three offset registers used to individually program the offset. Bits D7 through D0 control the offset range from
-315mV to 315mV in 256 increments.
The Table shows the offset range as a function of the bits D7 through D0.
D7
D6
D5
D4
D3
D2
D1
MSB
0
0
0
0
0
0
0
D0
LSB
Offset
(mV)
0
-315
:
:
1
0
0
0
:
:
0
0
0
0*
:
:
1
1
1
1
0
:
:
1
1
1
1
+315
Note :*Power-on default value
Offset Register Settings
ADC Input Black Level Adjust
The offset DAC block then adds the amount of fine offset
adjustment required to move the black level of the input
signal towards 0V, producing V2.
The output from the PGA should be offset to match the
full-scale range of the ADC (VFS=2.0V). For negative-going input video signals, a black level (zero differential) output from the PGA should be offset to the top of
the ADC range by setting register bits PGAFS[1:0]=10.
For positive going input signal the black level should be
offset to the bottom of the ADC range by setting
PGAFS[1:0]=11. Bipolar input video is accommodated
by setting PGAFS[1:0]=00 or PGAFS[1:0]=01 (zero differential input voltage gives mid-range ADC output).
The PGA block then amplifies the white level of the input
signal to maximise the ADC range, outputting voltage
V3.
The ADC block then converts the analogue signal, V3,
to a 16-bit unsigned digital output, D1. The digital output
is then inverted, if required, through the output invert
block to produce D2.
Calculating Output for any Given Input
Overall Signal Flow Summary
The following equations describe the processing of the
video and reset level signals through the HT82V42. The
values of V1, V2 and V3 are often calculated in reverse
order during device setup. The PGA value is written first
to set the input Voltage range, the Offset DAC is then
adjusted to compensate for any Black/Reset level offsets and finally the RLC DAC value is set to position the
reset level correctly during operation.
The input sampling block produces an effective input
voltage V1. For CDS, this is the difference between the
input video level VIN and the input reset level VRESET.
For non-CDS this is the difference between the input
video level VIN and the voltage on the VRLC/VBIAS pin,
VVRLC, optionally set via the RLC DAC.
Overall Signal Flow
Rev. 1.20
10
December 8, 2010
HT82V42
Input Sampling Block: Input Sampling and Referencing
If CDS = 1, (i.e. CDS operation) the previously sampled reset level, VRESET, is subtracted from the input video.
V1 = VIN - VRESET...................................................................Eqn. 1
If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted instead.
V1 = VIN - VVRLC .....................................................................Eqn. 2
If VRLCEXT = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS.
If VRLCEXT = 0, VVRLC is the output from the internal RLC DAC.
VVRLC = (VRLCSTEP ´ RLCV[3:0]) + VRLCBOT....................Eqn. 3
VRLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC.
OFFSET DAC Block: OFFSET (BLACK - LEVEL) Adjust
The resultant signal V1 is added to the Offset DAC output.
V2 = V1 + { 315mV ´ (DAC[7:0] - 127.5) } / 127.5.....................Eqn. 4
PGA NODE: GAIN Adjust
The signal is then multiplied by the PGA gain,
V3 = V2 ´ [186 / (278 - PGA[7:0] ) ]...........................................Eqn. 5
ADC Block: Analogue-Digital Conversion
The analogue signal is then converted to a 16-bit unsigned number, with input range configured by PGAFS[1:0].
D1[15:0] = INT{ (V3 /VFS) ´ 65535} + 32767
PGAFS[1:0] = 00 or 01 .................Eqn. 6
D1[15:0] = INT{ (V3 /VFS) ´ 65535}
PGAFS[1:0] = 11 ..........................Eqn. 7
D1[15:0] = INT{ (V3 /VFS) ´ 65535} + 65535
PGAFS[1:0] = 10 ..........................Eqn. 8
where the ADC full-scale range, VFS = 2.0V
if D1[15:0] < 0
D1[15:0] = 0
if D1[15:0] > 65535
D1[15:0] = 65535
Output Invert Block: Polarity Adjust
The polarity of the digital output may be inverted by control bit INVOP.
D2[15:0] = D1[15:0]
(INVOP = 0).....................................................Eqn. 9
D2[15:0] = 65535 - D1[15:0]
(INVOP = 1)...................................................Eqn. 10
Output Formats
M C L K
Latency of valid output data with respect to CDSCLK2 is
programmable by writing to control bits DEL[1:0]. The
latency for each mode is shown in the Operating Mode
Timing Diagrams section. Figure shows the output data
formats for Modes 1, 3 and 4. Figure shows the output
data formats for Mode 2. Table summarizes the output
data obtained for each format.
4 + 4 + 4 + 4 - B it
O u tp u t
A
B
A
B
C
Output Data Formats (Mode 2)
Output Format
Output Pins
Output
M C L K
4+4+4+4-Bit
(Nibble)
4 + 4 + 4 + 4 - B it
O u tp u t
A
B
C
A= d15~d12
B= d11~d8
C= d7~d4
D= d3~d0
OD3~OD0
D
Details of Output Data
Output Data Formats (Mode 1, 3, 4)
Rev. 1.20
D
11
December 8, 2010
HT82V42
Serial Interface Register Write
Control Interface
Timing Requirement
The internal control registers are programmed via the
serial digital control interface. The register contents can
be read back via the serial interface on pin OD3/SDO. It
is recommended that a software reset is carried out after
the power-up sequence, before writing to any other register. This ensures that all registers are set to their default values
To use this device a master clock (DCLK) of up to
30MHz and a per-pixel synchronisation clock
(CDSCLK2) of up to 15MHz are required. These clocks
drive a timing control block, which produces internal signals to control the sampling of the video signal. The
DCLK to CDSCLK2 ratios and maximum sample rates
for the various modes are shown in Table.
Serial Interface - Register Write
Programmable CDSCLK2 Detect Circuit
Figure shows the register writing in serial mode. Three
pins, SCK, SDI and SEN are used. A six-bit address (a5,
a4, a3, a2, a1, a0) is clocked in through SDI, MSB first,
followed by an eight-bit data word (b7, b6, b5, b4, b3,
b2, b1, b0), also MSB first. Each bit is latched on the rising edge of SCK. When the data has been shifted into
the device, a pulse is applied to SEN to transfer the data
to the appropriate internal register. Note all valid registers have address bit a4 equal to 0 in the write mode.
The CDSCLK2 input is used to determine the sampling
point and frequency of the HT82V42. Under normal operation a pulse of 1 DCLK period should be applied to
CDSCLK2 at the desired sampling frequency (as shown
in the Operating Mode Timing Diagrams) and the input
sample will be taken on the first rising DCLK edge after
CSDCLK2 has gone low. However, in certain applications such a signal may not be readily available. The
programmable CDSCLK2 detect circuit in the HT82V42
allows the sampling point to be derived from any signal
of the correct frequency, such as a CCD shift register
clock, when applied to the CDSCLK2 pin. When enabled, by setting the VSMPDET control bit, the circuit
detects either a rising or falling edge (determined by the
POSNNEG control bit) on the CDSCLK2 input pin and
generates an internal VSMP pulse. This pulse can optionally be delayed by a number of DCLK periods, specified by the VDEL[2:0] bits. Figure shows the internal
VSMP pulses that can be generated by this circuit for a
typical clock input signal. The internal VSMP pulse is
then applied to the timing control block in place of the
normal CDSCLK2 pulse provided from the input pin.
The sampling point then occurs on the first rising DCLK
edge after this internal VSMP pulse, as shown in the Operating Mode Timing Diagrams.
A software reset is carried out by writing to Address
²000100² with any value of data, i.e. Data Word =
XXXXXXXX.
Serial Interface - Register Read-back
Figure shows register read-back in serial mode.
Read-back is initiated by writing to the serial bus as described above but with address bit a4 set to 1, followed
by an 8-bit dummy data word. Writing address (a5, 1,
a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4,
d3, d2, d1, d0) of the corresponding register (a5, 0, a3,
a2, a1, a0) to be output MSB first on pin SDO (on the
falling edge of SCK). Note that pin SDO is shared with
an output pin, OD3. It must be noted that when reading
from a register the OD3 pin function will be disabled and
cannot be read by the external MCU. The next word
may be read in to SDI while the previous word is still being output on SDO.
Serial Interface Register Read-back
Rev. 1.20
12
December 8, 2010
HT82V42
Internal VSMP Pulse Generated by Programmable Internal Sample Detect Circuit
References
Line-by-Line Operation
The ADC reference voltages are derived from an internal bandgap reference, and buffered to pins VRT and
VRB, where they must be decoupled to ground. Pin
VRX is driven by a similar buffer, and also requires decoupling. The output buffer from the RLCDAC also requires decoupling at pin VRLC/VBIAS.
Certain linear sensors (e.g. Contact Image Sensors)
give a colour output on a line-by-line basis. i.e. a full line
of red pixels followed by a line of green pixels followed
by a line of blue pixels.
In this mode the input multiplexer and (optionally) the
PGA/Offset register multiplexers can be auto-cycled by
the application of pulses to the RLC/ACYC input pin by
setting the ACYCNRLC register bit. See Figure for detailed timing information. The multiplexers change on
the first DCLK rising edge after RLC/ACYC is taken
high. A write to the auto-cycle reset register causes
these multiplexers to be reset, selecting the colour R
and the RED offset/gain registers. Alternatively, all three
multiplexers can be controlled via the serial interface by
writing to register bits INTM[1:0] to select the desired
colour. It is also possible for the input multiplexer to be
controlled separately from the PGA and Offset
multiplexers. Table describes all the multiplexer selection modes that are possible.
Power Supply
The HT82V42 can run from a single 3.3V single supply.
Power Management
Power management for the device is performed via the
Control Interface. The device can be powered on or off
completely by clearing the EN bit low.
All the internal registers maintain their previously programmed value in the power down mode while the Serial Interface inputs remain active.
Rev. 1.20
13
December 8, 2010
HT82V42
ACYCNRLC
Name
Description
0
Internal no force mux
Input mux, offset and gain registers determined by internal register bits
INTM1, INTM0.
1
Auto-cycling, no force mux
Input mux, offset and gain registers auto-cycled, RINP ® GINP ®
BINP ® RINP ¼ on RLC/ACYC pulse.
Colour Selection Description in Line-by-Line Mode
Operating Modes
Mode
1
2
Description
Monochrome/Colour
Line-by-Line
Fast Monochrome/
Colour Line-by-Line
CDS
Yes
Yes
Maximum speed
3
Monochrome/Colour
No
Line-by-Line
4
Slow Monochrome/
Colour Line-by-Line
Yes
Max.
Sample
Rate
5
MSPS
10
MSPS
15
MSPS
3.75
MSPS
Sensor Interface
Description
Timing
Requirement
Register Contents
With CDS
Register Contents
Without CDS
Only one input channel DCLK = 30MHz
at a time is
DCLK: CDSCLK2
continuously sampled.
ratio is 6:1
Identical to mode 1
Identical to mode 1
DCLK: CDSCLK2
plus SetReg3: bits 5:4
ratio is 3:1
must be set to 0 (h)
DCLK: CDSCLK2
CDS not possible
ratio is 2:1
DCLK = 30MHz
Identical to mode 1
2D(h)
DCLK = 30MHz
DCLK = 30MHz
Identical to mode 1
SetReg1:
SetReg1 : 3F(h)
DCLK: CDSCLK2
ratio is 2n:1, n>=4
Identical to mode 1
Identical to
mode 1
SetReg1:
6D(h)
Identical to
mode 1
HT82V42 Operating Modes
Operating Mode Timing Diagrams
The following diagrams show 4-bit multiplexed output data and DCLK, CDSCLK2 and input video requirements for
most common operations as shown in Table.
Mode 1 Operation
Rev. 1.20
14
December 8, 2010
HT82V42
Mode 2 Operation
Mode 3 Operation
Mode 4 Operation
Rev. 1.20
15
December 8, 2010
HT82V42
Device Configuration
· Register Map
The following table describes the location of each control bit used to determine the device operation. The register
map is programmed by writing the required codes to the appropriate address via the serial interface.
Address
Description
DEF
R/W
(h)
Bit
7
6
5
4
3
2
1
0
000001 Setup Reg 1
0F
R/W
0
Mode3
PGAFS[1]
PGAFS[0]
1
1
CDS
EN
000010 Setup Reg 2
23
R/W
DEL[1]
DEL[0]
RLCDACRNG
0
VRLCEXT
INVOP
1
1
000011 Setup Reg 3
1F
R/W
0
0
CDSREF[1]
CDSREF[0]
RLVC[3]
RLVC[2]
RLVC[1]
RLVC[0]
000100 Software Reset
00
¾
¾
¾
¾
¾
¾
¾
¾
¾
000101 Auto-cycle Reset
00
¾
¾
¾
¾
¾
¾
¾
¾
¾
000110 Setup Reg 4
05
R/W
0
0
INTM[1]
INTM[0]
RLCINT
1
000111 Revision Number
41
R
¾
¾
¾
¾
¾
¾
¾
¾
001000 Setup Reg 5
00
R/W
0
0
0
PSENNEG
VDEL[2]
VDEL[1]
VDEL[0]
VSMPDET
001001 Setup Reg 6
00
R/W
ClkMotr
0
0
0
0
0
0
0
001010 Reserved
01
R
0
0
0
0
0
0
0
0
001011 Reserved
01
R
0
0
0
0
0
0
0
0
001100 Reserved
01
R
0
0
0
0
0
0
0
0
100000 Red Offset Value
80
R/W
RO[7]
RO[6]
RO[5]
RO[4]
RO[3]
RO[2]
RO[1]
RO[0]
100001 Green Offset Value
80
R/W
GO[7]
GO[6]
GO[5]
GO[4]
GO[3]
GO[2]
GO[1]
GO[0]
100010 Blue Offset Value
80
R/W
BO[7]
BO[6]
BO[5]
BO[4]
BO[3]
BO[2]
BO[1]
BO[0]
100011 RGB Offset Value
80
R/W
RGBO[7]
RGBO[6]
RGBO[5]
RGBO[4]
RGBO[3]
RGBO[2]
RGBO[1]
RGBO[0]
101000 Red PGA Gain
5C
R/W
RPGA[7]
RPGA[6]
RPGA[5]
RPGA[4]
RPGA[3]
RPGA[2]
RPGA[1]
RPGA[0]
101001 Green PGA Gain
5C
R/W
GPGA[7]
GPGA[6]
GPGA[5]
GPGA[4]
GPGA[3]
GPGA[2]
GPGA[1]
GPGA[0]
101010 Blue PGA Gain
5C
R/W
BPGA[7]
BPGA[6]
BPGA[5]
BPGA[4]
BPGA[3]
BPGA[2]
BPGA[1]
BPGA[0]
101011 RGB PGA Gain
5C
W
Rev. 1.20
ACYCNRLC LINEBYLINE
RGBPGA[7] RGBPGA[6] RGBPGA[5] RGBPGA[4] RGBPGA[3] RGBPGA[2] RGBPGA[1] RGBPGA[0]
16
December 8, 2010
HT82V42
· Register Map Description
Register
Bit
No.
Bit Name
POR
0
EN
1
0: Complete power down
1: fully active
1
CDS
1
Select correlated double sampling mode.
0: non-CDS mode
1: CDS mode
2
Reserved
1
Default 1
3
Reserved
1
Default 1
PGAFS[1:0]
0
Adjust PGA output to optimize the ADC range for different polarity sensor output signals. Zero differential PGA input signal
gives.
00: Zero output (use for bipolar video)
01: Zero output
10: Full-scale positive output (use for negative going video)
11: Full-scale negative output (use for positive going video)
6
Mode3
0
Mode3 setting
1: Mode3 enable
2
INVOP
0
Digitally inverts the polarity of output data
0: negative going video gives negative going output
1: negative going video gives positive going output
3
VRLCEXT
0
Setting this bit high, changes VRLC/VBIAS to Hi-Z, allowing
VRLC/VBIAS to be driven from an external power source.
5
RLCDACRN
G
1
Sets the output range of the RLCDAC.
0: RLCDAC ranges from 0 to AVDD.
1: RLCDAC ranges from 0 to VRT
00
Sets the output latency for the ADC clock periods.
1 ADC clock=2 DCLK periods. Under mode3, 1 ADC clock=3
DCLK periods.
00: Minimum latency
01: Delay by 1 ADC clock
10: Delay by 2 ADC clock
11: Delay by 3 ADC clock
1111
Controls RLCDAC driving The VRLC pin defines the single
ended signal reference voltage or Reset Level Clamp Voltage. Refer to the Electrical Characteristic section for details.
Setup Register 1
5~4
Setup Register 2
7~6
DEL[1:0]
3~0
RLVC[3:0]
5~
CDSREF[1:0]
01
Adjust reset timing under CDS mode
00: Advance 1 DCLK period
01: Normal
10: Retard 1 DCLK
11: Retard 2 DCLK
7~6
Reserved
00
Reserved
Setup Register 3
Software Reset
Rev. 1.20
Description
Any write to this register will cause all functions to be reset. It
is recommended to execute a software reset after each power
on reset and before any other register writes. When this register is written, the reset function will be initiated immediately by
an internal reset signal. If the DCLK exists, the internal reset
signal will keep active for about 2 DCLK cycles. Otherwise,
the device will keep in reset state all the time.
17
December 8, 2010
HT82V42
Register
Bit
No.
Bit Name
POR
Writing to this register will cause the auto-cycle counter to be
reset to colour R. This function is only required when
LINEBYLINE=1. When this register is written, the reset function will be initiated immediately by an internal reset signal. If
the DCLK exists, the internal reset signal will keep active for
about 2 DCLK cycles. Otherwise, the device will keep in reset
state all the time.
Auto-cycle Reset
0
1
LINEBYLINE
ACYCNRLC
1
Select line by line mode
0: normal operation
1: line by line operation
0
When LINEBYLINE=0, this bit has no effect
When LINEBYLINE=1, this bit controls the function of the
RLC/ACYC input signal and will control the multiplexer of the
offset/gain register.
0: RLC/ACYC pin enabled for Reset Level Clamp, internal selection of input and offset/gain multiplexers.
1: Auto cycling enabled by pulsing the RLC/ACYC input pin.
0
This bit is used to determine whether the Reset Level
Clamping is used.
0: RLC disable
1: RLC enable
00
Colour selection bits used for internal modes.
00: Red
01: Green
10: Blue
11: Reserved
0
0: Normal operation, signal on the CDSCLK2 input pin is applied directly to the Timing Control Block
1: Programmable CDSCLK2 detect circuit is enabled. An internal synchronization pulse is generated from the signal
applied to the CDSCLK2 input pin and is applied to the Timing
Control Block.
000
When VSMPDEL=0, these bits have no effect.
When VSMPDEL=1, these bits set the programmable delay
from the detected edge of the signal on CDSCLK2. The internal generated pulse is delayed by VDEL DCLK periods from
the detected edge.
0
When VSMPDEL=0, this bit has no effect
When VSMPDEL=1, this bit controls whether positive or negative edges are detected.
0: Negative edge on the CDSCLK2 pin is detected and used to
generate an internal timing pulse
1: Positive edge on the CDSCLK2 pin is detected and used to
generate an internal timing pulse
Setup Register 4
3
5~4
0
Setup Register 5
Description
3~1
4
RLCINT
INTM[1:0]
VSMPDET
VDEL[2:0]
POSNNEG
Internal clock monitor.
0: normal active, OD[3:0] output ADC data.
1: internal clock test mode.
Setup Register 6
Rev. 1.20
7
ClkMotr
0
18
Pin
ClkMotr=0
ClkMotr=1
OD3
OD3
INTVSMP
OD2
OD2
Video sample clock
OD1
OD1
ADC clock
OD0
OD0
Reset sample clock
December 8, 2010
HT82V42
Register
Bit
No.
Bit Name
POR
Description
Red Offset Value
7~0
RO
80
Red offset value
Green Offset Value
7~0
GO
80
Green offset value
Blue Offset Value
7~0
BO
80
Blue offset value
RGB Offset Value
7~0
RGBO
80
Writing to this register will overwrite the new value to the
R/G/B Offset value
Red PGA gain
5~0
RPGA
5C
Red PGA value
Green PGA gain
5~0
GPGA
5C
Green PGA value
Blue PGA gain
5~0
BPGA
5C
Blue PGA value
RGB PGA gain
5~0
RGBPGA
5C
Writing to this register will overwrite the new value to the
R/G/B PGA gain value
Application Circuits
Recommended External Components
Note:
1. All capacitors should be located as close to the HT82V42 as possible.
2. AGND and DGND should be connected as close to the HT82V42 as possible.
Rev. 1.20
19
December 8, 2010
HT82V42
Package Information
20-pin SSOP (209mil) Outline Dimensions
1 1
2 0
A
B
1
1 0
C
C '
G
H
D
E
=
F
· MO-150
Symbol
A
Nom.
Max.
0.291
¾
0.323
B
0.197
¾
0.220
C
0.009
¾
0.013
C¢
0.272
¾
0.295
D
¾
¾
0.079
E
¾
0.026
¾
F
0.002
¾
¾
G
0.022
¾
0.037
H
0.004
¾
0.008
a
0°
¾
8°
Symbol
A
Rev. 1.20
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
7.40
¾
8.20
B
5.00
¾
5.60
C
0.22
¾
0.33
C¢
6.90
¾
7.50
D
¾
2.00
E
¾
F
0.05
¾
¾
G
0.55
¾
0.95
H
0.09
¾
0.21
a
0°
¾
8°
0.65
20
¾
December 8, 2010
HT82V42
20-pin TSSOP Outline Dimensions
2 0
1 1
E 1
1
1 0
E
D
L
A
R
A 2
0 .1 0
e
A 1
B
C
G
y
(4 C O R N E R S )
Symbol
Min.
Nom.
Max.
A
0.041
¾
0.047
A1
0.002
¾
0.006
A2
0.037
¾
0.041
B
¾
0.009
¾
C
0.005
¾
0.007
D
0.252
¾
0.260
E
0.248
¾
0.256
E1
0.169
¾
0.177
e
¾
0.026
¾
L
0.018
¾
0.030
y
¾
¾
0.004
q
0°
¾
8°
Symbol
Rev. 1.20
Dimensions in inch
Dimensions in mm
Min.
Nom.
Max.
A
1.05
¾
1.20
A1
0.05
¾
0.15
A2
0.95
¾
1.05
B
¾
0.22
¾
C
0.13
¾
0.17
D
6.40
¾
6.60
E
6.30
¾
6.50
E1
4.30
¾
4.50
e
¾
0.65
¾
L
0.45
¾
0.75
y
¾
¾
0.10
q
0°
¾
8°
21
December 8, 2010
HT82V42
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SSOP 20N (209mil)
Symbol
Description
A
Reel Outer Diameter
B
Reel Inner Diameter
C
Spindle Hole Diameter
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
Dimensions in mm
330.0±1.0
100.0±1.5
13.0
+0.5/-0.2
2.0±0.5
16.8
+0.3/-0.2
22.2±0.2
TSSOP 20L
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330.0±1.0
B
Reel Inner Diameter
100.0±1.5
C
Spindle Hole Diameter
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
Rev. 1.20
13.0
+0.5/-0.2
2.0±0.5
16.4
+0.3/-0.2
19.1 max.
22
December 8, 2010
HT82V42
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
B 0
P
K 0
A 0
R e e l H o le
IC
p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .
SSOP 20N (209mil)
Symbol
Description
Dimensions in mm
16.0
+0.3/-0.1
W
Carrier Tape Width
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.10
F
Cavity to Perforation (Width Direction)
D
Perforation Diameter
7.5±0.1
1.5
1.50
+0.1/-0.0
+0.25/-0.00
D1
Cavity Hole Diameter
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
7.1±0.1
B0
Cavity Width
7.2±0.1
K0
Cavity Depth
2.0±0.1
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
13.3±0.1
TSSOP 20L
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
16.0±0.3
P
Cavity Pitch
8.0±0.1
E
Perforation Position
F
Cavity to Perforation (Width Direction)
D
Perforation Diameter
1.5
+0.1/-0.0
D1
Cavity Hole Diameter
1.5
+0.1/-0.0
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
6.8±0.1
B0
Cavity Width
6.9±0.1
K0
Cavity Depth
1.6±0.1
1.75±0.10
7.5±0.1
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
13.3±0.1
Rev. 1.20
23
December 8, 2010
HT82V42
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2010 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.20
24
December 8, 2010