WOLFSON WM8152CDS

WM8152
Single Channel 16-bit CIS/CCD AFE with 4-bit Wide Output
DESCRIPTION
FEATURES
The WM8152 is a 16-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
sample rates of up to 12MSPS.
The device includes a complete analogue signal processing
channel containing Reset Level Clamping, Correlated
Double Sampling, Programmable Gain and Offset adjust
functions. Internal multiplexers allow fast switching of offset
and gain for line-by-line colour processing. The output from
this channel is time multiplexed into a high-speed 16-bit
Analogue to Digital Converter. The digital output data is
available in 4-bit wide multiplexed format.
An internal 4-bit DAC is supplied for internal reference level
generation. This may be used to reference CIS signals or
during Reset Level Clamping to clamp CCD signals. An
external reference level may also be supplied. ADC
references are generated internally, ensuring optimum
performance from the device.
•
•
16-bit ADC
12MSPS conversion rate
•
•
•
Low power - 225mW typical
5V single supply or 5V/3.3V dual supply operation
Single channel operation
•
•
•
Correlated double sampling
Programmable gain (8-bit resolution)
Programmable offset adjust (8-bit resolution)
•
•
•
Programmable clamp voltage
4-bit wide multiplexed data output format
Internally generated voltage references
•
•
20-pin SSOP package
Serial control interface
APPLICATIONS
Using an analogue supply voltage of 5V, a digital core
voltage of 5V, and a digital interface supply of either 5V or
3.3V, the WM8152 typically only consumes 225mW when
operating from a single 5V supply.
•
Flatbed and sheetfeed scanners
•
•
•
USB compatible scanners
Multi-function peripherals
High-performance CCD sensor interface
BLOCK DIAGRAM
VSMP
RS VS
CL
AVDD
MCLK
M
G U
X
B
RLC
8
OFFSET
DAC
CDS
+
PGA
8
VRLC/VBIAS
R
G
B
VRT VRX VRB
DVDD2
VREF/BIAS
TIMING CONTROL
R
VINP
DVDD1
+
I/P SIGNAL
POLARITY
ADJUST
4
AGND1
WOLFSON MICROELECTRONICS plc
w :: www.wolfsonmicro.com
DATA
I/O
PORT
OP[0]
OP[1]
OP[2]
OP[3]/SDO
M
U
X
W
WM8152
RLC
DAC
16BIT
ADC
AGND2
CONFIGURABLE
SERIAL
CONTROL
INTERFACE
SEN
SCK
SDI
DGND
Production Data, January 2004, Rev 4.0
Copyright 2004 Wolfson Microelectronics plc
WM8152
Production Data
TABLE OF CONTENTS
DESCRIPTION .......................................................................................................1
FEATURES.............................................................................................................1
APPLICATIONS .....................................................................................................1
BLOCK DIAGRAM .................................................................................................1
TABLE OF CONTENTS .........................................................................................2
PIN CONFIGURATION...........................................................................................3
ORDERING INFORMATION ..................................................................................3
PIN DESCRIPTION ................................................................................................4
ABSOLUTE MAXIMUM RATINGS.........................................................................5
RECOMMENDED OPERATING CONDITIONS .....................................................5
ELECTRICAL CHARACTERISTICS ......................................................................6
INPUT VIDEO SAMPLING ............................................................................................. 8
OUTPUT DATA TIMING ................................................................................................ 8
SERIAL INTERFACE ..................................................................................................... 9
DEVICE DESCRIPTION.......................................................................................10
INTRODUCTION.......................................................................................................... 10
INPUT SAMPLING ....................................................................................................... 10
RESET LEVEL CLAMPING (RLC) ............................................................................... 10
CDS/NON-CDS PROCESSING ................................................................................... 11
OFFSET ADJUST AND PROGRAMMABLE GAIN....................................................... 12
ADC INPUT BLACK LEVEL ADJUST .......................................................................... 13
OVERALL SIGNAL FLOW SUMMARY ........................................................................ 13
CALCULATING OUTPUT FOR ANY GIVEN INPUT .................................................... 13
OUTPUT DATA FORMAT............................................................................................ 15
CONTROL INTERFACE .............................................................................................. 16
TIMING REQUIREMENTS ........................................................................................... 16
PROGRAMMABLE VSMP DETECT CIRCUIT ............................................................. 17
REFERENCES............................................................................................................. 18
POWER SUPPLY ........................................................................................................ 18
POWER MANAGEMENT ............................................................................................. 18
OPERATING MODES .................................................................................................. 18
OPERATING MODE TIMING DIAGRAMS ................................................................... 19
DEVICE CONFIGURATION .................................................................................21
REGISTER MAP .......................................................................................................... 21
REGISTER MAP DESCRIPTION ................................................................................. 22
APPLICATIONS INFORMATION .........................................................................24
RECOMMENDED EXTERNAL COMPONENTS........................................................... 24
RECOMMENDED EXTERNAL COMPONENTS VALUES............................................ 24
PACKAGE DIMENSIONS ....................................................................................25
IMPORTANT NOTICE ..........................................................................................26
ADDRESS:................................................................................................................... 26
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PIN CONFIGURATION
AGND2
1
20
VINP
DVDD1
2
19
VRLC/VBIAS
VSMP
3
18
VRX
MCLK
4
17
VRT
DGND
5
16
VRB
15
AGND1
WM8152
SEN
6
DVDD2
7
14
AVDD
SDI
8
13
OP[3]/SDO
SCK
9
12
OP[2]
OP[0]
10
11
OP[1]
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
MOISTURE
SENSITIVITY LEVEL
WM8152CDS
0 to 70oC
20-pin SSOP
MSL1
WM8152SCDS
0 to 70oC
20-pin SSOP
(lead free)
MSL1
WM8152CDS/R
0 to 70oC
20-pin SSOP
(tape and reel)
MSL1
WM8152SCDS/R
0 to 70oC
20-pin SSOP
(lead free, tape and reel)
MSL1
Note:
Reel quantity = 2,000
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PIN DESCRIPTION
PIN
NAME
TYPE
1
AGND2
Supply
DESCRIPTION
Analogue ground (0V).
2
DVDD1
Supply
Digital core (logic and clock generator) supply (5V)
3
VSMP
Digital input
Video sample synchronisation pulse.
4
MCLK
Digital input
Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or
any multiple of 2 thereafter depending on input sample mode).
5
DGND
Supply
6
SEN
Digital input
7
DVDD2
Supply
8
SDI
Digital input
Serial data input.
9
SCK
Digital input
Serial clock.
Digital ground (0V).
Enables the serial interface when high.
Digital supply (5V/3.3V), all digital I/O pins.
Digital multiplexed output data bus.
ADC output data (d15:d0) is available in 4-bit multiplexed format as shown below.
A
B
C
D
10
OP[0]
Digital output
d12
d8
d4
d0
11
OP[1]
Digital output
d13
d9
d5
d1
12
OP[2]
Digital output
d14
d10
d6
d2
13
OP[3]/SDO
Digital output
d15
d11
d7
d3
Alternatively, pin OP[3]/SDO may be used to output register read-back data when
address bit 4=1 and SEN has been pulsed high. See Serial Interface description in
Device Description section for further details.
14
AVDD
Supply
Analogue supply (5V)
15
AGND1
Supply
Analogue ground (0V).
16
VRB
Analogue output
Lower reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
17
VRT
Analogue output
Upper reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
18
VRX
Analogue output
Input return bias voltage.
This pin must be connected to AGND via a decoupling capacitor.
19
VRLC/VBIAS
Analogue I/O
20
VINP
Analogue input
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Selectable analogue output voltage for RLC or single-ended bias reference.
This pin would typically be connected to AGND via a decoupling capacitor.
VRLC can be externally driven if programmed Hi-Z.
Video input.
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Production Data
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
MIN
MAX
Analogue supply voltage: AVDD
GND - 0.3V
GND + 7V
Digital core voltage: DVDD1
GND - 0.3V
GND + 7V
Digital IO supply voltage: DVDD2
GND - 0.3V
GND + 7V
Digital ground: DGND
GND - 0.3V
GND + 0.3V
Analogue grounds: AGND1 − 2
GND - 0.3V
GND + 0.3V
Digital inputs, digital outputs and digital I/O pins
GND - 0.3V
DVDD2 + 0.3V
Analogue input (VINP)
GND - 0.3V
AVDD + 0.3V
Other pins
GND - 0.3V
AVDD + 0.3V
0°C
+70°C
-65°C
+150°C
Operating temperature range: TA
Storage temperature after soldering
Package body temperature (soldering, 10 seconds)
+260°C
Package body temperature (soldering, 2 minutes)
+183°C
Notes:
1.
GND denotes the voltage of any ground pin.
2.
AGND1, AGND2 and DGND pins are intended to be operated at the same potential. Differential voltages
between these pins will degrade performance.
RECOMMENDED OPERATING CONDITIONS
CONDITION
Operating temperature range
Analogue supply voltage
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MIN
TA
0
TYP
MAX
UNITS
70
°C
AVDD
4.75
5.0
5.25
V
DVDD1
4.75
5.0
5.25
V
5V I/O
DVDD2
4.75
5.0
5.25
V
3.3V I/O
DVDD2
2.97
3.3
3.63
V
Digital core supply voltage
Digital I/O supply voltage
SYMBOL
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ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25°C, MCLK = 24MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Overall System Specification (including 16-bit ADC, PGA, Offset and CDS functions)
Full-scale input voltage range
(see Note 1)
Max Gain
Min Gain
Input signal limits (see Note 2)
VIN
0.30
3.22
0
Vp-p
Vp-p
VDD
V
Full-scale transition error
Gain = 0dB;
PGA[7:0] = 07(hex)
-50
10
+50
mV
Zero-scale transition error
Gain = 0dB;
PGA[7:0] = 07(hex)
-50
10
+50
mV
Differential non-linearity
DNL
1.25
LSB
Integral non-linearity
INL
25
LSB
4.5
14
LSB rms
LSB rms
V
Total output noise
Min Gain
Max Gain
References
Upper reference voltage
VRT
2.70
Lower reference voltage
VRB
1.45
Input return bias voltage
VRX
1.55
1.65
1.75
Diff. reference voltage (VRT-VRB)
VRTB
1.15
1.25
1.35
Output resistance VRT, VRB, VRX
V
V
V
Ω
1
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
20
50
100
Ω
VRLC short-circuit current
1.86
2
4.5
mA
1
µA
0.27
V/step
VRLC output resistance
Ω
2
VRLC Hi-Z leakage current
VRLC = 0 to AVDD
RLCDAC resolution
4
RLCDAC step size, RLCDAC = 0
VRLCSTEP
RLCDAC step size, RLCDAC = 1
VRLCSTEP
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 0
VRLCBOT
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 1
VRLCBOT
RLCDAC output voltage at
code F(hex) RLCDACRNG, = 0
VRLCTOP
RLCDAC output voltage at
code F(hex), RLCDACRNG = 1
VRLCTOP
0.23
0.14
0.16
0.20
V/step
AVDD = 5.0V
0.34
0.39
0.44
V
0.20
0.26
0.31
V
4.0
4.16
4.3
V
2.56
2.66
2.76
V
LSB
AVDD = 5.0V
0.25
bits
AVDD = 5.0V
Offset DAC, Monotonicity Guaranteed
Resolution
8
bits
Differential non-linearity
DNL
0.1
0.5
Integral non-linearity
INL
0.25
1
Step size
Output voltage
2.04
Code 00(hex)
Code FF(hex)
-247
+247
-260
+260
LSB
mV/step
-273
+273
mV
mV
Notes:
1.
Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC input
range.
2.
Input signal limits are the limits within which the full-scale input voltage signal must lie.
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Test Conditions
AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25°C, MCLK = 24MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Programmable Gain Amplifier
Resolution
8
Gain equation
0.78 +
bits
PGA[7 : 0] × 7.57
255
V/V
Max gain
GMAX
6.8
8.35
8.7
V/V
Min gain
GMIN
0.75
0.78
0.82
V/V
1
2
Gain error
Internal channel offset
VOFF
10
%
mV
Analogue to Digital Converter
Resolution
16
Maximum Speed
Full-scale input range
(2*(VRT-VRB))
bits
12
MSPS
2.5
VFS
V
DIGITAL SPECIFICATIONS
Digital Inputs
0.7 ∗ DVDD2
High level input voltage
VIH
Low level input voltage
VIL
High level input current
IIH
1
µA
Low level input current
IIL
1
µA
Input capacitance
CI
V
0.2 ∗ DVDD2
5
V
pF
Digital Outputs
High level output voltage
VOH
IOH = 1mA
Low level output voltage
VOL
IOL = 1mA
DVDD2 - 0.5
V
0.5
V
Supply Currents
Total supply current − active
45
mA
Total analogue AVDD, supply
current − active
IAVDD
41
mA
Total digital core, DVDD1,
supply current − active
IDVDD1
3
mA
Digital I/O supply current,
DVDD2 − active (see note 3)
IDVDD2
3
mA
Supply current − full power down
mode
300
400
µA
Notes:
3.
Digital I/O supply current depends on the capacitive load attached to the pin. The Digital I/O supply current is
measured with approximately 50pF attached to the pin.
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INPUT VIDEO SAMPLING
tPER
tMCLKH tMCLKL
MCLK
tVSMPSU
tVSMPH
VSMP
INPUT
tVSU
tVH
tRSU
tRH
VIDEO
Figure 1 Input Video Timing
Note:
1.
See Page 15 (Programmable VSMP Detect Circuit) for video sampling description.
Test Conditions
VDD = 5.0V, DVDD = 3.3V, AGND = DGND = 0V, TA = 25°C, MCLK = 24MHz unless otherwise stated.
PARAMETER
SYMBOL
MCLK period
tPER
41.6
ns
tMCLKH
18.8
ns
MCLK low period
tMCLKL
18.8
ns
VSMP set-up time
tVSMPSU
6
ns
VSMP hold time
tVSMPH
3
ns
tVSU
10
ns
MCLK high period
Video level set-up time
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Video level hold time
tVH
3
ns
Reset level set-up time
tRSU
10
ns
Reset level hold time
tRH
3
ns
Notes:
1.
2.
tVSU and tRSU denote the set-up time required after the input video signal has settled.
Parameters are measured at 50% of the rising/falling edge.
OUTPUT DATA TIMING
MCLK
tPD
tPD
OP[3:0]
Figure 2 Output Data Timing
Test Conditions
VDD = 5.0V, DVDD = 3.3V, AGND = DGND = 0V, TA = 25°C, MCLK = 24MHz unless otherwise stated.
PARAMETER
Output propagation delay
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SYMBOL
TEST CONDITIONS
tPD
IOH = 1mA, IOL = 1mA
MIN
TYP
MAX
UNITS
20
ns
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Production Data
SERIAL INTERFACE
tSPER
tSCKL tSCKH
SCK
tSSU
tSH
SDI
tSCE
tSEW
tSEC
SEN
tSERD
tSCRD
t SCRDZ
ADC DATA
MSB
SDO
ADC
DATA
LSB
REGISTER DATA
Figure 3 Serial Interface Timing
Test Conditions
VDD = 5.0V, DVDD = 3.3V, AGND = DGND = 0V, TA = 25°C, MCLK = 24MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SCK period
tSPER
41.6
ns
SCK high
tSCKH
18.8
ns
SCK low
tSCKL
18.8
ns
SDI set-up time
tSSU
6
ns
SDI hold time
tSH
6
ns
SCK to SEN set-up time
tSCE
12
ns
SEN to SCK set-up time
tSEC
12
ns
SEN pulse width
tSEW
25
ns
SEN low to SDO = Register data
tSERD
30
ns
SCK low to SDO = Register data
tSCRD
30
ns
SCK low to SDO = ADC data
tSCRDZ
30
ns
Note:
1.
Parameters are measured at 50% of the rising/falling edge
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DEVICE DESCRIPTION
INTRODUCTION
A block diagram of the device showing the signal path is presented on Page 1.
The WM8152 processes the sampled video signal on VINP with respect to the video reset level or an
internally/externally generated reference level through the analogue processing channel.
This processing channel consists of an Input Sampling block with optional Reset Level Clamping
(RLC) and Correlated Double Sampling (CDS), an 8-bit programmable offset DAC and an 8-bit
Programmable Gain Amplifier (PGA).
The ADC then converts each resulting analogue signal to a 16-bit digital word. The digital output from
the ADC is presented on a 4-bit wide bus.
On-chip control registers determine the configuration of the device, including the offsets and gains
applied to each channel. These registers are programmable via a serial interface.
INPUT SAMPLING
The WM8152 has a single analogue processing channel and ADC which can be used in a flexible
manner to process both monochrome and line-by-line colour inputs.
Monochrome: VINP is sampled, processed by the analogue channel, and converted by the ADC.
The same offset DAC and PGA register values are always applied.
Colour Line-by-Line: VINP is sampled and processing by the analogue channel before being
converted by the ADC. The gains and offset register values applied to the PGA and offset DAC can
be switched between the independent Red, Green and Blue digital registers (e.g. Red → Green→
Blue → Red…) at the start of each line in order to facilitate line-by-line colour operation. The
INTM[1:0] bits determine which register contents are applied (see Table 1) to the PGA and offset
DAC. By using the INTM[1:0] bits to select the desired register values only one register write is
required at the start of each new colour line.
RESET LEVEL CLAMPING (RLC)
To ensure that the signal applied to the WM8152 VINP pin lies within the valid input range (0V to
VDD) the CCD output signal is usually level shifted by coupling through a capacitor, CIN. When
active, the RLC circuit clamps the WM8152 side of this capacitor to a suitable voltage during the
CCD reset period. The RLCINT register bit controls is used to activate the Reset Level Clamp circuit.
A typical input configuration is shown in Figure 4. The Timing Control Block generates a clamp pulse,
CL, from MCLK and VSMP (when RLCINT is high). When CL is active the voltage on the WM8152
side of CIN, at VINP, is forced to the VRLC/VBIAS voltage (VVRLC) by switch 1. When the CL pulse
turns off, the voltage at VINP initially remains at VVRLC but any subsequent variation in sensor voltage
(from reset to video level) will couple through CIN to VINP.
RLC is compatible with both CDS and non-CDS operating modes, as selected by switch 2. Refer to
the CDS/non-CDS Processing section.
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MCLK
VSMP
TIMING CONTROL
CL
RS
FROM CONTROL
INTERFACE
VS
CIN
S/H
VINP
+
TO OFFSET DAC
+
2
S/H
-
1
RLC
INPUT SAMPLING
BLOCK
CDS
EXTERNAL VRLC
CDS
VRLC/
VBIAS
4-BIT
RLC DAC
FROM CONTROL
INTERFACE
VRLCEXT
Figure 4 Reset Level Clamping and CDS Circuitry
Reset Level Clamping is controlled by register bit RLCINT. Figure 5 illustrates the effect of the
RLCINT bit for a typical CCD waveform, with CL applied during the reset period.
The RLCINT register bit is sampled on the positive edge of MCLK that occurs during each VSMP
pulse. The sampled level, high (or low) controls the presence (or absence) of the internal CL pulse on
the next reset level. The position of CL can be adjusted by using control bits CDSREF[1:0] (Figure 6).
MCLK
VSMP
ACYC/RLC
or RLCINT
1
X
X
0
X
X
0
Programmable Delay
CL
(CDSREF = 01)
INPUT VIDEO
RGB
RGB
RLC on this Pixel
RGB
No RLC on this Pixel
Figure 5 Relationship of RLCINT, MCLK and VSMP to Internal Clamp Pulse, CL
The VRLC/VBIAS pin can be driven internally by a 4-bit DAC (RLCDAC) by writing to control bits
RLCV[3:0]. The RLCDAC range and step size may be increased by writing to control bit
RLCDACRNG. Alternatively, the VRLC/VBIAS pin can be driven externally by writing to control bit
VRLCEXT to disable the RLCDAC and then applying a d.c. voltage to the pin.
CDS/NON-CDS PROCESSING
For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel
common mode noise. For CDS operation, the video level is processed with respect to the video reset
level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must
be set to 1 (default), this controls switch 2 (Figure 4) and causes the signal reference to come from
the video reset level. The time at which the reset level is sampled, by clock Rs/CL, is adjustable by
programming control bits CDSREF[1:0], as shown in Figure 6.
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MCLK
VSMP
VS
RS/CL (CDSREF = 00)
RS/CL (CDSREF = 01)
RS/CL (CDSREF = 10)
RS/CL (CDSREF = 11)
Figure 6 Reset Sample and Clamp Timing
For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed
with respect to the voltage on pin VRLC/VBIAS, generated internally or externally as described
above. The VRLC/VBIAS pin is sampled by Rs at the same time as Vs samples the video level in this
mode.
OFFSET ADJUST AND PROGRAMMABLE GAIN
The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset
DAC to compensate for offsets and then amplified by an 8-bit PGA. The gain and offset can be set
for each of three colours by writing to control bits DACx[7:0] and PGAx[7:0] (where x can be R, G or
B).
In colour line-by-line mode the gain and offset coefficients that are applied to the PGA and offset
DAC can be multiplexed by control of the INTM[1:0] bits as shown in Table 1.
INTM[1:0]
DESCRIPTION
00
Red offset and gain registers are applied to offset DAC and PGA
(DACR[7:0] and PGAR[7:0])
01
Green offset and gain registers applied to offset DAC and PGA
(DACG[7:0] and PGAG[7:0])
10
Blue offset and gain registers applied to offset DAC and PGA
(DACB[7:0] and PGAB[7:0])
11
Reserved.
Table 1 Offset DAC and PGA Register Control
The gain characteristic of the WM8152 PGA is shown in Figure 7. Figure 8 shows the maximum
input voltage (at VINP) that can be gained up to match the ADC full-scale input range (2.5V).
PEAK INPUT VOLTAGE TO MATCH ADC
FULL-SCALE RANGE
9
8
PGA GAIN V/V
7
6
5
4
3
2
1
0
0
64
128
192
GAIN REGISTER VALUE, PGA[7:0]
Figure 7 PGA Gain Characteristic
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256
3.5
3
2.5
2
1.5
1
0.5
0
0
64
128
192
256
GAIN REGISTER VALUE, PGA[7:0]
Figure 8 Peak Input Voltage to Match ADC Full-scale Range
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ADC INPUT BLACK LEVEL ADJUST
The output from the PGA should be offset to match the full-scale range of the ADC (VFS = 2.5V). For
negative-going input video signals, a black level (zero differential) output from the PGA should be
offset to the top of the ADC range by setting register bits PGAFS[1:0]=10. For positive going input
signal the black level should be offset to the bottom of the ADC range by setting PGAFS[1:0]=11.
Bipolar input video is accommodated by setting PGAFS[1:0]=00 or PGAFS[1:0]=01 (zero differential
input voltage gives mid-range ADC output).
OVERALL SIGNAL FLOW SUMMARY
Figure 9 represents the processing of the video signal through the WM8152.
INPUT
SAMPLING OFFSET DAC PGA
BLOCK
BLOCK
BLOCK
V1
+
VIN
V2
++
-
X
OUTPUT
INVERT
BLOCK
ADC BLOCK
V3
analog
x (65535/VFS)
+0
if PGAFS[1:0]=11
+65535 if PGAFS[1:0]=10
+32767 if PGAFS[1:0]=0x
OP[3:0]
digital
CDS = 1
D2 = D1 if INVOP = 0
D2 =65535-D1 if INVOP = 1
VRESET
PGA gain
A = 0.78+(PGA[7:0]*7.57)/255
CDS = 0
VVRLC
Offset
DAC
VRLCEXT=1
D2
D1
260mV*(DAC[7:0]-127.5)/127.5
VRLCEXT=0
RLC
DAC
VRLCSTEP*RLCV[3:0] + VRLCBOT
VIN is VINP voltage sampled on video sample
VRESET is VINP sampled during reset clamp
VVRLC is voltage applied to VRLC pin
CDS, VRLCEXT,RLCV[3:0], DAC[7:0],
PGA[7:0], PGAFS[1:0] and INVOP are set
by programming internal control registers.
CDS=1 for CDS, 0 for non-CDS
Figure 9 Overall Signal Flow
The INPUT SAMPLING BLOCK produces an effective input voltage V1. For CDS, this is the
difference between the input video level VIN and the input reset level VRESET. For non-CDS this is the
difference between the input video level VIN and the voltage on the VRLC/VBIAS pin, VVRLC,
optionally set via the RLC DAC.
The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the
black level of the input signal towards 0V, producing V2.
The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range,
outputting voltage V3.
The ADC BLOCK then converts the analogue signal, V3, to a 16-bit unsigned digital output, D1.
The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D2.
CALCULATING OUTPUT FOR ANY GIVEN INPUT
The following equations describe the processing of the video and reset level signals through
the WM8152.
INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING
If CDS = 1, (i.e. CDS operation) the previously sampled reset level, VRESET, is subtracted from the
input video.
V1
=
VIN - VRESET ...................................................................
Eqn. 1
If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted
instead.
V1
=
VIN - VVRLC ....................................................................
Eqn. 2
If VRLCEXT = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS.
If VRLCEXT = 0, VVRLC is the output from the internal RLC DAC.
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VVRLC
=
(VRLCSTEP ∗ RLCV[3:0]) + VRLCBOT .................................
Eqn. 3
VRLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC.
OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST
The resultant signal V1 is added to the Offset DAC output.
V2
=
V1 + {260mV ∗ (DAC[7:0]-127.5) } / 127.5 .....................
Eqn. 4
PGA NODE: GAIN ADJUST
The signal is then multiplied by the PGA gain,
V3
=
V2 ∗ [0.78+(PGA[7:0]*7.57)/255] ...................................
Eqn. 5
ADC BLOCK: ANALOGUE-DIGITAL CONVERSION
The analogue signal is then converted to a 16-bit unsigned number, with input range configured by
PGAFS[1:0].
D1[15:0] = INT{ (V3 /VFS) ∗ 65535} + 32767 PGAFS[1:0] = 00 or 01 ......
Eqn. 6
D1[15:0] = INT{ (V3 /VFS) ∗ 65535}
PGAFS[1:0] = 11 ...............
Eqn. 7
D1[15:0] = INT{ (V3 /VFS) ∗ 65535} + 65535 PGAFS[1:0] = 10 ...............
Eqn. 8
where the ADC full-scale range, VFS = 2.5V
if D1[15:0] < 0
D1[15:0] = 0
if D1[15:0] > 65535 D1[15:0] = 65535
OUTPUT INVERT BLOCK: POLARITY ADJUST
The polarity of the digital output may be inverted by control bit INVOP.
w
D2[15:0] = D1[15:0]
(INVOP = 0) ......................
Eqn. 9
D2[15:0] = 65535 – D1[15:0]
(INVOP = 1) ......................
Eqn. 10
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OUTPUT DATA FORMAT
The digital data output from the ADC is available to the user in 4-bit wide multiplexed. Latency of
valid output data with respect to VSMP is programmable by writing to control bits DEL[1:0]. The
latency for each mode is shown in the Operating Mode Timing Diagrams section.
Figure 10 shows the output data formats for Mode 1 and 3 – 6. Figure 11 shows the output data
formats for Mode 2. Table 2 summarises the output data obtained for each format.
MCLK
4+4+4+4-BIT
OUTPUT
MCLK
A
B
C
Figure 10 Output Data Formats
(Modes 1, 3, 4)
OUTPUT
FORMAT
OUTPUT
PINS
4+4+4+4-bit
(nibble)
OP[3:0]
4+4+4+4-BIT
OUTPUT
D
A B A B C D
Figure 11 Output Data Formats
(Mode 2)
OUTPUT
A = d15, d14, d13, d12
B = d11, d10, d9, d8
C = d7, d6, d5, d4
D = d3, d2, d1, d0
Table 2 Details of Output Data Shown in Figure 10 and Figure 11.
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CONTROL INTERFACE
The internal control registers are programmable via the serial digital control interface. The register
contents can be read back via the serial interface on pin OP[3]/SDO.
It is recommended that a software reset is carried out after the power-up sequence, before writing to
any other register. This ensures that all registers are set to their default values (as shown in Table
4).
SERIAL INTERFACE: REGISTER WRITE
Figure 12 shows register writing in serial mode. Three pins, SCK, SDI and SEN are used. A six-bit
address (a5, 0, a3, a2, a1, a0) is clocked in through SDI, MSB first, followed by an eight-bit data
word (b7, b6, b5, b4, b3, b2, b1, b0), also MSB first. Each bit is latched on the rising edge of SCK.
When the data has been shifted into the device, a pulse is applied to SEN to transfer the data to the
appropriate internal register. Note all valid registers have address bit a4 equal to 0 in write mode.
SCK
SDI
a5
0
a3
a2
a1
a0
b7
b6
b5
Address
b4
b3
b2
b1
b0
Data Word
SEN
Figure 12 Serial Interface Register Write
A software reset is carried out by writing to Address “000100” with any value of data, (i.e. Data Word
= XXXXXXXX.
SERIAL INTERFACE: REGISTER READ-BACK
Figure 13 shows register read-back in serial mode. Read-back is initiated by writing to the serial bus
as described above but with address bit a4 set to 1, followed by an 8-bit dummy data word. Writing
address (a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of
corresponding register (a5, 0, a3, a2, a1, a0) to be output MSB first on pin SDO (on the falling edge
of SCK). Note that pin SDO is shared with an output pin, OP[3], so no data can be read when reading
from a register. The next word may be read in to SDI while the previous word is still being output on
SDO.
SCK
SDI
a5
1 a3 a2 a1 a0
Address
x
x
x
x
x
x
x
x
Data Word
SEN
SDO
d7 d6 d5 d4 d3 d2 d1 d0
Output Data Word
Figure 13 Serial Interface Register Read-back
TIMING REQUIREMENTS
To use this device a master clock (MCLK) of up to 24MHz and a per-pixel synchronisation clock
(VSMP) of up to 12MHz are required. These clocks drive a timing control block, which produces
internal signals to control the sampling of the video signal. MCLK to VSMP ratios and maximum
sample rates for the various modes are shown in Table 3.
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PROGRAMMABLE VSMP DETECT CIRCUIT
The VSMP input is used to determine the sampling point and frequency of the WM8152. Under
normal operation a pulse of 1 MCLK period should be applied to VSMP at the desired sampling
frequency (as shown in the Operating Mode Timing Diagrams) and the input sample will be taken on
the first rising MCLK edge after VSMP has gone low. However, in certain applications such a signal
may not be readily available. The programmable VSMP detect circuit in the WM8152 allows the
sampling point to be derived from any signal of the correct frequency, such as a CCD shift register
clock, when applied to the VSMP pin.
When enabled, by setting the VSMPDET control bit, the circuit detects either a rising or falling edge
(determined by POSNNEG control bit) on the VSMP input pin and generates an internal VSMP pulse.
This pulse can optionally be delayed by a number of MCLK periods, specified by the VDEL[2:0] bits.
Figure 14 shows the internal VSMP pulses that can be generated by this circuit for a typical clock
input signal. The internal VSMP pulse is then applied to the timing control block in place of the
normal VSMP pulse provided from the input pin. The sampling point then occurs on the first rising
MCLK edge after this internal VSMP pulse, as shown in the Operating Mode Timing Diagrams.
MCLK
INPUT
PINS
VSMP
POSNNEG = 1
VS
(VDEL = 000) INTVSMP
VS
VS
(VDEL = 001) INTVSMP
VS
(VDEL = 010) INTVSMP
VS
VS
VS
(VDEL = 011) INTVSMP
(VDEL = 100) INTVSMP
VS
VS
VS
VS
VS
(VDEL = 101) INTVSMP
VS
VS
VS
VS
(VDEL = 110) INTVSMP
VS
VS
VS
VS
VS
(VDEL = 111) INTVSMP
VS
VS
VS
POSNNEG = 0
VS
(VDEL = 000) INTVSMP
VS
(VDEL = 001) INTVSMP
VS
VS
VS
VS
(VDEL = 110) INTVSMP
VS
VS
VS
(VDEL = 101) INTVSMP
VS
VS
VS
(VDEL = 100) INTVSMP
VS
VS
VS
(VDEL = 011) INTVSMP
VS
VS
VS
(VDEL = 010) INTVSMP
(VDEL = 111) INTVSMP
VS
VS
VS
VS
VS
VS
Figure 14 Internal VSMP Pulses Generated by Programmable VSMP Detect Circuit
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REFERENCES
The ADC reference voltages are derived from an internal bandgap reference, and buffered to pins
VRT and VRB, where they must be decoupled to ground. Pin VRX is driven by a similar buffer, and
also requires decoupling. The output buffer from the RLCDAC also requires decoupling at pin
VRLC/VBIAS when this is configured as an output.
POWER SUPPLY
The WM8152 can run from a 5V single supply or from split 5V (core) and 3.3V (digital interface)
supplies.
POWER MANAGEMENT
Power management for the device is performed via the Control Interface. The device can be powered
on or off completely by setting the EN bit low.
All the internal registers maintain their previously programmed value in power down mode and the
Control Interface inputs remain active.
OPERATING MODES
Table 3 summarises the most commonly used modes, the clock waveforms required and the register
contents required for CDS and non-CDS operation.
MODE
DESCRIPTION
CDS
AVAILABLE
MAX
SAMPLE
RATE
TIMING
REQUIREMENTS
REGISTER
CONTENTS WITH
CDS
REGISTER
CONTENTS
WITHOUT CDS
1
Monochrome/
Colour Line-by-Line
Yes
4MSPS
MCLK max = 24MHz
MCLK:VSMP ratio is
6:1
SetReg1: 0F(hex)
SetReg1: 0D(hex)
2
Fast Monochrome/
Colour Line-by-Line
Yes
8MSPS
MCLK max = 24MHz
MCLK:VSMP ratio is
3:1
Identical to Mode
1 plus SetReg3:
bits 5:4 must be
set to 0(hex)
Identical to
Mode 1
3
Maximum speed
Monochrome/
Colour Line-by-Line
No
12MSPS
MCLK max = 24MHz
MCLK:VSMP ratio is
2:1
CDS not possible
SetReg1: 4D(hex)
4
Slow Monochrome/
Colour Line-by-Line
Yes
3MSPS
MCLK max = 24MHz
MCLK:VSMP ratio is
2n:1, n ≥ 4
Identical to
Mode 1
Identical to
Mode 1
Table 3 WM8152 Operating Modes
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OPERATING MODE TIMING DIAGRAMS
The following diagrams show 4-bit multiplexed output data and MCLK, VSMP and input video
requirements for operation of the most commonly used modes as shown in Table 3. The diagrams
are identical for both CDS and non-CDS operation.
16.5 MCLK PERIODS
MCLK
VSMP
VINP
OP[3:0]
(DEL = 00)
OP[3:0]
(DEL = 01)
A B C
A B C
A B C
D
OP[3:0]
(DEL = 10)
OP[3:0]
(DEL = 11)
D
D
D
A B C
A B C
A B C
D
A B C
D
D
D
A B C
A B C
A B C
D
A B C
D
D
D
A B C D
A B C
D
D
A B C
D
A B C
D
A B C
A B C
D
D
A B C D
Figure 15 Mode 1 Operation
23.5 MCLK PERIODS
MCLK
VSMP
VINP
OP[3:0]
(DEL = 00)
OP[3:0]
(DEL = 01)
CD A B AB C DA B AB C DA B AB C D A B AB C DA B AB C D A B AB CDA B AB C D A B AB CD A B AB C DA B AB CD A B AB C DA B AB CD
CD A B AB C D A B AB C DA B AB CD A B AB C D A B AB CDA B AB C DA B AB C DA B AB C D A B AB C D A B AB CD A B AB C D A B AB C D
OP[3:0]
(DEL = 10)
CD A B AB C D A B AB C D A B AB C DA B AB C DA B AB C D A B AB C DA B AB C D A B AB CDA B AB C D A B AB CD A B AB C DA B AB CD
OP[3:0]
(DEL = 11)
CD A B AB C DA B AB C D A B AB CD A B AB C DA B AB C D A B AB C D A B AB C DA B AB CDA B AB C DA B AB CD A B AB C D A B AB CD
Figure 16 Mode 2 Operation
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16.5 MCLK PERIODS
MCLK
VSMP
VINP
OP[3:0]
(DEL = 00)
A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D
OP[3:0]
(DEL = 01)
A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D
OP[3:0]
(DEL = 10)
A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D
OP[3:0]
(DEL = 11)
A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D
Figure 17 Mode 3 Operation
16.5 MCLK PERIODS
MCLK
VSMP
VINP
OP[3:0]
(DEL = 00)
D
OP[3:0]
(DEL = 01)
A B C
D
OP[3:0]
(DEL = 10)
OP[3:0]
(DEL = 11)
D
A B C
D
A B C
D
A B C
A B C
D
A B C
D
D
A B C
D
A B C
D
A B C
A B C
D
A B C
D
A B C
D
D
D
A B C D
Figure 18 Mode 4 Operation (MCLK:VSMP Ratio = 8:1)
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DEVICE CONFIGURATION
REGISTER MAP
The following table describes the location of each control bit used to determine the operation of the
WM8152. The register map is programmed by writing the required codes to the appropriate
addresses via the serial interface.
ADDRESS
DESCRIPTION
<a5:a0>
000001
DEF
RW
(hex)
Setup Reg 1
0F
BIT
b7
b6
b5
b4
b3
b2
b1
b0
RW
0
MODE3
PGAFS[1]
PGAFS[0]
1
1
CDS
EN
000010
Setup Reg 2
23
RW
DEL[1]
DEL[0]
RLCDACRNG
0
VRLCEXT
INVOP
1
1
000011
Setup Reg 3
1F
RW
0
0
CDSREF [1]
CDSREF [0]
RLCV[3]
RLCV[2]
RLCV[1]
RLCV[0]
000100
Software Reset
00
W
000110
Setup Reg 4
05
RW
0
0
INTM[1]
INTM[0]
RLCINT
1
0
1
000111
Revision Number
41
R
0
1
0
0
0
0
0
1
001000
Setup Reg 5
00
RW
0
0
0
POSNNEG
VDEL[2]
VDEL[1]
VDEL[0]
VSMPDET
001001
Test Reg 1
00
RW
TCLK
0
0
0
0
0
0
0
001010
Reserved
00
RW
0
0
0
0
0
0
0
0
001011
Reserved
00
RW
0
0
0
0
0
0
0
0
001100
Reserved
00
RW
0
0
0
0
0
0
0
0
100000
DAC Value (Red)
80
RW
DACR[7]
DACR[6]
DACR[5]
DACR[4]
DACR[3]
DACR[2]
DACR[1]
DACR[0]
100001
DAC Value
(Green)
80
RW
DACG[7]
DACG[6]
DACG[5]
DACG[4]
DACG[3]
DACG[2]
DACG[1]
DACG[0]
100010
DAC Value (Blue)
80
RW
DACB[7]
DACB[6]
DACB[5]
DACB[4]
DACB[3]
DACB[2]
DACB[1]
DACB[0]
100011
DAC Value (RGB)
80
W
DAC[7]
DAC[6]
DAC[5]
DAC[4]
DAC[3]
DAC[2]
DAC[1]
DAC[0]
101000
PGA Gain (Red)
00
RW
PGAR[7]
PGAR[6]
PGAR[5]
PGAR[4]
PGAR[3]
PGAR[2]
PGAR[1]
PGAR[0]
101001
PGA Gain
(Green)
00
RW
PGAG[7]
PGAG[6]
PGAG[5]
PGAG[4]
PGAG[3]
PGAG[2]
PGAG[1]
PGAG[0]
101010
PGA Gain (Blue)
00
RW
PGAB[7]
PGAB[6]
PGAB[5]
PGAB[4]
PGAB[3]
PGAB[2]
PGAB[1]
PGAB[0]
101011
PGA Gain (RGB)
00
W
PGA[7]
PGA[6]
PGA[5]
PGA[4]
PGA[3]
PGA[2]
PGA[1]
PGA[0]
Table 4 Register Map
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REGISTER MAP DESCRIPTION
The following table describes the function of each of the control bits shown in Table 4.
REGISTER
Setup
Register 1
BIT
NO
BIT
NAME(S)
DEFAULT
DESCRIPTION
0
EN
1
0 = complete power down, 1 = fully active.
1
CDS
1
Select correlated double sampling mode: 0 = single ended mode,
1 = CDS mode.
5:4
PGAFS[1:0]
00
Offsets PGA output to optimise the ADC range for different polarity sensor
output signals. Zero differential PGA input signal gives:
00 = Zero output
(use for bipolar video)
01 = Zero output
Setup
Register 2
6
MODE3
0
Required when operating in MODE3: 0 = other modes, 1 = MODE3.
2
INVOP
0
Digitally inverts the polarity of output data.
0 = negative going video gives negative going output,
1 = negative-going video gives positive going output data.
3
VRLCEXT
0
When set powers down the RLCDAC, changing its output to Hi-Z, allowing
VRLC/VBIAS to be externally driven.
5
RLCDACRNG
1
Sets the output range of the RLCDAC.
0 = RLCDAC ranges from 0 to VDD (approximately),
1 = RLCDAC ranges from 0 to VRT (approximately).
7:6
DEL[1:0]
00
Sets the output latency in ADC clock periods.
1 ADC clock period = 2 MCLK periods except in Mode 2 where 1 ADC
clock period = 3 MCLK periods.
00 = Minimum latency
01 = Delay by one ADC clock
period
Setup
Register 3
3:0
RLCV[3:0]
1111
5:4
CDSREF[1:0]
01
Software
Reset
10 = Delay by two ADC clock periods
11 = Delay by three ADC clock
periods
Controls RLCDAC driving VRLC pin to define single ended signal
reference voltage or Reset Level Clamp voltage. See Electrical
Characteristics section for ranges.
CDS mode reset timing adjust.
00 = Advance 1 MCLK period
01 = Normal
Setup
Register 4
10 = Full-scale positive output
(use for negative going video)
11 = Full-scale negative output
(use for positive going video)
10 = Retard 1 MCLK period
11 = Retard 2 MCLK periods
Any write to Software Reset causes all cells to be reset.
It is recommended that a software reset be performed after a power-up
before any other register writes.
3
RLCINT
0
This bit is used to determine whether Reset Level Clamping is enabled.
0 = RLC disabled, 1 = RLC enabled.
5:4
INTM[1:0]
00
Colour selection bits used in internal modes.
00 = Red, 01 = Green, 10 = Blue and 11 = Reserved.
See Table 1 for details.
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REGISTER
Setup
Register 5
Test
Register 1
BIT
NO
BIT
NAME(S)
DEFAULT
DESCRIPTION
0
VSMPDET
0
3:1
VDEL[2:0]
000
4
POSNNEG
0
When VSMPDET = 0 this bit has no effect.
When VSMPDET = 1 this bit controls whether positive or negative edges
are detected:
0 = Negative edge on VSMP pin is detected and used to generate internal
timing pulse.
1 = Positive edge on VSMP pin is detected and used to generate internal
timing pulse.
See Figure 14 for further details.
7
TCLK
0
0 = Normal Operation, OP[3:0] output ADC data.
1 = Internal Clock Test Mode. This allows internal timing signals to be
multiplexed onto the OP[3:0] pins as follows.
0 = Normal operation, signal on VSMP input pin is applied directly to
Timing Control block.
1 = Programmable VSMP detect circuit is enabled. An internal
synchronisation pulse is generated from signal applied to VSMP input pin
and is applied to Timing Control block.
When VSMPDET = 0 these bits have no effect.
When VSMPDET = 1 these bits set a programmable delay from the
detected edge of the signal applied to the VSMP pin. The internally
generated pulse is delayed by VDEL MCLK periods from the detected
edge.
See Figure 14, Internal VSMP Pulses Generated for details.
PIN
TCLK=0
TCLK=1
OP[3]
OP[3]
INTVSMP
OP[2]
OP[2]
Video sample clock
OP[1]
OP[1]
ADC clock
OP[0]
OP[0]
Reset sample clock
Offset DAC
(Red)
7:0
DACR[7:0]
80
Red channel offset DAC value. Used under control of the INTM[1:0]
control bits.
Offset DAC
(Green)
7:0
DACG[7:0]
80
Green channel offset DAC value. Used under control of the INTM[1:0]
control bits.
Offset DAC
(Blue)
7:0
DACB[7:0]
80
Blue channel offset DAC value. Used under control of the INTM[1:0]
control bits.
Offset DAC
(RGB)
7:0
DAC[7:0]
PGA gain
(Red)
7:0
PGAR[7:0]
0
Determines the gain of the red channel PGA according to the equation:
Red channel PGA gain = [0.78+(PGAR[7:0]*7.57)/255]. Used under
control of the INTM[1:0] control bits.
PGA gain
(Green)
7:0
PGAG[7:0]
0
Determines the gain of the green channel PGA according to the equation:
Green channel PGA gain = [0.78+(PGAG[7:0]*7.57)/255]. Used under
control of the INTM[1:0] control bits.
PGA gain
(Blue)
7:0
PGAB[7:0]
0
Determines the gain of the blue channel PGA according to the equation:
Blue channel PGA gain = [0.78+(PGAB[7:0]*7.57)/255]. Used under
control of the INTM[1:0] control bits.
PGA gain
(RGB)
7:0
PGA[7:0]
A write to this register location causes the red, green and blue offset DAC
registers to be overwritten by the new value
A write to this register location causes the red, green and blue PGA gain
registers to be overwritten by the new value
Table 5 Register Control Bits
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WM8152
Production Data
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
DVDD2 DVDD1
DVDD2
DGND
DVDD1
C1
C2
AVDD
AGND1
AVDD
C3
AGND2
DGND DGND
AGND
AGND
VRT
Video
Input
VINP
C4
C5
VRX
VRB
C6
WM8152
C7
C8
VRLC/VBIAS
C9
AGND
AGND
DVDD2
DVDD1
AVDD
MCLK
Timing
Signals
VSMP
+ C10
+ C11
+ C12
OP[3]/SDO
Interface
Controls
SCK
OP[2]
SDI
OP[1]
SEN
OP[0]
Output
Data
Bus
DGND
DGND
AGND
NOTES: 1. C1-9 should be fitted as close to WM8152 as possible.
2. AGND and DGND should be connected as close to WM8152 as possible.
Figure 19 External Components Diagram
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT
REFERENCE
SUGGESTED
VALUE
DESCRIPTION
C1
100nF
De-coupling for DVDD2.
C2
100nF
De-coupling for DVDD1.
C3
100nF
De-coupling for AVDD.
C4
10nF
High frequency de-coupling between VRT and VRB.
C5
1µF
Low frequency de-coupling between VRT and VRB (non-polarised).
C6
100nF
De-coupling for VRB.
C7
100nF
De-coupling for VRX.
C8
100nF
De-coupling for VRT.
C9
100nF
De-coupling for VRLC.
C10
10µF
Reservoir capacitor for DVDD2.
C11
10µF
Reservoir capacitor for DVDD1.
C12
10µF
Reservoir capacitor for AVDD.
Table 6 External Components Descriptions
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WM8152
Production Data
PACKAGE DIMENSIONS
DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm)
b
DM0015.B
e
20
11
E1
1
E
GAUGE
PLANE
10
Θ
D
A A2
c
A1
L
0.25
L1
-C0.10 C
Symbols
A
A1
A2
b
c
D
e
E
E1
L
L1
θ
MIN
----0.05
1.65
0.22
0.09
6.90
7.40
5.00
0.55
o
0
REF:
Dimensions
(mm)
NOM
--------1.75
0.30
----7.20
0.65 BSC
7.80
5.30
0.75
0.125 REF
o
4
SEATING PLANE
MAX
2.0
----1.85
0.38
0.25
7.50
8.20
5.60
0.95
o
8
JEDEC.95, MO-150
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.
D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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WM8152
Production Data
IMPORTANT NOTICE
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or
service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing
orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale
supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation
of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s
standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support
this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used
by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical
components in life support devices or systems without the express written approval of an officer of the company. Life
support devices or systems are devices or systems that are intended for surgical implant into the body, or support or
sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be
reasonably expected to result in a significant injury to the user. A critical component is any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that
any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual
property right of WM covering or relating to any combination, machine, or process in which such products or services might
be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s
approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and
is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this
information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive
business practice, and WM is not responsible nor liable for any such use.
Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that
product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and
deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc
20 Bernard Terrace
Edinburgh
EH8 9NX
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: [email protected]
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