HT71D02/HT71D04 Power Line Data Transceiver Features · Complete Data Transmission on Power Line functions · High Maximum Input Voltage: 30V · Integrated Low Dropout Voltage Regulator · Integrated Voltage Detector for Power Supply Monitoring · Open drain NMOS drivers for flexible interfacing · Power and Reset Protection Features · 8-pin SOP package type · Minimal external component requirements General Description In systems where a master controller controls a number of individual interconnected subsystems such as found in smoke detector systems, water metering systems, solar energy system etc., the cost of the lengthy interconnecting cabling can be a major factor. By sending data along the power supply lines, the interconnecting cables can be reduced to a simple two line type, thus greatly reducing both cable and installation costs. With a the addition of a few external components, this power line data transceiver device contains all the internal components required to provide users with a system for power line data transmission and reception. Data is modulated onto the power line by the simple reduction of the power line voltage for a specific period of time. Power supply voltage changes can be initiated by the master controller for data reception or initiated by the HT71D0x devices for data transmission. An internal voltage regulator within the device ensures that a constant voltage power supply is provided to the interconnected subsystem units while an internal voltage detector monitors the power line voltage level. Selection Guide Rev. 1.00 Part No. LDO Voltage Detect Voltage Package HT71D02 3.3V 9.0V 8SOP HT71D04 5.0V 9.0V 8SOP 1 June 30, 2010 HT71D02/HT71D04 Power Line Data Transceiver Block Diagram VIN VCC VDD LDO 3.3V/5.0V VO Q1 CEB VCC RPU1 INT0 VDLY CDLY LVD 9.0V Q2 CX Q3 CN C1 + CP/TD VDD Q4 VPT VSS/TS RPU2 VDLY Protection Circuit TG C2 C2X Vref VPT VDLY C2X R Pin Assignment V S S /T S 1 8 T G C P /T D 2 7 C D L Y C N 3 6 C X V IN 4 5 V O H T 7 1 D 0 2 /H T 7 1 D 0 4 8 S O P -A Rev. 1.00 2 June 30, 2010 HT71D02/HT71D04 Power Line Data Transceiver Pin Description Pin Name I/O Pin-Shared Mapping VIN ¾ CN I Comparator Negative Terminal Input I Comparator positive input - CP O NMOS Driver Drain Terminal - TD ¾ Ground pin - VSS Input voltage CP/TD VSS/TS O NMOS Driver Source Terminal - TS TG I NMOS Gate Input CX O Comparator NMOS output CDLY O LDO Output Control - delay time determined by external capacitor VO ¾ LDO Output Voltage CP and TD share the same pin Absolute Maximum Ratings Maximum Input Supply Voltage ..................................................................................................33V Operating Temperature................................................................................................-40°C to 85°C Storage Temperature .................................................................................................-55°C to 150°C Maximum Junction Temperature ..............................................................................................150°C Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Ta=25°C Test Conditions Symbol Parameter VDD Min. Typ. Max. Unit Conditions VIN Operating Voltage ¾ ¾ 10 ¾ 30 V ICC Operating current of VIN ¾ VIN=24V , CP=5V, CN=2V, No Load ¾ 30 85 mA IOL1 Output Sink Current (Q1, VO pin) ¾ VIN=5V, VOL =0.5V 0.8 ¾ ¾ mA IOL2 Output Sink Current (Q2,CDLY pin) ¾ VIN=5V, VOL =0.5V 250 500 ¾ mA IOL3 Output Sink Current (Q3,CX pin) ¾ VIN=5V, VOL =0.5V 0.8 ¾ ¾ mA IOL4 Output Sink Current (Q4,TS pin) (NMOS driver) ¾ VGS=18V, VDS =1V 90 ¾ ¾ mA RPU1 Pull-up resistor 1 ¾ VIN=10V -50% 5 +50% MW RPU2 Pull-up resistor 2 ¾ VIN=10V -30% 50 +30% kW Rev. 1.00 3 June 30, 2010 HT71D02/HT71D04 Power Line Data Transceiver Test Conditions Symbol Parameter VDD Min. Typ. Max. Unit -20% 13.7 +20% V -20% 7.16 +20% V -20% 5.83 +20% V -20% 3.07 +20% V 3.201 3.300 3.399 V 4.850 5.000 5.150 V Conditions Inverter 0 (INT) Schmitt Trigger Window VH VL VSW (note) VH VL ¾ VIN=24V ¾ VIN=10V Inverter 0 (INT) Schmitt Trigger Window 3.3V VOUT LDO Output Voltage VIN=10V, IOUT=10mA 5.0V IOUT LDO Output Current ¾ VIN=10V, DVOUT=3% (Note1) 60 ¾ ¾ mA DVLOAD Load Regulation ¾ VIN=10V, 1mA£IOUT£30mA ¾ 60 100 mV DVLINE Line Regulation ¾ IOUT=1mA, 10V£VIN£24V ¾ 0.2 ¾ %/V ¾ VIN=10V, IOUT=10mA, CL=10mF ¾ 3.3 5.0 ms tSU Startup Time (Falling Egde of CE to VOUT Within Specification) ¾ VIN=10V, IOUT=10mA, CL=0.1mF ¾ 700 1400 ms ¾ ±0.50 ¾ mV/°C ¾ ±0.75 ¾ mV/°C VLVD-0.3 VLVD VLVD+0.3 V , V O , T U T Temperature Coefficient a 3.3V IOUT=10mA, 5.0V -40°C < Ta < +85°C Voltage Detector VDET Detection Voltage ¾ VLVD=9.0V VHYS Hysteresis Width ¾ ¾ ¾ 0.05 VDET ¾ V Temperature Coefficient ¾ -40°C < Ta < +85°C ¾ ±0.9 ¾ mV/°C , V D , T E T a Comparator tRES Response Time ¾ ¾ ¾ ¾ 10 ms VHC hysteresis Window ¾ ¾ ¾ 0.15 ¾ V VCOM Common-Mode Input Range ¾ ¾ VSS+1.5 ¾ VIN-1 V Note: 1. DVOUT is calculated as the difference between the output voltage under testing and the output voltage which is measured at IOUT =10mA. 2. VIO specification is design guaranteed. Rev. 1.00 4 June 30, 2010 HT71D02/HT71D04 Power Line Data Transceiver Functional Description These devices provide a way to transmit and receive data on the common power lines of an interconnected array of microcontroller based subsystems. By having one of these devices inside each subsystem, the shared power and data cabling can be reduced to a simple two line type, offering major installation cost reductions. P o s itiv e P o w e r S y p p ly L in e M a s te r C o n tr o lle r G r o u n d L in e H T 7 1 D 0 x H T 7 1 D 0 x H T 7 1 D 0 x M C U M C U M C U S u b s y s te m # 2 S u b s y s te m # n S u b s y s te m # 1 System Block Diagram Shared Power Line All microcontroller based subsystems are connected together via the same two line power connection. The ground line is hardwired to each subsystem while the positive power line is connected to the VIN pin on each of the HT71D0x devices. An internal Low Dropout Voltage Regulator within the HT71D0x devices, converts this input power supply voltage to a fixed voltage level which is supplied to the subsystem microcontroller and other circuit components. In this way when the power line voltage is changed due to the transmission or reception of data the subsystem circuits still continue to receive a regulated power supply. Rev. 1.00 5 June 30, 2010 HT71D02/HT71D04 Power Line Data Transceiver Data Transmission Refer to the application circuit when reading the following description. Data information can be transmitted onto the positive power line by reducing the voltage level for a short time duration. As the devices include a voltage regulator which is used as the power supply to the subsystem units, then the subsystem power supply voltage will not be affected as long as the regulator minimum dropout voltage is maintained. However a reduction in the power supply will be detected by the C1 internal comparators. The output of this comparator is connected to an open drain NMOS transistor, Q1, whose open drain output on pin CX can be connected to a microcontroller input for use as a data signal. P o w e r S u p p ly V o lta g e P u ls e T r a n s m itte d b y M a s te r V IN C N C o m p a ra to r - v e in p u t C P /T D C o m p a ra to r + v e in p u t C X D a ta P u ls e to M C U P u ls e w id th d e te r m in e d b y e x te r n a l R C n e tw o rk Power Line Data Reception Data Reception Refer to the application circuit when reading the following description. The individual subsystems can transmit data to the master controller along the power supply line by using one of its I/O lines to reduce the positive power line supply line voltage level for a short time duration. An output line on the subsystem microcontroller should be connected to the TG pin. An internal comparator, C2, whose positive input is connected to an internal voltage reference, will detect if this pin is pulled low. The comparator output is connected to an internal open drain NMOS transistor, Q4, which will pull the CP/TD line low. By connecting a suitable value resistor between the CP/TD pin and the power supply line, the correct value of power supply voltage reduction can be implemented. Protection Circuits The devices include an internal Voltage Detector function which monitors the power supply input voltage. Should the input power supply voltage fall below a safe level specified by the voltage detector level, then the voltage detector output will change state and disable the internal regulator thus removing the power supply source to the subsystem circuits. An internal NMOS transistor whose drain is connected to the output power supply line, VO will also turn on keeping the VO level close to zero. This ensures that the subsystem microcontroller receives the proper power on reset conditions. When power is applied an external capacitor, connected to pin CDLY, together with an internal resistor, RPU1, implement a power on delay time for the internal LDO. Rev. 1.00 6 June 30, 2010 HT71D02/HT71D04 Power Line Data Transceiver Application Considerations It is envisaged that the devices will be used together with microcontroller based subsystems which will be required to provide two I/O pins for data transmission and reception. The MCU pin connected to the TG pin must be setup as an output while the MCU pin connected to the CX pin must be setup as an input. The power supply impedence will play an important role in applications using these devices and must be well defined for reliable data transmission and reception. The external components connected to the CP/TD pin must be chosen carefully to ensure that an adequate pulse duration on pin CX is generated. The usual decoupling precautions must be taken to ensure reliable operation. Application Circuits The following application circuit shows the device used in conjunction with a microcontroller. VIN VCC R 47uF VO VDD LDO 3.3V/5.0V +24V VDD Q1 104 R1 104 VCC CEB RPU1 270 R2 LVD 9.0V 104 VSS CDLY 203 Q2 CX CN MCU VO RX I/O0 Q3 Note: RX = 80kX CP/TD C1 + VDD RPU2 Protection Circuit VSS/TS 0V TG I/O1 C2 Q4 Vref Rev. 1.00 7 June 30, 2010 HT71D02/HT71D04 Power Line Data Transceiver Package Information 8-pin SOP (150mil) Outline Dimensions 5 8 A B 4 1 C C ' G H D E = F MS-012 Symbol A Nom. Max. 0.228 ¾ 0.244 B 0.150 ¾ 0.157 C 0.012 ¾ 0.020 C¢ 0.188 ¾ 0.197 D ¾ ¾ 0.069 E ¾ 0.050 ¾ F 0.004 ¾ 0.010 G 0.016 ¾ 0.050 H 0.007 ¾ 0.010 a 0° ¾ 8° Symbol Rev. 1.00 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. A 5.79 ¾ 6.20 B 3.81 ¾ 3.99 C 0.30 ¾ 0.51 C¢ 4.78 ¾ 5.00 D ¾ ¾ 1.75 E ¾ 1.27 ¾ F 0.10 ¾ 0.25 G 0.41 ¾ 1.27 H 0.18 ¾ 0.25 a 0° ¾ 8° 8 June 30, 2010 HT71D02/HT71D04 Power Line Data Transceiver Reel Dimensions D T 2 A C B T 1 SOP 8N Symbol Description Dimensions in mm A Reel Outer Diameter 330.0±1.0 B Reel Inner Diameter 100.0±1.5 C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.00 13.0 +0.5/-0.2 2.0±0.5 12.8 +0.3/-0.2 18.2±0.2 9 June 30, 2010 HT71D02/HT71D04 Power Line Data Transceiver Carrier Tape Dimensions P 0 D P 1 t E F W B 0 C D 1 P K 0 A 0 R e e l H o le IC p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e . SOP 8N Symbol Description Dimensions in mm 12.0 +0.3/-0.1 W Carrier Tape Width P Cavity Pitch 8.0±0.1 E Perforation Position 1.75±0.1 F Cavity to Perforation (Width Direction) 5.5±0.1 D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 6.4±0.1 B0 Cavity Width 5.2±0.1 K0 Cavity Depth 2.1±0.1 t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 1.55±0.1 1.50 +0.25/-0.00 0.30±0.05 9.3±0.1 10 June 30, 2010 HT71D02/HT71D04 Power Line Data Transceiver Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor (China) Inc. (Dongguan Sales Office) Building No. 10, Xinzhu Court, (No. 1 Headquarters), 4 Cuizhu Road, Songshan Lake, Dongguan, China 523808 Tel: 86-769-2626-1300 Fax: 86-769-2626-1311 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com Copyright Ó 2010 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 11 June 30, 2010