HT25LC512 CMOS 64K´8-Bit SPI Serial OTP EPROM Technical Document · Tools Information · FAQs · Application Note Features · Operating voltage: 2.7V~3.6V · Serial interface architecture · Programming voltage - VPP=12.5V±0.2V · Serial Peripheral Interface (SPI) compatible - modes 0 and 3 - VCC=6.0V±0.2V · CMOS and TTL compatible inputs and outputs · 512K-bit OTP ROM, access command compatible · Pin assignment compatible with AT25F512 with AT25F512 · Commercial temperature range (0°C to +70°C) · 64K´8-bit organization · 8-pin SOP package · 12MHz max. clock frequency @VCC=2.7V 15MHz max. clock frequency @VCC=3.0V General Description vice is optimized for use in many commercial and industrial applications where high density, low pin count, low voltage, and low power consumption are essential. The device operates at clock frequencies up to 10MHZ. The HT25LC512 is a 512K-bit OTP ROM of which function and pin assignment are compatible with AT25F512 and can directly replace the AT25F512 for cost down purposes when the memory in the system is just read only. There are 512K bits of memory which are organized as 65536 words of 8 bits each. The HT25LC512 uses a serial interface to sequentially access its data. The simple serial interface facilitates hardware layout, increase system reliability, minimize switching noise, and reduce package size and active pin count. The de- The HT25LC512 is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK). The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Block Diagram S C K H O L D S C L K C lo c k G e n e ra to r S I C S S IP O R e g is te r V P P X -a d d r S C L K S I C S S ta tu s R e g is te r Y -a d d r S ta te C o n tro l C E O T P R O M O E O u tp u t M U X ID R e g is te r S C L K C S Rev. 1.10 1 P IS O R e g is te r S O October 17, 2005 HT25LC512 Pin Assignment C S 1 8 V C C S O 2 7 H O L D V P P 3 6 S C K G N D 4 5 S I H T 2 5 L C 5 1 2 8 S O P -A Pin Description Pin No. Pin Name Description 1 CS Chip select 2 SO Serial Output 3 VPP Program voltage supply 4 GND Negative power supply, ground 5 SI Serial input 6 SCK Serial clock 7 HOLD Suspends serial input 8 VCC Positive power supply Absolute Maximum Rating Operation Temperature Commercial ..........................................................................................................0°C to +70°C Storage Temperature.............................................................................................................................-65°C to 125 °C Applied VCC Voltage with Respect to VSS ................................................................................................-0.6V to 7.0V Applied Voltage on Input Pin with Respect to VSS .....................................................................................-0.6V to 7.0V Applied Voltage on Output Pin with Respect to VSS ......................................................................... -0.6V to VCC+0.5V Applied VPP Voltage with Respect to VSS...............................................................................................-0.6V to 13.5V Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol Parameter Ta=0°C to +70°C Test Conditions VCC Conditions Min. Typ. Max. Unit Read Operation VCC Supply Voltage ¾ ¾ 2.7 ¾ 3.6 V VIL Input Low Voltage ¾ ¾ -0.5 ¾ 0.2VCC V VIH Input High Voltage ¾ ¾ 0.7VCC ¾ VCC+0.5 V VOL Output Low Voltage 2.7V~ IOL=0.15mA; 3.6V 2.7V£ VCC£ 3.6V ¾ ¾ 0.2 V VOH Output High Voltage 2.7V~ IOH=-100mA 3.6V VCC-0.2 ¾ ¾ V Rev. 1.10 2 October 17, 2005 HT25LC512 Symbol Parameter Test Conditions Conditions VCC Min. Typ. Max. Unit ISTB Standby Current 2.7V~ CS=VCC=3.6V, all in3.6V puts at CMOS levels ¾ 2 10 mA ICC Active Current, Read Operation 2.7V~ f=10MHz; SO=open 3.6V VCC=3.6V ¾ 10 15 mA IIL Input Leakage Current 2.7V~ VIN=0V to VCC 3.6V -3 ¾ 3 mA IOL Output Leakage Current 2.7V~ VIN=0V to VCC 3.6V -3 ¾ 3 mA Programming Operation VCC Supply Voltage ¾ ¾ 5.8 6.0 6.2 V VPP Supply Voltage ¾ ¾ 12.3 12.5 12.7 V VIL Input Low Voltage 6.0V ¾ -0.5 ¾ 0.2VCC V VIH Input High Voltage 6.0V ¾ 0.7VCC ¾ VCC+0.5 V ICC VCC Supply current 6.0V ¾ ¾ ¾ 40 mA IPP VPP Supply Current 6.0V ¾ ¾ ¾ 10 mA Note: VPP overshoot/undershoot riaging caused by fast rising time must not go below 11V or above 13V. A.C. Characteristics Symbol fSCK tWH tWL Parameter SCK Frequency SCK High Time SCK Low Time Ta=0°C to +70°C, VCC=2.7V to 3.6V Test Conditions Min. Typ. Max. Unit VCC=2.7V~3.0V 0 ¾ 12 MHz VCC=3.0V~3.6V 0 ¾ 15 MHz VCC=2.7V~3.0V 36 ¾ ¾ ns VCC=3.0V~3.6V 28 ¾ ¾ ns VCC=2.7V~3.0V 36 ¾ ¾ ns VCC=3.0V~3.6V 28 ¾ ¾ ns tCS Minimum CS High Time VCC=2.7V~3.6V 25 ¾ ¾ ns tCSS CS Setup Time VCC=2.7V~3.6V 25 ¾ ¾ ns tCSH CS Hold Time VCC=2.7V~3.6V 25 ¾ ¾ ns tSU Data in Setup Time VCC=2.7V~3.6V 20 ¾ ¾ ns tH Data in Hold Time VCC=2.7V~3.6V 5 ¾ ¾ ns tCD HOLD Setup Time VCC=2.7V~3.6V 20 ¾ ¾ ns tHD HOLD Hold Time VCC=2.7V~3.6V 15 ¾ ¾ ns tHO Output Hold Time VCC=2.7V~3.6V 0 ¾ ¾ ns tDIS Output Disable Time VCC=2.7V~3.6V ¾ ¾ 100 ns tV VCC=2.7V~3.0V ¾ ¾ 36 ns Output Valid VCC=3.0V~3.6V ¾ ¾ 28 ns tLZ HOLD to Output Low Z VCC=2.7V~3.6V ¾ ¾ 200 ms tHZ HOLD to Output High Z VCC=2.7V~3.6V ¾ ¾ 200 ms Rev. 1.10 3 October 17, 2005 HT25LC512 Symbol Parameter Test Conditions Min. Typ. Max. Unit Programming the OTP ROM fSCK SCK Frequency 48 70 160 kHz tWH SCK High Time 3 7.5 10.5 ms tWL SCK Low Time 3 7.5 10.5 ms tCS Minimum CS High Time 2 ¾ ¾ ms tCSS CS Setup Time 2 ¾ ¾ ms tCSH CS Hold Time 2 ¾ ¾ ms tSU Data in Setup Time 100 ¾ ¾ ns tH Data in Hold Time 100 ¾ ¾ ns Note: For normal READ operation, don¢t use the 99H instruction. Test Waveforms and Measurements 2 .4 V 2 .0 V A C D r iv in g L e v e ls A C D e v ic e U n d e r T e s t M e a s u re m e n t L e v e l 0 .8 V 0 .4 5 V Output Test Load 3 0 p F tR, tF< 5ns (10% to 90%) Functional Description Device Operation · Memory read Reading the HT25LC512 via the SO (Serial Output) pin requires the following sequence. After the CS line is pulled low to select a device, the READ instruction is transmitted via the SI line followed by the byte address to read. Upon completion, any data on the SI line will be ignored. The data (D7-D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The READ instruction can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous READ instruction. The HT25LC512 operation is controlled by instructions from the host processor. The HT25LC512 has only 3 kinds of instructions, Memory Read, Status Register read and Product ID Read. Any invalid instruction will be ignored without response from the HT25LC512. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the memory address location. While the CS pin is low, toggling the SCK pin controls the loading of the opcode and the memory address location through the SI (serial input) pin. All instructions, addresses and data are transferred with the most significant bit (MSB) first. Memory read, bit sequence is shown as follows: Bit Sequential 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit data 0 0 0 0 x 0 1 1 x x x x x x x 0 16 17 18 19 20 21 Bit Sequential Bit data Note: A15 A14 A13 A12 A11 A10 22 23 24 25 26 27 28 29 30 31 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ²x² don¢t care Rev. 1.10 4 October 17, 2005 HT25LC512 · Status register read ¨ · HOLD The HOLD pin is used in conjunction with the CS pin to select the HT25LC512. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. Status register format Bit Sequential 0 1 2 3 4 5 6 7 Bit Data 0 0 1 1 0 0 0 1 The data in the status register will always be 8CH. To read the status register, the bit sequence is shown below. After the last bit of the opcode is shifted in, the eight bits of the status register, starting with the MSB (bit 7), will be shifted out on the SO pin during the next eight clock cycles. After bit 0 of the status register has been shifted out, the sequence will repeat itself (as long as CS remains low and SCK is being toggled) starting again with bit 7. ¨ Power-on State When power is first applied to the device, the SO pin will be in a high-impedance state, and a high-to-low transition on the CS pin will be required to start a valid instruction. The SPI mode will be automatically selected on every falling edge of CS by sampling the inactive clock state. Status register read Bit sequence is shown as follows: Bit Sequential 0 1 2 3 4 5 6 7 Bit Data 0 0 0 0 x 1 0 1 Programming the OTP ROM Note: ²x² don¢t care Programming the OTP ROM of the HT25LC512 via the SI (Serial Input) pin requires the following sequence. After the CS line is pulled low to select a device, the programming instruction is transmitted via the SI line followed by the byte address to the program. Then the programming data are transmitted following the address. If only one byte is to be programmed, the CS line should be driven high after one byte data has been transmitted. The programming instruction can be continued since the byte address is automatically incremented and data will continue to be shifted in. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be programmed in one continuous programming instruction. · Product ID read The RDID instruction allows the user to read the manufacturer and product ID of the device. The first byte after the instruction will be the manufacture code (1CH= HOLTEK), followed by the device code (83H for 512K OTP ROM). Product ID read, bit sequence is shown as follows: Bit Sequential 0 1 2 3 4 5 6 7 Bit Data 0 0 0 1 x 1 0 1 Note: x: don¢t care Programming the OTP ROM, bit sequence is shown as follows: Bit Sequential 0 1 2 3 4 5 6 7 Bit Data 1 0 0 1 1 0 0 1 Bit Sequential 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Bit Data Rev. 1.10 A15 A14 A13 A12 A11 A10 5 8 9 10 11 12 13 14 15 A23 A22 A21 A20 A19 A18 A17 A16 October 17, 2005 HT25LC512 · Programming the OTP ROM timing (VPP=12.5V) C S 0 1 2 3 4 5 6 7 9 8 1 0 1 1 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 S C K A 2 2 A 2 3 A 2 1 S I H ig h im p e d a n c e A 3 A 2 A 1 A 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 7 D 6 S O (C o n tin u e ) C S S C K S I D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 S O Serial Interface Waveform Two different timing diagrams are shown. Waveform 1 shows the SCK signal being low when CS makes a high-to-low transition, and Waveform 2 shows the SCK signal being high when CS makes a high-to-low transition. Both waveforms show valid timing diagrams. The setup and hold times for the SI signal are referenced to the low-to-high transition on the SCK signal. Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2 shows timing that is compatible with SPI Mode 3. · Waveform 1 - Inactive clock polarity low C S tC tC tW S S tW H tC L S S H S C K tV S O tH H ig h im p e d a n c e O tD H ig h im p e d a n c e V a lid O u t tS U IS tH V a lid In S I · Waveform 2 - Inactive clock polarity high C S tC tC S S tW tW H tC L S S H S C K tV S O tH H ig h - z Rev. 1.10 U IS H ig h im p e d a n c e V a lid O u t tS S I tD O tH V a lid In 6 October 17, 2005 HT25LC512 Timing Diagrams RDSR Timing C S 0 1 2 3 4 5 6 7 9 8 1 0 1 1 1 2 1 3 1 4 S C K S I In s tr u c tio n D a ta O u t H ig h Im p e d a n c e S O 7 6 5 4 3 1 2 0 M S B READ Timing C S 0 S C K 1 2 5 4 3 7 6 8 9 1 0 1 1 2 3 2 2 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 -B y te A d d re s s S I In s tr u c tio n 2 1 3 2 1 0 H ig h Im p e d a n c e S O 7 6 5 4 3 2 1 0 HOLD Timing C S tC tC D D S C K tH tH D D H O L D tH Z tL Z S O RDID Timing C S S C K S I S O 0 1 0 0 0 2 4 1 3 x 5 1 0 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 1 D a ta O u t H ig h Im p e d a n c e 7 M a n u fa c tu re r C o d e ( H o lte k ) Rev. 1.10 7 6 5 4 3 2 1 0 D e v ic e C o d e October 17, 2005 HT25LC512 Package Information 8-pin SOP (150mil) Outline Dimensions A 5 8 1 B 4 C C ' G H D E Symbol Rev. 1.10 = F Dimensions in mil Min. Nom. Max. A 228 ¾ 244 B 149 ¾ 157 C 14 ¾ 20 C¢ 189 ¾ 197 D 53 ¾ 69 E ¾ 50 ¾ F 4 ¾ 10 G 22 ¾ 28 H 4 ¾ 12 a 0° ¾ 10° 8 October 17, 2005 HT25LC512 Product Tape and Reel Specifications Reel Dimensions D T 2 A C B T 1 SOP 8N Symbol Description A Reel Outer Diameter B Reel Inner Diameter Dimensions in mm 330±1.0 62±1.5 13.0+0.5 -0.2 C Spindle Hole Diameter D Key Slit Width 2.0±0.15 T1 Space Between Flange 12.8+0.3 -0.2 T2 Reel Thickness 18.2±0.2 Rev. 1.10 9 October 17, 2005 HT25LC512 Carrier Tape Dimensions P 0 D P 1 t E F W C D 1 B 0 P K 0 A 0 SOP 8N Symbol Description Dimensions in mm W Carrier Tape Width 12.0+0.3 -0.1 P Cavity Pitch 8.0±0.1 E Perforation Position 1.75±0.1 F Cavity to Perforation (Width Direction) 5.5±0.1 D Perforation Diameter 1.55±0.1 D1 Cavity Hole Diameter 1.5+0.25 P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 6.4±0.1 B0 Cavity Width 5.20±0.1 K0 Cavity Depth 2.1±0.1 t Carrier Tape Thickness 0.3±0.05 C Cover Tape Width Rev. 1.10 9.3 10 October 17, 2005 HT25LC512 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor (China) Inc. (Dongguan Sales Office) Building No. 10, Xinzhu Court, (No. 1 Headquarters), 4 Cuizhu Road, Songshan Lake, Dongguan, China 523808 Tel: 86-769-2626-1300 Fax: 86-769-2626-1311 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com Copyright Ó 2005 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.10 11 October 17, 2005