HT9032C/HT9032D Calling Line Identification Receiver Features · Operating voltage: 3.5V~5.5V · Power down mode · Bell 202 FSK and V.23 demodulation · High input sensitivity · Ring detection input and output · HT9032C: 16-pin DIP/SOP package HT9032D: 8-pin DIP/SOP package · Carrier detection output Applications · Feature phones · Computer telephony interface products · Caller ID adjunct boxes · ADSI products · Fax and answering machines General Description receive and display the calling number, or message waiting indicator sent to subscribers from the central office facilities. The device also provides a carrier detection circuit and a ring detection circuit for easier system applications. The HT9032 calling line identification receiver is a low power CMOS integrated circuit designed for receiving physical layer signals transmitted according to Bellcore TR-NWT-000030 and ITU-T V.23 specifications. The primary application of this device is for products used to Block Diagram T IP R IN G B a n d P a s s F ilte r D e m o d u la to r V a lid D a ta D e te c tio n P D W N R T IM E D O U T C D O U T C D E T P o w e r U p L o g ic In te rn a l P o w e r U p L o g ic R D E T 1 R D E T 2 V D D V S S Rev. 1.40 R D E T R in g A n a ly s is C ir c u it R e fe re n c e V o lta g e 1 C lo c k G e n e ra to r X 1 X 2 September 30, 2002 HT9032C/HT9032D Pin Assignment T IP R IN G 1 1 6 2 1 5 V D D D O U T C R D E T 1 3 1 4 D O U T R D E T 2 4 1 3 T E S T 5 1 2 C D E T R D E T R T IM E P D W N 6 1 1 7 1 0 V S S 8 9 D O U T 1 8 X 1 N C X 1 V D D T IP 2 7 X 2 3 6 V S S X 2 R IN G 4 5 P D W N H T 9 0 3 2 C 1 6 D IP -A /S O P -A H T 9 0 3 2 D 8 D IP -A /S O P -A Pin Description Pin Name I/O Description Power Inputs VDD ¾ Power-VDD is the input power for the internal logic. VSS ¾ Ground-VSS is ground connection for the internal logic. PDWN I A logic ²1² on this pin puts the chip in power down mode. When a logic ²0² is on this pin, the chip in power up mode. This is a Schmitt trigger input. Clock X1 I X2 O A crystal or ceramic resonator should be connected to this pin and X2. This pin may be driven from an external clock source. A crystal or ceramic resonator should be connected to this pin and X1. Ring Detections RDET1 I It detects ring energy on the line through an attenuating network and enables the oscillator and ring detection. This is a Schmitt trigger input. RDET2 I It couples the ring signal to the precision ring detector through an attenuating network. RDET=²0² if a valid ring signal is detected. This is a Schmitt trigger input. I/O An RC network may be connected to this pin in order to hold the pin voltage below 2.2V between the peaks of the ringing signal. This pin controls internal power up and activates the partial circuitry needed to determine whether the incoming ring is valid or not. The input is a Schmitt trigger input. The output cell structure is an NMOS output. RTIME FSK Signal Inputs TIP I This input pin is connected to the tip side of the twisted pair wires. It is internally biased to 1/2 VDD when the device is in power up mode. This pin must be DC isolated from the line. RING I This input pin is connected to the ring side of the twisted pair wires. It is internally biased to 1/2 VDD when the device is in power up mode. This pin must be DC isolated from the line. Detection Results RDET O This open drain output goes low when a valid ringing signal is detected. When connected to PDWN pin, this pin can be used for auto power up. CDET O This open drain output goes low indicating that a valid carrier is present on the line. A hysteresis is built-in to allow for a momentary drop out of the carrier. When connected to PDWN pin, this pin can be used for auto power up. DOUT O This pin presents the output of the demodulator when chip in power up mode. This data stream includes the alternate ²1² and ²0² pattern, the marking, and the data. At all other times, this pin is held high. DOUTC O This output presents the output of the demodulator when chip in power up mode and when an internal validation sequence has been successfully passed. This data stream does not include the alternate ²1² and ²0² pattern. This pin is always held high. TEST O Output pin for testing purposes only. NC ¾ No connection Rev. 1.40 2 September 30, 2002 HT9032C/HT9032D Absolute Maximum Ratings Voltages are referenced to VSS, except where noted. Supply Voltage .........................................-0.5V to 6.0V All Input Voltages.................................................25mW Operating Temperature Range ...................0°C to 70°C Storage Temperature Range ................-40°C to 150°C Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol Crystal=3.58MHz, Ta=0~70°C Test Conditions Parameter VDD Conditions ¾ Min. Typ. Max. Unit 3.5 5 5.5 V VDD Supply Voltage ¾ IDD1 Supply Current 5V PDWN=0 (3.58MHz OSC on) ¾ 3.2 5 mA IDD2 Supply Current 5V PDWN=1 and RTIME=0 (3.58MHz OSC on and internal circuits partially on) ¾ 1.9 2.5 mA ISTBY Standby Current 5V PDWN=1 and RTIME=1 (3.58MHz OSC off) ¾ ¾ 1 mA VIL Input Voltage Logic 0 5V ¾ ¾ ¾ 0.2V VDD VIH Input Voltage Logic 1 5V ¾ 0.8V ¾ ¾ VDD IOL Output Voltage Logic 0 5V IOL=1.6mA ¾ ¾ 0.1V VDD IOH Output Voltage Logic 1 5V IOH=0.8mA 0.9V ¾ ¾ VDD IIN Input Leakage Current, All Inputs 5V -1 ¾ 1 mA VT- Input Low Threshold Voltage 5V RDET1, RTIME, PDWN 2.0 2.3 2.6 V VT+ Input High Threshold Voltage 5V RDET1, RTIME, PDWN 2.5 2.75 3.0 V VTRDET2 Input Threshold Voltage 5V RDET2 1.0 1.1 1.2 V RIN Input DC Resistance 5V TIP, RING ¾ 500 ¾ kW T IP R IN G ¾ V D D D O U T C R D E T 1 R D E T 2 R T IM E P D W N V S S ~ D O U T C D E T R D E T 0 .1 m F X 1 X 2 3 .5 8 M H z H T 9 0 3 2 C 1 0 M W 3 0 p F S u p p ly c u r r e n t te s tin g : A ll, e x c e p t P D W N a n d R T IM E , u n w ir e d p in s a r e le ft flo a tin g . Rev. 1.40 3 September 30, 2002 HT9032C/HT9032D A.C. Characteristics - FSK Detection VSS=0V, Crystal=3.58MHz, Ta=0 to 70°C, 0dBm=0.7746Vrms @ 600W Symbol Test Conditions Parameter Conditions VDD Min. Typ. Max. Unit Input Sensitivity: TIP, RING 5V -40 -45 ¾ dBm Signal to Noise Ratio 5V ¾ 20 ¾ dB Band Pass Filter 60Hz 550Hz 2700Hz 3300Hz 5V ¾ dB Carrier Detect Sensitivity 5V tDOSC Oscillator Start Up Time 5V tSUPD Power Up to FSK Signal Set Up Time tDAQ tDCH S/N Frequency Response Relative to 1700Hz @ 0dBm ¾ -64 -4 -3 -34 ¾ -48 ¾ dBm ¾ ¾ 2 ¾ ms 5V ¾ 15 ¾ ¾ ms Carrier Detect Acquisition Time 5V ¾ ¾ 14 ¾ ms End of Data to Carrier Detect High 5V ¾ 8 ¾ ¾ ms 2 S e c 0 .5 S e c 0 .5 S e c 1 0 1 0 1 0 1 .. R in g S ig n a l tD D A T A O S C R T IM E R D E T P D W N C D E T tS U P D tD tD A Q D O U T R a w D A T A D O U T C X 1 Rev. 1.40 C H C o o k e d D A T A 3 .5 8 M H z 4 September 30, 2002 HT9032C/HT9032D Functional Description · Logical 0 (Space)=2100Hz The HT9032 is designed to be the physical layer demodulator for products targeted for the caller ID market. The data signaling interface should conform to Bell 202, which is described as follows: · Transmission rate=1200bps Since the band pass filter of the HT9032 can pass the V.23 signal, hence the HT9032 also can demodulate the V.23 signal. · Analog, phase coherent, frequency shift keying · Logical 1 (Mark)=1200+/-12Hz Ring detection · Logical 0 (Space)=2200+/-22Hz The data will be transmitted in the silent period between the first and second power ring before a voice path is established. The HT9032 should first detect a valid ring and then perform the FSK demodulation. The typical ring detection circuit of the HT9032 is depicted below. The power ring signal is first rectified through a bridge circuit and then sent to a resistor network that attenuates the incoming power ring. The values of resistors and capacitor given in the figure have been chosen to provide a sufficient voltage at RDET1 pin to turn on the Schmitt trigger input with approximately a 40 Vrms or greater power ring input from tip and ring. When VT+ of the Schmitt is exceeded, the NMOS on the pin RTIME will be driven to saturation discharging capacitor on RTIME. This will initialize a partial power up, with only the portions of the part involved with the ring signal analysis enabled, including RDET2 pin. With RDET2 pin enabled, a portion of the power ring above 1.2V is fed to the ring analysis circuit. Once the ring signal is qualified, the RDET pin will be sent low. · Transmission rate=1200bps · Data application=serial, binary, asynchronous The interface should be arranged to allow simple data transmission from the terminating central office, to the CPE (Customer Premises Equipment), only when the CPE is in an on-hook state. The data will be transmitted in the silent period between the first and second power ring before a voice path is established. The transmission level from the terminating C.O. will be -13.5dBm+/-1.0. The worst case attenuation through the loop is expected to be -20dB. The receiver therefore, should have a sensitivity of approximately -34.5dBm to handle the worst case installations. The ITU-T V.23 is also using the FSK signaling scheme to transmit data in the general switched telephone network. For mode 2 of the V.23, the modulation rate and characteristic frequencies are listed below: · Analog, phase coherent, frequency shift keying · Logical 1 (Mark)=1300Hz P D W N V 2 7 0 k W R T IM E D D P o w e r U p L o g ic 0 .2 m F T o B r id g e 4 7 0 k W In te rn a l P o w e r U p L o g ic R D E T 1 1 8 k W R D E T 2 R D E T R in g A n a ly s is C ir c u it 1 5 k W 1 .2 V Operation mode There are three operation modes of the HT9032. They are power down mode, partial power up mode, and power up mode. The three modes are classified by the following conditions: Modes Conditions Current Consumption Power down PDWN=²1² and RTIME=²1² <1mA Partial power up PDWN=²1² and RTIME=²0² 1.9mA typically Power up PDWN=²0² 3.2mA typically Rev. 1.40 5 September 30, 2002 HT9032C/HT9032D PDWN pin is below VT-, the part will be fully powered up, and ready to receive FSK. During this mode, the device current will increase to approximately 3.2mA (typ). The state of the RTIME pin is now a ²don¢t care² as far as the part is concerned. After the FSK message has been received, the PDWN pin can be allowed to return to VDD and the part will return to the power down mode. Normally, the PDWN pin and the RTIME pin control the operation mode of the HT9032. When both pins are HIGH, the HT9032 is set at the power down mode, consuming less than 1mA of supply current. When a valid power ring arrives, the RTIME pin will be driven below VT- and the portions of the part involved in the ring signal analysis are enabled. This is partial power up mode, consuming approximately 1.9mA typically. Once the Application Circuits Application circuit 1 T IP V 0 .2 m F ~ 0 .0 1 m F D D H T 1 0 5 0 2 0 0 k W 9 V ~ 0 .1 m F 4 7 0 k W 0 .2 m F R IN G 0 .0 1 m F 2 0 0 k W T IP R IN G V D D D O U T 1 8 k W 1 5 k W P D W N V S S M C U X 1 3 .5 8 M H z X 2 1 0 M W H T 9 0 3 2 D 3 0 p F 3 0 p F Application circuit 2 T IP V 0 .2 m F ~ 0 .0 1 m F H T 1 0 5 0 2 0 0 k W 9 V ~ 0 .1 m F 4 7 0 k W 0 .2 m F 2 0 k W R IN G 0 .0 1 m F 2 0 0 k W R D E T 2 V 1 5 k W 2 7 0 k W D D R T IM E P D W N V S S H T 9 0 3 2 C 0 .2 m F 6 2 0 k W V D D D O U T C T IP R IN G R D E T 1 1 8 k W Rev. 1.40 D D D O U T C D E T R D E T M C U X 1 3 .5 8 M H z X 2 1 0 M W 3 0 p F 3 0 p F September 30, 2002 HT9032C/HT9032D Application circuit 3 ¾ power on reset T IP V 0 .2 m F ~ 0 .0 1 m F D D H T 1 0 5 0 2 0 0 k W 9 V ~ 0 .1 m F 4 7 0 k W 0 .2 m F R IN G 2 0 0 k W 0 .0 1 m F V 1 8 k W C T IP R IN G V D D D D D O U T M C U 1 P D W N 1 5 k W R 1 V S S X 1 3 .5 8 M H z X 2 1 0 M W H T 9 0 3 2 D 3 0 p F 3 0 p F Application circuit 4 ¾ power on reset T IP V 0 .2 m F ~ 0 .0 1 m F D D H T 1 0 5 0 2 0 0 k W 9 V ~ 0 .1 m F 4 7 0 k W 0 .2 m F 2 0 k W R IN G 0 .0 1 m F 2 0 0 k W R D E T 1 V C R D E T 2 D D V 1 5 k W 1 R 1 8 k W 2 7 0 k W D D R T IM E P D W N V S S H T 9 0 3 2 C 0 .2 m F 1 2 0 k W V D D D O U T C T IP R IN G D O U T C D E T R D E T M C U X 1 3 .5 8 M H z X 2 1 0 M W 3 0 p F 3 0 p F V D D P D W N V T - X 1 3 .5 8 M H z s ta b le Note: reference C1=0.1mF R1=81kW Rev. 1.40 7 September 30, 2002 HT9032C/HT9032D Package Information 8-pin DIP (300mil) outline dimensions A 8 B 5 4 1 H C D = G E I F Symbol A Rev. 1.40 Dimensions in mil Min. Nom. Max. 355 ¾ 375 B 240 ¾ 260 C 125 ¾ 135 D 125 ¾ 145 E 16 ¾ 20 F 50 ¾ 70 G ¾ 100 ¾ H 295 ¾ 315 I 335 ¾ 375 a 0° ¾ 15° 8 September 30, 2002 HT9032C/HT9032D 16-pin DIP (300mil) outline dimensions A B 1 6 9 8 1 H C D = G E I F Symbol Rev. 1.40 Dimensions in mil Min. Nom. Max. A 745 ¾ 775 B 240 ¾ 260 C 125 ¾ 135 D 125 ¾ 145 E 16 ¾ 20 F 50 ¾ 70 G ¾ 100 ¾ H 295 ¾ 315 I 335 ¾ 375 a 0° ¾ 15° 9 September 30, 2002 HT9032C/HT9032D 8-pin SOP (150mil) outline dimensions 5 8 A B 4 1 C C ' G H D E Symbol Rev. 1.40 = F Dimensions in mil Min. Nom. Max. A 228 ¾ 244 B 149 ¾ 157 C 14 ¾ 20 C¢ 189 ¾ 197 D 53 ¾ 69 E ¾ 50 ¾ F 4 ¾ 10 G 22 ¾ 28 H 4 ¾ 12 a 0° ¾ 10° 10 September 30, 2002 HT9032C/HT9032D 16-pin SOP (300mil) outline dimensions 1 6 9 A B 1 8 C C ' G H D E Symbol Rev. 1.40 = F Dimensions in mil Min. Nom. Max. A 394 ¾ 419 B 290 ¾ 300 C 14 ¾ 20 C¢ 390 ¾ 413 D 92 ¾ 104 E ¾ 50 ¾ F 4 ¾ ¾ G 32 ¾ 38 H 4 ¾ 12 a 0° ¾ 10° 11 September 30, 2002 HT9032C/HT9032D Product Tape and Reel Specifications Reel dimensions D T 2 A C B T 1 SOP 8N Symbol Description Dimensions in mm A Reel Outer Diameter 330±1.0 B Reel Inner Diameter 62±1.5 C Spindle Hole Diameter 13.0+0.5 -0.2 D Key Slit Width 2.0±0.15 T1 Space Between Flange 12.8+0.3 -0.2 T2 Reel Thickness 18.2±0.2 SOP 16W (300mil) Symbol Description Dimensions in mm A Reel Outer Diameter 330±1.0 B Reel Inner Diameter 62±1.5 C Spindle Hole Diameter 13.0±0.5 -0.2 D Key Slit Width 2.0±0.5 T1 Space Between Flange 16.8+0.3 -0.2 T2 Reel Thickness 22.2±0.2 Rev. 1.40 12 September 30, 2002 HT9032C/HT9032D Carrier tape dimensions P 0 D P 1 t E F W C D 1 B 0 P K 0 A 0 SOP 8N Symbol Description Dimensions in mm 12.0+0.3 -0.1 W Carrier Tape Width P Cavity Pitch 8.0±0.1 E Perforation Position 1.75±0.1 F Cavity to Perforation (Width Direction) 5.5±0.1 D Perforation Diameter 1.55±0.1 D1 Cavity Hole Diameter 1.5+0.25 P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 6.4±0.1 B0 Cavity Width 5.20±0.1 K0 Cavity Depth 2.1±0.1 t Carrier Tape Thickness 0.3±0.05 C Cover Tape Width 9.3 SOP 16W (300mil) Symbol Description Dimensions in mm W Carrier Tape Width 16.0±0.2 P Cavity Pitch 12.0±0.1 E Perforation Position 1.75±0.1 F Cavity to Perforation (Width Direction) 7.5±0.1 D Perforation Diameter 1.5+0.1 D1 Cavity Hole Diameter 1.5+0.25 P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 10.9±0.1 B0 Cavity Width 10.8±0.1 K0 Cavity Depth 3.0±0.1 t Carrier Tape Thickness 0.3±0.05 C Cover Tape Width Rev. 1.40 13.3 13 September 30, 2002 HT9032C/HT9032D Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Sales Office) 11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Shanghai) Inc. 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Holmate Semiconductor, Inc. 48531 Warm Springs Boulevard, Suite 413, Fremont, CA 94539 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright Ó 2002 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.40 14 September 30, 2002