HT16D724 16-Channel Constant Current LED Driver Features Applications • Logic supply voltage: 5V/3.3V • LED displays • Maximum output terminal voltage: 17V • Message boards • 16-channel constant current output • Other consumer applications • Channel output current range – 3~45mA @VDD=5V General Description – 3~30mA @VDD=3.3V The HT16D724 is a high accuracy constant current driver which is specifically designed for LED display applications. The device provides 16-channel stable and constant current outputs for driving LEDs. Communication with the outside world is managed using a fully integrated serial interface function, which provides designers with a means of easy communication with external peripheral hardware. In this way, many devices can be cascaded together to drive larger LED displays. • Excellent output current accuracy – Between channels: < ± 2.5% – Between devices: < ± 3% • Adjustable OE line output pulse width • Staggered output delay • Up to 25MHz serial interface clock frequency • Schmitt trigger input structure • Package types: 24-pin SSOP Block Diagram OUT0 R-EXT OE OUT1 OUT15 I-REG 16 bit Output Driver 16 LE 16 bit Output Latch 16 SDI 16 bit Shift Register SDO CLK Rev. 1.00 1 September 19, 2012 HT16D724 Pin Assignment Pin Description Pin Name I/O VDD — Positive power supply GND — Negative power supply, ground. SDI I Serial data input CLK I Clock input Transfers data on its rising edge and carry command information when the LE line is asserted. LE I Data latch control Data is latched into the internal latch register during an LE pin high level. OE I Output enable control 1: all outputs disabled 0: all outputs enabled R-EXT I External resistor connection input Connected to an external resistor to setup the output ports current level. OUT0~OUT15 O Parallel data outputs SDO O Serial data output Used for cascading of other LED driver devices. Rev. 1.00 Description 2 September 19, 2012 HT16D724 Approximate Internal Connections Absolute Maximum Ratings Logic Supply Voltage (VDD)....VGND-0.3V to VGND+7.0V Output Current ................................................... 50mA Logic Input Voltage . ..............VGND-0.3V to VDD+0.3V GND Terminal Current .................................... 800mA Output Voltage ................................ VGND-0.3V to 20V Storage Temperature ........................... -55°C to 150°C Operating Temperature.......................... -40°C to 85°C Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.00 3 September 19, 2012 HT16D724 D.C. Characteristics VDD= 5.0V, Ta= 25°C Symbol Parameter VDD Logic Supply Voltage Test Condition Min. Typ. Max. Unit — 4.5 5.0 5.5 V IOUT Output Current Current range VIH High Input Voltage (SDI, CLK, LE, OE pins) 3 — 45 mA Ta=-40°C~85°C 0.7VDD — VDD V VIL Low Input Voltage (SDI, CLK, LE, OE pins) Ta=-40°C~85°C 0 — 0.3VDD V VOH VOL SDO pin High-Level Output Voltage IOH=-1mA 4.6 — — V SDO pin Low-Level Output Voltage IOL=+1mA — — 0.4 V IOZ Output Leakage Current VDS=17V and channel off — — 0.5 uA IOUT1 Output Current 1 VDS=1V, Rext=6000Ω, — 3.1 — mA IOUT2 Output Current 2 VDS=1V, Rext=720Ω, — 25.8 — mA dIOUT1 Current Skew IOUT=3.1mA, VDS=1V, Rext=6000Ω — ±1.5 ±2 % dIOUT2 Current Skew IOUT=25.8mA, VDS=1V, Rext =720Ω — ±1.5 ±2.5 % %/dVDS Output Current vs. Output Voltage Regulation VDS =1.0V~3.0V — ±0.1 — %/V %/dVDD Output Current vs. Supply Voltage Regulation VDD = 4.5V~5.5V — — ±1.0 %/V RPU OE Pin Pull High Resistor — 250 450 800 KΩ RPD LE Pin Pull Low Resistor — 250 450 800 KΩ Rext=open, OUT0~OUT15=off — 2 2.8 mA Rext=1240Ω, OUT0~OUT15=off — 4 4.8 mA Rext=620Ω, OUT0~OUT15=off — 6 6.8 mA Rext=1240Ω, OUT0~OUT15=on — 5.2 8.2 mA Rext=620Ω, OUT0~OUT15=on — 6.5 9.5 mA IDD Rev. 1.00 Supply Current 4 September 19, 2012 HT16D724 VDD= 3.3V, Ta= 25°C Symbol Parameter Test Condition Min. Typ. Max. Unit — 3 3.3 3.6 V 3 — 30 mA VDD Logic Supply Voltage IOUT Output Current Current range VIH High Input Voltage (SDI, CLK, LE, OE pins) Ta=-40°C~85°C 0.7VDD — VDD V VIL Low Input Voltage (SDI, CLK, LE, OE pins) Ta=-40°C~85°C 0 — 0.3VDD V VOH SDO pin High-Level Output Voltage IOH=-1mA 2.9 — — V VOL SDO pin Low-Level Output Voltage IOL=+1mA — — 0.4 V IOZ Output Leakage Current VDS=17V and channel off — — 0.5 uA IOUT1 Output Current 1 VDS=1V, Rext=6000Ω, — 3.1 — mA IOUT2 Output Current 2 VDS=1V, Rext=720Ω, — 25.8 — mA dIOUT1 Current Skew IOUT=3.1mA, VDS=1V, Rext=6000Ω — ±1.5 ±2 % dIOUT2 Current Skew IOUT=25.8mA, VDS=1V, Rext =720Ω — ±1.5 ±2.5 % %/dVDS Output Current vs. Output Voltage Regulation VDS =1.0V~3.0V — ±0.1 — %/V %/dVDD Output Current vs. Supply Voltage Regulation VDD = 3V~3.6V — — ±1.0 %/V RPU OE Pin Pull High Resistor — 250 450 800 KΩ RPD LE Pin Pull Low Resistor — IDD Supply Current 250 450 800 KΩ Rext=open, OUT0~OUT15=off — 1.7 2.3 mA Rext=1851Ω, OUT0~OUT15=off — 3.9 4.5 mA Rext=748Ω, OUT0~OUT15=off — 5.2 5.8 mA Rext=1851Ω, OUT0~OUT15=on — 3.9 4.5 mA Rext=748Ω, OUT0~OUT15=on — 5.2 5.8 mA D.C. Characteristics Test Circuit Rev. 1.00 5 September 19, 2012 HT16D724 A.C. Characteristics Symbol VDD= 5.0V, Ta= 25°C Min. Typ. Max. Unit Propagation Delay Time (“L” to “H”, CLK→SDO) — 20 40 ns Propagation Delay Time (“L” to “H”, CLK→OUT2n — 45 65 ns Propagation Delay Time (“L” to “H”, CLK→OUT2n+1) — 30 50 ns Propagation Delay Time (“L” to “H”, LE→OUT2n) — 45 65 ns Propagation Delay Time (“L” to “H”, LE→OUT2n+1) — 30 50 ns Propagation Delay Time (“L” to “H”, OE→OUT2n) — 45 65 ns Propagation Delay Time (“L” to “H”, OE→OUT2n+1) — 30 50 ns Propagation Delay Time (“H” to “L”, CLK→SDO) — 20 40 ns — 60 85 ns — 50 65 ns — 60 85 ns — 50 65 ns — 70 95 ns Propagation Delay Time (“H” to “L”, OE→OUT2n+1) — 60 75 ns tW(CLK) Pulse Width 20 — — ns tW(LE) Pulse Width 20 — — ns tW(OE) OE Pulse Width 70 100 — ns FCLK Data Clock Frequency — — 25 MHz th(LE) LE Hold Time 30 — — ns tsu(LE) LE Setup Time 5 — — ns th(SDI) SDI Hold Time 5 — — ns tsu(SDI) SDI Setup Time 3 — — ns tr Maximum CLK Rise Time (See Note) — — 500 ns tf Maximum CLK Fall Time (See Note) — — 500 ns tor VOUT Output Rise Time — 40 — ns tof VOUT Output Fall Time — 55 — ns tPLH tPLH1 tPLH2 tPLH3 tPHL tPHL1 tPHL2 tPHL3 Rev. 1.00 Parameter Propagation Delay Time (“H” to “L”, CLK→OUT2n) Propagation Delay Time (“H” to “L”, CLK→OUT2n+1) Test Condition VDS= 1.0V VIH= VDD Propagation Delay Time (“H” to “L”, LE→OUT2n) VIL= GND Propagation Delay Time (“H” to “L”, LE→OUT2n+1) VL= 4.5V Propagation Delay Time (“H” to “L”, OE→OUT2n) CL= 10pF Rext= 930Ω RL= 162Ω 6 September 19, 2012 HT16D724 VDD= 3.3V, Ta= 25°C Symbol Min. Typ. Max. Unit Propagation Delay Time (“L” to “H”, CLK→SDO) — 20 40 ns Propagation Delay Time (“L” to “H”, CLK→OUT2n — 70 100 ns Propagation Delay Time (“L” to “H”, CLK→OUT2n+1) — 50 80 ns Propagation Delay Time (“L” to “H”, LE→OUT2n) — 70 100 ns Propagation Delay Time (“L” to “H”, LE→OUT2n+1) — 50 80 ns Propagation Delay Time (“L” to “H”, OE→OUT2n) — 70 100 ns Propagation Delay Time (“L” to “H”, OE→OUT2n+1) — 50 80 ns Propagation Delay Time (“H” to “L”, CLK→SDO) — 20 40 ns — 100 120 ns — 80 100 ns — 100 120 ns — 80 100 ns — 90 105 ns Propagation Delay Time (“H” to “L”, OE→OUT2n+1) — 70 90 ns tW(CLK) Pulse Width 20 — — ns tW(LE) Pulse Width 20 — — ns tW(OE) OE Pulse Width 100 130 — ns FCLK Data Clock Frequency — — 25 MHz th(LE) LE Hold Time 30 — — ns tsu(LE) LE Setup Time 5 — — ns th(SDI) SDI Hold Time 5 — — ns tsu(SDI) SDI Setup Time 3 — — ns tr Maximum CLK Rise Time (See Note) — — 500 ns tf Maximum CLK Fall Time (See Note) — — 500 ns tor VOUT Output Rise Time — 40 — ns tof VOUT Output Fall Time — 60 — ns tPLH tPLH1 tPLH2 tPLH3 tPHL tPHL1 tPHL2 tPHL3 Parameter Propagation Delay Time (“H” to “L”, CLK→OUT2n) Propagation Delay Time (“H” to “L”, CLK→OUT2n+1) Test Condition VDS= 1.0V VIH= VDD Propagation Delay Time (“H” to “L”, LE→OUT2n) VIL= GND Propagation Delay Time (“H” to “L”, LE→OUT2n+1) VL= 3V Propagation Delay Time (“H” to “L”, OE→OUT2n) CL= 10pF Rext= 930Ω RL= 100Ω Note: The output channel exist 35ns delay time between odd numbers OUT2n+1 and even numbers OUT2n . Rev. 1.00 7 September 19, 2012 HT16D724 A.C. Characteristics Test Circuit Timing Waveforms t W(CLK) CLK 50% t su(SDI) SDI 50% 50% t h(SDI) 50% 50% t pLH,t pHL SDO 50% t h(LE) 50% LE OE tsu( LE) t W( LE) 50% ｀L＇ t pLH 2, t pHL2 50% OUTn t pLH1,t pHL1 tW(OE) OE 50% 50% tpHL3 tpHL3 OUT0 90% 50% 10% tof Rev. 1.00 8 90% 50% 10% tor September 19, 2012 HT16D724 Functional Description Serial-to-Parallel Operation Two operation methods are provided. The first is serial to serial operation which is used to transfer data in from an external microcontroller and transfer data out into another cascaded device. The other is serial to parallel operation which is used to transfer the device data to the external LED driver pins. If the LE pin is high and no clock is toggled on the CLK pin, then data will be latched from the shift register into an internal latch for transfer to the OUTn pins. Data from the internal latch is transferred to the OUTn pins using the OE pin. If the OE pin is low, then the data in the latch register will be transmitted to the output pins. The OUTn pins can be disabled into a high state by setting the OE pin to a high level. The SDO pin will not be affected by the LE or OE pin status. Serial-to-Serial Operation The serial-to-serial function is implemented using the SDI and SDO pins. The SDI pin is used to receive serial input data for transfer into the LSB of the internal shift register while the SDO pin is used to transmit the MSB of the internal shift register to cascaded devices. Each bit of the data is shifted in from the SDI pin into the register on the rising edge of the CLK input signal where it will become the LSB of the internal shift register. At the same time, the SDO pin will shift out the MSB in the shift register to any connected cascaded devices. The following timing diagram illustrates both the serial-to-serial and serial-to-parallel operational waveform. 1 0 0 1 2 3 4 5 6 7 8 9 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 CLK 1 1 D5 D4 1 2 D3 1 3 1 4 D2 1 5 D1 D0 SDI SD0 LE OE OUT0 D0 OFF ON OUT1 D1 OFF ON OUT2 D2 OFF ON OUT3 D3 OFF ON OUT13 D13 OFF ON OUT14 D14 OFF ON OUT15 D15 OFF ON Truth Table CLK Rev. 1.00 LE OE SDI OUT0.…OUT3…. OUT15 SDO H L L Dn Dn………....Dn-7….......…Dn-15 Dn-15 L Dn+1 No Change Dn-14 H L Dn+2 Dn+2…....….Dn-5…..……Dn-13 Dn-13 X L Dn+3 Dn+2…....….Dn-5…..……Dn-13 Dn-13 X H Dn+3 Off Dn-13 9 September 19, 2012 HT16D724 Constant Current Output The constant current can be calculated using the following formula: The output constant current for the output channels is set by a single external resistor, REXT, which is connected between the R-EXT pin and GND. The current level is set according to the value of this resistor. The current variation between channels is less than ±2.5% while the current variation between different devices is less than ±3%. The characteristic curve in the saturation region is flat and users can refer to the charts as shown below. The output current remains constant regardless of LED forward voltage (VF) variations. I OUT = VR −EXT 18.9 × M1 = R EXT R EXT The following I-V curve chart it provided for reference purposes. HT16D724 IOUT vs. VDS at various Rext, V DD=5V 50 40 IOUT(mA) 30 20 10 0 0 0.5 1 1.5 VDS(V) 2 2.5 3 2.5 3 HT16D724 IOUT vs. VDS at various Rext, V DD=3.3V IOUT(mA) 30 20 10 0 0 Rev. 1.00 0.5 1 1.5 VDS(V) 10 2 September 19, 2012 HT16D724 HT16D724 Rext vs. IOUT 50 IOUT(mA) 40 30 20 10 0 0 1000 2000 3000 Rext(Ω) 4000 5000 6000 Load Supply Voltage (VLED) HT16D724 can be operated very well when VDS is set from 0.7V to 2V. It is recommended to use the lowest supply voltage (VLED) to reduce the VDS value in order to lower both the power consumption of HT16D724 and IC ���� temperature. VLED Control Signal VF VDS≥0.7V HT16D724 Rev. 1.00 11 September 19, 2012 HT16D724 Application Circuit VLED LED Matrix Control signal of scanning Cn Micro-contoller SDI CLK LE OE 16 16 OUT0~OUT15 SDO OUT0~OUT15 Rev. 1.00 CLK LE OE 12 SDO OUT0~OUT15 HT16D724 HT16D724 SDI 16 SDI CLK LE OE SDO HT16D724 SDI CLK LE OE September 19, 2012 HT16D724 Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website (http://www.holtek.com.tw/english/ literature/package.pdf) for the latest version of the package information. 24-pin SSOP (150mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A 0.228 — 0.244 B 0.150 — 0.157 C C׳ 0.008 — 0.012 0.335 — 0.346 D 0.054 — 0.060 E — 0.025 — F 0.004 — 0.010 G 0.022 — 0.028 H 0.007 — 0.010 α 0° — 8° Symbol Rev. 1.00 Dimensions in mm Min. Nom. Max. A 5.79 — 6.20 B 3.81 — 3.99 C C׳ 0.20 8.51 — 8.79 D 1.37 — 1.52 E — 0.64 — F 0.10 — 0.25 G 0.56 — 0.71 H 0.18 — 0.25 α 0° — 8° 0.30 13 September 19, 2012 HT16D724 Reel Dimensions SSOP 24S (150mil) Symbol Rev. 1.00 Description Dimensions in mm A Reel Outer Diameter 330.0±1.0 B Reel Inner Diameter 100.0±1.5 C Spindle Hole Diameter 13.0+0.5/-0.2 D Key Slit Width T1 Space Between Flang 16.8+0.3/-0.2 2.0±0.5 T2 Reel Thickness 22.2±0.2 14 September 19, 2012 HT16D724 Carrier Tape Dimensions SSOP 24S (150mil) Symbol Description Dimensions in mm 16.0+0.3/-0.1 W Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) 7.5±0.1 D Perforation Diameter 1.5+0.1/-0.0 D1 Cavity Hole Diameter 1.50+0.25/-0.00 P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 6.5±0.1 B0 Cavity Width 9.5±0.1 K0 Cavity Depth 2.1±0.1 8.0±0.1 1.75±0.10 t Carrier Tape Thickness 0.30±0.05 C Cover Tape Width 13.3±0.1 Rev. 1.00 15 September 19, 2012 HT16D724 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor (China) Inc. (Dongguan Sales Office) Building No.10, Xinzhu Court, (No.1 Headquarters), 4 Cuizhu Road, Songshan Lake, Dongguan, China 523808 Tel: 86-769-2626-1300 Fax: 86-769-2626-1311, 86-769-2626-1322 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com Copyright© 2012 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 16 September 19, 2012