Data Sheet

DATASHEET
Low Noise, Low Power, 100 Taps, Digitally Controlled
Potentiometer (XDCP™)
X9317
Features
The Intersil X9317 is a digitally controlled potentiometer
(XDCP™). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory. The wiper
position is controlled by a 3-wire interface.
• Solid-state potentiometer
The potentiometer is implemented by a resistor array
composed of 99 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The position of the
wiper element is controlled by the CS, U/D, and INC inputs. The
position of the wiper can be stored in nonvolatile memory and
then be recalled upon a subsequent power-up operation.
The device can be used as a three-terminal potentiometer for
voltage control or as a two-terminal variable resistor for current
control in a wide variety of applications.
Applications
• LCD bias control
• 100 wiper tap points
- Wiper position stored in nonvolatile memory and recalled
on power-up
• 99 resistive elements
- Temperature compensated
- End-to-end resistance range ±20%
• Low power CMOS
- VCC = 2.7V to 5.5V, and 5V ±10%
- Standby current <5µA
• High reliability
- Endurance, 100,000 data changes per bit
- Register data retention, 100 years
• RTOTAL values = 10kΩ, 50kΩ, 100kΩ
• DC bias adjustment
• Packages
- 8 Ld SOIC, TSSOP, and MSOP
• Gain and offset trim
• Laser diode bias control
• Pb-free (RoHS compliant)
• Voltage regulator output control
U/D
INC
VCC (SUPPLY VOLTAGE)
CS
UP/DOWN
COUNTER
CONTROL
AND
MEMORY
97
7-BIT
NONVOLATILE
MEMORY
RW
DEVICE SELECT
(CS)
RH
99
98
RH
UP/DOWN
(U/D)
INCREMENT
(INC)
• 3-wire serial up/down interface
RL
96
ONE
OF
ONE
HUNDRED
DECODER
WIPER
SWITCHES
RESISTOR
ARRAY
2
VSS (GROUND)
GENERAL
VCC
VSS
STORE AND
RECALL
CONTROL
CIRCUITRY
1
0
RL
RW
DETAILED
FIGURE 1. BLOCK DIAGRAM
November 4, 2014
FN8183.9
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2004, 2005, 2008, 2009, 2012, 2014. All Rights Reserved
Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
X9317
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
VCC LIMITS
(V)
RTOTAL
(kΩ)
TEMPERATURE
RANGE (°C)
5 ±10%
10
0 to +70
8 Ld MSOP
M8.118
-40 to +85
8 Ld MSOP
M8.118
8 Ld SOIC
M8.15E
PACKAGE
(Pb-Free)
PKG.
DWG. #
X9317WM8Z
DCW
X9317WM8IZ
DCT
X9317WS8Z
X9317W Z
0 to +70
X9317WS8IZ
X9317W ZI
-40 to +85
8 Ld SOIC
M8.15E
X9317WV8Z
9317W Z
0 to +70
8 Ld TSSOP
M8.173
X9317WV8IZ
9317W IZ
-40 to +85
8 Ld TSSOP
M8.173
X9317UM8Z
DCS
0 to +70
8 Ld MSOP
M8.118
X9317UM8IZ
DCR
-40 to +85
8 Ld MSOP
M8.118
X9317US8Z
X9317U Z
0 to +70
8 Ld SOIC
M8.15E
X9317US8IZ
X9317U ZI
-40 to +85
8 Ld SOIC
M8.15E
X9317UV8Z
9317U Z
0 to +70
8 Ld TSSOP
M8.173
X9317UV8IZ
9317U IZ
-40 to +85
8 Ld TSSOP
M8.173
X9317TM8Z
DCN
0 to +70
8 Ld MSOP
M8.118
X9317TM8IZ
DCL
-40 to +85
8 Ld MSOP
M8.118
X9317TS8Z
X9317T Z
0 to +70
8 Ld SOIC
M8.15E
X9317TS8IZ
X9317T ZI
-40 to +85
8 Ld SOIC
M8.15E
X9317TV8Z
9317T Z
0 to +70
8 Ld TSSOP
M8.173
X9317TV8IZ
9317T IZ
-40 to +85
8 Ld TSSOP
M8.173
X9317WM8Z-2.7
DCX
0 to +70
8 Ld MSOP
M8.118
X9317WM8IZ-2.7
DCU
-40 to +85
8 Ld MSOP
M8.118
X9317WS8Z-2.7
X9317W ZF
0 to +70
8 Ld SOIC
M8.15E
X9317WS8IZ-2.7
X9317W ZG
-40 to +85
8 Ld SOIC
M8.15E
X9317WV8Z-2.7
9317W FZ
0 to +70
8 Ld TSSOP
M8.173
X9317WV8IZ-2.7
AKZ
-40 to +85
8 Ld TSSOP
M8.173
X9317UM8Z-2.7
AOB
0 to +70
8 Ld MSOP
M8.118
X9317UM8IZ-2.7
AOH
-40 to +85
8 Ld MSOP
M8.118
X9317US8Z-2.7
X9317U ZF
0 to +70
8 Ld SOIC
M8.15E
X9317US8IZ-2.7
X9317U ZG
-40 to +85
8 Ld SOIC
M8.15E
X9317UV8Z-2.7
9317U FZ
0 to +70
8 Ld TSSOP
M8.173
X9317UV8IZ-2.7
9317U GZ
-40 to +85
8 Ld TSSOP
M8.173
X9317TM8Z-2.7
DCP
0 to +70
8 Ld MSOP
M8.118
50
100
2.7 to 5.5
10
50
100
X9317TM8IZ-2.7
DCM
-40 to +85
8 Ld MSOP
M8.118
X9317TS8Z-2.7
X9317T ZF
0 to +70
8 Ld SOIC
M8.15E
X9317TS8IZ-2.7
X9317T ZG
-40 to +85
8 Ld SOIC
M8.15E
X9317TV8Z-2.7
9317T FZ
0 to +70
8 Ld TSSOP
M8.173
X9317TV8IZ-2.7
9317T GZ
-40 to +85
8 Ld TSSOP
M8.173
NOTES:
1. Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for X9317. For more information on MSL please see tech brief TB363.
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FN8183.9
November 4, 2014
X9317
Pin Configurations
Pin Descriptions
X9317
(8 LD TSSOP)
TOP VIEW
CS
1
8
RL
VCC
2
7
RW
INC
3
6
VSS
U/D
4
5
RH
X9317
(8 LD SOIC, 8 LD MSOP)
TOP VIEW
INC
1
8
VCC
U/D
2
7
CS
RH
3
6
RL
VSS
4
5
RW
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3
SOIC/MSOP
TSSOP
SYMBOL
BRIEF DESCRIPTION
1
3
INC
Increment Toggling INC while CS
is low moves the wiper either up
or down.
2
4
U/D
Up/Down The U/D input controls
the direction of the wiper
movement.
3
5
RH
The high terminal is equivalent to
one of the fixed terminals of a
mechanical potentiometer.
4
6
VSS
Ground
5
7
R
The wiper terminal is equivalent
to the movable terminal of a
mechanical potentiometer.
6
8
RL
The low terminal is equivalent to
one of the fixed terminals of a
mechanical potentiometer.
7
1
CS
Chip Select The device is
selected when the CS input is
LOW, and de-selected when CS is
high.
8
2
VCC
Supply Voltage
W
FN8183.9
November 4, 2014
X9317
Absolute Maximum Ratings
Thermal Information
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±8.8mA
RH, RW, RL to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V
Voltage on CS, INC, U/D and VCC
with Respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1V to +7V
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
SOIC Package (Notes 4, 5) . . . . . . . . . . . . .
115
60
MSOP Package (Notes 4, 5) . . . . . . . . . . . .
145
55
TSSOP Package (Notes 4, 5). . . . . . . . . . . .
155
49
Junction Temperature Under Bias . . . . . . . . . . . . . . . . . . . -65C to +135C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For JC, the “case temp” location is taken at the package top center.
Potentiometer Specifications
(Industrial) and 0°C to +70°C (Commercial).
SYMBOL
VCC = full range. Boldface limits apply across the operating temperature range, -40°C to +85°C
PARAMETER
TEST CONDITIONS/NOTES
MIN
(Note 13)
TYP
(Note 9)
MAX
(Note 13)
UNIT
RTOTAL
End-to-end Resistance Tolerance
See “Ordering Information” on page 2 for
values
-20
+20
%
VRH/RL
RH/RL Terminal Voltage
VSS = 0V
VSS
VCC
V
Power Rating
RTOTAL ≥ 10kΩ
10
mW
RW
IW
Wiper Resistance
IW = [V(RH) - V(RL)]/ RTOTAL, VCC = 5V
200
400
Ω
IW = [V(RH) - V(RL)]/ RTOTAL, VCC = 2.7V
400
1000
Ω
+4.4
mA
Wiper Current (Note 10)
See “Test Circuit” on page 5
Noise (Note 12)
Ref: 1kHz
-4.4
Resolution
VCC
dBV
1
%
Absolute Linearity (Note 6)
V(RH) = VCC, V(RL) = 0V
-1
+1
MI
(Note 8)
Relative Linearity (Note 7)
V(RH) = VCC, V(RL) = 0V
-0.2
+0.2
MI
(Note 8)
RTOTAL Temperature Coefficient (Note 10)
V(RH) = VCC, V(RL) = 0V
Ratiometric Temperature Coefficient
(Notes 10, 11)
CH/CL/CW
(Note 10)
-120
±300
ppm/°C
±20
ppm/°C
10/10/25
pF
Potentiometer Capacitances
See “Equivalent Circuit” on page 5
Supply Voltage
X9317
4.5
5.5
V
X9317-2.7
2.7
5.5
V
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FN8183.9
November 4, 2014
X9317
DC Electrical Specifications
VCC = 5V ±10%. Boldface limits apply across the operating temperature range, -40°C to +85°C
(Industrial) and 0°C to +70°C (Commercial).
SYMBOL
PARAMETER
MIN
(Note 13)
TEST CONDITIONS
TYP
(Note 9)
MAX
(Note 13)
UNIT
ICC1
VCC Active Current (Increment)
CS = VIL, U/D = VIL or VIH and INC = VIL/VIH at
min. tCYC
RL, RH, RW not connected
80
µA
ICC2
VCC Active Current (Store)
(non-volatile write)
CS = VIH, U/D = VIL or VIH and INC = VIL or VIH.
RL, RH, RW not connected
400
µA
ISB
Standby Supply Current
CS  VIH, U/D and INC = VIL
RL, RH, RW not connected
5
µA
ILI
CS, INC, U/D Input Leakage Current
VIN = VSS to VCC
-10
+10
µA
VIH
CS, INC, U/D Input HIGH Voltage
VCC x 0.7
VCC + 0.5
V
VIL
CS, INC, U/D Input LOW Voltage
-0.5
VCC x 0.1
V
CIN (Note 10)
CS, INC, U/D Input Capacitance
VCC = 5V, VIN = VSS, TA = +25°C, f = 1MHz
10
pF
Endurance and Data Retention VCC = 5V ±10%, TA = Full Operating Temperature Range.
PARAMETER
MIN
UNIT
Minimum Endurance
100,000
Data changes per bit
Data Retention
100
Years
Test Circuit
Equivalent Circuit
TEST POINT
AC Conditions of Test
RTOTAL
RH
CW
CH
RW
FORCE
CURRENT
CL
10pF
RL
Input pulse levels
0V to 3V
Input rise and fall times
10ns
Input reference levels
1.5V
25pF
10pF
RW
AC Electrical Specifications
(Industrial) and 0°C to +70°C (Commercial).
VCC = 5V ±10%. Boldface limits apply across the operating temperature range, -40°C to +85°C
SYMBOL
tCl
PARAMETER
MIN
(Note 13)
TYP
(Note 9)
MAX
(Note 13)
UNIT
CS to INC Setup
50
ns
tlD (Note 10)
INC HIGH to U/D Change
100
ns
tDI (Note 10)
U/D to INC Setup
1
µs
tlL
INC LOW Period
960
ns
tlH
INC HIGH Period
960
ns
tlC
INC Inactive to CS Inactive
1
µs
tCPHS
CS Deselect Time (STORE)
10
ms
CS Deselect Time (NO STORE)
100
ns
tCPHNS
(Note 10)
tIW
INC to RW Change
tCYC
INC Cycle Time
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5
1
2
5
µs
µs
FN8183.9
November 4, 2014
X9317
AC Electrical Specifications
VCC = 5V ±10%. Boldface limits apply across the operating temperature range, -40°C to +85°C
(Industrial) and 0°C to +70°C (Commercial). (Continued)
SYMBOL
tR, tF
(Note 10)
tPU (Note 10)
tR VCC
(Note 10)
tWR
PARAMETER
MIN
(Note 13)
TYP
(Note 9)
INC Input Rise and Fall Time
Power-up to Wiper Stable
VCC Power-up Rate
0.2
Store Cycle
5
MAX
(Note 13)
UNIT
500
µs
5
µs
50
V/ms
10
ms
NOTES:
6. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [V(RW(n)(actual))-V(RW(n)(expected))]/MI
V(RW(n)(expected)) = n(V(RH)-V(RL))/99 + V(RL), with n from 0 to 99.
7. Relative linearity is a measure of the error in step size between taps = [V(RW(n+1))-(V(RW(n)) - MI)]/MI.
8. 1 Ml = Minimum Increment = [V(RH)-V(RL)]/99.
9. Typical values are for TA = +25°C and nominal supply voltage.
10. This parameter is not 100% tested.
11. Ratiometric temperature coefficient = (V(RW)T1(n)-V(RW)T2(n))/[V(RW)T1(n)(T1-T2) x 106], with T1 and T2 being 2 temperatures, and n from 0 to 99.
12. Measured with wiper at tap position 99, RL grounded, using test circuit.
13. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Power-up and Down
Requirements
The recommended power-up sequence is to apply VCC/VSS first,
then the potentiometer voltages. During power-up, the data sheet
parameters for the DCP do not fully apply until 1ms after VCC
reaches its final value. The VCC ramp spec is always in effect. In
order to prevent unwanted tap position changes, or an
inadvertent store, bring the CS and INC high before or
concurrently with the VCC pin on power-up.
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November 4, 2014
X9317
AC Timing
CS
tCYC
tCI
tIL
tIH
tCPHNS
tCPHS
tIC
90%
90%
10%
INC
tID
tDI
tF
tR
U/D
tIW
MI
RW
(3)
Typical Performance Characteristic
0
-50
PPM
-100
-150
-200
-250
-300
-350
-55 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105115 125
TEMPERATURE (°C)
FIGURE 2. TYPICAL TOTAL RESISTANCE TEMPERATURE COEFFICIENT
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X9317
Pin Descriptions
Instructions and Programming
RH and RL
The INC, U/D and CS inputs control the movement of the wiper
along the resistor array. With CS set LOW, the device is selected
and enabled to respond to the U/D and INC inputs. HIGH-to-LOW
transitions on INC will increment or decrement (depending on the
state of the U/D input) a 7-bit counter. The output of this counter
is decoded to select one of one hundred wiper positions along
the resistive array.
The high (RH) and low (RL) terminals of the X9317 are equivalent
to the fixed terminals of a mechanical potentiometer. The
terminology of RL and RH references the relative position of the
terminal in relation to wiper movement direction selected by the
U/D input and not the voltage potential on the terminal.
RW
RW is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the control inputs. The
wiper terminal series resistance is typically 200Ω.
Up/Down (U/D)
The U/D input controls the direction of the wiper movement and
whether the counter is incremented or decremented.
Increment (INC)
The INC input is negative-edge triggered. Toggling INC will move
the wiper and either increment or decrement the counter in the
direction indicated by the logic level on the U/D input.
Chip Select (CS)
The device is selected when the CS input is LOW. The current
counter value is stored in nonvolatile memory when CS is
returned HIGH while the INC input is also HIGH. After the store
operation is complete, the X9317 will be placed in the low power
standby mode until the device is selected once again.
Principles of Operation
There are three sections of the X9317: the control section, the
nonvolatile memory, and the resistor array. The control section
operates just like an up/down counter. The output of this counter
is decoded to turn on a single electronic switch connecting a
point on the resistor array to the wiper output. The contents of the
counter can be stored in nonvolatile memory and retained for
future use. The resistor array is comprised of 99 individual
resistors connected in series. Electronic switches at either end of
the array and between each resistor provide an electrical
connection to the wiper pin, RW.
The wiper acts like its mechanical equivalent and does not move
beyond the first or last position. That is, the counter does not
wrap around when clocked to either extreme.
The electronic switches on the device operate in a “make before
break” mode when the wiper changes tap positions. If the wiper
is moved several positions, multiple taps are connected to the
wiper for tIW (INC to VW change). The RTOTAL value for the device
can temporarily be reduced by a significant amount if the wiper
is moved several positions.
The value of the counter is stored in nonvolatile memory
whenever CS transitions HIGH while the INC input is also HIGH.
The system may select the X9317, move the wiper and deselect
the device without having to store the latest wiper position in
nonvolatile memory. After the wiper movement is performed as
previously described and once the new position is reached, the
system must keep INC LOW while taking CS HIGH. The new wiper
position will be maintained until changed by the system or until a
power-up/down cycle recalls the previously stored data.
This procedure allows the system to always power-up to a preset
value stored in nonvolatile memory; then during system
operation minor adjustments could be made. The adjustments
might be based on user preference, system parameter changes
due to temperature drift, etc.
The state of U/D may be changed while CS remains LOW. This
allows the host system to enable the device and then move the
wiper up and down until the proper trim is attained.
Mode Selection
CS
INC
U/D
MODE
L
H
Wiper up
L
L
Wiper down
H
X
Store wiper position to nonvolatile
memory
X
X
Standby
L
X
No store, return to standby
L
H
Wiper up (not recommended)
L
L
Wiper down (not recommended)
H
Applications Information
Electronic digitally controlled (XDCP) potentiometers provide
three powerful application advantages:
1. The variability and reliability of a solid-state potentiometer,
2. The flexibility of computer-based digital controls, and
3. The retentivity of nonvolatile memory used for the storage of
multiple potentiometer settings or data.
When the device is powered-down, the last wiper position stored
will be maintained in the nonvolatile memory. When power is
restored, the contents of the memory are recalled and the wiper
is set to the value last stored.
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FN8183.9
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X9317
Basic Configurations of Electronic Potentiometers
VREF
VREF
RH
RW
RL
I
FIGURE 3. THREE TERMINAL POTENTIOMETER; VARIABLE VOLTAGE
DIVIDER
FIGURE 4. TWO TERMINAL VARIABLE RESISTOR; VARIABLE CURRENT
Basic Circuits
+V
+V
R1
R1
+5V
R2
VS
+V
+5V
RW
VREF
+
X
RW
LMC7101
-
-
100k
+V
VOUT
LMC7101
RW
(a)
VOUT = VW/RW
FIGURE 5. BUFFERED REFERENCE VOLTAGE
VIN
VO (REG)
317
R2
LT311A
-
VO
VO
}
}
10kΩ
+
LMC7101
10kΩ
R2
9
VS
+5V
100kΩ
Iadj
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FIGURE 7. SINGLE SUPPLY INVERTING
AMPLIFIER
VS
+
FIGURE 8. VOLTAGE REGULATOR
VO = (R2/R1)VS
FIGURE 6. CASCADING TECHNIQUES
R1
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
100k
(b)
R1
VO
+
+5V
R1
R2
10kΩ
+5V
FIGURE 9. OFFSET VOLTAGE ADJUSTMENT
VUL = {R1/(R1+R2)} VO(max)
VLL = {R1/(R1+R2)} VO(min)
FIGURE 10. COMPARATOR WITH
HYSTERESIS
FN8183.9
November 4, 2014
X9317
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
November 4, 2014
FN8183.9
CHANGE
Added Revision History
Converted to New Template and added new Intersil Standards.
Updated Ordering Information to show all U parts in column for Rtotal (kΩ) to show 50 as the value.
Added thermal information (Tja and Tjc).
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
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For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
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X9317
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 7/11
5
3.0±0.05
A
DETAIL "X"
D
8
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.55 ± 0.15
0.25
3°±3°
0.85±010
H
DETAIL "X"
C
SEATING PLANE
0.25 - 0.36
0.08 M C A-B D
0.10 ± 0.05
0.10 C
SIDE VIEW 1
(5.80)
NOTES:
(4.40)
(3.00)
1. Dimensions are in millimeters.
(0.65)
(0.40)
(1.40)
TYPICAL RECOMMENDED LAND PATTERN
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2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
FN8183.9
November 4, 2014
X9317
Package Outline Drawing
M8.173
8 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 2, 01/10
A
2
4
3.0 ±0.5
SEE DETAIL "X"
5
8
6.40
CL
4.40 ±0.10
3
4
0.20 C BA
PIN 1
ID MARK
1
4
0.09-0.20
B
0.65
TOP VIEW
END VIEW
1.00 REF
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
0.25 +0.05/-0.06
0.10 C
0.10
GAUGE
PLANE
0.25
6
CBA
0°-8°
0.05 MIN
0.15 MAX
0.60 ±0.15
DETAIL "X"
SIDE VIEW
(1.45)
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
(5.65)
PACKAGE BODY
OUTLINE
2. Dimension does not include mold flash, protrusions or
gate burrs. Mold flash, protrusions or gate burrs shall
not exceed 0.15 per side.
3. Dimension does not include interlead flash or protrusion.
Interlead flash or protrusion shall not exceed 0.15 per side.
4. Dimensions are measured at datum plane H.
5. Dimensioning and tolerancing per ASME Y14.5M-1994.
(0.35 TYP)
(0.65 TYP)
TYPICAL RECOMMENDED LAND PATTERN
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12
6. Dimension on lead width does not include dambar protrusion.
Allowable protrusion shall be 0.08 mm total in excess of
dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm.
7. Conforms to JEDEC MO-153, variation AC. Issue E
FN8183.9
November 4, 2014
X9317
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
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13
FN8183.9
November 4, 2014