X9116
®
Low Noise, Low Power, Low Cost
Data Sheet
September 26, 2006
Digitally Controlled Potentiometer
(XDCP™)
Features
The Intersil X9116 is a digitally controlled nonvolatile
potentiometer designed to be used in trimmer applications.
The pot consists of 15 equal resistor segments that connect
to the wiper pin through programmable CMOS switches. The
tap position is programmed through a 3-wire up/down serial
port. The last position of the wiper is stored in a nonvolatile
memory location which is recalled at the time of power up of
the device.
• 16 wiper taps
FN8160.2
• Solid-state nonvolatile
• 3-wire up/down serial interface
• VCC = 2.7V and 5V
• Active current < 50µA max.
• Standby current < 1µA max.
• RTOTAL = 10kΩ
The wiper moves through sequential tap positions with
inputs on the serial port. A falling edge on INC (bar) causes
the tap position to increment one position up or down based
on whether the U/D (bar) pin is held high or low.
• Packages: 8 Ld MSOP, 8 Ld SOIC
• Pb-free plus anneal available (RoHS compliant)
Pinout
The X9116 can be used in many applications requiring a
variable resistance. In many cases it can replace a
mechanical trimmer and offers many advantages such as
temperature and time stability as well as the reliability of a
solid state solution.
SOIC/MSOP
INC
1
8
VCC
U/D
2
7
CS
VH/RH
3
6
VL/RL
V SS
4
5
VW/RW
X9116
Block Diagram
VCC (Supply Voltage)
RH/VH
Up/Down
(U/D)
Increment
(INC)
Control
and
Memory
Device Select
(CS)
RW/VW
RL/VL
VSS (Ground)
RW-RL Resistance
General
15
RH
14
13
*
3
2
1
RL
1
0
10kΩ
9.34kΩ
8.68kΩ
* kΩ
2.08kΩ
1.42kΩ
760Ω
100Ω
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9116
Ordering Information
PART NUMBER
(BRAND)
PART MARKING
VCC LIMITS
(V)
RTOTAL
(kΩ)
TEMP. RANGE
(°C)
5V ±10%
10
0 to +70
8 Ld MSOP Tape and Reel M8.118
8 Ld MSOP (Pb-free)
Tape and Reel
M8.118
PKG.
DWG. #
PACKAGE
X9116WM8T1
AAZ
X9116WM8ZT1 (Note)
AKY
0 to +70
X9116WM8I*
AFL
-40 to +85
8 Ld MSOP
M8.118
X9116WM8IZ* (Note)
DCG
-40 to +85
8 Ld MSOP (Pb-free)
M8.118
X9116WS8*
X9116W
0 to +70
8 Ld SOIC
M8.15
X9116WS8Z* (Note)
X9116W Z
0 to +70
8 Ld SOIC (Pb-free)
M8.15
X9116WS8I*
X9116W I
-40 to +85
8 Ld SOIC
M8.15
X9116WS8IZ* (Note)
X9116W ZI
-40 to +85
8 Ld SOIC (Pb-free)
M8.15
X9116WM8-2.7**
AFK
0 to +70
8 Ld MSOP
M8.118
X9116WM8Z-2.7* (Note)
AOJ
0 to +70
8 Ld MSOP (Pb-free)
M8.118
X9116WM8I-2.7*
ABA
-40 to +85
8 Ld MSOP
M8.118
X9116WM8IZ-2.7* (Note)
AKS
-40 to +85
8 Ld MSOP (Pb-free)
M8.118
X9116WS8-2.7*
X9116W F
0 to +70
8 Ld SOIC
M8.15
X9116WS8Z-2.7* (Note)
X9116W ZF
0 to +70
8 Ld SOIC (Pb-free)
M8.15
X9116WS8I-2.7*
X9116W G
-40 to +85
8 Ld SOIC
M8.15
X9116WS8IZ-2.7* (Note)
X9116W ZG
-40 to +85
8 Ld SOIC (Pb-free)
M8.15
-2.7-5.5
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and
100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
*Add "T1" suffix for tape and reel.
**Add “T2” suffix for tape and reel.
Pin Descriptions
Chip Select (CS)
VH /RH and VL /RL
The high (VH/RH) and low (VL/RL) terminals of the X9116
are equivalent to the fixed terminals of a mechanical
potentiometer. The minimum voltage is VSS and the
maximum is VCC.
VW/RW
Rw/Rw is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the control inputs.
The wiper terminal series resistance is typically 200Ω to
400Ω depending upon VCC.
The device is selected when the CS input is LOW. The
current counter value is stored in nonvolatile memory when
CS is returned HIGH while the INC input is also HIGH. After
the store operation is complete the X9116 will be placed in
the low power standby mode until the device is selected
once again.
Pin Descriptions
SYMBOL
VH/RH
High Terminal
VW/RW
Wiper Terminal
VL/RL
Up/Down (U/D)
The U/D input controls the direction of the wiper movement
and whether the counter is incremented (up) or decremented
(down).
Increment (INC)
The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the
counter in the direction indicated by the logic level on the
U/D input.
2
DESCRIPTION
Low Terminal
VSS
Ground
VCC
Supply Voltage
U/D
Up/Down Control Input
INC
Increment Control Input
CS
Chip Select Input
FN8160.2
September 26, 2006
X9116
Principles of Operation
There are three sections of the X9116: the input control,
counter and decode section; the nonvolatile memory; and
the resistor array. The input control section operates just like
an up/down counter. The output of this counter is decoded to
turn on a single electronic switch connecting a point on the
resistor array to the wiper output. Under the proper
conditions the contents of the counter can be stored in
nonvolatile memory and retained for future use. The resistor
array is comprised of 15 individual resistors connected in
series. At either end of the array and between each resistor
is an electronic switch that transfers the potential at that
point to the wiper pin.
The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions. If
the wiper is moved several positions, multiple taps are
connected to the wiper for tIW (INC to VW change). The
RTOTAL value for the device can temporarily be reduced by
a significant amount if the wiper is moved several positions.
When the device is powered-down, the last wiper position
stored will be maintained in the nonvolatile memory. When
power is restored, the contents of the memory are recalled
and the wiper is set to the value last stored.
Instructions and Programming
The INC, U/D and CS inputs control the movement of the
wiper along the resistor array. With CS set LOW, the device
is selected and enabled to respond to the U/D and INC
inputs. HIGH to LOW transitions on INC will increment or
decrement (depending on the state of the U/D input) a four
bit counter. The output of this counter is decoded to select
one of 16 wiper positions along the resistive array.
This procedure allows the system to always power-up to a
preset value stored in nonvolatile memory; then during
system operation, minor adjustments could be made. The
adjustments might be based on user preference, system
parameter changes due to temperature drift, etc.
The state of U/D may be changed while CS remains LOW.
This allows the host system to enable the device and then
move the wiper up and down until the proper trim is attained.
Mode Selection
CS
INC
U/D
MODE
L
H
Wiper Up
L
L
Wiper Down
H
X
Store Wiper Position
X
X
Standby Current
L
X
No Store, Return to Standby
H
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
The value of the counter is stored in nonvolatile memory
whenever CS transitions HIGH while the INC input is also
HIGH.
The system may select the X9116, move the wiper, and
deselect the device without having to store the latest wiper
position in nonvolatile memory. After the wiper movement is
performed as described above and once the new position is
reached, the system must keep INC LOW while taking CS
HIGH. The new wiper position will be maintained until
changed by the system or until a power-up/down cycle
recalls the previously stored data.
3
FN8160.2
September 26, 2006
X9116
Absolute Maximum Ratings
Recommended Operating Conditions
Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on CS, INC, U/D, VH/RH, VL/RL
and VCC with respect to VSS . . . . . . . . . . . . . . . . . . . . . -1V to +7V
ΔV = |VH/RH-VL/RL| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . +300°C
IW (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±10.0mA
Temperature Range
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (VCC) Limits
X9116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ± 10%
X9116-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Potentiometer Specifications Over recommended operating conditions unless otherwise stated
SYMBOL
RTOTAL
PARAMETER
TEST CONDITIONS/NOTES
End to end resistance variation
MIN
TYP
MAX
UNIT
-20
+20
%
VVH
VH/RH terminal voltage
VSS = 0V
VSS
VCC
V
VVL
VL/RL terminal voltage
VSS = 0V
VSS
VCC
V
Power rating
RTOTAL = 10kΩ
10
mW
RW
Wiper resistance
IW = 1mA, VCC = 5V
200
400
Ω
RW
Wiper resistance
IW = 1mA, VCC = 2.7V
400
1000
Ω
IW
Wiper current
+5.0
mA
-5.0
Noise
Ref: 1kHz
Resolution
Absolute linearity (Note 1)
Vw(n)(actual) - Vw(n)(expected)
Relative linearity (Note 2)
Vw(n+1) - [Vw(n) + MI]
-120
dBV√Hz
6
%
-1
+1
MI (Note 3)
-0.2
+0.2
MI (Note 3)
RTOTAL temperature coefficient
±300
Ratiometric temperature coefficient
CH/CL/CW
Potentiometer capacitances
ppm/°C
±20
See Circuit #3
10/10/25
ppm/°C
pF
NOTES:
1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (Vw(n)(actual) - Vw(n)(expected)) = ±1 Ml Maximum.
2. Relative linearity is a measure of the error in step size between taps = VW(n+1 ) -[Vw(n) + Ml] = ±0.2 Ml.
3. 1 Ml = Minimum Increment = RTOT/15.
4
FN8160.2
September 26, 2006
X9116
DC Electrical Specifications
SYMBOL
Over recommended operating conditions unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN TYP (Note 4)
MAX
UNIT
ICC1
VCC active current (Increment)
CS = VIL, U/D = VIL or VIH and
INC = 0.4V/2.4V @ max tCYC
150
µA
ICC2
VCC active current (Store) (EEPROM Store)
CS = VIH, U/D = VIL or VIH and
INC = VIH @ max tWR
400
µA
ISB
Standby supply current
CS = VCC – 0.3V, U/D and INC = VSS or
VCC – 0.3V
1
µA
ILI
CS, INC, U/D input leakage current
VIN = VSS to VCC
±10
µA
VIH
CS, INC, U/D input HIGH voltage
2V
VCC + 0.5
V
VIL
CS, INC, U/D input LOW voltage
-0.5
0.8
V
10
pF
CIN (Note 5) CS, INC, U/D input capacitance
VCC = 5V, VIN = VSS, TA = 25°C,
f = 1MHz
4. Typical values are for TA = +25°C and nominal supply voltage.
5. This parameter is periodically sampled and not 100% tested.
Endurance And Data Retention
PARAMETER
MIN
UNIT
Minimum endurance
100,000
Data changes per bit
Data retention
100
Years
Test Circuit #1
Test Circuit #2
Circuit #3 SPICE Macro Model
VH/RH
VH/RH
RTOTAL
RH
VS
Test Point
VW/RW
VWVW
/RW
V L /RL
VL/RL
CH
Test Point
Force
Current
CW
CL
RL
10pF
25pF
10pF
RW
A.C. Conditions of Test
Input pulse levels
0V to 3V
Input rise and fall times
10ns
Input reference levels
1.5V
5
FN8160.2
September 26, 2006
X9116
DC Electrical Specifications
Over recommended operating conditions unless otherwise specified
SYMBOL
PARAMETER
MIN
TYP (NOTE 6)
MAX
UNIT
tCl
CS to INC setup
100
ns
tlD
INC HIGH to U/D change
100
ns
tDI
U/D to INC setup
2.9
µs
tlL
INC LOW period
1
µs
tlH
INC HIGH period
1
µs
tlC
INC inactive to CS inactive
1
µs
tCPH
CS deselect time (STORE)
10
ms
INC to Vw change
tIW
tCYC
1
INC cycle time
tR, tF (Note 7)
5
4
µs
INC input rise and fall time
tPU (Note 7)
Power up to wiper stable
tR VCC (Note 7)
VCC Power-up rate
tWR
µs
15
Store cycle
5
500
µs
5
µs
50
mV/µs
10
ms
Power Up and Down Requirements
There are no restrictions on the power-up or power-down conditions of VCC and the voltages applied to the potentiometer pins
provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL, VW. The VCC ramp rate spec is
always in effect.
A.C. Timing
CS
tCYC
tCI
tIL
(store)
tIH
tCPH
tIC
90%
90%
10%
INC
tID
tDI
tF
tR
U/D
tIW
MI
VW
(NOTE 8)
NOTES:
6. Typical values are for TA = +25°C and nominal supply voltage.
7. This parameter is not 100% tested.
8. MI in the A.C. timing diagram refers to the minimum incremental change in the VW output due to a change in the wiper position.
6
FN8160.2
September 26, 2006
X9116
Basic Configurations of Electronic Potentiometers
VR
VR
VH
VW/RW
VL
I
THREE-TERMINAL POTENTIOMETER;
VARIABLE VOLTAGE DIVIDER
TWO-TERMINAL VARIABLE RESISTOR;
VARIABLE CURRENT
Basic Circuits
BUFFERED REFERENCE VOLTAGE
R1
+V
+V
NONINVERTING AMPLIFIER
CASCADING TECHNIQUES
+5V
+V
VS
+5V
VREF
VW
VOUT
–
-5V
X
VW/RW
R2
+V
–5V
R1
VW
VOUT = VW/RW
(a)
VOLTAGE REGULATOR
VIN
VO
–
OP-07
+
LM308A
+
VO = (1+R2/R1)VS
COMPARATOR WITH HYSTERESIS
VO (REG)
317
(b)
VS
LT311A
R1
–
+
VO
Iadj
}
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
}
R2
R1
R2
VUL = {R1/(R1+R2)} VO(max)
VLL = {R1/(R1+R2)} VO(min)
(FOR ADDITIONAL CIRCUITS, SEE AN115)
7
FN8160.2
September 26, 2006
X9116
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010) M
H
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
B S
0.050 BSC
-
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
α
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
1.27 BSC
H
N
NOTES:
MILLIMETERS
8
0°
8
8°
0°
7
8°
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
8
FN8160.2
September 26, 2006
X9116
Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1
INCHES
E
-B-
INDEX
AREA
1 2
0.20 (0.008)
A B C
TOP VIEW
4X θ
0.25
(0.010)
R1
R
GAUGE
PLANE
A
SEATING
PLANE -C-
A2
A1
b
-He
D
0.10 (0.004)
4X θ
L1
SEATING
PLANE
C
0.20 (0.008)
C
a
CL
E1
C D
MAX
MIN
MAX
NOTES
0.037
0.043
0.94
1.10
-
A1
0.002
0.006
0.05
0.15
-
A2
0.030
0.037
0.75
0.95
-
b
0.010
0.014
0.25
0.36
9
c
0.004
0.008
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.116
0.120
2.95
3.05
4
0.026 BSC
0.65 BSC
-
E
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
0.037 REF
N
C
0.20 (0.008)
MIN
A
L1
-A-
SIDE VIEW
SYMBOL
e
L
MILLIMETERS
0.95 REF
8
R
0.003
R1
0
α
-
8
-
0.07
0.003
-
5o
15o
0o
6o
7
-
-
0.07
-
-
5o
15o
-
0o
6o
-B-
Rev. 2 01/03
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A -H- .
and - B - to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
FN8160.2
September 26, 2006