X9271 Datasheet

X9271
Single Supply/Low Power/256-Tap/SPI Bus
Data Sheet
Single, Digitally Controlled (XDCP™)
Potentiometer
The X9271 integrates a single, digitally controlled
potentiometer (XDCP™) on a monolithic CMOS integrated
circuit.
The digitally controlled potentiometer is implemented by
using 255 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the SPI bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and four nonvolatile data registers that can
be directly written to and read by the user. The contents of
the WCR control the position of the wiper on the resistor
array though the switches. Power-up recalls the contents of
the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
July 18, 2014
FN8174.4
Features
• 256 Resistor Taps
• SPI Serial Interface for Write, Read, and Transfer
Operations of Potentiometer
• Wiper Resistance, 100Ω typical at VCC = 5V
• 16 Nonvolatile Data Registers
• Nonvolatile Storage of Multiple Wiper Positions
• Power-on Recall; Loads Saved Wiper Position on
Power-up
• Standby Current <3µA Max
• VCC = 2.7V to 5.5V Operation
• 50kΩ End-to-End Resistance
• 100-yr Data Retention
• Endurance: 100,000 Data Changes per Bit per Register
• 14-Lead TSSOP
• Low-power CMOS
• Pb-Free Plus Anneal Available (RoHS Compliant)
Functional Diagram
VCC
SPI
BUS
INTERFACE
ADDRESS
DATA
STATUS
RH
WRITE
READ
TRANSFER
INC/DEC
WIPER COUNTER
REGISTER (WCR)
BUS
INTERFACE
AND CONTROL
CONTROL
VSS
1
50kΩ
256 TAPS
POWER-ON RECALL
POT
DATA REGISTERS
16 Bytes
RW
RL
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2005, 2011, 2014. All Rights Reserved
Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
X9271
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
VCC LIMITS
(V)
POTENTIOMETER TEMP. RANGE
ORGANIZATION (kΩ)
(°C)
X9271UV14IZ (Note 1)
X9271 UVZI
5 ±10%
50
X9271UV14Z (Note 1)
X9271 UVZ
5 ±10%
X9271UV14IZ-2.7
X9271 UVZG
2.7 to 5.5
PACKAGE
Pb-Free
PKG.
DWG. #
-40 to +85
14 Ld TSSOP (4.4mm)
M14.173
50
0 to +70
14 Ld TSSOP (4.4mm)
M14.173
50
-40 to +85
14 Ld TSSOP (4.4mm)
M14.173
X9271UV14IZ-2.7T1
X9271 UVZG
2.7 to 5.5
50
-40 to +85
14 Ld TSSOP (4.4mm)
M14.173
X9271UV14Z-2.7
X9271 UVZF
2.7 to 5.5
50
0 to +70
14 Ld TSSOP (4.4mm)
M14.173
X9271UV14Z-2.7T1
X9271 UVZF
2.7 to 5.5
50
0 to +70
14 Ld TSSOP (4.4mm)
M14.173
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for X9271. For more information on MSL please see Tech Brief TB363.
Pin Configuration
X9271
14 LD TSSOP
TOP VIEW
S0
1
14
VCC
A0
2
13
RL
NC
3
12
RH
CS
4
11
RW
SCK
5
10
HOLD
SI
6
9
A1
VSS
7
8
WP
Pin Descriptions
PIN NUMBER
PIN NAME
FUNCTION
1
SO
Serial Data Output
2
A0
Device Address
3
NC
No Connect
4
CS
Chip Select
5
SCK
6
SI
Serial Data Input
7
VSS
System Ground
8
WP
Hardware Write Protect
Device Address
Serial Clock
9
A1
10
HOLD
11
RW
Wiper Terminal of Potentiometer
12
RH
High Terminal of Potentiometer
13
RL
Low Terminal of Potentiometer
14
VCC
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Device Select. Pause the serial bus.
System Supply Voltage
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X9271
Detailed Functional Diagram
VCC
R0
R1
R2
R3
HOLD
CS
SCK
Interface
and
Control
Circuitry
SO
SI
A0
A1
50kΩ
256 Taps
Power-on Recall
Bank 0
Wiper
Counter
Register
(WCR)
RH
RL
RW
D ATA
WP
Control
Bank 1
Bank 2
Bank 3
R0
R1
R0
R1
R0
R1
R2
R3
R2
R3
R2
R3
12 Additional Nonvolatile Registers
3 Banks of 4 Registers x 8 Bits
VSS
Circuit-Level Applications
System-Level Applications
• Vary the gain of a voltage amplifier.
• Adjust the contrast in LCD displays.
• Provide programmable DC reference voltages for
comparators and detectors.
• Control the power level of LED transmitters in
communication systems.
• Control the volume in audio circuits.
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems.
• Trim out the offset voltage error in a voltage amplifier
circuit.
• Set the output voltage of a voltage regulator.
• Trim the resistance in Wheatstone bridge circuits.
• Control the gain, characteristic frequency, and
Q-factor in filter circuits.
• Set the scale factor and zero point in sensor signal
conditioning circuits.
• Vary the frequency and duty cycle of timer ICs.
• Vary the DC biasing of a pin diode attenuator in RF
circuits.
• Control the gain in audio and home entertainment
systems.
• Provide the variable DC bias for tuners in RF
wireless systems.
• Set the operating points in temperature control
systems.
• Control the operating point for sensors in industrial
systems.
• Trim offset and gain errors in artificial intelligence
systems.
• Provide a control variable (I, V, or R) in feedback
circuits.
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X9271
Pin Descriptions
Supply Pins
Bus Interface Pins
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (VSS)
SERIAL OUTPUT (SO)
The Serial Output (SO) is the serial data output pin. During a
read cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
The System Supply Voltage (VCC) pin is the system supply
voltage. The Supply Ground (VSS) pin is the system ground.
Other Pins
SERIAL INPUT (SI)
HARDWARE WRITE PROTECT INPUT (WP)
The Serial Input (SI) is the serial data input pin. All
operational codes, byte addresses, and data to be written to
the potentiometers and potentiometer registers are input on
this pin. Data is latched by the rising edge of the serial clock.
The Hardware Write Protect Input (WP) pin, when LOW,
prevents nonvolatile writes to the data registers.
NO CONNECT
SERIAL CLOCK (SCK)
No Connect pins should be left floating. These pins are used
for Intersil manufacturing and testing purposes.
The Serial Clock (SCK) input is used to clock data into and
out of the X9271.
Principles of Operation
HOLD (HOLD)
Device Description
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence is under
way, HOLD may be used to pause the serial communication with
the controller without resetting the serial sequence. To pause,
HOLD must be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while SCK is LOW.
If the pause feature is not used, HOLD should be held HIGH at all
times. CMOS level input.
SERIAL INTERFACE
DEVICE ADDRESS (A1 - A0)
The Device Address (A1 - A0) inputs are used to set the 8-bit
slave address. A match in the slave address serial data
stream must be made with the address input in order to
initiate communication with the X9271.
CHIP SELECT (CS)
When Chip Select (CS) is HIGH, the X9271 is deselected,
the SO pin is at high impedance and (unless an internal write
cycle is under way) the device is in standby state. CS LOW
enables the X9271, placing it in the active power mode. It
should be noted that after a power-up, a HIGH to LOW
transition on CS is required prior to the start of any
operation.
Potentiometer Pins
RH, RL
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer.
RW
The wiper pin (RW) is equivalent to the wiper terminal of a
mechanical potentiometer.
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The X9271 supports the SPI interface hardware
conventions. The device is accessed via the SI input with
data clocked in on the rising SCK. CS must be LOW and the
HOLD and WP pins must be HIGH during the entire
operation.
The SO and SI pins can be connected together, since they
have three-state outputs. This can help to reduce system pin
count.
ARRAY DESCRIPTION
The X9271 is composed of a resistor array (Figure 1). The
array contains the equivalent of 255 discrete resistive
segments that are connected in series. The physical ends of
each array are equivalent to the fixed terminals of a
mechanical potentiometer (RH and RL inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (RW)
output. Within each individual array, only one switch may be
turned on at a time.
These switches are controlled by a Wiper Counter Register
(WCR). The eight bits of the WCR (WCR[7:0]) are decoded
to select, and enable, one of 256 switches (Table 1).
POWER-UP AND POWER-DOWN RECOMMENDATIONS
There are no restrictions on the power-up or power-down
conditions of VCC and the voltages applied to the
potentiometer pins, provided that VCC is always more
positive than or equal to VH, VL, and VW; i.e., VCC  VH, VL,
VW. The VCC ramp rate specification is always in effect.
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SERIAL DATA PATH
RH
SERIAL
BUS
INPUT
FROM INTERFACE
CIRCUITRY
REGISTER 0
(DR0)
8
PARALLEL
BUS
INPUT
8
BANK_0 Only
REGISTER 2
(DR2)
C
O
U
N
T
E
R
REGISTER 1
(DR1)
REGISTER 3
(DR3)
D
E
C
O
D
E
WIPER
COUNTER
REGISTER
(WCR)
INC/DEC
LOGIC
IF WCR = 00[H] THEN RW = RL
IF WCR = FF[H] THEN RW = RH
UP/DN
MODIFIED SCK
UP/DN
RL
CLK
RW
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
Device Description
Wiper Counter Register (WCR)
The X9271 contains a Wiper Counter Register (WCR) for the
DCP potentiometer. The WCR can be envisioned as an 8-bit
parallel and serial load counter, with its outputs decoded to
select one of 256 switches along its resistor array (Table 1).
The contents of the WCR can be altered in four ways:
1. It can be written directly by the host via the Write Wiper
Counter Register instruction (serial load).
2. It can be written indirectly by transferring the contents of
one of four associated data registers via the XFR Data
Register instruction (parallel load).
3. It can be modified one step at a time by the Increment/
Decrement instruction.
4. It is loaded with the contents of its Data Register zero
(DR0) upon power-up.
The WCR is a volatile register; that is, its contents are lost
when the X9271 is powered down. Although the register is
automatically loaded with the value in DR0 upon power-up,
this may be different from the value present at power-down.
Power-up guidelines are recommended to ensure proper
loading of the R0 value into the WCR. The DR0 value of
Bank 0 is the default value.
Data Registers (DR3–DR0)
The potentiometer has four 8-bit nonvolatile Data Registers.
These can be read or written directly by the host (Table 2).
Data can also be transferred between any of the four Data
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Registers and the associated WCR. All operations changing
data in one of the Data Registers are nonvolatile operations
and take a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system parameters or
user preference data.
Bits [7:0] are used to store one of the 256 wiper positions or
data (0 ~255).
Status Register (SR)
The 1-bit Status Register is used to store the system status
(Table 3).
WIP: Write In Progress status bit; read only.
• WIP = 1 indicates that a high-voltage write cycle is in
progress.
• WIP = 0 indicates that no high-voltage write cycle is in
progress
.
TABLE 1. WIPER COUNTER REGISTER, WCR (8-bit),
WCR[7:0]: Used to store current wiper position
(Volatile, V)
WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0
V
(MSB)
V
V
V
V
V
V
V
(LSB)
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X9271
REGISTER BANK SELECTION (R1, R0, P1, P0)
.
TABLE 2. DATA REGISTER, DR (8-BIT), DR[7:0]: Used to
store wiper positions or data (Nonvolatile, NV)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NV
NV
NV
NV
NV
NV
NV
NV
MSB
LSB
TABLE 3. STATUS REGISTER, SR (WIP is 1-bit)
WIP
There are 16 registers organized into four banks. Bank 0 is
the default bank of registers. Only Bank 0 registers can be
used for the data register to Wiper Counter Register
operations.
Banks 1, 2, and 3 are additional banks of registers (12 total)
that can be used for SPI write and read operations. The data
registers in Banks 1, 2, and 3 cannot be used for direct
read/write operations to the Wiper Counter Register
(Tables 5 and 6).
(LSB)
TABLE 4. IDENTIFICATION BYTE FORMAT
Device Description
Instructions
DEVICE TYPE IDENTIFIER
IDENTIFICATION BYTE (ID AND A)
The first byte sent to the X9271 from the host, following a CS
going HIGH to LOW, is called the Identification byte. The
most significant four bits of the slave address are a device
type identifier. The ID[3:0] bit is the device ID for the X9271;
this is fixed as 0101[B] (Table 4).
The A1 - A0 bits in the ID byte are the internal slave address.
The physical device address is defined by the state of the A1
- A0 input pins. The slave address is externally specified by
the user. The X9271 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9271 to successfully
continue the command sequence. Only the device for which
slave address matches the incoming device address sent by
the master executes the instruction. The A1 - A0 inputs can
be actively driven by CMOS input signals or tied to VCC or
VSS.
INSTRUCTION BYTE (I[3:0])
ID3
ID2
ID1
ID0
0
1
0
1
SET TO 0 FOR
PROPER
OPERATION
0
0
INTERNAL
SLAVE
ADDRESS
A1
A0
(MSB)
(LSB)
TABLE 5. REGISTER SELECTION (DR0 TO DR3)
RB
RA
REGISTER
SELECTION
0
0
0
Data Register Read and Write; Wiper
Counter Register Operations
0
1
1
Data Register Read and Write; Wiper
Counter Register Operations
1
0
2
Data Register Read and Write; Wiper
Counter Register Operations
1
1
3
Data Register Read and Write; Wiper
Counter Register Operations
OPERATIONS
TABLE 6. REGISTER BANK SELECTION (BANK 0 TO BANK 3)
The next byte sent to the X9271 contains the instruction and
register pointer information. The three most significant bits
are used to provide the instruction operation code (I[3:0]).
The RB and RA bits point to one of the four Data Registers.
P0 is the POT selection; since the X9271 is single POT,
P0 = 0. The format is shown in Table 7.
P1
P0
BANK
SELECTION
0
0
0
Data Register Read and Write; Wiper
Counter Register Operations
0
1
1
Data Register Read and Write Only
1
0
2
Data Register Read and Write Only
1
1
3
Data Register Read and Write Only
OPERATIONS
TABLE 7. INSTRUCTION BYTE FORMAT
REGISTER BANK SELECTION FOR
SP1 REGISTER WRITE AND READ OPERATIONS)
I3
I2
I1
POTENTIOMETER SELECTION
(WCR SELECTION) (Note 4)
REGISTER
SELECTION
INSTRUCTION OPCODE
P0
(MSB)
RB
RA
P1
P0
(LSB)
NOTE:
4. Set to P0 = 0 for potentiometer operations.
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X9271
associated register. The Read Status Register instruction is
the only unique format (Figure 3).
Device Description
Instructions
Five of the eight instructions are three bytes in length. These
instructions are:
• Read Wiper Counter Register: Read the current wiper
position of the potentiometer.
• Write Wiper Counter Register: Change current wiper
position of the potentiometer.
Two instructions require a 2-byte sequence to complete
(Figure 4). These instructions transfer data between the host
and the X9271; either between the host and one of the data
registers, or directly between the host and the Wiper
Counter Register. These instructions are:
• XFR Data Register to Wiper Counter Register:
Transfers the contents of one specified Data Register to
the associated Wiper Counter Register.
• Read Data Register: Read the contents of the selected
Data Register.
• XFR Wiper Counter Register to Data Register:
Transfers the contents of the specified Wiper Counter
Register to the associated Data Register.
• Write Data Register: Write a new value to the selected
Data Register.
• Read Status: This command returns the contents of the
WIP bit, which indicates if the internal write cycle is in
progress.
See Table 8 for details of the instruction set.
The basic sequence of the 3-byte instruction is shown in
Figure 2. These 3-byte instructions exchange data between
the WCR and one of the Data Registers. A transfer from a
Data Register to a WCR is essentially a write to a static
RAM, with the static RAM controlling the wiper position. The
response of the wiper to this action is delayed by tWRL. A
transfer from the WCR (current wiper position) to a Data
Register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers, or it may occur globally, where the
transfer occurs between all potentiometers and one
The final command is Increment/Decrement
(Figures 5 and 6). It is different from the other commands,
because its length is indeterminate. Once the command is
issued, the master can clock the selected wiper up and/or
down in one resistor segment step, thereby providing a finetuning capability to the host. For each SCK clock pulse
(tHIGH) while SI is HIGH, the selected wiper moves one
resistor segment towards the RH terminal. Similarly, for each
SCK clock pulse while SI is LOW, the selected wiper moves
one resistor segment towards the RL terminal.
Write-in-Process (WIP) Bit
The contents of the Data Registers are saved to nonvolatile
memory when the CS pin goes from LOW to HIGH after a
complete write sequence is received by the device. The
progress of this internal write operation can be monitored by
the Write-in-Process bit (WIP). The WIP bit is read with a
Read Status command.
CS
SCL
SI
0
1
0
1
ID3 ID2 ID1 ID0
0
0
0
0
A1 A0
Internal
Address
Device ID
I3
I2
I1
I0
Instruction
Opcode
RB RA P1 P0
Register
Address
D7 D6 D5 D4 D3 D2 D1 D0
Pot/BankWCR[7:0] valid only when P1 = P0 = 0;
Address
or
Data Register Bit [7:0] for all values of P1 and P0
FIGURE 2. THREE-BYTE INSTRUCTION SEQUENCE (WRITE)
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July 18, 2014
X9271
CS
SCL
SI
0
1
0
1
ID3 ID2 ID1 ID0
0
0
0
0
X
A1 A0
I3
Internal
Address
Device ID
I2
I1 I0
Instruction
Opcode
X
X
RB RA P1 P0
X
X
X
X
X
Don’t Care
Pot/Bank
Address
Register
Address
S0
D7 D6 D5 D4 D3 D2 D1 D0
WCR[7:0] valid only when P1 = P0 = 0;
or
Data Register Bit [7:0] for all values of P1 and P0
FIGURE 3. THREE-BYTE INSTRUCTION SEQUENCE (READ)
CS
SCK
SI
1
0
ID3 ID2 ID1 ID0
0
0
1
0
0
0
0
A1
A0
I3
Internal
Address
Device ID
I2
I1 I0
0
RB RA P1 P0
Instruction
Opcode
Register
Address
Pot/Bank
Address
These commands only valid when P1 = P0 = 0
FIGURE 4. TWO-BYTE INSTRUCTION SEQUENCE
CS
SCL
SI
0
1
0
1
ID3 ID2 ID1 ID0
0
0
0
0
0
A1 A0
Internal
Address
Device ID
I3
I2
I1
Instruction
Opcode
I0
0
RA RB P1 P0
Register
Address
Pot/Bank
Address
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
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X9271
tWRID
SCK
SI
VOLTAGE OUT
VW
INC/DEC CMD ISSUED
FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS
TABLE 8. INSTRUCTION SET
INSTRUCTION SET
(1/0 = DATA IS ONE OR ZERO)
I3
I2
I1
I0
RB
RA
P1
P0
Read Wiper Counter Register
1
0
0
1
0
0
0
1/0
Read contents of Wiper Counter Register.
Write Wiper Counter Register
1
0
1
0
0
0
0
1/0
Write new value to Wiper Counter Register.
Read Data Register
1
0
1
1
1/0
1/0
1/0
1/0
Read contents of Data Register pointed to by P1 - P0
and RB - RA.
Write Data Register
1
1
0
0
1/0
1/0
1/0
1/0
Write new value to Data Register pointed to by P1 - P0
and RB - RA.
XFR Data Register to
Wiper Counter Register
1
1
0
1
1/0
1/0
0
0
Transfer contents of Data Register pointed to by
RB - RA (Bank 0 only) to Wiper Counter Register.
XFR Wiper Counter
Register to Data Register
1
1
1
0
1/0
1/0
0
0
Transfer contents of Wiper Counter Register to Register
pointed to by RB-RA (Bank 0 only).
Increment/Decrement
Wiper Counter Register
0
0
1
0
0
0
0
0
Enable increment/decrement of the Wiper Counter
Register.
Read Status (WIP Bit)
0
1
0
1
0
0
0
1
Read status of internal write cycle by checking WIP bit.
INSTRUCTION
OPERATION
Instruction Format
Read Wiper Counter Register (WCR)
CS
Falling
Edge
Device Type
Identifier
0
1
0
1
Device
Addresses
0
0
A1
A0
Instruction
Opcode
1
0
0
DR/Bank
Addresses
1
0
0
0
Wiper Position
(Sent by X9271 on SO)
0
W W W W W W W W
C C C C C C C C
R R R R R R R R
7 6 5 4 3 2 1 0
CS
Rising
Edge
Write Wiper Counter Register (WCR)
CS
Falling
Edge
Device Type
Identifier
0
1
0
1
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Device
Addresses
0
0
9
A1
A0
Instruction
Opcode
1
0
1
DR/Bank
Addresses
0
0
0
0
Data Byte
(Sent by Host on SI)
0
W W W W W W W W
C C C C C C C C
R R R R R R R R
7 6 5 4 3 2 1 0
CS
Rising
Edge
FN8174.4
July 18, 2014
X9271
Read Data Register (DR)
CS
Falling
Edge
Device Type
Identifier
0
1
0
Device
Addresses
1
0
0
A1
Instruction
Opcode
A0
1
0
1
DR/Bank
Addresses
1
RB RA
Data Byte
(Sent by X9271 on SO)
P1
P0
D7 D 6 D5
D4
D3
D2
D1
D0
CS
Rising
Edge
CS
Falling
Edge
Device Type
Identifier
0
1
0
Device
Addresses
1
0
0
A1
Instruction
Opcode
A0
1
1
0
DR/Bank
Addresses
0
RB
RA
P1
Data Byte
(Sent by Host on SI)
P0
D7 D 6 D5
D4
D3
D2
D1
D0
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
Write Data Register (DR)
Transfer Wiper Counter Register (WCR) to Data Register (DR)
CS
Falling
Edge
Device Type
Identifier
0
1
0
1
Device
Addresses
0
0
A1
Instruction
Opcode
A0
1
1
1
DR/Bank
Addresses
0
RB
RA
0
CS
Rising
Edge
0
HIGH-VOLTAGE
WRITE CYCLE
Transfer Data Register (DR) to Wiper Counter Register (WCR) (Notes 5, 6)
CS
Falling
Edge
Device Type
Identifier
0
1
0
1
Device
Addresses
0
0
A1
Instruction
Opcode
A0
1
1
0
DR/Bank
Addresses
1
RB
RA
0
CS
Rising
Edge
0
Increment/Decrement Wiper Counter Register (WCR) (Notes 5, 6, 7, 8, 9)
CS
Falling
Edge
Device Type
Identifier
0
1
0
1
Device
Addresses
0
0
A1
Instruction
Opcode
A0
0
0
1
DR/Bank
Addresses
0
X
X
0
Increment/Decrement
(Sent by Master on SDA)
0
I/D
I/D
.
.
.
.
I/D
I/D
CS
Rising
Edge
Read Status Register (SR) (Note 5)
CS
Falling
Edge
Device Type
Identifier
0
1
0
1
Device
Addresses
0
0
A1
Instruction
Opcode
A0
0
1
0
DR/Bank
Addresses
1
0
0
0
Data Byte
(Sent by X9271 on SO)
1
0
0
0
0
0
0
0
WIP
CS
Rising
Edge
NOTES:
5. “A1 ~ A0”: stands for the device addresses sent by the master.
6. WCRx refers to wiper position data in the Wiper Counter Register.
7. “I”: stands for the increment operation. SI held HIGH during active SCK phase (high).
8. “D”: stands for the decrement operation. SI held LOW during active SCK phase (high).
9. “X:”: Don’t Care.
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X9271
Absolute Maximum Ratings
Thermal Information
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Voltage on SCK, any Address Input,
with Respect to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
V = |(VH - VL)| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
IW (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Supply Voltage (VCC) Limits:
X9271 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ± 10%
X9271-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Temperature Range (Commercial). . . . . . . . . . . . . . . . 0°C to +70°C
Temperature Range (Industrial) . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
Analog Characteristics
Across recommended industrial operating conditions unless otherwise specified.
LIMITS
SYMBOL
RTOTAL
PARAMETER
MIN
(Note 17)
End to End Resistance
TYP
MAX
(Note 17)
50
UNITS
kΩ
TEST CONDITIONS
U version
End to End Resistance
Tolerance
±20
%
Power Rating
50
mW
IW
Wiper Current
±3
mA
RW
Wiper Resistance
300
W
IW = ± 3mA at VCC = 3V
RW
Wiper Resistance
150
W
IW = ± 3mA at VCC = 5V
VTERM
Voltage on any RH or RL Pin
VCC
V
VSS = 0V
Noise
Resolution
VSS
-120
dBVHz
0.4
%
Ref: 1V
Absolute Linearity (Note 10)
±1
MI
(Note 12)
Rw(n)(actual) - Rw(n)(expected)
(Note 14)
Relative Linearity (Note 11)
±0.2
MI
(Note 12)
Rw(n + 1) - [Rw(n) + MI] (Note 14)
Temperature Coefficient of
RTOTAL
±300
Ratiometric Temp.
Coefficient
CH/CL/CW
+25°C, each pot
Potentiometer
Capacitance
ppm/C
20
10/10/25
ppm/°C
pF
See macro model
NOTES:
10. Absolute linearity is used to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
11. Relative linearity is used to determine actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
12. MI = RTOT / 255 or (RH - RL) / 255, single pot.
13. During power-up, VCC > VH, VL, and VW.
14. n = 0, 1, 2, …,255; m = 0, 1, 2, …., 254.
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FN8174.4
July 18, 2014
X9271
D.C. Operating Characteristics
Across the recommended operating conditions unless otherwise specified.
LIMITS
SYMBOL
MIN
(Note 17)
PARAMETER
TYP
MAX
(Note 17)
UNITS
400
µA
fSCK = 2.5MHz, SO = Open, VCC = 6V
Other Inputs = VSS
5
mA
fSCK = 2.5MHz, SO = Open, VCC = 6V
Other Inputs = VSS
TEST CONDITIONS
ICC1
VCC Supply Current
(Active)
ICC2
VCC Supply Current
(Nonvolatile Write)
ISB
VCC Current (Standby)
3
µA
SCK = SI = VSS, Addr. = VSS,
CS = VCC = 6V
ILI
Input Leakage Current
10
µA
VIN = VSS to VCC
ILO
Output Leakage Current
10
µA
VOUT = VSS to VCC
VIH
Input HIGH Voltage
VCC x 0.7
VCC + 1
V
VIL
Input LOW Voltage
-1
VCC x 0.3
V
VOL
Output LOW Voltage
0.4
V
IOL = 3mA
VOH
Output HIGH Voltage
VCC - 0.8
V
IOH = -1mA, VCC  +3V
VOH
Output HIGH Voltage
VCC - 0.4
V
IOH = -0.4mA, VCC  +3V
1
Endurance and Data Retention
PARAMETER
MIN.
(Note 17)
UNITS
Minimum Endurance
100,000
Data changes per bit per register
Data Retention
100
Years
Capacitance
SYMBOL
TEST
MAX.
(Note 17)
UNITS
TEST CONDITIONS
CIN/OUT (Note 15)
Input / Output Capacitance (SI)
8
pF
VOUT = 0V
COUT (Note 15)
Output Capacitance (SO)
8
pF
VOUT = 0V
CIN (Note 15)
Input Capacitance (A0, CS, WP, HOLD, and SCK)
6
pF
VIN = 0V
Power-Up Timing
SYMBOL
PARAMETER
MIN.
(Note 17)
MAX.
(Note 17)
UNITS
0.2
50
V/ms
tr VCC (Note 15)
VCC Power-up Rate
tPUR (Note 16)
Power-up to Initiation of Read Operation
1
ms
tPUW (Note 16)
Power-up to Initiation of Write Operation
50
ms
A.C. Test Conditions
INPUT PULSE LEVELS
VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times
10ns
Input and Output Timing Level
VCC x 0.5
NOTES:
15. This parameter is not 100% tested.
16. tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These
parameters are periodically sampled and are not 100% tested.
17. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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FN8174.4
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X9271
Equivalent A.C. Load Circuit
5V
SPICE MACROMODEL
3V
1462Ω
1382
RTOTAL
RH
SO pin
RL
SO pin
2714 Ω
1217
100pF
CW
CL
100pF
CL
10pF
25pF
10pF
RW
AC Timing
SYMBOL
PARAMETER
MIN
MAX
UNITS
2.5
MHz
fSCK
SSI/SPI Clock Frequency
tCYC
SSI/SPI Clock Cycle Time
500
ns
tWH
SSI/SPI Clock High Time
200
ns
tWL
SSI/SPI Clock Low Time
200
ns
tLEAD
Lead Time
250
ns
tLAG
Lag Time
250
ns
tSU
SI, SCK, HOLD and CS Input Setup Time
50
ns
tH
SI, SCK, HOLD and CS Input Hold Time
50
ns
tRI
SI, SCK, HOLD and CS Input Rise Time
2
µs
tFI
SI, SCK, HOLD and CS Input Fall Time
2
µs
tDIS
SO Output Disable Time
250
ns
tV
SO Output Valid Time
200
ns
tHO
SO Output Hold Time
tRO
SO Output Rise Time
100
ns
tFO
SO Output Fall Time
100
ns
tHOLD
HOLD Time
400
ns
tHSU
HOLD Setup Time
100
ns
tHH
HOLD Hold Time
100
ns
tHZ
HOLD Low to Output in High Z
100
ns
tLZ
HOLD High to Output in Low Z
100
ns
TI
Noise Suppression Time Constant at SI, SCK, HOLD and CS Inputs
10
ns
tCS
CS Deselect Time
2
µs
tWPASU
WP, A0 Setup Time
0
ns
tWPAH
WP, A0 Hold Time
0
ns
0
0
ns
High-voltage Write Cycle Timing
SYMBOL
tWR
PARAMETER
High-voltage Write Cycle Time (Store Instructions)
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13
TYP
MAX
UNITS
5
10
ms
FN8174.4
July 18, 2014
X9271
XDCP Timing
SYMBOL
PARAMETER
MIN
MAX
UNITS
tWRPO
Wiper Response Time After Third (Last) Power Supply is Stable
5
10
µs
tWRL
Wiper Response Time After Instruction Issued (All Load Instructions)
5
10
µs
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be steady
Will be steady
May change from Low to High
Will change from Low to High
May change from High to Low
Will change from High to Low
Don’t Care: Changes Allowed
Changing: State Not Known
N/A
Center Line is High Impedance
Timing Diagrams
Input Timing
tCS
CS
SCK
tSU
tH
...
tWH
tWL
tRI
tFI
...
MSB
SI
tLAG
tCYC
tLEAD
LSB
High Impedance
SO
Output Timing
CS
SCK
tV
MSB
SO
SI
tHO
...
...
tDIS
LSB
ADDR
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FN8174.4
July 18, 2014
X9271
Hold Timing
CS
tHSU
tHH
SCK
...
tRO
tFO
SO
tHZ
tLZ
SI
tHOLD
HOLD
XDCP Timing (for All Load Instructions)
CS
SCK
...
...
MSB
SI
tWRL
LSB
VWx
SO
High Impedance
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
tWPASU
WP
tWPAH
A0
A1
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FN8174.4
July 18, 2014
X9271
Applications information
Basic Configurations of Electronic Potentiometers
+VR
VR
RW
I
3-terminal Potentiometer;
Variable Voltage Divider
2-terminal Variable Resistor;
Variable Current
Application Circuits
VS
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj
FIGURE 7. NONINVERTING AMPLIFIER
R1
R2
FIGURE 8. VOLTAGE REGULATOR
VS
VS
–
+
VO
100kΩ
–
VO
}
TL072
}
+
R1
R2
10kΩ
10kΩ
+12V
10kΩ
VUL = {R1/(R1+R2)} VO(max)
RLL = {R1/(R1+R2)} VO(min)
-12V
FIGURE 9. OFFSET VOLTAGE ADJUSTMENT
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FIGURE 10. COMPARATOR WITH HYSTERESIS
FN8174.4
July 18, 2014
X9271
Application Circuits (Continued)
C
VS
R2
R1
R
VO
+
R3
R4
R2
R1 = R2 = R3 = R4 = 10k
R1
GO = 1 + R2/R1
fc = 1/(2RC)
VO = G VS
-1/2  G  +1/2
FIGURE 11. ATTENUATOR
FIGURE 12. FILTER
R2
C1
R2
VS
}
VS
}
R1
VO
–
–
VS
+
+
–
–
VO
+
R1
ZIN
R3
VO = G VS
G = - R2/R1
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
FIGURE 13. INVERTING AMPLIFIER
FIGURE 14. EQUIVALENT L-R CIRCUIT
C
R2
–
+
R1
–
} RA
+
} RB
Frequency  R1, R2, C
Amplitude  RA, RB
FIGURE 15. FUNCTION GENERATOR
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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FN8174.4
July 18, 2014
X9271
Package Outline Drawing
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 3, 10/09
A
1
3
5.00 ±0.10
SEE
DETAIL "X"
8
14
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
1
0.20 C B A
7
B
0.65
0.09-0.20
TOP VIEW
END VIEW
1.00 REF
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
0.25 +0.05/-0.06
0.10 C
0.10
GAUGE
PLANE
0.25
5
0°-8°
0.05 MIN
0.15 MAX
CBA
SIDE VIEW
0.60 ±0.15
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
(5.65)
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.80mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead is 0.07mm.
(0.65 TYP)
(0.35 TYP)
TYPICAL RECOMMENDED LAND PATTERN
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18
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153, variation AB-1.
FN8174.4
July 18, 2014