ISL97656 SEPIC for 3VIN to 12VIN to 3.3VOUT at 1A Application ® Application Note January 29, 2008 Introduction AN1379.0 generates approximately 3.1V, which supplies input power to the chip. Once the external soft-start capacitor times out, the ISL97656 starts switching at 1.2MHz since the “Freq” pin is grounded and starts regulating 3.3V on the output. At this time, output turns on Q1 which turns-off Q2 and Q3, turning D2 zener diode off. At this point, the ISL97656 is powered from the output through D3, Schottky diode. The purpose of disconnecting the zener diode from the circuit by using Q1, Q2 and Q3, is to prevent excessive power loss when the input voltage is 12V. This power loss across the zener diode will translate into poor SEPIC efficiency at load currents of less than 200mA. If output efficiency is not a major concern, then remove R5, R6, R7, Q1, Q2, and Q3 and connect the top side of R1 directly to the input supply. The bill of material for this evaluation board is listed in Table 1, and the front and back side of this evaluation board is shown in Figures 2 and 3. There are several applications where one needs to generate a constant output voltage which is right in the middle of the input voltage range. This circuit can easily be implemented by using any boost regulator, as long as it can handle the input voltage range, and the output load current configured in a SEPIC (Single Ended Primary Inductively Coupled) configuration. The SEPIC circuit in Figure 1 is designed for a raid disk application to generate a constant 3.3Vout to provide power to an FPGA, white LED driver, and EEPROM from an input voltage source that ranges from 3V to 12V by using ISL97656. The ISL97656 is a selectable 640kHz, or 1.2MHz constant switching frequency, high efficiency boost regulator for 2.3VIN to 5.5VIN applications. It has an internal 120mΩ, 4A power switch which allows over 90% efficiency and has an external compensation pin which allows ceramic capacitors on the output. Figure 4 shows the ISL97656 efficiency from 12VIN, and Figure 5 from 3VIN. It can be seen that the ISL97656 SEPIC circuit is 80+% efficient from 12VIN vs. about 75% from 3VIN. Figure 6 shows the output voltage ripple of 71mV at 0.7A of load current. The output voltage ripple is about 2% and can be further reduced by adding another output capacitor in parallel. Since the input voltage range on the ISL97656 is from 2.3V to 5.5V and the system applications requires input to vary from 3V to 12V, a discrete bias supply is created by using D2 (3.1V zener) and R1 (100Ω). This bias supply is only used for start-up, and gets disconnected when the ISL97656 starts regulating 3.3V on the output. When there is no output voltage, Q1 is off, Q2 and Q3 are on, hence, D2 zener diode 3.3V/1A 3V-12VIN J1 L1A 30µH C1 1 D1 J3 B220 CON1 2 1 3 1 4.7µF/16V CON1 R7 200k J2 L1B C2 30µH BH-510-1022 1 22µF C4 330µF AVX-TPSD337M006R0045 Lx D3 8 R1 100 BAT54C R2 16.6k Lx 6 Q3 TP0610K 7 4 CON1 IN J4 C3 2.2µF 9 Freq 1 ISL97656 3 CON1 EN D2 Q1 2N7002 GND GND C5 27nF 5 4 U1 1 Q2 2N7002 2 FB SS GND BZT52C3V0T 11 R5 200k Comp 10 R4 10k C6 4.7nF R6 200k R3 10k FIGURE 1. ISL97656 SEPIC SCHEMATIC FOR 3V to 12VIN TO 3.3VOUT AT 1A 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Application Note 1379 TABLE 1. ISL97656 SEPIC BILL OF MATERIAL PART TYPE DESIGNATOR 2.2µF C3 4.7µF/16V C1 2N7002 Q1 TPK0610K Q3 2N7002 Q2 10k R3 4.7nF C6 10K R4 16.6k R2 22µF C2 27nF C5 100 R1 200k R6 200k R7 200k R5 330µF C4 B220 D1 BAT54C D3 BZT52C3V0T D2 BH Elect, 510-1022 L1A/B U1 ISL97656 2 AN1379.0 January 29, 2008 Application Note 1379 FIGURE 2. ISL97656 SEPIC TEST BOARD – FRONT SIDE FIGURE 3. ISL97656 SEPIC TEST BOARD – BACK SIDE 3 AN1379.0 January 29, 2008 Application Note 1379 100 80 EFFCIENCY (%) EFFICIENCY (%) 85 75 70 65 60 55 80 60 40 20 0 50 0 0.2 0.4 0.6 0.8 1.0 1.2 LOAD (A) FIGURE 4. ISL97656 SEPIC BOARD EFFICIENCY FROM 12VIN 0 0.2 0.4 0.6 0.8 1.0 1.2 LOAD (A) FIGURE 5. ISL97656 SEPIC BOARD EFFICIENCY FROM 3VIN FIGURE 6. ISL97656 SEPIC BOARD OUTPUT VOLTAGE RIPPLE FOR 12VIN TO 3.3VOUT AT 0.7A Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 4 AN1379.0 January 29, 2008