Electrical Specifications Subject to Change LTC6802-1 Multicell Battery Stack Monitor FEATURES DESCRIPTION n The LTC®6802-1 is a complete battery monitoring IC that includes a 12-bit ADC, a precision voltage reference, a high voltage input multiplexer and a serial interface. Each LTC6802-1 can measure up to 12 series connected battery cells with an input common mode voltage up to 60V. Using a unique level-shifting serial interface, multiple LTC6802-1 devices can be connected in series, without optocouplers or isolators, allowing for monitoring of every cell in a long string of series-connected batteries. n n n n n n n n n n n Measures up to 12 Li-Ion Cells in Series (60V Max) Stackable Architecture Enables >1000V Systems 0.25% Maximum Total Measurement Error 13ms to Measure All Cells in a System Cell Balancing: On-Chip Passive Cell Balancing Switches Provision for Off-Chip Passive Balancing Two Thermistor Inputs Plus On-board Temperature Sensor 1MHz Serial Interface with Packet Error Checking High EMI Immunity Delta Sigma Converter With Built In Noise Filter Open Wire Connection Fault Detection Low Power Modes 44-Lead SSOP Package APPLICATIONS n n n n When multiple LTC6802-1 devices are connected in series they can operate simultaneously, permitting all cell voltages in the stack to be measured within 13ms. To minimize power, the LTC6802-1 offers a measure mode to monitor each cell for overvoltage and undervoltage conditions. A standby mode is also provided. Each cell input has an associated MOSFET switch for discharging overcharged cells. Electric and Hybrid Electric Vehicles High Power Portable Equipment Backup Battery Systems High Voltage Data Acquisition Systems The related LTC6802-2 offers an individually addressable serial interface. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION Typical Application Measurement Error Over Extended Temperature LTC6802-1 SERIAL DATA TO LTC6802-1 ABOVE DIE TEMP V+ REGISTERS AND CONTROL 12-CELL BATTERY STRING 0.30 0.25 MEASUREMENT ERROR (%) NEXT 12-CELL PACK ABOVE MUX 12-BIT Δ∑ ADC 0.20 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 –0.25 V– NEXT 12-CELL PACK BELOW 10ppm VOLTAGE REFERENCE EXTERNAL TEMP SERIAL DATA TO LTC6802-1 BELOW –0.30 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 68021 TA01a 100k 100k NTC 68021p 1 LTC6802-1 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) TOP VIEW Total Supply Voltage (V+ to V–) .................................60V Input Voltage (Relative to V–) C1 ............................................................ –0.7V to 9V C12 ..........................................V+ – 0.7V to V+ + 0.7V Sn pins ............................... Cn-1 – 0.7V to Cn-1 + 9V CSBO, SCKO, SDOI ..................V+ – 1.4V to V+ + 0.7V All other pins ........................................... –0.7V to 7V Voltage Between Inputs Cn to Cn-1 ............................................... –0.7V to 9V Input Current All Pins ............................................................±10mA Operating Temperature Range.................. –40°C to 85°C Specified Temperature Range .................. –40°C to 85°C Junction Temperature ........................................... 150°C Storage Temperature Range................... –65°C to 150°C *n = 2 to 11 CSBO 1 44 CSBI SDOI 2 43 SDO SCKO 3 42 SDI V+ 4 41 SCKI C12 5 40 VMODE S12 6 39 GPIO2 C11 7 38 GPIO1 S11 8 37 WDTB C10 9 36 MMB S10 10 25 TOS C9 11 34 VREG S9 12 33 VREF C8 13 32 VTEMP2 S8 14 31 VTEMP1 C7 15 30 NC S7 16 29 V– C6 17 28 S1 S6 18 27 C1 C5 19 26 S2 S5 20 25 C2 C4 21 24 S3 S4 22 23 C3 G PACKAGE 44-LEAD PLASTIC SSOP TJMAX = 150°C, θJA = 70°C/W ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC6802IG-1#PBF LTC6802IG-1#TRPBF LTC6802IG-1 44-Lead Plastic SSOP –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 68021p 2 LTC6802-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 43.2V, V– = 0V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DC Specifications VACC VERR VCELL VCM VREF Measurement Resolution Quantization of the ADC l ADC Offset Voltage (Note 2) l –0.5 0.5 mV ADC Gain Error (Note 2) l –0.12 –0.22 0.12 0.22 % % Total Measurement Error (Note 4) VCELL = 0V VCELL = 2.3V VCELL = 2.3V VCELL = 3.6V VCELL = 3.6V VCELL = 4.2V VCELL = 4.2V VCELL = 4.6V VTEMP = 2.3V VTEMP = 3.6V VTEMP = 4.2V Cell Voltage Range 1.5 0.75 l l l ±8 Full Scale Voltage Range 5.175 Range of Inputs C4 thru C11 Range of Input C3 Range of Inputs C1, C2 l l l 3.7 1.8 0 Overvoltage (OV) Detection Level Programmed for 4.2V l 4.182 Undervoltage (UV) Detection Level Programmed for 2.3V l 2.290 Die Temperature Measurement Error Error in Measurement at 125°C l Reference Pin Voltage RLOAD = 100k to V– 3.040 3.035 l 15 10 V V V 4.200 4.218 V 2.300 2.310 V ±10 °C 3.072 3.072 3.105 3.110 V V ppm/°C 100 ppm 60 10 < V+ < 50, No Load ILOAD = 4mA Regulator Pin Short Circuit Current Limit VS Supply Voltage, V+ Relative to V– VERR Specifications Met Timing Specifications Met IB Input Bias Current In/Out of Pins C1 Thru C12 When Measuring Cells When Not Measuring Cells IS Supply Current, Active Current Into the V+ Pin when Measuring Voltages with the ADC IM Supply Current, Monitor Mode Average Current Into the V+ Pin While Monitoring for UV and OV Conditions Continuous Monitoring Monitor Every 130ms Monitor Every 500ms Monitor Every 2s IQS Supply Current, Idle Current into the V+ Pin When Idle All Serial Port Pins at Logic ‘1’ ICS Supply Current, Serial I/O Current into the V+ Pin During Serial Communications. All Serial Port Pins at Logic ‘0’ VMODE = 0, This Current is Added to IS or IQS l l 4.5 4.1 l 5 l l 10 4 5.0 5.0 ppm/√khr 5.5 50 50 V V 10 μA pA 1.1 1.2 mA mA 100 1 950 300 175 130 l l 3.1 3.0 V V mA –10 l mV mV mV mV mV mV mV mV mV mV mV V V+ 5 25°C to 85°C and 25°C to –40°C Reference Voltage Long Term Drift Regulator Pin Voltage 2.76 4.32 5.04 –2.76 –4.32 –5.04 Reference Voltage Temperature Coefficient VREG 2.76 5.06 4.32 7.92 5.04 9.24 –2.76 –5.06 –4.32 –7.92 –5.04 –9.24 Common Mode Voltage Range Measured Relative to V– Reference Voltage Thermal Hysteresis mV/Bit μA μA μA μA 50 55 60 μA μA 3.6 4.3 4.5 mA mA 68021p 3 LTC6802-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 43.2V, V– = 0V, unless otherwise noted. SYMBOL PARAMETER Discharge Switch On-Resistance CONDITIONS MIN l VCELL > 3V (Note 3) l Temperature Range TYP MAX 10 20 Ω 85 °C –40 Thermal Shutdown Temperature Thermal Shutdown Hysteresis UNITS 145 °C 5 °C Voltage Mode Timing Specifications tCYCLE Measurement Cycle Time Time Required to Measure 11 or 12 Cells Time Required to Measure Up to 10 Cells Time Required to Measure 1 Cell l l 13 11 2 ms ms ms t1 SDI Valid to SCKI Rising Setup l 10 ns t2 SDI Valid to SCKI Rising Hold l 200 ns t3 SCKI Low l 400 ns t4 SCKI High l 400 ns t5 CSBI Pulse Width l 400 ns t6 SCKI Rising to CSBI Rising l 100 ns t7 CSBI Falling to SCKI Rising l 100 t8 SCKI Falling to SDO Valid l 200 Clock Frequency l 1 MHz Watchdog Timer Time Out Period l 2 s ns 1 ns Timing Specifications tPD1 CSBI to CSBO CCSBO = 150pF l 600 ns tPD2 SCKI to SCKO CSCKO = 150pF l 300 ns tPD3 SDI to SDOI Write Delay CSDOI = 150pF l 300 ns tPD4 SDOI to SDO Read Delay CSDO = 150pF l 300 ns Voltage Mode Digital I/O Specifications VIH Digital Input Voltage High Pins VMODE, SCKI, SDI, and CSBI l VIL Digital Input Voltage Low Pins VMODE, SCKI, SDI, and CSBI l 0.8 V VOL Digital Output Voltage Low Pin SDO; Sinking 500μA l 0.3 V 3 5 μA μA 2 V Current Mode Digital I/O Specifications IIH1 Digital Input Current High Pins CSBI, SCKI, and SDI (Write) l IIL1 Digital Input Current Low Pins CSBI, SCKI, and SDI (Write) l 1000 1200 1500 –1500 –1200 –1000 –5 –3 IIH2 Digital Input Current High Pin SDOI (Read) l IIL2 Digital Input Current Low Pin SDOI (Read) l μA μA IOH1 Digital Output Current High Pins CSBO, SCKO, and SDOI (Write) l 3 5 μA IOL1 Digital Output Current Low Pins CSBO, SCKO, and SDOI (Write) l 1000 1200 1500 μA IOH2 Digital Output Current High Pin SDI (Read) l –1500 –1200 –1000 μA IOL2 Digital Output Current Low Pin SDI (Read) l –5 –3 0 μA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. The ADC specifications are guaranteed by the Total Measurement Error (VERR) specification. Note 3. Due to the contact resistance of the production tester, this specification is tested to relaxed limits. The 20Ω limit is guaranteed by design. Note 4. VCELL refers to the voltage applied across the following pin combinations: V+ to C11, Cn to Cn-1 for n = 2 to 11, C1 to V–. VTEMP refers to the voltage applied from VTEMP1 or VTEMP2 to V– 68021p 4 LTC6802-1 PIN FUNCTIONS CSBO (Pin 1): Chip Select Output (Active Low). CSBO is a buffered version of the chip select input, CSBI. CSBO drives the next IC in the daisy chain. See Serial Port in the Applications Information section. SDOI (Pin 2): Serial Data I/O Pin. SDOI transfers data to and from the next IC in the daisy chain. See Serial Port in the Applications Information section. SCKO (Pin 3): Serial Clock Output. SCKO is a buffered version of SCKI. SCKO drives the next IC in the daisy chain. See Serial Port in the Applications Information section. V+ (Pin 4): Tie pin 4 to the most positive potential in the battery stack. Typically V+ is the same potential as C12. C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1 (Pins 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27): C1 through C12 are the inputs for monitoring battery cell voltages. Up to 12 cells can be monitored. The lowest potential is tied to pin V–. The next lowest potential is tied to C1 and so forth. See the figures in the Applications Information section for more details on connecting batteries to the LTC6802-1. The LTC6802-1 can monitor a series connection of up to 12 cells. The LTC6802-1 cannot monitor parallel combinations of series cells. For example, 3 parallel groups of 4 series cells are not allowed. S12, S11, S10, S9, S8, S7, S6, S5, S4, S3, S2, S1 (Pins 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28): S1 though S12 pins are used to balance battery cells. If one cell in a series becomes over charged, an S output can be used to discharge the cell. Each S output has an internal N-channel MOSFET for discharging. See the Block Diagram. The NMOS has a maximum on resistance of 20Ω. An external resistor should be connected in series with the NMOS to dissipate heat outside of the LTC6802-1 package. When using the internal MOSFETs to discharge cells, the die temperature should be monitored. See Power Dissipation and Thermal Shutdown in the Applications Information section. The S pins also feature an internal 10k pull-up resistor. This allows the S pins to be used to drive the gates of external MOSFETs for higher discharge capability. V– (Pin 29): Connect V– to the most negative potential in the series of cells. NC (Pin 30): Pin 30 is internally connected to V– through 10Ω. Pin 30 can be left unconnected or connected to pin 29 on the PCB. VTEMP1, VTEMP2 (Pins 31, 32): Temperature Sensor Inputs. The ADC measures the voltage on VTEMPx with respect to V– and stores the result in the TMP registers. The ADC measurements are relative to the VREF pin voltage. Therefore a simple thermistor and resistor combination connected to the VREF pin can be used to monitor temperature. The VTEMP inputs can also be general purpose ADC inputs. Any voltage from 0V to 5.125V referenced to V– can be measured. VREF (Pin 33): 3.075V Voltage Reference Output. This pin should be bypassed with a 1μF capacitor. The VREF pin can drive a 100k resistive load connected to V–. Larger loads should be buffered with an LT6003 op amp, or similar device. VREG (Pin 34): Linear Voltage Regulator Output. This pin should be bypassed with a 1μF capacitor. The VREG pin is capable of supplying up to 4mA to an external load. The VREG pin does not sink current. TOS (Pin 35): Top of Stack Input. Tie TOS to VREG when the LTC6802-1 is the top device in a daisy chain. Tie TOS to V– when the LTC6802-1 is any other device in a daisy chain. When TOS is tied to VREG, the LTC6802-1 ignores the SDOI input. When TOS is tied to V–, the LTC6802-1 expects data to be passed to and from the SDOI pin. MMB (Pin 36): Monitor Mode (Active Low) Input. When MMB is low (same potential as V–), the LTC6802-1 goes into monitor mode. See Modes of Operation in the Applications Information section. WDTB (Pin 37): Watchdog Timer Output (Active Low). If there is no activity on the SCKI pin for 2 seconds, the WDTB output is asserted. The WDTB pin is an open drain NMOS output. When asserted it pulls the output down to V– and resets the configuration register to its default state. The watchdog timer function can be disabled by setting WDTEN = 0 in the configuration register. See Watchdog Timer Circuit in the Applications Information section. 68021p 5 LTC6802-1 PIN FUNCTIONS GPIO1, GPIO2 (Pins 38, 39): General Purpose Input/Output. The operation of these pins depends on the state of the MMB pin. When MMB is high, the pins behave as traditional GPIOs. By writing a “0” to a GPIO configuration register bit, the open drain output is activated and the pin is pulled to V–. By writing a logic “1” to the configuration register bit, the corresponding GPIO pin is high impedance. An external resistor is needed to pull the pin up to VREG. By reading the configuration register locations GPIO1 and GPIO2, the state of the pins can be determined. For example, if a “0” is written to register bit GPIO1, a “0” is always read back because the output NMOSFET pulls pin 38 to V–. If a “1” is written to register bit GPIO1, the pin becomes high impedance. Either a “1” or a “0” is read back, depending on the voltage present at pin 38. The GPIOs makes it possible to turn on/off circuitry around the LTC6802-1, or read logic values from a circuit around the LTC6802-1. When the MMB pin is low, the GPIO pins and the WDTB pin are treated as inputs that set the number of cells to be monitored. See Monitor Mode in the Applications Information section. VMODE (Pin 40): Voltage Mode Input. When VMODE is tied to VREG, the SCKI, SDI, SDO, and CSBI pins are configured as voltage inputs and outputs. This means these pins accept standard TTL logic levels. Connect VMODE to VREG when the LTC6802-1 is the bottom device in a daisy chain. When VMODE is connected to V–, the SCKI, SDI, and CSBI pins are configured as current inputs and outputs, and SDO is unused. Connect VMODE to V– when the LTC6802-1 is being driven by another LTC6802-1 in a daisy chain. SCKI (Pin 41): Serial Clock Input. The SCKI pin interfaces to any logic gate (TTL levels) if VMODE is tied to VREG. SCKI must be driven by the SCKO pin of another LTC6802-1 if VMODE is tied to V–. See Serial Port in the Applications Information section. SDI (Pin 42): Serial Data Input. The SDI pin interfaces to any logic gate (TTL levels) if VMODE is tied to VREG. SDI must be driven by the SDOI pin of another LTC6802-1 if VMODE is tied to V–. See Serial Port in the Applications Information section. SDO (Pin 43): Serial Data Output. The SDO pin is an NMOS open drain output if VMODE is tied to VREG. SDO is not used if VMODE is tied to V–. See Serial Port in the Applications Information section. CSBI (Pin 44): Chip Select (Active Low) Input. The CSBI pin interfaces to any logic gate (TTL levels) if VMODE is tied to VREG. CSBI must be driven by the CSBO pin of another LTC6802-1 if VMODE is tied to V–. See Serial Port in the Applications Information section. 68021p 6 LTC6802-1 BLOCK DIAGRAM 4 V+ 5 REGULATOR C12 VREG 34 10k 6 7 S12 WATCHDOG TIMER WDTB C11 SCKO SDOI 10k CSBO 24 S3 Δ∑ A/D CONVERTER MUX 25 12 RESULTS REGISTER AND COMMUNICATIONS C2 CSBI SDO 10k 26 SDI S2 SCKI 27 C1 REFERENCE VMODE 10k 28 29 GPIO2 CONTROL S1 NC GPIO1 MMB V– 10Ω 30 37 TOS 3 2 1 44 43 42 41 40 39 38 36 35 EXTERNAL TEMP DIE TEMP VTEMP1 31 VTEMP2 32 VREF 33 68021 BD 68021p 7 LTC6802-1 TIMING DIAGRAM Timing Diagram of the Serial Interface t4 t1 t2 t6 t3 t7 SCKI D3 SDI D2 D1 D7 … D4 D0 D3 t5 CSBI t8 SDO D4 D3 D2 PREVIOUS COMMAND D1 D0 D7 … D4 CURRENT COMMAND D3 6915 TD OPERATION THEORY OF OPERATION The LTC6802-1 is a data acquisition IC capable of measuring the voltage of 12 series connected battery cells. An input multiplexer connects the batteries to a 12-bit delta-sigma analog to digital converter (ADC). An internal 10ppm voltage reference combined with the ADC give the LTC6802-1 its outstanding measurement accuracy. The inherent benefits of the delta-sigma ADC vs other types of ADCs (e.g. successive approximation) are explained in Advantages of Delta-Sigma ADCs in the Applications Information section. Communication between the LTC6802-1 and a host processor is handled by a SPI compatible serial interface. As shown in Figure 1, the LTC6802-1’s can pass data up and down a stack of devices using simple diodes for isolation. This operation is described in Serial Port in the Applications Information section. The LTC6802-1 also contains circuitry to balance cell voltages. Internal MOSFETs can be used to discharge cells. These internal MOSFETs can also be used to control external balancing circuits. Figure 1 illustrates cell balancing by internal discharge. Figure 4 shows the S pin controlling an external balancing circuit. It is important to note that the LTC6802-1 makes no decisions about turning on/off the internal MOSFETs. This is completely controlled by the host processor. The host processor writes values to a configuration register inside the LTC6802-1 to control the switches. The watchdog timer on the LTC6802-1 can be used to turn off the discharge switches if communication with the host processor is interrupted. OPEN CONNECTION DETECTION The open connection detection algorithm assures that an open circuit is not misinterpreted as a valid cell reading. In the absence of external noise filtering, the input resistance of the ADC will cause open wires to produce a near zero reading. Internal current sources can be used to determine if the wire is truly open. For example, an open on input C3 will result in a near zero reading for both cells connected to C3. For illustration these cells are labeled B3 and B4 in Figure 2. If a near zero reading is encountered for B3 and B4, the MPU can command the LTC6802-1 to place 100μA current sources from the ADC inputs to V–. If input C3 is open, the new reading will show B3 to be zero and B4 to be full-scale. Some applications may include external noise filtering to improve the quality of the ADC readings. When an RC network is used to filter noise, an open wire may not produce 68021p 8 LTC6802-1 OPERATION BATTERY POSITIVE 350V CSBO SDOI SCKO V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 CSBO SDOI SCKO V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 LTC6802-1 IC #8 CSBI SDO SDI SCKI BATTERIES #25–#84 AND LTC6802-1 ICs #3–#7 CSBO SDOI SCKO V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 VMODE GPIO2 GPIO1 WDTB MMB TOS VREG VREF VTEMP2 VTEMP1 NC V− S1 C1 S2 C2 S3 C3 LTC6802-1 IC #1 V2– OE2 LTC6802-1 IC #2 CSBI SDO SDI SCKI VMODE GPIO2 GPIO1 WDTB MMB TOS VREG VREF VTEMP2 VTEMP1 NC V− S1 C1 S2 C2 S3 C3 3V V1– OE1 CS MISO MOSI CLK CSBI SDO SDI SCKI V2+ V2– VMODE GPIO2 GPIO1 WDTB MMB TOS VREG VREF VTEMP2 VTEMP1 NC V− S1 C1 S2 C2 S3 C3 V1– V1+ MPU MODULE IO 3V DIGITAL ISOLATOR 68021 F01 Figure 1. 96-Cell Battery Stack, Daisy Chain Interface. This Application Schematic illustrates the Simplest Possible System 68021p 9 LTC6802-1 OPERATION DISCHARGING DURING CELL MEASUREMENTS LTC6802-1 The primary cell voltage A/D measurement commands (STCVAD and STOWAD) automatically turn off a cell’s discharge switch while its voltage is being measured. The discharge switches for the cell above and the cell below will also be turned off during the measurement. For example, discharge switches S4, S5, and S6 will be disabled while cell 5 is being measured. C4 B4 C3 B3 MUX C2 C1 V– 100μA 68021 F02 Figure 2. Open Connection a zero reading because the ADC input resistance is too large to discharge the capacitors on the input pin. Consider the example in Figure 3 where input C3 is open. After several cycles of measuring battery cells B3 and B4, the ADC input resistance charges capacitors CF3 and CF4. The resulting potential on input C3 will be approximately midway between C2 and C4. The ADC readings of B3 and B4 may indicate a valid cell voltage when in fact the exact state of B3 and B4 is unknown. If the 100μA current sources are engaged, the potential at C3 will be pulled down. The ADC reading for B3 will approach zero and the reading for B4 will approach full scale. The amount of change in the cell voltage reading is a function of the external filter capacitor and time that the 100μA current sources are connected to the cell. LTC6802-1 C4 B4 B3 CF4 CF3 When using the STCVDC for all cells (command 0x60), for each cell (CN) that is discharging, the adjacent lower cell (CN-1) will return a cell voltage value near 0V. To avoid misinterpretation of the cell voltages read after using this command, there are two recommendations: 1. Use the STCVDC command for all cell voltages (command 0x60) with only one discharge switch on at a time. The value returned for the cell directly below the cell being discharged will be invalid and read close to 0V. The voltage reading of all other cells, including the cell being discharged, will be valid. 2. Use the individual cell commands with discharge permitted (STCVDC commands 0x61 thru 0x6c) and only turn on the discharge switch for the cell being measured. The voltage reading for the individual cell being measured and discharged will be valid. All discharge switches are automatically disabled during OV and UV comparison measurements. C3 C2 In some systems it may be desirable to allow discharging to continue during cell voltage measurements. The cell voltage A/D conversion commands STCVDC and STOWDC allow any enabled discharge switches to remain on during cell voltage measurements. This feature allows the system to perform a self-test to verify the discharge functionality and multiplexer operation. MUX A/D CONVERTER DIGITAL SELF TEST C1 V– 100μA 68021 F03 Figure 3. Open Connection with RC Filtering Two self test commands can be used to verify the functionality of the digital portions of the ADC. The self tests also verify the cell voltage registers and temperature monitoring registers. During these self tests a test signal is applied to the ADC. If the circuitry is working properly all cell voltage and temperature registers will contain 68021p 10 LTC6802-1 OPERATION identical codes. For Self Test 1 the registers will contain 0x555. For Self Test 2, the registers will contain 0xAAA. The time required for the self test function is the same as required to measure all cell voltages or all temperature sensors. Perform the self test function with CDC[2:0] set to 1 in the configuration register. USING THE S PINS AS DIGITAL OUTPUTS OR GATE DRIVERS The S outputs include an internal 10k pull-up resistor. Therefore the S pins will behave as a digital output when loaded with a high impedance, e.g. the gate of an external MOSFET. For applications requiring high battery discharge currents, connect a discrete PMOS switch device and suitable discharge resistor to the cell, and the gate terminal to the S output pin, as illustrated in Figure 4. C(n) SI2351DS 15Ω 1W VISHAY CRCW2512 SERIES S(n) C(n – 1) 68021 F04 Figure 4. External Discharge FET Connection (One Cell Shown) POWER DISSIPATION AND THERMAL SHUTDOWN The MOSFETs connected to the pins S1 through S12 can be used to discharge battery cells. An external resistor should be used to limit the power dissipated by the MOSFETs. The maximum power dissipation in the MOSFETs is limited by the amount of heat that can be tolerated by the LTC6802-1. Excessive heat results in elevated die temperatures. The electrical characteristics are guaranteed for die temperatures up to 85°C. Little or no degradation will be observed in the measurement accuracy for die temperatures up to 105°C. Damage may occur near 150°C, therefore the recommended maximum die temperature is 125°C. To protect the LTC6802-1 from damage due to overheating, a thermal shutdown circuit is included. Overheating of the device can occur when dissipating significant power in the cell discharge switches or when communicating frequently to the device using the current-mode serial interface. The problem is exacerbated when operating with a large voltage between V+ and V– or when the thermal conductivity of the system is poor. The thermal shutdown circuit is enabled whenever the device is not in standby mode (see Modes of Operation). For the LTC6802-1, the thermal shutdown circuit will also be enabled when any current mode input or output is sinking or sourcing current. If the temperature detected on the device goes above approximately 145°C, the configuration registers will be reset to default states, turning off all discharge switches and disabling A/D conversions. Also, for the LTC6802-1, the current mode interface will not operate until the overtemperature condition goes away. When a thermal shutdown has occurred, the THSD bit in the temperature register group will go high. The bit is cleared by performing a read of the temperature registers (RDTMP command). Since thermal shutdown interrupts normal operation, the internal temperature monitor should be used to determine when the device temperature is approaching unacceptable levels. APPLICATIONS INFORMATION USING THE LTC6802-1 WITH LESS THAN 12 CELLS The LTC6802-1 can be used with as few as four cells. The minimum number of cells is governed by the supply voltage requirements of the LTC6802-1. The sum of the cell voltages must be 10V to guarantee that all electrical specifications are met. Figure 5 shows an example of the LTC6802-1 when used to monitor seven cells. The lowest C inputs connect to the seven cells and the upper C inputs connect to V+. Other configurations, e.g. 9 cells, would be configured in the same way: the lowest C inputs connected to the battery cells and the unused C inputs connected to V+. The unused inputs will result in a reading of 0V for those channels. 68021p 11 LTC6802-1 APPLICATIONS INFORMATION The read back value of that bit will be the logic level that appears at the GPIO pin. NEXT HIGHER GROUP OF 7 CELLS LTC6802-1 V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 S2 C1 S1 V− NEXT LOWER GROUP OF 7 CELLS When the MMB pin is low, the GPIO pins and the WDTB pin are treated as inputs that set the number of cells to be monitored. See the Monitor Mode section. WATCHDOG TIMER CIRCUIT The LTC6802-1 includes a watchdog timer circuit. If no activity is detected on the SCKI pin for 2 seconds, the WDTB open drain output is asserted low. The WDTB pin remains low until an edge is detected on the SCKI pin. When the watchdog timer circuit times out, the configuration bits are reset to their default (power-up) state. In the power-up state, the S outputs are off. Therefore, the watchdog timer provides a means to turn off cell discharging should communications to the MPU be interrupted. The IC is in the minimum power standby mode after a time out. Note that externally pulling the WDTB pin low will not reset the configuration bits. 68021 F05 Figure 5. Monitoring 7 Cells with the LTC6802-1 The ADC can also be commanded to measure a stack of cells by making 10 or 12 measurements, depending on the state of the CELL10 bit in the control register. Data from all 10 or 12 measurements must be down loaded when reading the conversion results. The ADC can be commanded to measure any individual cell voltage. USING THE GENERAL PURPOSE INPUTS/OUTPUTS (GPIO1, GPIO2) The LTC6802-1 has two general purpose digital inputs/outputs. By writing a GPIO configuration register bit to a logic low, the open drain output can be activated. The GPIOs give the user the ability to turn on/off circuitry around the LTC6802-1. One example might be a circuit to verify the operation of the system. When a GPIO configuration bit is written to a logic high, the corresponding GPIO pin may be used as an input. The configuration bit WDTEN (byte CNFG0, bit 7) allows the user to disable the watchdog timer operation. The default value is WDTEN = 1 (enabled). The watchdog timer operation is disabled when MMB is low. When reading the configuration register, byte CNFG0 bit 7 will reflect the state of the WDTB pin, independent of what value was written to the WDTEN bit. Consequently, if the watchdog timer is disabled by writing the WDTEN bit to 0, the WDTB pin can be used as a general purpose input, with the read value of the WDTEN bit reflecting an input applied to the WDTB pin. REVISION CODE The temperature register group contains a 3-bit revision code. If software detection of device revision is necessary, then contact the factory for details. Otherwise, the code can be ignored. In all cases, however, the values of all bits must be used when calculating the packet error code (PEC) CRC byte on data reads. 68021p 12 LTC6802-1 APPLICATIONS INFORMATION MODES OF OPERATION The LTC6802-1 has three modes of operation: standby, measure, and monitor. Standby mode is a power saving state where all circuits except the serial interface are turned off. In measure mode, the LTC6802-1 is used to measure cell voltages and store the results in memory. Measure mode will also monitor each cell voltage for overvoltage (OV) and undervoltage (UV) conditions. In monitor mode, the device will only monitor cells for UV and OV conditions. A signal is output on the SDO pin to indicate the UV/OV status. The serial interface is disabled. Standby Mode The LTC6802-1 defaults (powers up) to standby mode. Standby mode is the lowest possible supply current state. All circuits are turned off except the serial interface and the voltage regulator. For the lowest possible standby current consumption all SPI logic inputs should be set to a logic 1 level. The LTC6802-1 can be programmed for standby mode by setting the comparator duty cycle configuration bits, CDC[2:0], to 0. If the part is put into standby mode while ADC measurements are in progress, the measurements will be interrupted and the cell voltage registers will be in an indeterminate state. To exit standby mode, the CDC bits must be written to a value other than 0. If fewer than 12 cells are connected to the LTC6802-1 then it is necessary to mask the unused input channels. The MCxI bits in the configuration registers are used to mask channels. If the CELL10 bit is high, then the inputs for cells 11 and 12 are automatically masked. The LTC6802-1 can monitor UV and OV conditions continuously. Alternatively, the duty cycle of the UV and OV comparisons can be reduced or turned off to lower the overall power consumption. The CDC bits are used to control the duty cycle. To initiate cell voltage measurements while in measure mode, a Start A/D Conversion and Poll Status command must be sent. After the command has been sent, the LTC6802-1 will send the A/D converter status using either the toggle polling or the level polling method, as described in the Serial Port section. If the CELL10 bit is high, then only the bottom 10 cell voltages will be measured, thereby reducing power consumption and measurement time. By default the CELL10 bit is low, enabling measurement of all 12 cell voltages. During cell voltage measurement commands, UV and OV flag conditions, reflected in the flag register group, are also updated. When the measurements are complete, the part will go back to monitoring UV and OV conditions at the rate designated by the CDC bits. Monitor Mode Measure Mode LTC6802-1 is in measure mode when the CDC bits are programmed with a value from 1 to 7. The IC monitors each cell voltage and produces an interrupt signal on the SDO pin indicating all cell voltages are within the UV and OV limits. There are two methods for indicating the UV/OV interrupt status: toggle polling (using a 1kHz output signal) and level polling (using a high or low output signal). The polling methods are described in the Serial Port section. The UV/OV limits are set by the VUV and VOV values in the configuration registers. When a cell voltage exceeds the UV/OV limits a bit is set in the flag register. The UV and OV flag status for each cell can be determined using the Read Flag Register Group. The LTC6802-1 can be used as a simple monitoring circuit with no serial interface by pulling the MMB pin low. When in this mode, the interrupt status is indicated on the SDO pin using the toggle polling mode described in the Serial Port section. Unlike serial port polling commands, however, the toggling is independent of the state of the CSBI pin. See Figure 6. When the MMB pin is low, all the device configuration values are reset to the default states shown in Table 12. When MMB is held low the VUV, VOV, and CDC register values are ignored. Instead VUV and VOV use factoryprogrammed setings. CDC is set to state 5. The number of cells to be monitored is set by the logic levels on the WDTB and GPIO pins, as shown in Table 1. 68021p 13 LTC6802-1 APPLICATIONS INFORMATION BATTERY POSITIVE 350V LTC6802-1 CSBI SDO SDI SCKI VMODE GPIO2 GPIO1 WDTB MMB TOS VREG VREF VTEMP2 VTEMP1 NC V− S1 C1 S2 C2 S3 C3 CSBO SDOI SCKO V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 CSBO SDOI SCKO V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 LTC6802-1 IC #8 CSBI SDO SDI SCKI VMODE GPIO2 GPIO1 WDTB MMB TOS VREG VREF VTEMP2 VTEMP1 NC V− S1 C1 S2 C2 S3 C3 IC #3 TO IC #7 LTC6802-1 CSBI SDO SDI SCKI VMODE GPIO2 GPIO1 WDTB MMB TOS VREG VREF VTEMP2 VTEMP1 NC V− S1 C1 S2 C2 S3 C3 CSBO SDOI SCKO V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 CSBO SDOI SCKO V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 LTC6802-1 IC #2 CSBI SDO SDI SCKI VMODE GPIO2 GPIO1 WDTB MMB TOS VREG VREF VTEMP2 VTEMP1 NC V− S1 C1 S2 C2 S3 C3 3V LTC6802-1 CSBI SDO SDI SCKI VMODE GPIO2 GPIO1 WDTB MMB TOS VREG VREF VTEMP2 VTEMP1 NC V− S1 C1 S2 C2 S3 C3 CSBO SDOI SCKO V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 CSBO SDOI SCKO V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 LTC6802-1 IC #1 V2− OE2 V1− OE1 MPU VMODE GPIO2 GPIO1 WDTB MMB TOS VREG VREF VTEMP2 VTEMP1 NC V− S1 C1 S2 C2 S3 C3 MODULE IO CS MISO MOSI CLK CSBI SDO SDI SCKI V2+ V2− V1− V1+ DIGITAL ISOLATOR 3V 68021 F06 Figure 6. Redundant Monitoring Circuit 68021p 14 LTC6802-1 APPLICATIONS INFORMATION Table 1. Monitor Mode Cell Selection WDTB GPIO2 GPIO1 CELL INPUTS MONITORED 0 0 0 Cells 1 to 5 0 0 1 Cells 1 to 6 0 1 0 Cells 1 to 7 0 1 1 Cells 1 to 8 1 0 0 Cells 1 to 9 1 0 1 Cells 1 to 10 1 1 0 Cells 1 to 11 1 1 1 Cells 1 to 12 If MMB is low then brought high, all device configuration values are reset to the default states including the VUV, VOV, and CDC configuration bits. SERIAL PORT Overview The LTC6802-1 has an SPI bus compatible serial port. Several devices can be daisy chained in series. There are two sets of serial port pins, designated as low side and high side. The low side and high side ports enable devices to be daisy chained even when they operate at different power supply potentials. In a typical configuration, the positive power supply of the first, bottom device is connected to the negative power supply of the second, top device, as shown in Figure 1. When devices are stacked in this manner, they can be daisy chained by connecting the high side port of the bottom device to the low side port of the top device. With this arrangement, the master writes to or reads from the cascaded devices as if they formed one long shift register. The LTC6802-1 translates the voltage level of the signals between the low side and high side ports to pass data up and down the battery stack. Physical Layer On the LTC6802-1, seven pins comprise the low side and high side ports. The low side pins are CSBI, SCKI, SDI, and SDO. The high side pins are CSBO, SCKO and SDOI. CSBI and SCKI are always inputs, driven by the master or by the next lower device in a stack. CSBO and SCKO are always outputs that can drive the next higher device in a stack. SDI is a data input when writing to a stack of devices. For devices not at the bottom of a stack, SDI is a data output when reading from the stack. SDOI is a data output when writing to and a data input when reading from a stack of devices. SDO is an open drain output that is only used on the bottom device of a stack, where it may be tied with SDI, if desired, to form a single, bi-directional port. The SDO pin on the bottom device of a stack requires a pull-up resistor. For devices up in the stack, SDO should be tied to the local V– or left floating. To communicate between daisy-chained devices, the high side port pins of a lower device (CSBO, SCKO, and SDOI) must be connected through PN junction diodes to the respective low side port pins of the next higher device (CSBI, SCKI, and SDI). In this configuration, the devices communicate using current rather than voltage. To signal a logic high from the lower device to the higher device, the lower device sinks a smaller current from the higher device pin. To signal a logic low, the lower device sinks a larger current. Likewise, to signal a logic high from the higher device to the lower device, the higher device sources a larger current to the lower device pin. To signal a logic low, the higher device sources a smaller current. See Figure 7. Standby current consumed in the current mode serial interface is minimized when CSBI, SCKI, and SDI are all high. VSENSE (WRITE) + – LOW SIDE PORT ON HIGHER DEVICE READ 1 WRITE HIGH SIDE PORT ON LOWER DEVICE VSENSE (READ) + – 68021 F07 Figure 7. Current Mode Interface 68021p 15 LTC6802-1 APPLICATIONS INFORMATION The voltage mode pin (VMODE) determines whether the low side serial port is configured as voltage mode or current mode. For the bottom device in a daisy-chain stack, this pin must be pulled high (tied to VREG). The other devices in the daisy chain must have this pin pulled low (tied to V–) to designate current mode communication. To designate the top-of-stack device for polling commands, the TOS pin on the top device of a daisy chain must be tied high. The other devices in the stack must have TOS tied low. See Figure 1. Data Transfers: Every byte consists of 8 bits. Bytes are transferred with the most significant bit (MSB) first. On a write, the data value on SDI is latched into the device on the rising edge of SCKI (Figure 8). Similarly, on a read, the data value output on SDO is valid during the rising edge of SCKI and transitions on the falling edge of SCKI (Figure 9). Data Link Layer CSBI must remain low for the entire duration of a command sequence, including between a command byte and subsequent data. On a write command, data is latched in on the rising edge of CSBI. Clock Phase And Polarity: The LTC6802-1 SPI-compatible interface is configured to operate in a system using CPHA=1 and CPOL=1. Consequently, data on SDI must be stable during the rising edge of SCKI. After a polling command has been entered, the SDO output will immediately be driven by the polling state, with the SCKI input ignored (Figure 10). See the Toggle Polling and Level Polling sections. CSBI SCKI SDI MSB (CMD) BIT6 (CMD) LSB (CMD) MSB (DATA) LSB (DATA) 68021 F08 Figure 8. Transmission Format (Write) CSBI SCKI SDI SDO MSB (CMD) BIT6 (CMD) LSB (CMD) MSB (DATA) LSB (DATA) 68021 F09 Figure 9. Transmission Format (Read) 68021p 16 LTC6802-1 APPLICATIONS INFORMATION CSBI SCKI SDI MSB (CMD) BIT6 (CMD) SDO LSB (CMD) POLL STATE 68021 F10 Figure 10. Transmission Format (Poll) Network Layer Broadcast Commands: A broadcast command is one to which all devices on the bus will respond, regardless of device address. See the Bus Protocols and Commands sections. In daisy chained configurations, all devices in the chain receive the command bytes simultaneously. For example, to initiate A/D conversions in a stack of devices, a single STCVAD command byte is sent, and all devices will start conversions at the same time. For read and write commands, a single command byte is sent, and then the stacked devices effectively turn into a cascaded shift register, in which data is shifted through each device to the next higher (on a write) or the next lower (on a read) device in the stack. See the Serial Command Examples section. PEC Byte: The Packet Error Code (PEC) byte is a CRC value calculated for all of the bits in a register group in the order they are read, using the following characteristic polynomial: x8 + x2 + x + 1 On a read command, after sending the last byte of a register group, the device will shift out the calculated PEC, MSB first. For daisy-chained devices, after the PEC is read from the first device, the data from any daisy-chained devices will follow in the same order. For example, when reading the flag registers from two stacked devices (bottom device A and top device B), the data will be output in the following order: FLGR0(A), FLGR1(A), FLGR2(A), PEC(A), FLGR0(B), FLGR1(B), FLGR2(B), PEC(B) Toggle Polling: Toggle polling allows a robust determination both of device states and of the integrity of the connections between the devices in a stack. Toggle polling is enabled when the LVLPL bit is low. After entering a polling command, the data out line will be driven by the slave devices based on their status. When polling for the A/D converter status, data out will be low when any device is busy performing an A/D conversion and will toggle at 1kHz when no device is busy. Similarly, when polling for interrupt status, the output will be low when any device has an interrupt condition and will toggle at 1kHz when none has an interrupt condition. Toggle Polling—Daisy-Chained Broadcast Polling: The SDO pin (bottom device) or SDI pin (stacked devices) will be low if a device is busy/in interrupt. If it is not busy/not in interrupt, the device will pass the signal from the SDOI input to data out (if not the top-of-stack device) or toggle the data out line at 1kHz (if the top-of-stack device). The master pulls CSBI high to exit polling. Level polling: Level polling is enabled when the LVLPL bit is high. After entering a polling command, the data out line will be driven by the slave devices based on their status. When polling for the A/D converter status, data 68021p 17 LTC6802-1 APPLICATIONS INFORMATION out will be low when any device is busy performing an A/D conversion and will be high when no device is busy. Similarly, when polling for interrupt status, the output will be low when any device has an interrupt condition and will be high when none has an interrupt condition. Level polling—Daisy-Chained Broadcast Polling: The SDO pin (bottom device) or SDI pin (stacked devices) will be low if a device is busy/in interrupt. If it is not busy/not in interrupt, the device will pass the level from the SDOI input to data out (if not the top-of-stack device) or hold the data out line high (if the top-of-stack device). Therefore, if any device in the chain is busy or in interrupt, the SDO signal at the bottom of the stack will be low. If all devices are not busy/not in interrupt, the SDO signal at the bottom of the stack will be high. conversion time to pass before reading the results. The second method is to hold CSBI low after an A/D start command has been sent. The A/D conversion status will be output on SDO. A problem with the second method is that the controller is not free to do other serial communication while waiting for A/D conversions to complete. The third method overcomes this limitation. The controller can send an A/D start command, perform other tasks, and then send a Poll A/D Converter Status (PLADC) command to determine the status of the A/D conversions. For OV/UV interrupt status, the Poll Interrupt Status (PLINT) command can be used to quickly determine whether any cell in a stack is in an overvoltage or undervoltage condition. Bus Protocols The master pulls CSBI high to exit polling. Polling Methods: For A/D conversions, three methods can be used to determine A/D completion. First, a controller can start an A/D conversion and wait for the specified There are 3 different protocol formats, depicted in Table 3 through Table 5. Table 2 is the key for reading the protocol diagrams. Table 2. Protocol Key PEC Packet error code (CRC-8) Master-to-slave N Number of bits Slave-to-master … Continuation of protocol Complete byte of data Table 3. Broadcast Poll Command 8 Command Poll Data Table 4. Broadcast Read 8 8 Command Data Byte Low … 8 8 8 Data Byte High PEC Shift Byte 1 8 8 Data Byte High Shift Byte 1 8 … Shift Byte N Table 5. Broadcast Write 8 8 Command Data Byte Low … 8 … Shift Byte N 68021p 18 LTC6802-1 APPLICATIONS INFORMATION Commands Table 6. Command Codes Write Configuration Register Group WRCFG 0x01 Read Configuration Register Group RDCFG 0x02 Read Cell Voltage Register Group RDCV 0x04 Read Flag Register Group RDFLG 0x06 Read Temperature Register Group RDTMP 0x08 Start Cell Voltage A/D Conversions and Poll Status STCVAD 0x10 (all cell voltage inputs) 0x11 (cell 1 only) 0x12 (cell 2 only) … 0x1A (cell 10 only) 0x1B (cell 11 only, if CELL10 bit=0) 0x1C (cell 12 only, if CELL10 bit=0) 0x1D (unused) 0x1E (cell self test 1; all CV=0x555) 0x1F (cell self test 2; all CV=0xAAA) Start Open Wire A/D Conversions and Poll Status STOWAD 0x20 (all cell voltage inputs) 0x21 (cell 1 only) 0x22 (cell 2 only) … 0x2A (cell 10 only) 0x2B (cell 11 only, if CELL10 bit=0) 0x2C (cell 12 only, if CELL10 bit=0) 0x2D (unused) 0x2E (cell self test 1; all CV=0x555) 0x2F (cell self test 2; all CV=0xAAA) Start Temperature A/D Conversions and Poll Status STTMPAD 0x30 (all temperature inputs) 0x31 (external temp 1 only) 0x32 (external temp 1 only) 0x33 (internal temp only) 0x34—0x3D (unused) 0x3E (temp self test 1; all TMP=0x555) 0x3F (temp self test 2; all TMP=0xAAA) Poll A/D Converter Status PLADC 0x40 Poll Interrupt Status PLINT 0x50 Start Cell Voltage A/D Conversions and Poll Status, with Discharge Permitted STCVDC 0x60 (all cell voltage inputs) 0x61 (cell 1 only) 0x62 (cell 2 only) … 0x6A (cell 10 only) 0x6B (cell 11 only, if CELL10 bit=0) 0x6C (cell 12 only, if CELL10 bit=0) 0x6D (unused) 0x6E (cell self test 1; all CV=0x555) 0x6F (cell self test 2; all CV=0xAAA) Start Open Wire A/D Conversions and Poll Status, with Discharge Permitted STOWDC 0x70 (all cell voltage inputs) 0x71 (cell 1 only) 0x72 (cell 2 only) … 0x7A (cell 10 only) 0x7B (cell 11 only, if CELL10 bit=0) 0x7C (cell 12 only, if CELL10 bit=0) 0x7D (unused) 0x7E (cell self test 1; all CV=0x555) 0x7F (cell self test 2; all CV=0xAAA) 68021p 19 LTC6802-1 APPLICATIONS INFORMATION Memory Map Table 7 through Table 12 show the memory map for the LTC6802-1. Table 12 gives bit descriptions. Table 7. Configuration (CFG) Register Group REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CFGR0 RD/WR WDTEN GPIO2 GPIO1 LVLPL CELL10 CDC[2] CDC[1] CDC[0] CFGR1 RD/WR DCC8 DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 CFGR2 RD/WR MC4I MC3I MC2I MC1I DCC12 DCC11 DCC10 DCC9 CFGR3 RD/WR MC12I MC11I MC10I MC9I MC8I MC7I MC6I MC5I CFGR4 RD/WR VUV[7] VUV[6] VUV[5] VUV[4] VUV[3] VUV[2] VUV[1] VUV[0] CFGR5 RD/WR VOV[7] VOV[6] VOV[5] VOV[4] VOV[3] VOV[2] VOV[1] VOV[0] BIT 3 BIT 2 BIT 1 BIT 0 Table 8. Cell Voltage (CV) Register Group REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 CVR00 RD C1V[7] C1V[6] C1V[5] C1V[4] C1V[3] C1V[2] C1V[1] C1V[0] CVR01 RD C2V[3] C2V[2] C2V[1] C2V[0] C1V[11] C1V[10] C1V[9] C1V[8] CVR02 RD C2V[11] C2V[10] C2V[9] C2V[8] C2V[7] C2V[6] C2V[5] C2V[4] CVR03 RD C3V[7] C3V[6] C3V[5] C3V[4] C3V[3] C3V[2] C3V[1] C3V[0] CVR04 RD C4V[3] C4V[2] C4V[1] C4V[0] C3V[11] C3V[10] C3V[9] C3V[8] CVR05 RD C4V[11] C4V[10] C4V[9] C4V[8] C4V[7] C4V[6] C4V[5] C4V[4] CVR06 RD C5V[7] C5V[6] C5V[5] C5V[4] C5V[3] C5V[2] C5V[1] C5V[0] CVR07 RD C6V[3] C6V[2] C6V[1] C6V[0] C5V[11] C5V[10] C5V[9] C5V[8] CVR08 RD C6V[11] C6V[10] C6V[9] C6V[8] C6V[7] C6V[6] C6V[5] C6V[4] CVR09 RD C7V[7] C7V[6] C7V[5] C7V[4] C7V[3] C7V[2] C7V[1] C7V[0] CVR10 RD C8V[3] C8V[2] C8V[1] C8V[0] C7V[11] C7V[10] C7V[9] C7V[8] CVR11 RD C8V[11] C8V[10] C8V[9] C8V[8] C8V[7] C8V[6] C8V[5] C8V[4] CVR12 RD C9V[7] C9V[6] C9V[5] C9V[4] C9V[3] C9V[2] C9V[1] C9V[0] CVR13 RD C10V[3] C10V[2] C10V[1] C10V[0] C9V[11] C9V[10] C9V[9] C9V[8] CVR14 RD C10V[11] C10V[10] C10V[9] C10V[8] C10V[7] C10V[6] C10V[5] C10V[4] CVR15* RD C11V[7] C11V[6] C11V[5] C11V[4] C11V[3] C11V[2] C11V[1] C11V[0] CVR16* RD C12V[3] C12V[2] C12V[1] C12V[0] C11V[11] C11V[10] C11V[9] C11V[8] CVR17* RD C12V[11] C12V[10] C12V[9] C12V[8] C12V[7] C12V[6] C12V[5] C12V[4] *Registers CVR15, CVR16, and CVR17 can only be read if the CELL10 bit in register CFGR0 is low 68021p 20 LTC6802-1 APPLICATIONS INFORMATION Table 9. Flag (FLG) Register Group REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FLGR0 RD C4OV C4UV C3OV C3UV C2OV C2UV C1OV C1UV FLGR1 RD C8OV C8UV C7OV C7UV C6OV C6UV C5OV C5UV FLGR2 RD C12OV* C12UV* C11OV* C11UV* C10OV C10UV C9OV C9UV * Bits C11UV, C12UV, C11OV, and C12OV are always low if the CELL10 bit in register CFGR0 is high Table 10. Temperature (TMP) Register Group REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TMPR0 RD ETMP1[7] ETMP1[6] ETMP1[5] ETMP1[4] ETMP1[3] ETMP1[2] ETMP1[1] ETMP1[0] TMPR1 RD ETMP2[3] ETMP2[2] ETMP2[1] ETMP2[0] ETMP1[11] ETMP1[10] ETMP1[9] ETMP1[8] TMPR2 RD ETMP2[11] ETMP2[10] ETMP2[9] ETMP2[8] ETMP2[7] ETMP2[6] ETMP2[5] ETMP2[4] TMPR3 RD ITMP[7] ITMP[6] ITMP[5] ITMP[4] ITMP[3] ITMP[2] ITMP[1] ITMP[0] TMPR4 RD REV[2] REV[1] REV[0] THSD ITMP[11] ITMP[10] ITMP[9] ITMP[8] Table 11. Packet Error Code (PEC) REGISTER PEC RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RD PEC[7] PEC[6] PEC[5] PEC[4] PEC[3] PEC[2] PEC[1] PEC[0] 68021p 21 LTC6802-1 APPLICATIONS INFORMATION Table 12. Memory Bit Descriptions NAME CDC DESCRIPTION Comparator Duty Cycle VALUES CDC UV/OV COMPARATOR PERIOD VREF POWERED DOWN BETWEEN MEASUREMENTS CELL VOLTAGE MEASUREMENT TIME 0 (default) N/A (Comparator Off) Standby Mode Yes N/A 1 N/A (Comparator Off) No 13ms 2 13ms No 13ms 3 130ms No 13ms 4 500ms No 13ms 5* 130ms Yes 21ms 6 500ms Yes 21ms 7 2000ms Yes 21ms *when MMB pin is low, the CDC value is set to 5 CELL10 10-Cell Mode 0=12-cell mode (default); 1=10-cell mode LVLPL Level Polling Mode 0=toggle polling (default); 1=level polling GPIO1 GPIO1 Pin Control GPIO2 GPIO2 Pin Control WDTEN Watchdog Timer Enable DCCx Discharge Cell x VUV Undervoltage Comparison Voltage* VOV Overvoltage Comparison Voltage* MCxI Mask Cell x Interrupts CxV Cell x Voltage* CxUV Cell x Undervoltage Flag CxOV Cell x Overvoltage Flag ETMPx External Temperature Measurement* Write: 0=GPIO1 pin pull down on; 1=GPIO1 pin pull down off (default) Read: 0=GPIO1 pin at logic ‘0’; 1=GPIO1 pin at logic ‘1’ Write: 0=GPIO2 pin pull down on; 1=GPIO2 pin pull down off (default) Read: 0=GPIO2 pin at logic ‘0’; 1=GPIO2 pin at logic ‘1’ Write: 0=watchdog timer disabled; 1=watchdog timer enabled (default) Read: 0=WDTB pin at logic ‘0’; 1=WDTB pin at logic ‘1’ x=1..12 0=turn off shorting switch for cell ‘x’ (default); 1=turn on shorting switch Comparison voltage = VUV * 16 * 1.5mV (default VUV=0. When MMB pin is low a factory programmed comparison voltage is used) Comparison voltage = VOV * 16 * 1.5mV (default VOV=0. When MMB pin is low a factory programmed comparison voltage is used) x=1..12 0=enable interrupts for cell ‘x’ (default) 1=turn off interrupts and clear flags for cell ‘x’ x=1..12 12-bit ADC measurement value for cell ‘x’ cell voltage for cell ‘x’ = CxV * 1.5mV reads as 0xFFF while A/D conversion in progress x=1..12 cell voltage compared to VUV comparison voltage 0=cell ‘x’ not flagged for under voltage condition; 1=cell ‘x’ flagged x=1..12 cell voltage compared to VOV comparison voltage 0=cell ‘x’ not flagged for over voltage condition; 1=cell ‘x’ flagged Temperature measurement voltage = ETMPx * 1.5mV 0= thermal shutdown has not occurred; 1=thermal shutdown has occurred THSD Thermal Shutdown Status REV Revision Code Device revision code ITMP Internal Temperature Measurement* Temperature measurement voltage = ITMP * 1.5mV = 8mV * T(°K) PEC Packet Error Code CRC value for reads Status cleared to ‘0’ on read of Thermal Register Group *Voltage determinations use the decimal value of the registers, 0 to 4095 for 12-bit and 0 to 255 for 8-bit registers 68021p 22 LTC6802-1 APPLICATIONS INFORMATION SERIAL COMMAND EXAMPLES LTC6802-1 (Daisy Chained Configuration) Examples below use a configuration of three stacked devices: bottom (B), middle (M), and top (T) Write Configuration Registers 1. 2. 3. 4. 5. 6. Pull CSBI low Send WRCFG command byte Send CFGR0 byte for top device, then CFGR1 (T), CFGR2 (T), … CFGR5 (T) Send CFGR0 byte for middle device, then CFGR1 (M), CFGR2 (M), … CFGR5 (M) Send CFGR0 byte for bottom device, then CFGR1 (B), CFGR2 (B), … CFGR5 (B) Pull CSBI high; data latched into all devices on rising edge of CSBI Calculation of serial interface time for sequence above: Number of devices in stack= N Number of bytes in sequence = B = 1 command byte and 6 data bytes per device = 1+6*N Serial port frequency per bit = F Time = (1/F) * B * 8 bits/byte = (1/F) * (1+6*N) * 8 Time for 3-cell example above, with 1MHz serial port = (1/1000000) * (1+6*3)*8 = 152us Read Cell Voltage Registers (12 Cell Mode) 1. 2. 3. 4. 5. 6. Pull CSBI low Send RDCV command byte Read CVR00 byte of bottom device, then CVR01 (B), CVR02 (B), … CVR17 (B), and then PEC (B) Read CVR00 byte of middle device, then CVR01 (M), CVR02 (M), … CVR17 (M), and then PEC (M) Read CVR00 byte for top device, then CVR01 (T), CVR02 (T), … CVR17 (T), and then PEC (T) Pull CSBI high Calculation of serial interface time for sequence above: Number of devices in stack= N Number of bytes in sequence = B = 1 command byte, and 18 data bytes plus 1 PEC byte per device = 1+19*N Serial port frequency per bit = F Time = (1/F) * B * 8 bits/byte = (1/F) * (1+19*N) * 8 Time for 3-cell example above, with 1MHz serial port = (1/1000000) * (1+19*3)*8 =464us Start Cell Voltage A/D Conversions and Poll Status (Toggle Polling) 1. 2. 3. 4. 5. Pull CSBI low Send STCVAD command byte (all devices in stack start A/D conversions simultaneously) SDO output from bottom device pulled low for approximately 12ms SDO output toggles at 1kHz rate, indicating conversions complete for all devices in daisy chain Pull CSBI high to exit polling 68021p 23 LTC6802-1 APPLICATIONS INFORMATION Poll Interrupt Status (Level Polling) 1. 2. 3. 4. Pull CSBI low Send PLINT command byte SDO output from bottom device pulled low if any device has an interrupt condition; otherwise, SDO high Pull CSBI high to exit polling FAULT PROTECTION Overview Care should always be taken when using high energy sources such as batteries. There are numerous ways that systems can be [mis-]configured when considering the assembly and service procedures that might affect a battery system during its useful lifespan. Table 13 shows the various situations that should be considered when planning protection circuitry. The first five scenarios are to be anticipated during production and appropriate protection is included within the LTC6802-1 device itself. Table 13. LTC6802-1 Failure Mechanism Effect Analysis SCENARIO EFFECT DESIGN MITIGATION Cell input open-circuit (random) Power-up sequence at IC inputs Clamp diodes at each pin to V+ & V– (within IC) provide alternate power-path. Cell input open-circuit (random) Differential input voltage overstress Zener diodes across each cell voltage input pair (within IC) limits stress. Top cell input connection loss (V+) Power will come from highest connected cell input or via data port fault current Bottom cell input connection loss (V–) Clamp diodes at each pin to V+ & V– (within IC) provide alternate power-path. Diode conduction at data ports will impair communication with higher-potential units. Power will come from lowest connected cell input or Clamp diodes at each pin to V+ & V– (within IC) provide alternate power-path. Diode conduction at data ports will impair via data port fault current communication with higher-potential units. Disconnection of a harness Loss of supply connection to the IC between a group of battery cells and the IC (in a system of stacked groups) Clamp diodes at each pin to V+ & V– (within IC) provide an alternate power-path if there are other devices (which can supply power) connected to the LTC6802-1. Diode conduction at data ports will impair communication with higher-potential units. Data link disconnection between stacked LTC6802-1 units. Break of "daisy chain" communication (no stress to ICs). Communication will be lost to devices above the disconnection. The devices below the disconnection are still able to communicate and perform all functions, however, the polling feature is disabled. If the watchdog timer is enabled, all units above the disconnection will enter standby mode within 2 seconds of disconnect. Discharge switches are disabled in standby mode. Cell-pack integrity, break between stacked units Daisy-chain voltage reversal up to full stack potential Use series protection diodes with top-port I/O connections during pack discharge (RS07J for up to 600V). Use isolated data link at bottom-most data port. Cell-pack integrity, break between stacked units Daisy-chain positive overstress during charging Add redundant current path link Cell-pack integrity, break within stacked unit Cell input reverse overstress during discharge Add parallel Schottky diodes across each cell for load-path redundancy. Diode and connections must handle full operating current of stack, will limit stress on IC Cell-pack integrity, break within stacked unit Cell input positive overstress during charge Add SCR across each cell for charge-path redundancy. SCR and connections must handle full charging current of stack, will limit stress on IC by selection of trigger Zener 68021p 24 LTC6802-1 APPLICATIONS INFORMATION Battery Interconnection Integrity The FMEA scenarios involving a break in the stack of battery cells are potentially the most damaging. In the case where the battery stack has a discontinuity between groupings of cells monitored by LTC6802-1 ICs, any load will force a large reverse potential on the daisy-chain connection. This situation might occur in a modular battery system during initial installation or a service procedure. The daisy chain ports are protected from the reverse potential in this scenario by external series high-voltage diodes required in the upper-port data connections as shown in Figure 11. During the charging phase of operation, this fault would lead to forward biasing of daisy-chain ESD clamps that would also lead to part damage. An alternative connection to carry current during this scenario will avoid this stress from being applied (Figure 11). unpredictable voltage clamping or current flow. Limiting the current flow at any pin to ±10mA will prevent damage to the IC. LTC6802-1 V+ SCKO C12 S12 SDOI C11 S11 ZCLAMP C10 CSBO S10 C9 S9 C8 S8 C7 − V SDO PROTECT AGAINST BREAK HERE OPTIONAL REDUNDANT CURRENT PATH S7 LTC6802-1 (NEXT HIGHER IN STACK) SDI ZCLAMP C6 S6 SCKI CSBI RS07J (3x) SDOI SCKO CSBO V+ LTC6802-1 (NEXT LOWER IN STACK) 68021 F11 Figure 11. Reverse-Voltage Protection for the Daisy-Chain (One Link Connection Shown) Internal Protection Diodes Each pin of the LTC6802-1 has protection diodes to help prevent damage to the internal device structures caused by external application of voltages beyond the supply rails as shown in Figure 12. The diodes shown are conventional silicon diodes with a forward breakdown voltage of 0.5V. The unlabeled zener diode structures have a reverse breakdown characteristic which initially breaks down at 12V then snaps back to a 7V clamping potential. The zener diodes labeled ZCLAMP are higher voltage devices with an initial reverse breakdown of 30V snapping back to 25V. The forward voltage drop of all zeners is 0.5V. Refer to this diagram in the event of C5 S5 CSBI C4 SDO S4 SDI C3 SCKI VMODE S3 ZCLAMP C2 GPIO2 S2 GPIO1 C1 WDTB S1 MMB – TOS V 68021 F12 Figure 12. Internal Protection Diodes Cell-Voltage Filtering The LTC6802-1 employs a sampling system to perform its analog-to-digital conversions and provides a conversion result that is essentially an average over the 0.5ms conversion window, provided there isn’t noise aliasing with respect to the delta-sigma modulator rate of 512kHz. This indicates that a lowpass filter with useful attenuation at 68021p 25 LTC6802-1 APPLICATIONS INFORMATION 500kHz may be beneficial. Since the delta-sigma integration bandwidth is about 1kHz, the filter corner need not be lower than this to assure accurate conversions. Series resistors of 100Ω may be inserted in the input paths without introducing meaningful measurement error, provided only external discharge switch FETs are being used. Shunt capacitors may be added from the cell inputs to V–, creating RC filtering as shown in Figure 13. Note that this filtering is not compatible with use of the internal discharge switches to carry current since this would induce settling errors at the time of conversion as any activated switches temporarily open to provide Kelvin mode cell sensing. As a discharge switch opens, cell wiring resistance will also form a small voltage step (recovery of the small IR drop), so keeping the frequency cutoff of the filter relatively high will allow adequate settling prior to the actual conversion. A guard time of about 60μs is provided in the ADC timing, so a 16kHz LP is optimal and offers about 30dB of noise rejection. No resistor should be placed in series with the V– pin. Because the supply current flows from the V– pin, any resistance on this pin could generate a significant conversion error for CELL1. LTC6802-1 100k VREG VREF VTEMP2 VTEMP1 NC V− 100k 100k NTC 1μF 1μF 100k NTC 68021 F14 Figure 14. Driving Thermistors Directly from VREF For sensors that require higher drive currents, a buffer op amp may be used as shown in Figure 15. Power for the sensor is actually sourced indirectly from the VREG pin in this case. Probe loads up to about 1mA maximum are supported in this configuration. Since VREF is shutdown during the LTC6802-1 idle and shutdown modes, the thermistor drive is also shut off and thus power dissipation minimized. Since VREG remains always on, the buffer op amp (LT6000 shown) is selected for its ultralow power consumption (10μA). + LTC6000 – C(n) 100Ω 100nF LTC6802-1 S(n) C(n – 1) 100Ω 100nF 68021 F13 VREG VREF VTEMP2 VTEMP1 NC V− Figure 13. Adding RC Filtering to the Cell Inputs (One Cell Connection Shown) 10k 10k 10k NTC 10k NTC 68021 F15 READING EXTERNAL TEMPERATURE PROBES Using Dedicated Inputs The LTC6802-1 includes two channels of ADC input, VTEMP1 and VTEMP2, that are intended to monitor thermistors (tempco about –4%/°C generally) or diodes (–2.2mV/°C typical) located within the cell array. Sensors can be powered directly from VREF as shown in Figure 14 (up to 60μA total). Figure 15. Buffering VREF for Higher-Current Sensors Expanding Probe Count The LTC6802-1 provides general purpose I/O pins, GPIO1 and GPIO2, that may be used to control multiplexing of several temperature probes. Using just one of the GPIO pins, the sensor count can double to four as shown in 68021p 26 LTC6802-1 APPLICATIONS INFORMATION Figure 16. Using both GPIO pins, up to eight sensor inputs can be supported. ADDING CALIBRATION AND FULL-STACK MEASUREMENTS Another method of multiple sensor support is possible without the use of any GPIO pins. If the sensors are PN diodes and several used in parallel, then the hottest diode will produce the lowest forward voltage and effectively establish the input signal to the VTEMP input(s). The hottest diode will therefore dominate the readout from the VTEMP inputs that the diodes are connected to. In this scenario, the specific location or distribution of heat is not known, but such information may not be important in practice. Figure 17 shows the basic concept. By adding multiplexing hardware, additional signals can be digitized by the CELL1 ADC channel. One useful signal to provide is a high-accuracy voltage reference, such as from an LT1461A-4. By periodic readings of this signal, host software can provide correction of the LTC6802-1 readings to improve the accuracy over that of the internal LTC6802-1 reference, and/or validate ADC operation. Another useful signal is a measure of the total stack potential. This provides a redundant operational measurement of the cells in the event of a malfunction in the normal acquisition process, or as a faster means of monitoring the entire stack potential. Figure 18 shows a means of providing both of these features. A resistor divider is used to provide a low-voltage representation of the full stack potential (C12 to C0 voltage) with MOSFETs that decouple the divider current under unneeded conditions. Other MOSFETs, in conjunction with an op amp having a shutdown mode, form a voltage selector that allows measurement of the normal cell1 potential (when GPIO1 is low) or a buffered MUX signal. When the MUX is active (GPIO1 is high), selection can be made between the reference (4.096V) or the full-stack voltage divider (GPOI2 set low will select the reference). During idle time when the LTC6802-1 WTB signal goes low, the external circuitry goes into a power down condition, reducing battery drain to a minimum. When not actively performing measurements, GPIO1 should be set low and GPIO2 should be set high to achieve the lowest power state for the configuration shown. In any of the sensor configurations shown, a full-scale cold readout would be an indication of a failed-open sensor connection to the LTC6802-1. LTC6802-1 SN74LVC1G3157 OR SIMILAR DEVICE GPIO1 100k 100k VREG VREF 100k NTC 100k 100k NTC VTEMP2 VTEMP1 NC V− 100k NTC 1μF 100k NTC 68021 F16 Figure 16. Expanding Sensor Count with Multiplexing 200k LTC6802-1 VREG VREF PROVIDING HIGH-SPEED OPTO-ISOLATION OF THE SPI DATA-PORT 200k VTEMP2 VTEMP1 NC V− 68021 F17 Figure 17. Using Diode Sensors as Hot-Spot Detectors Isolation techniques that are capable of supporting the 1Mbps data rate of the LTC6802-1 require more power on the isolated (battery) side than can be furnished by the VREG output of the LTC6802-1. To keep battery drain minimal, this means that a DC/DC function must be implemented along with a suitable data isolation circuit, such as shown in Figure 19. Here an optimal Avago 4-channel (3/1 bidirectional) opto-coupler is used, with a simple isolated supply generated by an LTC1693-2 configured as a 200kHz oscillator. The DC/DC function provides an unregulated 68021p 27 LTC6802-1 APPLICATIONS INFORMATION TP0610K CELL12 1M 2.2M 0 = REF_EN GPIO2 VSTACK12 0 = CELL1 GPIO1 WDTB 1M 1M LT1461A-4 10M 1M VREG 2N7002 LTC6802-1 1μF 90.9k 2N7002 DNC DNC VIN DNC SD VOUT GND DNC V− 4.096V 2.2μF C1 150Ω TP0610K + TP0610K TP0610K 100Ω VDD CH0 CH1 SEL SD LT1636 100nF TC4W53FU – CELL1 COM INH VEE VSS 1M 68021 F18 Figure 18. Providing Measurement of Calibration Reference and Full-Stack Voltage Through CELL1 Port 330Ω 3.57k 3.57k +5V_HOST 100k CSBI 3.57k 100k SDI CSBI TP0610K SDO 100k 330Ω SDI SCKI TP0610K 330Ω SCKI TP0610K VREG SDO 100nF 4.99k 249Ω LTC6802-1 GND_HOST ACSL-6410 ISOLATED VLOGIC BAT54S 1μF 1μF BAT54S 6• 4 V− VCC1 •1 3 PE68386 470pF 20k IN1 OUT1 GND1 33nF VCC2 IN2 OUT2 GND2 10k LTC1693-2 68021 F19 Figure 19. Providing an Isolated High-Speed Data Interface 68021p 28 LTC6802-1 APPLICATIONS INFORMATION logic voltage (~4V) to the opto-coupler isolated side, from energy provided by host-furnished 5V. This circuit provides totally galvanic isolation between the batteries and the host processor, with an insulation rating of 560V continuous, 2500V transient. PCB LAYOUT CONSIDERATIONS The VREG and VREF pins should be bypassed with a 1μF capacitor for best performance. The LTC6802-1 is capable of operation with as much as 60V between V+ and V–. Care should be taken on the PCB layout to maintain physical separation of traces at different potentials. The pinout of the LTC6802-1 was chosen to facilitate this physical separation. Figure 20 shows the DC voltage on each pin with respect to V– when twelve 3.6V battery cells are connected to the LTC6802-1. There is no more then 5.5V between any two adjacent pins. The package body is used to separate the highest voltage (43.5V) from the lowest voltage (0V). LTC6802-1 42.5V 42.5V 42.5V 43.2V 43.2V 43.2V 39.6V 39.6V 36V 36V 32.4V 32.4V 28.8V 28.8V 25.2V 25.2V 21.6V 21.6V 18V 18V 14.4V 14.4V CSBO SDOI SCKO V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 CSBI SDO SDI SCKI VMODE GPIO2 GPIO1 WDTB MMB TOS VREG VREF VTEMP2 VTEMP1 NC V− S1 C1 S2 C2 S3 C3 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 5.5V 3.1V 1.5V 1.5V 0V 0V 3.6V 3.6V 7.2V 7.2V 10.8V 10.8V ADVANTAGES OF DELTA-SIGMA ADCS The LTC6802-1 employs a delta sigma analog to digital converter for voltage measurement. The architecture of delta sigma converters can vary considerably, but the common characteristic is that the input is sampled many times over the course of a conversion and then filtered or averaged to produce the digital output code. In contrast, a SAR converter takes a single snapshot of the input voltage and then performs the conversion on this single sample. For measurements in a noisy environment, a delta sigma converter provides distinct advantages over a SAR converter. While SAR converters can have high sample rates, the fullpower bandwidth of a SAR converter is often greater than 1MHz, which means the converter is sensitive to noise out to this frequency. And many SAR converters have much higher bandwidths – up to 50MHz and beyond. It is possible to filter the input, but if the converter is multiplexed to measure several input channels a separate filter will be required for each channel. A low frequency filter cannot reside between a multiplexer and an ADC and achieve a high scan rate across multiple channels. Another consequence of filtering a SAR ADC is that any noise reduction gained by filtering the input cancels the benefit of having a high sample rate in the first place, since the filter will take many conversion cycles to settle. For a given sample rate, a delta sigma converter can achieve excellent noise rejection while settling completely in a single conversion – something that a filtered SAR converter cannot do. Noise rejection is particularly important in high voltage switching controllers, where switching noise will invariably be present in the measured voltage. Other advantages of delta sigma converters are that they are inherently monotonic, meaning they have no missing codes, and they have excellent DC specifications. 68021 F20 Figure 20. Typical Pin Voltages for 12 3.6V Cells 68021p 29 LTC6802-1 APPLICATIONS INFORMATION Converter Details Each conversion consists of two phases – an autozero phase and a measurement phase. The ADC is autozeroed at each conversion, greatly improving CMRR. The second half of the conversion is the actual measurement. Noise Rejection Figure 21 shows the frequency response of the ADC. The rolloff follows a Sinc2 response, with the first notch at 4kHz. Also shown is the response of a 1 pole, 850Hz filter (187μs time constant) which has the same integrated response to wideband noise as the LTC6802-1’s ADC, which is about 1350Hz. This means that if wideband noise is applied to the LTC6802-1 input, the increase in noise seen at the digital output will be the same as an ADC with a wide bandwidth (such as a SAR) preceded by a perfect 1350Hz brickwall lowpass filter. Thus if an analog filter is placed in front of a SAR converter to achieve the same noise rejection as the LTC6802-1 ADC, 0 FILTER GAIN (dB) The LTC6802-1’s ADC has a second order delta sigma modulator followed by a Sinc2, finite impulse response (FIR) digital filter. The front-end sample rate is 512ksps, which greatly reduces input filtering requirements. A simple 16kHz, 1 pole filter composed of a 100Ω resistor and a 0.1μF capacitor at each input will provide adequate filtering for most applications. These component values will not degrade the DC accuracy of the ADC. 10 –10 –20 –30 –40 –50 –60 10 100 1k 10k FREQUENCY (Hz) 100k 68021 F20 Figure 21. Noise Filtering of the LTC6802-1 ADC the SAR will have a slower response to input signals. For example, a step input applied to the input of the 850Hz filter will take 1.55ms to settle to 12 bits of precision, while the LTC6802-1 ADC settles in a single 1ms conversion cycle. This also means that very high sample rates do not provide any additional information because the analog filter limits the frequency response. While higher order active filters may provide some improvement, their complexity makes them impractical for high-channel count measurements as a single filter would be required for each input. Also note that the Sinc2 response has a 2nd order rolloff envelope, providing an additional benefit over a single pole analog filter. 68021p 30 LTC6802-1 PACKAGE DESCRIPTION G Package 44-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1754 Rev Ø) 12.50 – 13.10* (.492 – .516) 1.25 ±0.12 7.8 – 8.2 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 5.3 – 5.7 7.40 – 8.20 (.291 – .323) 0.50 BSC 0.25 ±0.05 RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 – 5.60* (.197 – .221) PARTING LINE 0.10 – 0.25 (.004 – .010) 2.0 (.079) MAX 1.65 – 1.85 (.065 – .073) 0° – 8° 0.55 – 0.95** (.022 – .037) 1.25 (.0492) REF NOTE: 1.DRAWING IS NOT A JEDEC OUTLINE 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSIONS ARE IN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 MILLIMETERS (INCHES) 4. DRAWING NOT TO SCALE 5. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.08mm AT SEATING PLANE 0.50 (.01968) BSC SEATING PLANE 0.20 – 0.30† (.008 – .012) TYP 0.05 (.002) MIN G44 SSOP 0607 REV Ø *DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS, BUT DO INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH SHALL NOT EXCEED .15mm PER SIDE **LENGTH OF LEAD FOR SOLDERRING TO A SUBSTRATE †THE MAXIMUM DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSIONS DO NOT EXCEED 0.13mm PER SIDE 68021p Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LTC6802-1 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC6802-2 Multicell Battery Stack Monitor with Parallel Addressed Serial Interface Functionality equivalent to LTC6802-1, Allows for Individually Addressable Battery Stack Topologies 68021p 32 Linear Technology Corporation LT 0808 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008