INTERSIL ISL28107FRTZ-T7A

ISL28107, ISL28207, ISL28407
Features
The ISL28107, ISL28207 and ISL28407 are single, dual
and quad amplifiers featuring low noise, low input bias
current, and low offset and temperature drift. This makes
them the ideal choice for applications requiring both high
DC accuracy and AC performance. The combination of
precision, low noise, and small footprint provides the
user with outstanding value and flexibility relative to
similar competitive parts.
• Low Input Offset . . . . . . . . . . . . . . . . 75µV, Max.
• Input Bias Current . . . . . . . . . . . . . . . . . . . .15pA
• Superb Temperature Drift
- Voltage Offset . . . . . . . . . . . . . 0.65µV/°C, Max.
- Input Current . . . . . . . . . . . . . . . 0.9pA/°C, Max
• Outstanding ESD performance
- Human Body Model . . . . . . . . . . . . . . . . . 4.5kV
- Machine Model . . . . . . . . . . . . . . . . . . . . .500V
- Charged Device Model . . . . . . . . . . . . . . . 1.5kV
• Very Low Voltage Noise, 10Hz . . . . . . . . 14nV/√Hz
• Low Current Consumption (per amp). . . . 0.29mA, Max.
• Gain-bandwidth Product . . . . . . . . . . . . . . . 1MHz
• Wide Supply Range. . . . . . . . . . . . . . . 4.5V to 40V
• Operating Temperature Range . . . -40°C to +125°C
• No Phase Reversal
• Pb-Free (RoHS Compliant)
Applications for these amplifiers include precision active
filters, medical and analytical instrumentation, precision
power supply controls, and industrial controls.
The ISL28107 is available in an 8 Ld SOIC, MSOP and
TDFN package. The ISL28207 is available in the 8 Ld
SOIC and MSOP packages. The ISL28407 will be offered
in an 14 Ld SOIC, TSSOP and 16 Ld QFN packages. All
devices are offered in standard pin configurations and
operate over the extended temperature range to -40°C
to +125°C.
Related Literature*(see page 26)
Applications*(see page 26)
•
•
•
•
•
•
•
•
Precision Instruments
Medical Instrumentation
Spectral Analysis Equipment
Active Filter Blocks
Microphone Pre-amplifier
Thermocouples and RTD Reference Buffers
Data Acquisition
Power Supply Control
Typical Application
• See AN1508 “ISL281X7SOICEVAL1Z Evaluation
Board User’s Guide”
• See AN1509 “ISL282X7SOICEVAL2Z Evaluation
Board User’s Guide”
Input Noise Voltage Spectral
Density
C1
V+
VIN
R1
OUTPUT
R2
+
19.1k 48.7k
3.3nF
C2
V-
Sallen-Key Low Pass Filter (1kHz)
INPUT NOISE VOLTAGE (nV/√Hz)
1000
8.2nF
V+ = ±19V
AV = 1
100
10
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
September 9, 2010
FN6631.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL28107, ISL28207, ISL28407
Precision Single, Dual and Quad Low Noise
Operational Amplifiers
ISL28107, ISL28207, ISL28407
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL28107FBZ
28107 FBZ
-40 to +125
8 Ld SOIC
M8.15E
ISL28107FBZ-T7 (Note 1)
28107 FBZ
-40 to +125
8 Ld SOIC
M8.15E
ISL28107FBZ-T13 (Note 1)
28107 FBZ
-40 to +125
8 Ld SOIC
M8.15E
ISL28107FBZ-T7A (Note 1)
28107 FBZ
-40 to +125
8 Ld SOIC
M8.15E
ISL28107FUZ
8107Z
-40 to +125
8 Ld MSOP
M8.118
ISL28107FUZ-T7 (Note 1)
8107Z
-40 to +125
8 Ld MSOP
M8.118
ISL28107FUZ-T13 (Note 1)
8107Z
-40 to +125
8 Ld MSOP
M8.118
ISL28107FUZ-T7A (Note 1)
8107Z
-40 to +125
8 Ld MSOP
M8.118
ISL28107FRTZ
107Z
-40 to +125
8 Ld TDFN
L8.3x3A
ISL28107FRTZ-T7 (Note 1)
107Z
-40 to +125
8 Ld TDFN
L8.3x3A
ISL28107FRTZ-T13 (Note 1)
107Z
-40 to +125
8 Ld TDFN
L8.3x3A
ISL28107FRTZ-T7A (Note 1)
107Z
-40 to +125
8 Ld TDFN
L8.3x3A
ISL28207FBZ
28207 FBZ
-40 to +125
8 Ld SOIC
M8.15E
ISL28207FBZ-T7 (Note 1)
28207 FBZ
-40 to +125
8 Ld SOIC
M8.15E
ISL28207FBZ-T13 (Note 1)
28207 FBZ
-40 to +125
8 Ld SOIC
M8.15E
ISL28207FBZ-T7A (Note 1)
28207 FBZ
-40 to +125
8 Ld SOIC
M8.15E
ISL28207FRTZ
207Z
-40 to +125
8 Ld TDFN
L8.3x3A
ISL28207FRTZ-T7 (Note 1)
207Z
-40 to +125
8 Ld TDFN
L8.3x3A
ISL28207FRTZ-T13 (Note 1)
207Z
-40 to +125
8 Ld TDFN
L8.3x3A
ISL28207FRTZ-T7A (Note 1)
207Z
-40 to +125
8 Ld TDFN
L8.3x3A
Coming Soon
ISL28407FBZ
28407
-40 to +125
14 Ld SOIC
M14.15
Coming Soon
ISL28407FBZ-T7A (Note 1)
28407
-40 to +125
14 Ld SOIC
M14.15
Coming Soon
ISL28407FVZ (Note 1)
28407
-40 to +125
14 Ld TSSOP
M14.173
Coming Soon
ISL28407FVZ-T13 (Note 1)
28407
-40 to +125
14 Ld TSSOP
M14.173
Coming Soon
ISL28407FVZ-T7A (Note 1)
28407
-40 to +125
14 Ld TSSOP
M14.173
Coming Soon
ISL28407FRZ
28407
-40 to +125
16 Ld QFN
L16.4x4
Coming Soon
ISL28407FRZ-T13 (Note 1)
28407
-40 to +125
16 Ld QFN
L16.4x4
Coming Soon
ISL28407FRZ-T7A (Note 1)
28407
-40 to +125
16 Ld QFN
L16.4x4
ISL28107SOICEVAL1Z
Evaluation Board
ISL28207SOICEVAL2Z
Evaluation Board
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28107, ISL28207 and ISL28407. For more
information on MSL please see techbrief TB363.
2
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
Pin Configurations
ISL28107
(8 LD TDFN)
TOP VIEW
ISL28107
(8 LD SOIC, MSOP)
TOP VIEW
1
-IN
2
-+
8
NC
NC 1
7
V+
-IN 2
+IN 3
6
VOUT
V- 4
5
NC
8 NC
+IN 3
6 VOUT
5 NC
V- 4
ISL28207
(8 LD TDFN)
TOP VIEW
ISL28207
(8 LD SOIC)
TOP VIEW
VOUTA
1
-IN_A
2
+IN_A
3
V-
4
8
- +
+ -
V+
7
VOUTB
6
-IN_B
5
+IN_B
VOUT_A 1
8 V+
-IN_A 2
+IN_A 3
5 +IN_B
V- 4
ISL28407
(16 LD QFN)
TOP VIEW
NC
VOUT_A
VOUT_D
NC
12 +IN_D
16
15
14
13
- +
B
+ C
9 -IN_C
+IN_A
2
V+
3
+IN_B
4
+ -
3
D
A
8 VOUT_C
VOUT_B 7
12 -IN_D
1
11 +IN_D
10
V-
9
+IN_C
C
B
5
6
7
8
-IN_C
10 +IN_C
+IN_B 5
-IN_A
VOUT_C
V-
VOUT_B
11
- +
V+ 4
- +
D
+ -
+IN_A 3
-IN_B 6
13 -IN_D
14 VOUT_D
A
- +
6 -IN_B
+ -
-IN_B
-IN_A 2
7 VOUT_B
- +
ISL28407
(14 LD SOIC, TSSOP)
TOP VIEW
VOUT_A 1
7 V+
- +
+ -
NC
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
Pin Descriptions
ISL28407
(14 LD SOIC,
TSSOP)
ISL28207
ISL28107
(8 LD SOIC, (8 LD SOIC,
TDFN)
MSOP, TDFN)
ISL28407
(16 LD QFN)
PIN
NAME
EQUIVALENT
CIRCUIT
Circuit 1
Amplifier non-inverting input
DESCRIPTION
3
-
-
-
+IN
-
3
3
2
+IN_A
-
5
5
4
+IN_B
-
-
10
9
+IN_C
-
-
12
11
+IN_D
4
4
11
10
V-
Circuit 3
Negative power supply
Circuit 1
Amplifier inverting input
2
-
-
-
-IN
-
2
2
1
-IN_A
-
6
6
5
-IN_B
-
-
9
8
-IN_C
-
-
13
12
-IN_D
7
8
4
3
V+
Circuit 3
Positive power supply
Circuit 2
Amplifier output
6
-
-
-
VOUT
-
1
1
15
VOUT_A
-
7
7
6
VOUT_B
-
-
8
7
VOUT_C
-
-
14
14
VOUT_D
1, 5, 8
-
-
13, 16
NC
-
No internal connection
PD
PD
-
PD
PD
-
Thermal Pad - TDFN and QFN
packages only. Connect thermal pad
to ground or most negative
potential.
IN-
500Ω
V+
V+
IN+
OUT
500Ω
V+
CAPACITIVELY
TRIGGERED
V-
V-
CIRCUIT 1
CIRCUIT 2
4
VCIRCUIT 3
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
Table of Contents
Absolute Maximum Ratings ................................................................................................................ 6
Thermal Information .......................................................................................................................... 6
Operating Conditions .......................................................................................................................... 6
Electrical Specifications. ..................................................................................................................... 6
Electrical Specifications ...................................................................................................................... 8
Typical Performance Curves ............................................................................................................. .10
Applications Information ................................................................................................................... 19
Functional Description......................................................................................................................
Operating Voltage Range..................................................................................................................
Input ESD Diode Protection ..............................................................................................................
Output Current Limiting ...................................................................................................................
Output Phase Reversal.....................................................................................................................
Using Only One Channel...................................................................................................................
Power Dissipation............................................................................................................................
ISL28107, ISL28207, ISL28407 SPICE Model ......................................................................................
License Statement...........................................................................................................................
19
19
19
19
19
19
19
20
20
Characterization vs Simulation Results.............................................................................................. 23
Revision History ................................................................................................................................ 25
Products ............................................................................................................................................ 26
Package Outline Drawing ................................................................................................................. 27
Package Outline Drawing ................................................................................................................. 28
Package Outline Drawing ................................................................................................................. 29
Package Outline Drawing ................................................................................................................. 30
Package Outline Drawing ................................................................................................................. 31
Package Outline Drawing ................................................................................................................. 32
5
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
Absolute Maximum Ratings
Thermal Information
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 42V
Maximum Differential Input Current . . . . . . . . . . . . . 20mA
Maximum Differential Input Voltage . . . (V-) - 0.5V to (V+) + 0.5V
Min/Max Input Voltage . . . . . . . . (V-) - 0.5V to (V+) + 0.5V
Max/Min Input Current for Input Voltage >V+ or <V- . . . . ±20mA
Output Short-Circuit Duration (1 Output at a Time) . . . Indefinite
ESD Tolerance
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . 4.5kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . 1.5kV
Thermal Resistance (Typical)
θJA (°C/W)
θJC (°C/W)
8 Ld SOIC (ISL28107, Notes 4, 5) . . .
120
60
8 Ld SOIC (ISL28207, Notes 4, 5) . . .
105
50
8 Ld MSOP (ISL28107, Notes 4, 5) . .
155
50
8 Ld TDFN (ISL28107, Notes 6, 7) .
48
7
8 Ld TDFN (ISL28207, Notes 6, 7) .
43
2
14 Ld SOIC (ISL28407) . . . . . . . .
TBD
TBD
14 Ld TSSOP (ISL28407) . . . . . . .
TBD
TBD
16 Ld QFN (ISL28407) . . . . . . . . .
TBD
TBD
Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Ambient Operating Temperature Range. . . . -40°C to +125°C
Maximum Operating Junction Temperature . . . . . . . +150°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
5. For θJC, the “case temp” location is taken at the package top center.
6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
7. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless
otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits
apply over the operating temperature range, -40°C to +125°C. Temperature data
established by characterization.
PARAMETER
VOS
DESCRIPTION
CONDITIONS
Offset Voltage Magnitude;
SOIC Package
TYP
MAX
(Note 8)
UNIT
-75
5
75
µV
140
µV
100
µV
180
µV
100
µV
190
µV
100
µV
175
µV
-140
Offset Voltage Magnitude;
MSOP Package
Offset Voltage Magnitude;
TDFN Package
MIN
(Note 8)
-100
5
-180
ISL28107
-100
10
-190
ISL28207
-100
10
-175
TCVOS
Offset Voltage Drift; SOIC
Package
-0.65
0.1
0.65
µV/°C
Offset Voltage Drift; MSOP
Package
-0.85
0.1
0.85
µV/°C
ISL28107
-0.9
0.1
0.9
µV/°C
ISL28207
-0.75
0.1
0.75
µV/°C
TA = -40°C to +85°C
-300
15
300
pA
TA = -40°C to +125°C
-600
600
pA
Offset Voltage Drift; TDFN
Package
IB
Input Bias Current
6
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits
apply over the operating temperature range, -40°C to +125°C. Temperature data
established by characterization. (Continued)
PARAMETER
TCIB
IOS
TCIOS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNIT
TA = -40°C to +85°C
-0.9
0.19
0.9
pA/°C
TA = -40°C to +125°C
-3.5
0.26
3.5
pA/°C
TA = -40°C to +85°C
-300
15
300
pA
TA = -40°C to +125°C
-600
600
pA
TA = -40°C to +85°C
-0.9
0.19
0.9
pA/°C
TA = -40°C to +125°C
-3.5
0.26
3.5
pA/°C
13
V
DESCRIPTION
Input Bias Current Drift
Input Offset Current
Input Offset Current Drift
CONDITIONS
VCM
Input Voltage Range
Guaranteed by CMRR test
-13
CMRR
Common-Mode Rejection
Ratio
VCM = -13V to +13V
115
145
dB
PSRR
Power Supply Rejection Ratio VS = ±2.25V to ±20V
115
145
dB
AVOL
Open-Loop Gain
VO = -13V to +13V, RL = 10kΩ to ground
3,000
40,000
V/mV
VOH
Output Voltage High
RL = 10kΩ to ground
13.5
13.7
V
13.2
RL = 2kΩ to ground
13.3
V
13.55
V
13.1
VOL
Output Voltage Low
RL = 10kΩ to ground
-13.7
RL = 2kΩ to ground
IS
Supply Current/Amplifier
-13.55
RL = Open
ISC
Output Short-Circuit Current (Note 9)
VSUPPLY
Supply Voltage Range
Guaranteed by PSRR
V
0.21
-13.5
V
-13.2
V
-13.3
V
-13.1
V
0.29
mA
0.35
mA
±40
±2.25
mA
±20
V
AC SPECIFICATIONS
GBW
Gain Bandwidth Product
1
MHz
enp-p
Voltage Noise
0.1Hz to 10Hz, VS = ±19V
340
nVP-P
en
Voltage Noise Density
f = 10Hz, VS = ±19V
14
nV/√Hz
en
Voltage Noise Density
f = 100Hz, VS = ±19V
13
nV/√Hz
en
Voltage Noise Density
f = 1kHz, VS = ±19V
13
nV/√Hz
en
Voltage Noise Density
f = 10kHz, VS = ±19V
13
nV/√Hz
in
Current Noise Density
f = 10kHz, VS = ±19V
53
fA/√Hz
THD + N
Total Harmonic Distortion +
Noise
1kHz, G = 1, VO = 3.5VRMS,
RL = 2kΩ
0.0035
%
±0.32
V/µs
TRANSIENT RESPONSE
SR
Slew Rate
AV = 10, RL = 10kΩ, VO = 10VP-P
tr, tf, Small
Signal
Rise Time
10% to 90% of VOUT
AV = 1, VOUT = 100mVP-P, Rf = 0Ω,
RL = 2kΩ to VCM
355
ns
Fall Time
90% to 10% of VOUT
AV = 1, VOUT = 100mVP-P, Rf = 0Ω, RL = 2kΩ
to VCM
365
ns
7
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits
apply over the operating temperature range, -40°C to +125°C. Temperature data
established by characterization. (Continued)
PARAMETER
ts
tOL
DESCRIPTION
VOS
MIN
(Note 8)
TYP
29
µs
Settling Time to 0.01%
10V Step; 10% to VOUT
AV = -1, VOUT = 10VP-P, Rg = Rf =10k,
RL = 2kΩ to VCM
31.2
µs
Output Overload Recovery
Time
AV = 100, VIN = 0.2V, RL = 2kΩ to VCM
6
µs
VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply
over the operating temperature range, -40°C to +125°C. Temperature data
established by characterization.
DESCRIPTION
CONDITIONS
Offset Voltage Magnitude;
SOIC Package
Offset Voltage Magnitude;
TDFN Package
MIN
(Note 8)
TYP
MAX
(Note 8)
UNIT
-75
5
75
µV
140
µV
100
µV
180
µV
100
µV
190
µV
100
µV
175
µV
-140
-100
5
-180
ISL28107
-100
10
-190
ISL28207
-100
10
-175
Offset Voltage Drift; SOIC
Package
-0.65
0.1
0.65
µV/°C
Offset Voltage Drift; MSOP
Package
-0.85
0.1
0.85
µV/°C
ISL28107
-0.9
0.1
0.9
µV/°C
ISL28207
-0.75
0.1
0.75
µV/°C
TA = -40°C to +85°C
-300
15
300
pA
TA = -40°C to +125°C
-600
600
pA
TA = -40°C to +85°C
-0.9
0.19
0.9
pA/°C
TA = -40°C to +125°C
-3.5
0.26
3.5
pA/°C
TA = -40°C to +85°C
-300
15
300
pA
TA = -40°C to +125°C
-600
600
pA
TA = -40°C to +85°C
-0.9
0.19
0.9
pA/°C
TA = -40°C to +125°C
-3.5
0.26
3.5
pA/°C
3
V
Offset Voltage Drift; TDFN
Package
IB
TCIB
IOS
TCIOS
UNIT
AV = -1 VOUT = 10VP-P, Rg = Rf =10k,
RL = 2kΩ to VCM
Offset Voltage Magnitude;
MSOP Package
TCVOS
MAX
(Note 8)
Settling Time to 0.1%
10V Step; 10% to VOUT
Electrical Specifications
PARAMETER
CONDITIONS
Input Bias Current
Input Bias Current Drift
Input Offset Current
Input Offset Current Drift
VCM
Common Mode Input Voltage
Range
Guaranteed by CMRR test
CMRR
Common-Mode Rejection
Ratio
VCM = -3V to +3V
115
145
dB
PSRR
Power Supply Rejection Ratio
VS = ±2.25V to ±5V
115
145
dB
AVOL
Open-Loop Gain
VO = -3V to +3V, RL = 10kΩ to ground
3,000
40,000
V/mV
8
-3
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
Electrical Specifications
PARAMETER
VOH
VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply
over the operating temperature range, -40°C to +125°C. Temperature data
established by characterization. (Continued)
DESCRIPTION
Output Voltage High
CONDITIONS
RL = 10kΩ to ground
MIN
(Note 8)
TYP
3.5
3.7
MAX
(Note 8)
V
3.2
RL = 2kΩ to ground
3.3
V
3.55
V
3.1
VOL
Output Voltage Low
RL = 10kΩ to ground
RL = 2kΩ to ground
IS
ISC
Supply Current/Amplifier
Output Short-Circuit Current
RL = Open
(Note 9)
UNIT
V
-3.7
-3.55
0.21
-3.5
V
-3.2
V
-3.3
V
-3.1
V
0.29
mA
0.35
mA
± 40
mA
1
MHz
0.0053
%
AC SPECIFICATIONS
GBW
Gain Bandwidth Product
THD + N
Total Harmonic Distortion +
Noise
1kHz, G = 1, VO = 2.5VRMS, RL = 2kΩ
TRANSIENT RESPONSE
SR
Slew Rate
AV = 10, RL = 2kΩ
0.32
V/µs
tr, tf, Small
Signal
Rise Time
10% to 90% of VOUT
AV = 1, VOUT = 100mVP-P, Rf = 0Ω,
RL = 2kΩ to VCM
355
ns
Fall Time
90% to 10% of VOUT
AV = 1, VOUT = 100mVP-P, Rf = 0Ω,
RL = 2kΩ to VCM
370
ns
Settling Time to 0.1%
4V Step; 10% to VOUT
AV = -1, VOUT = 4VP-P, Rf = Rg = 2kΩ,
RL = 2kΩ to VCM
12.4
µs
Settling Time to 0.01%
4V Step; 10% to VOUT
AV = -1, VOUT = 4VP-P, Rf = Rg = 2kΩ,
RL = 2kΩ to VCM
22
µs
ts
NOTES:
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
9. Output Short Circuit Current is the minimum current (source or sink) when the output is driven into the supply rails with
RL = 0Ω to ground.
9
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, TA = +25°C unless otherwise
specified.
30
30
VS = ±5V
20
20
10
10
Vos (µV)
Vos (µV)
VS = ±15V
0
0
-10
-10
-20
-20
-30
-50
0
50
TEMPERATURE (°C)
100
-30
-50
150
0
50
TEMPERATURE (°C)
100
FIGURE 2. INPUT OFFSET VOLTAGE vs
TEMPERATURE, VS = ±5V
FIGURE 1. INPUT OFFSET VOLTAGE vs
TEMPERATURE, VS = ±15V
1400
1400
VS = ±5V
1200
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
VS = ±15V
1000
800
600
400
200
0
-100 -80
-60
-40
-20
0
20
VOS (µV)
40
60
80
1200
1000
800
600
400
200
0
-100
100
FIGURE 3. INPUT OFFSET VOLTAGE DISTRIBUTION,
VS = ±15V
-80
-60
-40
-20
0
20
VOS (µV)
40
60
100
16
VS = ±5V
VS = ±15V
14
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
80
FIGURE 4. INPUT OFFSET VOLTAGE DISTRIBUTION,
VS = ±5V
16
12
10
8
6
4
14
12
10
8
6
4
2
2
0
-0.45
150
-0.30
-0.15
0
0.15
TCVOS (µV/°C)
0.30
0.45
FIGURE 5. TCVOS vs NUMBER OF AMPLIFIERS,
VS = ±15V
10
0
-0.45
-0.30
-0.15
0
0.15
TCVOS (µV/°C)
0.30
0.45
FIGURE 6. TCVOS vs NUMBER OF AMPLIFIERS,
VS = ±5V
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, TA = +25°C unless otherwise
specified. (Continued)
200
200
VS = ± 5V
VS = ±15V
100
Ib+ (pA)
Ib+ (pA)
100
0
-100
0
-100
-200
-50
-25
0
25
50
75
100
125
-200
-50
150
-25
0
25
50
75
TEMPERATURE (°C)
TEMPERATURE (°C)
100
125
FIGURE 8. POSITIVE BIAS CURRENT vs
TEMPERATURE, VS = ±5V
FIGURE 7. POSITIVE BIAS CURRENT vs
TEMPERATURE, VS = ±15V
80
80
VS = ±5V
70
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
VS = ±15V
60
50
40
30
20
10
0
70
60
50
40
30
20
10
-1.8
-1.4
-1.0
-0.6
-0.2
0.2
TCIb+ (pA/°C)
0.6
0
1.0
FIGURE 9. TCIb+ vs NUMBER OF AMPLIFIERS,
VS = ±15V
-1.8
-1.4
-1.0
-0.6
-0.2
0.2
TCIb+ (pA/°C)
0.6
200
Vs = ± 5V
VS = ± 15V
100
Ib- (pA)
100
0
0
-100
-100
-200
-50
1.0
FIGURE 10. TCIb+ vs NUMBER OF AMPLIFIERS,
VS = ±5V
200
Ib- (pA)
150
-25
0
25
50
75
TEMPERATURE (°C)
100
FIGURE 11. NEGATIVE BIAS CURRENT vs
TEMPERATURE, VS = ±15V
11
125
150
-200
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
125
150
FIGURE 12. NEGATIVE BIAS CURRENT vs
TEMPERATURE, VS = ±5V
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
Typical Performance Curves
100
80
VS = ±5V
NUMBER OF AMPLIFIERS
90
NUMBER OF AMPLIFIERS
VS = ±15V, VCM = 0V, RL = Open, TA = +25°C unless otherwise
specified. (Continued)
80
70
60
50
40
30
20
60
50
40
30
20
10
10
0
VS = ±15V
70
-1.8
-1.4
-1.0
-0.6
-0.2
0.2
TCIb- (pA/°C)
0.6
0
1.0
-1.8
-1.4
-1.0
-0.6
-0.2
0.2
TCIb- (pA/°C)
0.6
FIGURE 14. TCIb- vs NUMBER OF AMPLIFIERS,
VS = ±15V
FIGURE 13. TCIb- vs NUMBER OF AMPLIFIERS,
VS = ±5V
200
200
VS = ±5V
150
150
100
100
50
50
IOS (pA)
IOS (pA)
VS = ±15V
0
-50
-50
-100
-150
-150
-200
-50
0
50
TEMPERATURE (°C)
100
-200
-50
150
FIGURE 15. OFFSET CURRENT vs TEMPERATURE,
VS = ±15V
0
50
TEMPERATURE (°C)
100
150
FIGURE 16. OFFSET CURRENT vs TEMPERATURE,
VS = ±5V
50
50
VS = ±15V
40
35
30
25
20
15
10
5
VS = ±5V
45
NUMBER OF AMPLIFIERS
45
NUMBER OF AMPLIFIERS
0
-100
0
1.0
40
35
30
25
20
15
10
5
-0.7
-0.5
-0.3
-0.1
0.1
0.3
TCIOS (pA/°C)
0.5
0.7
FIGURE 17. TCIOS- vs NUMBER OF AMPLIFIERS,
VS = ±15V
12
0
-0.7
-0.5
-0.3
-0.1
0.1
0.3
TCIOS (pA/°C)
0.5
0.7
FIGURE 18. TCIOS- vs NUMBER OF AMPLIFIERS,
VS = ±5V
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, TA = +25°C unless otherwise
specified. (Continued)
180
180
Vcm = ±13V
VS = ± 2.25V TO ± 20V
PSRR (dB)
CMRR (dB)
160
160
140
140
120
120
-50
0
50
TEMPERATURE (°C)
100
100
-50
150
0
50
100
TEMPERATURE (°C)
FIGURE 20. PSRR vs TEMPERATURE
FIGURE 19. CMRR vs TEMPERATURE
63000
14.4
Vs = ±15V
RL = 10kΩ
53000
14.2
43000
14.0
VOH (V)
AVOL (V/mV)
VO = ±13V
33000
13.8
23000
13.6
13000
13.4
3000
-50
0
50
TEMPERATURE (°C)
100
13.2
-50
150
FIGURE 21. AVOL vs TEMPERATURE
-13.2
14.4
100
150
14.0
VOH (V)
VOL (V)
50
TEMPERATURE (°C)
VS = ±15V
RL = 2kΩ
14.2
-13.6
-13.8
13.8
-14.0
13.6
-14.2
13.4
-14.4
-50
0
FIGURE 22. VOH vs TEMPERATURE, VS = ±15V,
RL = 10kΩ
VS = ±15V
RL = 10kΩ
-13.4
150
0
50
100
TEMPERATURE (°C)
FIGURE 23. VOL vs TEMPERATURE, VS = ±15V,
RL = 10kΩ
13
150
13.2
-50
0
50
100
TEMPERATURE (°C)
150
FIGURE 24. VOH vs TEMPERATURE, VS = ±15V,
RL = 2kΩ
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
Typical Performance Curves
-13.2
VS = ±15V, VCM = 0V, RL = Open, TA = +25°C unless otherwise
specified. (Continued)
4.4
VS = ±15V
RL = 2kΩ
-13.4
4.2
4.0
VOH (V)
VOL (V)
-13.6
-13.8
3.8
-14.0
3.6
-14.2
3.4
-14.4
-50
VS = ±5V
RL = 10kΩ
0
50
100
TEMPERATURE (°C)
50
TEMPERATURE (°C)
100
150
0.40
VS = ±5V
RL = 10kΩ
-3.4
0
FIGURE 26. VOH vs TEMPERATURE, VS = ±5V,
RL = 10kΩ
FIGURE 25. VOL vs TEMPERATURE, VS = ±15V,
RL = 2kΩ
-3.2
3.2
-50
150
0.35
±15V
0.30
IS (mA)
VOL (V)
-3.6
-3.8
±2.25V
0.25
-4.0
0.20
-4.2
0.15
-4.4
-50
0
50
TEMPERATURE (°C)
100
150
FIGURE 27. VOL vs TEMPERATURE, VS = ±5V,
RL = 10kΩ
0.10
-50
50
50
45
45
ISC- (mA)
ISC+ (mA)
55
40
35
40
35
30
30
25
25
100
150
FIGURE 29. POSITIVE SHORT CIRCUIT CURRENT vs
TEMPERATURE
14
150
ISC- @ ±15V
55
50
TEMPERATURE (°C)
100
60
ISC+ @ ±15V
0
50
TEMPERATURE (°C)
FIGURE 28. SUPPLY CURRENT vs TEMPERATURE
60
20
-50
0
20
-50
0
50
TEMPERATURE (°C)
100
150
FIGURE 30. NEGATIVE SHORT CIRCUIT CURRENT vs
TEMPERATURE
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, TA = +25°C unless otherwise
specified. (Continued)
1000
INPUT NOISE VOLTAGE (nV/√Hz)
INPUT NOISE VOLTAGE (nV)
200
150
100
50
0
-50
-100
V+ = ±19V
RL = INF, CL = 4pF
Rg = 10, Rf = 100k
AV = 10,000
-150
-200
0
1
2
3
4
5
6
7
8
9
V+ = ±19V
AV = 1
100
10
0.1
10
1
10
FIGURE 31. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz
10k
100k
100
80
PSRR- VS = ±5V, VS = ±15V
60
PSRR (dB)
INPUT NOISE CURRENT (pA/√Hz)
1k
FIGURE 32. INPUT NOISE VOLTAGE SPECTRAL
DENSITY
1
0.1
V+ = ±19V
AV = 1
0.01
0.1
1
10
100
1k
10k
100k
40
20 R = INF
L
CL = 4pF
0 AV = +1
VSOURCE = 1VP-P PSRR+ VS = ±5V, VS = ±15V
-20
10
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 34. PSRR vs FREQUENCY, VS = ±5V, ±15V
160
60
RL = INF
CL = 4pF
AV = +1
VCM = 1VP-P
140
120
40
+125°C
20
VOS (µV)
100
80
60
+25°C
0
-20
-40°C
40
-40
20
0
0.1
1M
FREQUENCY (Hz)
FIGURE 33. INPUT NOISE CURRENT SPECTRAL
DENSITY
CMRR (dB)
100
FREQUENCY (Hz)
TIME (s)
VS = ±2.25V, ±5V, ±15V
1
10
100
1k
10k
100k
1M
10M 100M
FREQUENCY (Hz)
FIGURE 35. CMRR vs FREQUENCY, VS = ±2.25, ±5V,
±15V
15
-60
-15
-10
-5
0
5
10
15
INPUT COMMON MODE VOLTAGE
FIGURE 36. INPUT OFFSET VOLTAGE vs INPUT
COMMON MODE VOLTAGE, VS = ±15V
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
VS = ±15V, VCM = 0V, RL = Open, TA = +25°C unless otherwise
specified. (Continued)
200
180
160
140
PHASE
120
100
80
60
40
20
GAIN
0
-20 R = 10k
L
-40
CL = 10pF
-60
SIMULATION
-80
-100
0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1M 10M 100M
OPEN LOOP GAIN (dB)/PHASE (°)
OPEN LOOP GAIN (dB)/PHASE (°)
Typical Performance Curves
200
180
160
140
PHASE
120
100
80
60
40
20
GAIN
0
-20 R = 10k
L
-40
CL = 100pF
-60
SIMULATION
-80
-100
0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 37. OPEN-LOOP GAIN, PHASE vs
FREQUENCY, RL = 10kΩ, CL = 10pF
FIGURE 38. OPEN-LOOP GAIN, PHASE vs
FREQUENCY, RL = 10kΩ, CL = 100pF
8
70
Rg = 100, Rf = 100k
AV = 1000
GAIN (dB)
40
AV = 100
V+ = ±20V
CL = 4pF
RL = 10k
VOUT = 100mVP-P
30
20
AV = 10
Rg = 10k, Rf = 100k
10
0
6
Rg = 1k, Rf = 100k
50
AV = 1
-10
Rg = OPEN, Rf = 0
-20
10
100
1k
10k
100k
1M
NORMALIZED GAIN (dB)
60
4
Rf = Rg = 100k
2
0
Rf = Rg = 1k
-2
-4 V+ = ±5V
-6 RL = 10k
CL = 4pF
-8
AV = +2
-10 V
OUT = 10mVP-P
-12
1k
10M
10k
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
10M
0
-1
RL = 100k
-2
-3
RL = 10k
-4
RL = 1k
-5
RL = 499
-9
1M
1
0
-8
100k
FIGURE 40. FREQUENCY RESPONSE vs FEEDBACK
RESISTANCE Rf/Rg
1
-7
Rf = Rg = 100
FREQUENCY (Hz)
FIGURE 39. FREQUENCY RESPONSE vs CLOSED LOOP
GAIN
-6
Rf = Rg = 10k
V+ = ±5V
CL = 4pF
AV = +1
VOUT = 10mVP-P
1k
10k
-1
-3
1M
FREQUENCY (Hz)
FIGURE 41. GAIN vs FREQUENCY vs RL
16
10M
RL = 10k
-4
RL = 1k
-5
RL = 499
-6
-7
-8
100k
RL = 100k
-2
-9
V+ = ±20V
CL = 4pF
AV = +1
VOUT = 100mVP-P
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 42. GAIN vs FREQUENCY vs RL
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, TA = +25°C unless otherwise
specified. (Continued)
8
1
0
CL = 334pF
4
CL = 224pF
2
CL = 104pF
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
6
0
-2
-6
-8
CL = 51pF
VS = ±15V
RL = 10k
AV = +1
VOUT = 100mVP-P
-4
1k
10k
CL = 4pF
-2
-3
-4
VOUT = 10mVP-P
-5
VOUT = 50mVP-P
-6
-7
-8
100k
FREQUENCY (Hz)
1M
VS = ±5V
VOUT = 100mVP-P
CL = 4pF
AV = +1
RL = INF
VOUT = 200mVP-P
-91k
10M
VOUT = 500mVP-P
VOUT = 1VP-P
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 44. GAIN vs FREQUENCY vs OUTPUT
VOLTAGE
FIGURE 43. GAIN vs FREQUENCY vs CL
2
140
0
120
-2
CROSSTALK (dB)
NORMALIZED GAIN (dB)
-1
-4
-6
VS = ±20V
-8
VS = ±5V
-10 C = 4pF
L
-12 RL = 10k
AV = +1
-14 VOUT = 100mVP-P
-16
1k
10k
VS = ±15V
VS = ±2.25V
100k
FREQUENCY (Hz)
1M
80
60
RL = 10k
40 C = 4pF
L
AV = +1
20
VOUT = 1VP-P
0
10
10M
FIGURE 45. GAIN vs FREQUENCY vs SUPPLY
VOLTAGE
100
100
VS = ±5V
VS = ±15V
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 46. CROSSTALK vs FREQUENCY, VS = ±5V,
±15V
2.5
6
2.0
V+ = ±15V
CL = 4pF
AV = 11
Rf = 10k, Rg = 1k
VOUT = 10VP-P
2
1.5
LARGE SIGNAL (V)
LARGE SIGNAL (V)
4
0
RL = 10k
-2
RL = 2k
VS = ±5V, ±15V, RL = 10k
1.0
0.5
VS = ±5V, ±15V, RL = 2k
0
-0.5
-1.0
CL = 4pF
AV = 1
VOUT = 4VP-P
-1.5
-4
-2.0
-6
0
50
100
150
200
250
300
350
400
TIME (µs)
FIGURE 47. LARGE SIGNAL 10V STEP RESPONSE,
VS = ±15V
17
-2.5
0
5
10
15
20
25
30
35
TIME (µs)
FIGURE 48. LARGE SIGNAL TRANSIENT RESPONSE vs
RL VS = ±5V, ±15V
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
VS = ±15V, VCM = 0V, RL = Open, TA = +25°C unless otherwise
specified. (Continued)
0.26
0.06
0.22
0.04
0.18
VS = ±5V, ±15V, ±20V
INPUT (V)
0.02
0.00
-0.02
RL = 2k, 10k
CL = 4pF
AV = 1
VOUT = 100mVP-P
-0.04
-0.06
-0.08
0
5
10
15
30
35
0.02
INPUT
INPUT (V)
-0.06
-0.10
-0.18
-0.22
-0.26
-1
45
0
20
40
60
-11
18
20
40
-1
80 100 120 140 160 180 200
TIME (µs)
60
VS = ±15V
RL = 10k
AV = 1
VOUT = 100mVP-P
35
O
SH
ER
OV
30
25
E
OV
H
RS
OT
OO
+
T-
20
15
10
-13
-15
80 100 120 140 160 180 200
TIME (µs)
FIGURE 51. NEGATIVE OUTPUT OVERLOAD
RESPONSE TIME, VS = ±15V
1
OUTPUT
40
-3
-9
3
INPUT
FIGURE 50. POSITIVE OUTPUT OVERLOAD
RESPONSE TIME, VS = ±15V
50
-7
VS = ±15V
RL = 10k
CL = 4pF
AV = 100
Rf = 10k, Rg = 100
VIN = 200mVP-P
-0.14
5
1
-5
9
0.06
0
OUTPUT (V)
OUTPUT
11
7
-0.06
40
13
0.10
-0.02
20
25
TIME (µs)
-0.02
0.14
0.02
FIGURE 49. SMALL SIGNAL TRANSIENT RESPONSE
VS = ±5V, ±15V, ±20V
0.06
15
VS = ±15V
RL = 10k
CL = 4pF
AV = 100
Rf = 10k, Rg = 100
VIN = 200mVP-P
OUTPUT (V)
0.08
OVERSHOOT (%)
SMALL SIGNAL (V)
Typical Performance Curves
5
0
1
10
100
1,000
CAPACITANCE (pF)
10,000
FIGURE 52. % OVERSHOOT vs LOAD CAPACITANCE,
VS = ±15V
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
Applications Information
Functional Description
The ISL28107, ISL28207 and ISL28407 are single, dual
and quad, very low 1/f noise (14nV/√Hz @ 10Hz)
precision op-amps. These amplifiers feature very high
open loop gain (50kV/mV) for excellent CMRR (145dB),
and gain accuracy. Both devices are fabricated in a new
precision 40V complementary bipolar DI process.
The super-beta NPN input stage with bias current
cancellation provides bipolar-like levels of AC
performance with the low input bias currents
approaching JFET levels. The temperature stabilization
provided by bias current cancellation removes the high
input bias current temperature coefficient commonly
found in JFET amplifiers. Figures 7 and 8 show the input
bias current variation over temperature.
The input offset voltage (VOS) has an very low, worst
case value of 75µV max at +25°C and a maximum TC of
0.65µV/°C. Figure 36 shows VOS as a function of supply
voltage and temperature with the common mode voltage
at 0V for split supply operation.
The complimentary bipolar output stage maintains
stability driving large capacitive loads (to 10nF) without
external compensation. The small signal overshoot vs.
load capacitance is shown in Figure 52.
Output Current Limiting
The output current is internally limited to approximately
±40mA at +25°C and can withstand a short circuit to
either rail as long as the power dissipation limits are not
exceeded. This applies to only 1 amplifier at a time for
the dual op-amp. Continuous operation under these
conditions may degrade long term reliability.
Output Phase Reversal
Output phase reversal is a change of polarity in the
amplifier transfer function when the input voltage
exceeds the supply voltage. The ISL28107, ISL28207
and ISL28407 are immune to output phase reversal,
even when the input voltage is 1V beyond the supplies.
Using Only One Channel
The ISL28207 is a dual op-amp. If the application only
requires one channel, the user must configure the
unused channel to prevent it from oscillating. The unused
channel will oscillate if the input and output pins are
floating. This will result in higher than expected supply
currents and possible noise injection into the channel
being used. The proper way to prevent this oscillation is
to short the output to the inverting input and ground the
positive input (as shown in Figure 53).
-
Operating Voltage Range
The devices are designed to operate over the 4.5V
(±2.25V) to 40V (±20V) range and are fully
characterized at 10V (±5V) and 30V (±15V). Both DC
and AC performance remain virtually unchanged over the
complete 4.5V to 40V operating voltage range.
Parameter variation with operating voltage is shown in
the “Typical Performance Curves” beginning on page 10.
The input common mode voltage range sensitivity to
temperature is shown in Figure 36 (±15V).
Input ESD Diode Protection
The input terminals (IN+ and IN-) each have internal
ESD protection diodes to the positive and negative
supply rails, a series connected 500Ω current limiting
resistor followed by an anti-parallel diode pair across
the input NPN transistors (Circuit 1 in “Pin Descriptions”
on page 4).
The resistor-ESD diode configuration enables a wide
differential input voltage range equal to the lesser of the
Maximum Supply Voltage in the “Absolute Maximum
Ratings” on page 6 (42V) or, a maximum of 0.5V beyond
the V+ and V- supply voltage. The internal protection
resistors eliminate the need for external input current
limiting resistors in unity gain connections and other
circuit applications where large voltages or high slew
rate signals are present. Although the amplifier is fully
protected, high input slew rates that exceed the amplifier
slew rate (±0.32V/µs) may cause output distortion.
+
FIGURE 53. PREVENTING OSCILLATIONS IN
UNUSED CHANNELS
Power Dissipation
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power supply
conditions. It is therefore important to calculate the
maximum junction temperature (TJMAX) for all
applications to determine if power supply voltages, load
conditions, or package type need to be modified to
remain in the safe operating area. These parameters are
related using Equation 1:
(EQ. 1)
T JMAX = T MAX + θ JA xPD MAXTOTAL
where:
• PDMAXTOTAL is the sum of the maximum power
dissipation of each amplifier in the package (PDMAX)
• PDMAX for each amplifier can be calculated using
Equation 2:
V OUTMAX
PD MAX = V S × I qMAX + ( V S - V OUTMAX ) × ---------------------------R
(EQ. 2)
L
where:
• TMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation of 1 amplifier
• VS = Total supply voltage
19
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
• IqMAX = Maximum quiescent supply current of 1
amplifier
• VOUTMAX = Maximum output voltage swing of the
application
• RL = Load resistance
ISL28107, ISL28207, ISL28407 SPICE
Model
Figure 54 shows the SPICE model schematic and
Figure 55 shows the net list for the ISL28107, ISL28207
and ISL28407 SPICE model. The model is a simplified
version of the actual device and simulates important AC
and DC parameters. AC parameters incorporated into
the model are: 1/f and flatband noise, Slew Rate,
CMRR, Gain and Phase. The DC parameters are VOS,
IOS, total supply current and output voltage swing. The
model uses typical parameters given in the “Electrical
Specifications” Table beginning on page 6. The AVOL is
adjusted for 155dB with the dominate pole at 0.01Hz.
The CMRR is set (145dB, fcm = 100Hz). The input stage
models the actual device to present an accurate AC
representation. The model is configured for ambient
temperature of +25°C.
Figures 56 through 66 show the characterization vs
simulation results for the Noise Voltage, Closed Loop
Gain vs Frequency, Closed Loop Gain vs RL, Large Signal
Step Response, Open Loop Gain Phase and Simulated
CMRR vs Frequency.
20
License Statement
The information in this SPICE model is protected under
the United States copyright laws. Intersil Corporation
hereby grants users of this macro-model hereto referred
to as “Licensee”, a nonexclusive, nontransferable licence
to use this model as long as the Licensee abides by the
terms of this agreement. Before using this macro-model,
the Licensee should read this license. If the Licensee
does not accept these terms, permission to use the
model is not granted.
The Licensee may not sell, loan, rent, or license the
macro-model, in whole, in part, or in modified form, to
anyone outside the Licensee’s company. The Licensee
may modify the macro-model to suit his/her specific
applications, and the Licensee may make copies of this
macro-model for use within their company only.
This macro-model is provided “AS IS, WHERE IS, AND
WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED
OR IMPLIED, INCLUDING BUY NOT LIMITED TO ANY
IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE.”
In no event will Intersil be liable for special, collateral,
incidental, or consequential damages in connection with
or arising out of the use of this macro-model. Intersil
reserves the right to make changes to the product and
the macro-model without prior notice.
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
V++
V++
R3
R4
4.45k
4.45k
4
5
CASCODE
Q4
C4
2pF
Vin-
VIN-
D1
3
SUPERB
SUPERB
DX
R1
C6
1.2pF
0.1V
7
EOS
1
IOS
Mirror
VCM
15pA
+
-
5E11
+
-
En
In+
VIN+
Vmid
9
IEE
200E-6
R2
600
Vc
+
-
+
-
Q3
R17
C5
2pF
8
5E11
25
5
Q1 Q2
24
D12
4
6
-
+
CASCODE
Q5
2
V5
DN
IEE1
96E-6
+
VOS
-
5E-6
V-VCM
Voltage Noise
Input Stage
V++
V++
10
+
-
4
5
D2
DX
+
V1
- 1.86V
G3
13
+
-
R5
1
D4
DX
+
V3
- 1.86V
11
G5
R7
2.55E10
Vg
12
-
R8
G4
V2
1.86V
+
+
-
+
D3
DX
+
V-VCM
R6
1
G2
1ST Gain Stage
14
-
1.59E-3
17
R11
1
Vc
Vmid
Vc
Vmid
+
-
R9
1
C2
6.25pF
R10
1
C3
2.55E10
V4
1.86V
L1
6.25pF
R12
1
G6
18
VCM
D5
DX
Vg
+
-
G1
L2
1.59E-3
V--
2nd Gain Stage
Mid Supply Ref
Common Mode Gain Stage
V++
+
-
D9
DX
G7
+
E2
22
ISY
0.21mA
Vg
D6
DX
23
V5
20
1.12V
V-
1.12V
G8
+
E3
V-
V--
D10
DY
+
G9
+
-
D11
DY
R16
90
+
-
+
VOUT
VOUT
V6
21
+
DX
-
D7
R15
90
-
+
-
D8
DX
V+
+
V+
G10
Output Stage
Supply Isolation Stage
FIGURE 54. SPICE SCHEMATIC
21
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
* source ISL28107_SPICEmodel
* Revision A, October 28th 2009 LaFontaine
* Model for Noise, supply currents, 145dB f=100Hz
CMRR, *155dB f=0.01Hz AOL
*Copyright 2009 by Intersil Corporation
*Refer to data sheet “LICENSE STATEMENT” Use of
*this model indicates your acceptance with the
*terms and provisions in the License Statement.
* Connections: +input
*
|
-input
*
|
|
+Vsupply
*
|
|
|
-Vsupply
*
|
|
|
|
output
*
|
|
|
|
|
.subckt ISL28107subckt Vin+ Vin-V+ V- VOUT
* source ISL28127_SPICEMODEL_0_0
*
*Voltage Noise
E_En
IN+ VIN+ 25 0 1
R_R17
25 0 600
D_D12
24 25 DN
V_V7
24 0 0.1
*
*Input Stage
I_IOS
IN+ VIN- DC 15e-12
C_C6
IN+ VIN- 1.2E-12
R_R1
VCM VIN- 5e11
R_R2
IN+ VCM 5e11
Q_Q1
2 VIN- 1 SuperB
Q_Q2
3 8 1 SuperB
Q_Q3
V-- 1 7 Mirror
Q_Q4
4 6 2 Cascode
Q_Q5
5 6 3 Cascode
R_R3
4 V++ 4.45e3
R_R4
5 V++ 4.45e3
C_C4 VIN- 0 2e-12
C_C5 8 0 2e-12
D_D1
6 7 DX
I_IEE
1 V-- DC 200e-6
I_IEE1
V++ 6 DC 96e-6
V_VOS
9 IN+ 5e-6
E_EOS
8 9 VC VMID 1
*
*1st Gain Stage
G_G1
V++ 11 4 5 101.6828e-3
G_G2
V-- 11 4 5 101.6828e-3
R_R5
11 V++ 1
R_R6
V-- 11 1
D_D2
10 V++ DX
D_D3
V-- 12 DX
V_V1
10 11 1.86
V_V2
11 12 1.86
*
*2nd Gain Stage
G_G3
V++ VG 11 VMID 2.21e-3
G_G4
V-- VG 11 VMID 2.21e-3
R_R7
VG V++ 2.55e10
R_R8
V-- VG 2.55e10
C_C2
VG V++ 6.25e-10
C_C3
V-- VG 6.25e-10
D_D4
13 V++ DX
D_D5
V-- 14 DX
V_V3
13 VG 1.86
V_V4
VG 14 1.86
*
*Mid supply Ref
R_R9
VMID V++ 1
R_R10
V-- VMID 1
I_ISY
V+ V- DC 0.21E-3
E_E2
V++ 0 V+ 0 1
E_E3
V-- 0 V- 0 1
*
*Common Mode Gain Stage with Zero
G_G5
V++ VC VCM VMID 5.62e-8
G_G6
V-- VC VCM VMID 5.62e-8
R_R11
VC 17 1
R_R12
18 VC 1
L_L1
17 V++ 1.59e-3
L_L2
18 V-- 1.59e-3
*
*Output Stage with Correction Current Sources
G_G7
VOUT V++ V++ VG 1.11e-2
G_G8
V-- VOUT VG V-- 1.11e-2
G_G9
22 V-- VOUT VG 1.11e-2
G_G10
23 V-- VG VOUT 1.11e-2
D_D6
VG 20 DX
D_D7
21 VG DX
D_D8
V++ 22 DX
D_D9
V++ 23 DX
D_D10
V-- 22 DY
D_D11
V-- 23 DY
V_V5
20 VOUT 1.12
V_V6
VOUT 21 1.12
R_R15
VOUT V++ 9E1
R_R16
V-- VOUT 9E1
*
.model SuperB npn
+ is=184E-15 bf=30e3 va=15 ik=70E-3 rb=50
+ re=0.065 rc=35 cje=1.5E-12 cjc=2E-12
+ kf=0 af=0
.model Cascode npn
+ is=502E-18 bf=150 va=300 ik=17E-3 rb=140
+ re=0.011 rc=900 cje=0.2E-12 cjc=0.16E-12f
+ kf=0 af=0
.model Mirror pnp
+ is=4E-15 bf=150 va=50 ik=138E-3 rb=185
+ re=0.101 rc=180 cje=1.34E-12 cjc=0.44E-12
+ kf=0 af=0
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28107subckt
FIGURE 55. SPICE NET LIST
22
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
Characterization vs Simulation Results
1000
INPUT NOISE VOLTAGE (nV/√Hz)
INPUT NOISE VOLTAGE (nV/√Hz)
1000
V+ = ±19V
AV = 1
100
10
0.1
1
10
100
1k
10k
100
10
100m
100k
1.0
10
100
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 56. CHARACTERIZED INPUT NOISE VOLTAGE
70
Rg = 100, Rf = 100k
AV = 1000
AV = 100
V+ = ±20V
CL = 4pF
RL = 10k
VOUT = 100mVP-P
30
AV = 10
20
Rg = 10k, Rf = 100k
10
AV = 100
40
AV = 10
20
Rg = 10k, Rf = 100k
AV = 1
0
-10
Rg = OPEN, Rf = 0
-20
10
100
Rg = OPEN, Rf = 0
1k
10k
100k
FREQUENCY (Hz)
1M
-20
10M
10
1
0
0
RL = 100k
RL = 10k
-4
RL = 1k
-5
RL = 499
-6
-7
-8
-9
NORMALIZED GAIN (dB)
-1
-3
V+ = ±20V
CL = 4pF
AV = +1
VOUT = 100mVP-P
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 60. CHARACTERIZED CLOSED LOOP GAIN vs
RL
23
10k
100k
1M
10M
FIGURE 59. SIMULATED CLOSED LOOP GAIN vs
FREQUENCY
1
-2
1k
100
FREQUENCY (Hz)
FIGURE 58. CHARACTERIZED CLOSED LOOP GAIN vs
FREQUENCY
NORMALIZED GAIN (dB)
Rg = 1k, Rf = 100k
AV = 1
0
Rg = 100, Rf = 100k
60
GAIN (dB)
GAIN (dB)
AV = 1000
Rg = 1k, Rf = 100k
50
40
100k
FIGURE 57. SIMULATED INPUT NOISE VOLTAGE
70
60
10k
RL = 100k
RL = 1k
-2
RL = 10k
-4
RL = 499
V+ = ±15V
-6
CL = 4pF
AV = +1
-8
VOUT = 100mVP-P
-9
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 61. SIMULATED CLOSED LOOP GAIN vs RL
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
Characterization vs Simulation Results (Continued)
20
6
LARGE SIGNAL (V)
2
0
LARGE SIGNAL (V)
V+ = ±15V
CL = 4pF
AV = 11
Rf = 10k, Rg = 1k
VOUT = 10VP-P
4
RL = 10k
-2
RL = 2k
10
OUTPUT
0
INPUT
-10
-4
0
50
100
150
200
250
TIME (µs)
300
350
-20
0
400
OPEN LOOP GAIN (dB)/PHASE (°)
50
100
150
TIME (µs)
200
250
300
FIGURE 63. SIMULATED LARGE SIGNAL 10V STEP
RESPONSE
FIGURE 62. CHARACTERIZED LARGE SIGNAL 10V
STEP RESPONSE
200
180
160
140
PHASE
120
100
80
60
40
20
GAIN
0
-20 R = 10k
L
-40
CL = 10pF
-60
SIMULATION
-80
-100
0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FIGURE 64. SIMULATED OPEN-LOOP GAIN, PHASE vs
FREQUENCY
200
OPEN LOOP GAIN (dB)/PHASE (°)
-6
150
PHASE
100
50
0
RL = 10k
CL = 10pF
SIMULATION
-50
1m 10m
1
GAIN
100
10K
FREQUENCY (Hz)
1M
100M
FIGURE 65. SIMULATED OPEN-LOOP GAIN, PHASE vs
FREQUENCY
CMRR (dB)
150
100
50
SIMULATION
0
1m
100m
10
1k
100k
FREQUENCY (Hz)
10M
100M
FIGURE 66. SIMULATED CMRR vs FREQUENCY
24
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
Web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
9/7/10
FN6631.3 1. General changes:
a. Added in ISL28407 Quad devices for SOIC, TSSOP and QFN packages.
b. Added in TDFN packages for single ISL28107 and dual ISL28207 devices.
c. Added in new VOS and TCVOS limits for TDFN packages
2. Specific changes:
a. On page 1 – Added in ISL28407 to title and front page info. Corrected Input Bias Current in Features
from 60pA to 15pA (in order to match Spec Table)
b. On page 2 - Added in ISL28107FRTZ, ISL28207FRTZ, ISL28407FBZ, ISL28407FVZ, and ISL28407FRZ
packages to Ordering information. Added in –T7, T-13 & -T7A tape and reel extensions where applicable.
c. On page 2 -Corrected part marking for ISL28207FRTZ parts from 207Z to 8207
d. On page 3 – Added in TDFN, 14 Ld SOIC, 14 Ld TSSOP and 16 Ld QFN to pin configurations.
e. On page 4 – Updated “Pin Descriptions” with newly added packages.
f. On page 6 – in “Thermal Information”, added in thermal packaging info & applicable notes for TDFN
packages.
g. On page 6 and page 8 Electrical Specifications Tables – Added two new line items for VOS spec. TDFN
package ISL28107 limits ±100uV 25C and ±190uV full temp. TDFN package ISL28207 limits ±100uV 25C
and ±175uV full temp.
h. On page 6 and page 8 Electrical Specifications Table – Added two new line items for TCVOS spec. TDFN
package ISL28107 limits ±0.9uV/C full temp. TDFN package ISL28207 limits ±0.75uV/C.
i. On page 28 to page 32 - Added in POD for L8.3x3A, M14.15, M14.173, and L16.4x4
3/9/10
FN6631.2 1. Added MSOP package to the ordering information and added applicable POD M8.118 to end of datasheet
2. Separated each part number with it's own specific -T7 and -T13 suffix. Removed “Add
“-T7” or “-T13” suffix for Tape and Reel.” from Note 1.
3. Added MSOP to the Pin Configuration and Pin Descriptions
4. Updated ±15 and ±5V Electrical Specification table with the following edits:
A) Separated VOS specs for SOIC and MSOP packages. Added new VOS specs for MSOP Grade
package.
B) Separated TCVOS specs for SOIC and MSOP packages. Added new TCVOS specs for MSOP
package.
5. Added Theta JA and JC for the 8 Ld MSOP package. Added Theta JC values for both SOIC package
options. Changed Theta JA for 8 Ld SOIC (ISL28207) from 115 to 105.
2/22/10
1. Added “Related Literature*(see page 26)” on page 1.
2. Added Evaluation Boards to “Ordering Information” on page 2.
3. “Electrical Specifications” Tables, page 6 to page 9. Unbolded MIN/MAX specs with “TA = -40°C to
+85°C” conditions (since only MIN/MAX specs with “TA = -40°C to +125°C” conditions should be bolded,
per note in common conditions)
4. Corrected Note reference in ISC parameter on page 7 and page 9 from Note 3 to Note 9.
11/10/09 FN6631.1 1.
2.
3.
4.
5.
6.
7.
6/5/09
Updated VOS, IB, and IOS electrical specifications.
Added Typical performance curves, Figures 1 through 30.
Output Short Circuit Current test condition has been clarified with Note 9.
Updated POD.
Added Spice Model, associated text and Figures 56 through 66.
Deleted old Figures 6, 7, 8, 10, 11 and 12.
Added Licence Statement on page 16 and referenced in spice model.
FN6631.0 Initial Release.
25
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL28107, ISL28207 and ISL28407.
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
26
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
27
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 3, 3/10
5
3.0±0.05
A
DETAIL "X"
D
8
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.55 ± 0.15
0.25
3°±3°
0.85±010
H
DETAIL "X"
C
SEATING PLANE
0.25 - 0.036
0.08 M C A-B D
0.10 ± 0.05
0.10 C
SIDE VIEW 1
(5.80)
NOTES:
(4.40)
(3.00)
1. Dimensions are in millimeters.
(0.65)
(0.40)
(1.40)
TYPICAL RECOMMENDED LAND PATTERN
28
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
Package Outline Drawing
L8.3x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 2/10
( 2.30)
3.00
( 1.95)
A
B
3.00
( 8X 0.50)
6
PIN 1
INDEX AREA
(4X)
(1.50)
( 2.90 )
0.15
PIN 1
TOP VIEW
(6x 0.65)
( 8 X 0.30)
TYPICAL RECOMMENDED LAND PATTERN
SEE DETAIL "X"
2X 1.950
PIN #1
INDEX AREA
0.10 C
0.75 ±0.05
6X 0.65
C
0.08 C
1
SIDE VIEW
6
1.50 ±0.10
8
C
8X 0.30 ±0.05
8X 0.30 ± 0.10
0 . 2 REF
5
4
0.10 M C A B
0 . 02 NOM.
0 . 05 MAX.
2.30 ±0.10
DETAIL "X"
BOTTOM VIEW
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.20mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
7.
Compliant to JEDEC MO-229 WEEC-2 except for the foot length.
either a mold or mark feature.
29
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
Package Outline Drawing
M14.15
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 10/09
4
0.10 C A-B 2X
8.65
A 3
6
14
DETAIL"A"
8
0.22±0.03
D
6.0
3.9
4
0.10 C D 2X
0.20 C 2X
7
PIN NO.1
ID MARK
5
0.31-0.51
B 3
(0.35) x 45°
4° ± 4°
6
0.25 M C A-B D
TOP VIEW
0.10 C
1.75 MAX
H
1.25 MIN
0.25
GAUGE PLANE C
SEATING PLANE
0.10 C
0.10-0.25
1.27
SIDE VIEW
(1.27)
DETAIL "A"
(0.6)
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Datums A and B to be determined at Datum H.
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5. The pin #1 indentifier may be either a mold or mark feature.
(1.50)
6. Does not include dambar protrusion. Allowable dambar protrusion
shall be 0.10mm total in excess of lead width at maximum condition.
7. Reference to JEDEC MS-012-AB.
TYPICAL RECOMMENDED LAND PATTERN
30
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
Package Outline Drawing
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 3, 10/09
A
1
3
5.00 ±0.10
SEE
DETAIL "X"
8
14
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
1
0.20 C B A
7
B
0.65
0.09-0.20
TOP VIEW
END VIEW
1.00 REF
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
0.25 +0.05/-0.06
0.10 C
0.10
GAUGE
PLANE
0.25
5
0°-8°
0.05 MIN
0.15 MAX
CBA
SIDE VIEW
0.60 ±0.15
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
(5.65)
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.80mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead is 0.07mm.
(0.65 TYP)
(0.35 TYP)
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153, variation AB-1.
TYPICAL RECOMMENDED LAND PATTERN
31
FN6631.3
September 9, 2010
ISL28107, ISL28207, ISL28407
Package Outline Drawing
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 6, 02/08
4X 1.95
4.00
12X 0.65
A
B
13
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
16
1
4.00
12
2 . 10 ± 0 . 15
9
4
0.15
(4X)
5
8
TOP VIEW
0.10 M C A B
+0.15
16X 0 . 60
-0.10
4 0.28 +0.07 / -0.05
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
1.00 MAX
C
BASE PLANE
( 3 . 6 TYP )
SEATING PLANE
0.08 C
SIDE VIEW
(
2 . 10 )
( 12X 0 . 65 )
( 16X 0 . 28 )
C
0 . 2 REF
5
( 16 X 0 . 8 )
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
32
FN6631.3
September 9, 2010