RENESAS 4518

4518 Group
REJ03B0008-0301
Rev.3.01
2005.06.15
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 4518 Group is a 4-bit single-chip microcomputer designed with
CMOS technology. Its CPU is that of the 4500 series using a
simple, high-speed instruction set. The computer is equipped with
serial interface, four 8-bit timers (each timer has one or two reload
registers), a 10-bit A/D converter, interrupts, and oscillation circuit
switch function.
The various microcomputers in the 4518 Group include variations
of the built-in memory size as shown in the table below.
FEATURES
●Minimum instruction execution time .................................. 0.5 µs
(at 6 MHz oscillation frequency, in XIN through-mode)
●Supply voltage
Mask ROM version ...................................................... 1.8 to 5.5 V
One Time PROM version ............................................. 2.5 to 5.5 V
(It depends on operation source clock, oscillation frequency and operation mode)
●Timers
Timer 1 ...................................... 8-bit timer with a reload register
Timer 2 ...................................... 8-bit timer with a reload register
Timer 3 ...................................... 8-bit timer with a reload register
Timer 3 ................................. 8-bit timer with two reload registers
Part number
M34518M2-XXXFP
M34518M2-XXXSP
M34518M4-XXXFP
M34518M4-XXXSP
M34518M6-XXXFP
M34518M8-XXXFP
M34518E8FP (Note)
M34518E8SP (Note)
ROM (PROM) size
(✕ 10 bits)
2048 words
2048 words
4096 words
4096 words
6144 words
8192 words
8192 words
8192 words
Note: Shipped in blank.
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●Interrupt ........................................................................ 8 sources
●Key-on wakeup function pins ................................................... 10
●Serial interface ............................................................. 8 bits ✕ 1
● A/D converter .......... 10-bit successive comparison method, 4ch
●Voltage drop detection circuit
Reset occurrence .................................... Typ. 3.5 V (Ta = 25 °C)
Reset release .......................................... Typ. 3.7 V (Ta = 25 °C)
●Watchdog timer
●Clock generating circuit
(ceramic resonator/RC oscillation/quartz-crystal oscillation/onchip oscillator)
●LED drive directly enabled (port D)
APPLICATION
Electrical household appliance, consumer electronic products, office automation equipment, etc.
RAM size
(✕ 4 bits)
256 words
256 words
256 words
256 words
384 words
384 words
384 words
384 words
Package
ROM type
PLQP0032GB-A
PRDP0032BA-A
PLQP0032GB-A
PRDP0032BA-A
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
PRDP0032BA-A
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
One Time PROM
One Time PROM
4518 Group
P02
P01
P00
P63/AIN3
P62/AIN2
P61/AIN1
P60/AIN0
P31/INT1
PIN CONFIGURATION
24
23
22
21
20
19
18
17
P03
25
16
P30/INT0
P10
26
15
VDCE
P11
27
14
VDD
P12
28
13
VSS
P13
29
12
XIN
D0
30
11
XOUT
D1
31
10
CNVSS
D2
32
9
RESET
2
3
4
5
6
7
8
D5
D6/CNTR0
D7/CNTR1
P20/SCK
P21/SOUT
P22/SIN
D3
1
D4
M34518Mx-XXXFP
M34518E8FP
OUTLINE PLQP0032GB-A (32P6U-A)
Pin configuration (top view) (4518 Group)
1
32
P13
D1
2
31
P12
D2
3
30
P11
D3
4
29
P10
D4
5
28
P03
D5
6
27
P02
D6/CNTR0
7
26
P01
D7/CNTR1
8
25
P00
P20/SCK
9
24
P63/AIN3
P21/SOUT
10
23
P62/AIN2
P22/SIN
11
22
P61/AIN1
RESET
12
21
P60/AIN0
CNVSS
13
20
P31/INT1
XOUT
14
19
P30/INT0
XIN
15
18
VDCE
VSS
16
17
VDD
M34518Mx-XXXSP
M34518E8SP
D0
OUTLINE PRDP0032BA-A (32P4B)
Pin configuration (top view) (4518 Group)
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Port P0
Block diagram (4518 Group)
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Serial I/O
(8 bits ✕ 1)
A/D converter
(10 bits ✕ 4 ch)
Watchdog timer (16 bits)
Timer 1(8 bits)
Timer 2(8 bits)
Timer 3(8 bits)
Timer 4(8 bits)
Timer
4
Port P1
Register A (4 bits)
Register B (4 bits)
Register E (8 bits)
Register D (3 bits)
Stack register SK (8 levels)
Interrupt stack register SDP (1 level)
ALU(4 bits)
3
Port P2
4500 series
CPU core
Internal peripheral functions
I/O port
4
Voltage drop detection circuit
Port D
256, 384 words ✕ 4 bits
RAM
2048, 4096, 6144, 8192 words
✕ 10 bits
ROM
Memory
4
Port P6
System clock generation circuit
XIN -XOUT
(Ceramic/Quartz-crystal/RC)
On-chip oscillator
Port P3
2
8
4518 Group
4518 Group
PERFORMANCE OVERVIEW
Parameter
Number of basic instructions
Minimum instruction execution time
Memory sizes ROM M34518M2
Function
148
0.5 µs (at 6.0 MHz oscillation frequency, in XIN through-mode)
2048 words ✕ 10 bits
4096 words ✕ 10 bits
6144 words ✕ 10 bits
8192 words ✕ 10 bits
256 words ✕ 4 bits
384 words ✕ 4 bits
Input/Output
Eight independent I/O ports;
Ports D6 and D7 are also used as CNTR0 and CNTR1, respectively.
ports
The output structure is switched by software.
4-bit I/O port; a pull-up function, a key-on wakeup function and output structure can be switched
by software.
P10–P13 I/O
4-bit I/O port; a pull-up function, a key-on wakeup function and output structure can be switched
by software.
P20–P22 I/O
3-bit I/O port; ports P20, P21 and P22 are also used as SCK, SOUT and SIN, respectively.
P30, P31 I/O
2-bit I/O port ; ports P30 and P31 are also used as INT0 and INT1, respectively.
P60–P63 I/O
4-bit I/O port ; ports P60–P63 are also used as AIN0–AIN3, respectively.
Timer 1
Timers
8-bit timer with a reload register is also used as an event counter.
Also, this is equipped with a period/pulse width measurement function.
Timer 2
8-bit timer with a reload register.
Timer 3
8-bit timer with a reload register is also used as an event counter.
Timer 4
8-bit timer with two reload registers and PWM output function.
A/D converter
10-bit wide ✕ 4 ch, This is equipped with an 8-bit comparator function.
Serial I/O
8-bit ✕ 1
Sources
Interrupt
8 (two for external, four for timer, one for A/D, and one for serial I/O)
Nesting
1 level
Subroutine nesting
8 levels
Device structure
CMOS silicon gate
Package
32-pin plastic molded LQFP (PLQP0032GB-A)/SDIP (PRDP0032BA-A)
Operating temperature range
–20 °C to 85 °C
Supply voltage Mask ROM version
1.8 V to 5.5 V (It depends on operation source clock, oscillation frequency and operating mode.)
One Time PROM version 2.5 V to 5.5 V (It depends on operation source clock, oscillation frequency and operating mode.)
Active mode
Power
2.8 mA (Ta=25 °C, VDD=5V, f(XIN)=6 MHz, f(STCK)=f(XIN), on-chip oscillator stop)
dissipation
70 µA (Ta=25 °C, VDD=5V, f(XIN)=32 kHz, f(STCK)=f(XIN), on-chip oscillator stop)
(typical value)
150 µA (Ta=25 °C, VDD=5V, on-chip oscillator is used, f(STCK)=f(RING), f(XIN) stop)
RAM back-up mode
0.1 µA (Ta=25 °C, VDD = 5 V, output transistors in the cut-off state)
M34518M4
M34518M6
M34518M8/E8
RAM M34518M2/M4
M34518M6/M8/E8
D0–D7
I/O (Input is
examined by
skip decision)
P00–P03 I/O
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4518 Group
PIN DESCRIPTION
Pin
VDD
RESET
Name
Power supply
Ground
CNVSS
Voltage drop
detection circuit
enable
Reset input/output
XIN
Main clock input
XOUT
Main clock output
D0–D7
I/O port D
Input is examined by
skip decision.
I/O
P00–P03
I/O port P0
I/O
P10–P13
I/O port P1
I/O
P20–P23
I/O port P2
I/O
P30–P33
I/O port P3
I/O
P60–P63
I/O port P6
I/O
CNTR0,
CNTR1
Timer input/output
I/O
INT0, INT1
Interrupt input
Input
AIN0–AIN3
Analog input
Input
SCK
SOUT
SIN
Serial I/O data I/O
Serial I/O data output
Serial I/O clock input
VSS
CNVSS
VDCE
Rev.3.01 2005.06.15
REJ03B0008-0301
Input/Output
—
—
—
Input
I/O
Input
Output
I/O
Output
Input
page 5 of 157
Function
Connected to a plus power supply.
Connected to a 0 V power supply.
Connect CNVSS to VSS and apply “L” (0V) to CNVSS certainly.
This pin is used to operate/stop the voltage drop detection circuit. When “H“ level is
input to this pin, the circuit starts operating. When “L“ level is input to this pin, the
circuit stops operating.
An N-channel open-drain I/O pin for a system reset. When the SRST instruction,
watchdog timer, the built-in power-on reset or the voltage drop detection circuit
causes the system to be reset, the RESET pin outputs “L” level.
I/O pins of the main clock generating circuit. When using a ceramic resonator, connect
it between pins XIN and XOUT. When using a 32 kHz quartz-crystal oscillator, connect it
between pins XIN and XOUT. A feedback resistor is built-in between them. When using
the RC oscillation, connect a resistor and a capacitor to XIN, and leave XOUT pin open.
Each pin of port D has an independent 1-bit wide I/O function. The output structure
can be switched to N-channel open-drain or CMOS by software. For input use, set
the latch of the specified bit to “1” and select the N-channel open-drain. Ports D6, D7
is also used as CNTR0 pin and CNTR1 pin, respectively.
Port P0 serves as a 4-bit I/O port. The output structure can be switched to N-channel
open-drain or CMOS by software. For input use, set the latch of the specified bit to
“1” and select the N-channel open-drain. Port P0 has a key-on wakeup function and
a pull-up function. Both functions can be switched by software.
Port P1 serves as a 4-bit I/O port. The output structure can be switched to N-channel
open-drain or CMOS by software. For input use, set the latch of the specified bit to
“1” and select the N-channel open-drain. Port P1 has a key-on wakeup function and
a pull-up function. Both functions can be switched by software.
Port P2 serves as a 3-bit I/O port. The output structure is N-channel open-drain. For
input use, set the latch of the specified bit to “1”.
Ports P20–P22 are also used as SCK, SOUT, SIN, respectively.
Port P3 serves as a 2-bit I/O port. The output structure is N-channel open-drain. For
input use, set the latch of the specified bit to “1”.
Ports P30 and P31 are also used as INT0 pin and INT1 pin, respectively.
Port P6 serves as a 4-bit I/O port. The output structure can be switched to N-channel
open-drain. For input use, set the latch of the specified bit to “1”. Ports P60–P63 are
also used as AIN0–AIN3, respectively.
CNTR0 pin has the function to input the clock for the timer 1 event counter, and to
output the timer 1 or timer 2 underflow signal divided by 2.
CNTR1 pin has the function to input the clock for the timer 3 event counter, and to
output the PWM signal generated by timer 4.CNTR0 pin and CNTR1 pin are also
used as Ports D6 and D7, respectively.
INT0 pin and INT1 pin accept external interrupts. They have the key-on wakeup function which can be switched by software. INT0 pin and INT1 pin are also used as
Ports P30 and P31, respectively.
A/D converter analog input pins. AIN0–AIN3 are also used as ports P60–P63, respectively.
Serial I/O data transfer synchronous clock I/O pin. SCK pin is also used as port P20..
Serial I/O data output pin. SOUT pin is also used as port P21.
Serial I/O data input pin. SIN pin is also used as port P22.
4518 Group
MULTIFUNCTION
Pin
D6
D7
P20
P21
P22
P30
P31
Multifunction
CNTR0
CNTR1
SCK
SOUT
SIN
INT0
INT1
Pin
CNTR0
CNTR1
SCK
SOUT
SIN
INT0
INT1
Multifunction
D6
D7
P20
P21
P22
P30
P31
Pin
P60
P61
P62
P63
Multifunction
AIN0
AIN1
AIN2
AIN3
Pin
AIN0
AIN1
AIN2
AIN3
Multifunction
P60
P61
P62
P63
Notes 1: Pins except above have just single function.
2: The input/output of P30 and P31 can be used even when INT0 and INT1 are selected.
3: The input of ports P20–P22 can be used even when SIN, SOUT and SCK are selected.
4: The input/output of D6 can be used even when CNTR0 (input) is selected.
5: The input of D6 can be used even when CNTR0 (output) is selected.
6: The input/output of D7 can be used even when CNTR1 (input) is selected.
7: The input of D7 can be used even when CNTR1 (output) is selected.
DEFINITION OF CLOCK AND CYCLE
● Operation source clock
The operation source clock is the source clock to operate this
product. In this product, the following clocks are used.
• Clock (f(XIN)) by the external ceramic resonator
• Clock (f(XIN)) by the external RC oscillation
• Clock (f(XIN)) by the external input
• Clock (f(RING)) of the on-chip oscillator which is the internal
oscillator
• Clock (f(XIN)) by the external quartz-crystal oscillation
Table Selection of system clock
Register MR
System clock
MR3
MR2
MR1
MR0
0
0
0
0
f(STCK) = f(XIN)
✕
1
f(STCK) = f(RING)
0
1
0
0
f(STCK) = f(XIN)/2
✕
1
f(STCK) = f(RING)/2
1
0
0
0
f(STCK) = f(XIN)/4
✕
1
f(STCK) = f(RING)/4
1
1
0
0
f(STCK) = f(XIN)/8
✕
1
f(STCK) = f(RING)/8
✕: 0 or 1
Note: The f(RING)/8 is selected after system is released from reset.
When on-chip oscillator clock is selected for main clock, set
the on-chip oscillator to be operating state.
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● System clock (STCK)
The system clock is the basic clock for controlling this product.
The system clock is selected by the clock control register MR
shown as the table below.
● Instruction clock (INSTCK)
The instruction clock is the basic clock for controlling CPU. The
instruction clock (INSTCK) is a signal derived by dividing the
system clock (STCK) by 3. The one instruction clock cycle generates the one machine cycle.
● Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
Operation mode
XIN through mode
Ring through mode
XIN divided by 2 mode
Ring divided by 2 mode
XIN divided by 4 mode
Ring divided by 4 mode
XIN divided by 8 mode
Ring divided by 8 mode
4518 Group
PORT FUNCTION
Port
Port D
Pin
Input
Output
I/O
(8)
N-channel open-drain/
CMOS
I/O
(4)
N-channel open-drain/
CMOS
4
Output structure
I/O
unit
1
Control
instructions
SD, RD
SZD
CLD
OP0A
IAP0
Control
registers
FR1, FR2
W6
W4
FR0
PU0
K0, K1
Port P0
D0–D5
D6/CNTR0
D7/CNTR1
P00–P03
Port P1
P10–P13
I/O
(4)
N-channel open-drain/
CMOS
4
OP1A
IAP1
FR0
PU1
K0
Port P2
3
N-channel open-drain
2
P60/AIN0–P63/AIN3
N-channel open-drain
4
OP2A
IAP2
OP3A
IAP3
OP6A
IAP6
J1
Port P6
I/O
(3)
I/O
(2)
I/O
(4)
N-channel open-drain
Port P3
P20/SCK, P21/SOUT
P22/SIN
P30/INT0, P31/INT1
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I1, I2
K2
Q2
Q1
Remark
Output structure selection
function (programmable)
Built-in programmable pull-up
functions, key-on wakeup
functions and output structure
selection functions
Built-in programmable pull-up
functions, key-on wakeup
functions and output structure
selection functions
4518 Group
CONNECTIONS OF UNUSED PINS
Connection
Pin
XIN
XOUT
D0–D5
D6/CNTR0
D7/CNTR1
P00–P03
Open.
Open.
Open.
Connect to VSS.
Open.
Connect to VSS.
Open.
Connect to VSS.
Open.
Connect to VSS.
P10–P13
Open.
Connect to VSS.
P20/SCK
Open.
Connect to VSS.
Open.
Connect to VSS.
Open.
Connect to VSS.
Open.
Connect to Vss.
Open.
Connect to Vss.
Open.
Connect to Vss.
P21/SOUT
P22/SIN
P30/INT0
P31/INT1
P60/AIN0–P63/AIN3
Usage condition
Internal oscillator is selected.
Internal oscillator is selected.
RC oscillator is selected.
External clock input is selected for main clock.
N-channel open-drain is selected for the output structure.
CNTR0 input is not selected for timer 1 count source.
N-channel open-drain is selected for the output structure.
CNTR1 input is not selected for timer 3 count source.
N-channel open-drain is selected for the output structure.
The key-on wakeup function is not selected.
N-channel open-drain is selected for the output structure.
The pull-up function is not selected.
The key-on wakeup function is not selected.
The key-on wakeup function is not selected.
N-channel open-drain is selected for the output structure.
The pull-up function is not selected.
The key-on wakeup function is not selected.
SCK pin is not selected.
(Note 1)
(Note 1)
(Note 2)
(Note 3)
(Note 4)
(Note 4)
(Note 4)
(Note 6)
(Note 5)
(Note 4)
(Note 6)
(Note 7)
(Note 5)
(Note 4)
(Note 7)
SIN pin is not selected.
“0” is set to output latch.
“0” is set to output latch.
Notes 1: After system is released from reset, the internal oscillation (on-chip oscillator) is selected for system clock (RG0=0, MR0=1).
2: When the CRCK instruction is executed, the RC oscillation circuit becomes valid. Be careful that the swich of system clock is not executed at oscillation start only by the CRCK instruction execution.
In order to start oscillation, setting the main clock f(XIN) oscillation to be valid (MR1=0) is required. (If necessary, generate the oscillation stabilizing
wait time by software.)
Also, when the main clock (f(XIN)) is selected as system clock, set the main clock f(XIN) oscillation (MR1=0) to be valid, and select main clock f(XIN)
(MR0=0). Be careful that the switch of system clock cannot be executed at the same time when main clock oscillation is started.
3: In order to use the external clock input for the main clock, select the ceramic resonance by executing the CMCK instruction at the beggining of software, and then set the main clock (f(XIN)) oscillation to be valid (MR1=0). Until the main clock (f(XIN)) oscillation becomes valid (MR1=0) after ceramic
resonance becomes valid, XIN pin is fixed to “H”. When an external clock is used, insert a 1 kΩ resistor to XIN pin in series for limits of current.
4: Be sure to select the output structure of ports D0–D5 and the pull-up function of P00–P03 and P10–P13 with every one port. Set the corresponding
bits of registers for each port.
5: Be sure to select the output structure of ports P00–P03 and P10–P13 with every two ports. If only one of the two pins is used, leave another one
open.
6: The key-on wakeup function is selected with every two bits. When only one of key-on wakeup function is used, considering that the value of key-on
wake-up control register K1, set the unused 1-bit to “H” input (turn pull-up transistor ON and open) or “L” input (connect to VSS, or open and set the
output latch to “0”).
7: The key-on wakeup function is selected with every two bits. When one of key-on wakeup function is used, turn pull-up transistor of the unused one
ON and open.
(Note when connecting to VSS and VDD)
● Connect the unused pins to VSS and VDD using the thickest wire at the shortest distance against noise.
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4518 Group
PORT BLOCK DIAGRAMS
Skip decision
Register Y
Decoder
CLD
instruction
SZD instruction
(Note 3) FR1i
(Note 1)
S
SD instruction
R Q
RD instruction
D0—D3 (Note 2)
(Note 1)
Skip decision
Register Y
Decoder
CLD
instruction
SZD instruction
FR20
(Note 1)
S
SD instruction
R Q
RD instruction
D4
(Note 2)
(Note 1)
Skip decision
Register Y
Decoder
CLD
instruction
SZD instruction
FR21
(Note 1)
S
SD instruction
RD instruction
R Q
D5
(Note 2)
(Note 1)
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
3: i represents bits 0 to 3.
Port block diagram (1)
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4518 Group
Register Y
Decoder
Skip decision
SZD instruction
CLD
instruction
FR22
(Note 1)
S
SD instruction
D6/CNTR0
(Note 2)
W60
RD instruction
R Q
0
W23
1
Timer 1 underflow signal
1/2
0
Timer 2 underflow signal
1/2
1
W62
0
Clock (input) for timer 1 event count
or period measurement signal input
W10
1
W11
W50
W51
Register Y
Decoder
Skip decision
SZD instruction
CLD
instruction
FR23
(Note 1)
S
SD instruction
D7/CNTR1
(Note 2)
W43
R Q
RD instruction
PWMOD
0
1
W63
0
Clock (input) for timer 3 event count
1
W30
W31
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
Port block diagram (2)
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4518 Group
(Note 3)
IAP0 instruction
Register A
Aj
FR00
PU0j
(Note 3)
D
Aj
OP0A instruction
(Note 1)
P00, P01(Note 2)
(Note 1)
T Q
K10
K11
Key-on
wakeup
Pull-up
transistor
0
Level detection circuit
0
1
Edge detection circuit
1
K00
(Note 4)
IAP0 instruction
Register A
Ak
FR01
PU0k
(Note 4)
D
Ak
OP0A instruction
(Note 1)
P02, P03(Note 2)
(Note 1)
T Q
K13
Key-on
wakeup
Pull-up
transistor
K12
0
Level detection circuit
0
1
Edge detection circuit
1
K01
(Note 3)
IAP1 instruction
Register A
Aj
FR02
PU1j
(Note 3)
D
Aj
OP1A instruction
Key-on
wakeup
Pull-up
transistor
(Note 1)
P10, P11(Note 2)
(Note 1)
T Q
Level detection circuit
K02
(Note 4)
IAP1 instruction
Register A
Ak
FR03
Ak
OP1A instruction
Key-on
wakeup
Pull-up
transistor
PU1k
(Note 4)
D
K03
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
3: j represents bits 0 and 1.
4: k represents bits 2 and 3.
Port block diagram (3)
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P12, P13(Note 2)
(Note 1)
T Q
Level detection circuit
(Note 1)
4518 Group
Register A
IAP2 instruction
(Note 1)
A0
P20/SCK
(Note 2)
J12
J13
A0
OP2A instruction
D Q
T
Synchronous clock (output)
for serial data transfer
J10
J11
Synchronous clock (input)
for serial data transfer
Register A
IAP2 instruction
(Note 1)
A1
P21/SOUT
(Note 2)
J10
A1
OP2A instruction
D Q
T
0
1
Serial data output
Register A
A2
IAP2 instruction
(Note 1)
P22/SIN
(Note 2)
A2
OP2A instruction
D Q
T
J11
Serial data input
This symbol represents a parasitic diode on the port.
Notes 1:
2: Applied potential to these ports must be VDD or less.
Port block diagram (4)
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4518 Group
Register A
A0
IAP3 instruction
(Note 1)
P30/INT0
(Note 2)
A0
OP3A instruction
D Q
T
(Note 3)
External 0 interrupt
Key-on wakeup input
Timer 1 count start synchronous circuit input
Period measurement circuit input
Register A
A1
External 0 interrupt circuit
IAP3 instruction
(Note 1)
P31/INT1
(Note 2)
A1
OP3A instruction
D Q
T
(Note 3)
External 1 interrupt
Key-on wakeup input
Timer 3 count start synchronous circuit input
External 1 interrupt circuit
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
3: As for details, refer to the external interrupt circuit structure.
Port block diagram (5)
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4518 Group
(Note 3)
Register A
Aj
IAP6 instruction
(Note 1)
Q2j
(Note 3)
Aj
OP6A instruction
P60/AIN0, P61/AIN1
(Note 2)
D Q
Q1
T
Decoder
Analog input
(Note 4)
Register A
Ak
IAP6 instruction
(Note 1)
Q22
P62/AIN2, P63/AIN3
(Note 2)
Ak
OP6A instruction
D Q
T
Q1
Decoder
Analog input
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
3: j represents bits 0 and 1.
4: k represents bits 2 and 3.
Port block diagram (6)
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4518 Group
I12
Falling
(Note 1)
0
One-sided edge
detection circuit
I11
0
P30/INT0
External 0
interrupt
Period measurement
circuit input
Timer 1 count start
synchronous circuit
EXF0
1
Rising
I13
Both edges
detection circuit
1
(Note 2)
Level detection circuit
K20
K21
0
Key-on wakeup
(Note 3)
Edge detection circuit
1
Skip decision
(SNZI0 instruction)
I22
Falling
(Note 1)
0
One-sided edge
detection circuit
I21
0
P31/INT1
External 1
interrupt
EXF1
1
Rising
I23
Both edges
detection circuit
1
(Note 2)
Level detection circuit
K22
(Note 3)
Edge detection circuit
Timer 3 count start
synchronous circuit
K23
0
Key-on wakeup
1
Skip decision
(SNZI1 instruction)
This symbol represents a parasitic diode on the port.
Notes 1:
2: I12 (I22) = 0: “L” level detected
I12 (I22) = 1: “H” level detected
3: I12 (I22) = 0: Falling edge detected
I12 (I22) = 1: Rising edge detected
Port block diagram (7)
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4518 Group
FUNCTION BLOCK OPERATIONS
CPU
<Carry>
(CY)
(1) Arithmetic logic unit (ALU)
(M(DP))
The arithmetic logic unit ALU performs 4-bit arithmetic such as 4bit data addition, comparison, AND operation, OR operation, and
bit manipulation.
ALU
Addition
(A)
<Result>
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation.
Carry flag CY is a 1-bit flag that is set to “1” when there is a carry
with the AMC instruction (Figure 1).
It is unchanged with both A n instruction and AM instruction. The
value of A0 is stored in carry flag CY with the RAR instruction (Figure 2).
Carry flag CY can be set to “1” with the SC instruction and cleared
to “0” with the RC instruction.
Fig. 1 AMC instruction execution example
<Set>
SC instruction
<Clear>
RC instruction
CY
A3 A2 A1 A0
<Rotation>
RAR instruction
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4-bit
data, and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data transfer
with register B used as the high-order 4 bits and register A as the
low-order 4 bits (Figure 3).
Register E is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value.
A0
CY A3 A2 A1
Fig. 2 RAR instruction execution example
Register B
TAB instruction
B3 B2 B1 B0
(4) Register D
Register A
A3 A2 A1 A0
TEAB instruction
Register D is a 3-bit register.
It is used to store a 7-bit ROM address together with register A and
is used as a pointer within the specified page when the TABP p,
BLA p, or BMLA p instruction is executed. Also, when the TABP p
instruction is executed, the high-order 2 bits of the reference data
in ROM is stored to the low-order 2 bits of register D, and the contents of the high-order 1 bit of register D is “0”. (Figure 4).
Register D is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value.
Register E E7 E6 E5 E4 E3 E2 E1 E0
TABE instruction
A3 A2 A1 A0
B3 B2 B1 B0
Register B
TBA instruction
Register A
Fig. 3 Registers A, B and register E
TABP p instruction
ROM
Specifying address
p6 p5
PCH
p4 p3 p2 p1 p0
PCL
DR2 DR1DR0 A3 A2 A1 A0
8
4
0
Low-order 4bits
Register A (4)
Middle-order 4 bits
Register B (4)
High-order 2 bits
Immediate field
value p
The contents of The contents of
register D
register A
Fig. 4 TABP p instruction execution example
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Register D (3)
High-order 1 bit of
register D is “0”.
4518 Group
(5) Stack registers (SKS) and stack pointer (SP)
Stack registers (SKs) are used to temporarily store the contents of
program counter (PC) just before branching until returning to the
original routine when;
• branching to an interrupt service routine (referred to as an interrupt service routine),
• performing a subroutine call, or
• executing the table reference instruction (TABP p).
Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers
is used respectively when using an interrupt service routine and
when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations
together. The contents of registers SKs are destroyed when 8 levels are exceeded.
The register SK nesting level is pointed automatically by 3-bit
stack pointer (SP). The contents of the stack pointer (SP) can be
transferred to register A with the TASP instruction.
Figure 5 shows the stack registers (SKs) structure.
Figure 6 shows the example of operation at subroutine call.
(6) Interrupt stack register (SDP)
Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the
contents of data pointer, carry flag, skip flag, register A, and register B just before an interrupt until returning to the original routine.
Unlike the stack registers (SKs), this register (SDP) is not used
when executing the subroutine call instruction and the table reference instruction.
Program counter (PC)
Executing BM
instruction
Executing RT
instruction
SK0
(SP) = 0
SK1
(SP) = 1
SK2
(SP) = 2
SK3
(SP) = 3
SK4
(SP) = 4
SK5
(SP) = 5
SK6
(SP) = 6
SK7
(SP) = 7
Stack pointer (SP) points “7” at reset or
returning from RAM back-up mode. It points “0”
by executing the first BM instruction, and the
contents of program counter is stored in SK0.
When the BM instruction is executed after eight
stack registers are used ((SP) = 7), (SP) = 0
and the contents of SK0 is destroyed.
Fig. 5 Stack registers (SKs) structure
(SP) ← 0
(SK0) ← 000116
(PC) ← SUB1
Main program
Subroutine
Address
(7) Skip flag
Skip flag controls skip decision for the conditional skip instructions
and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt
stack register (SDP) and the skip condition is retained.
SUB1 :
000016 NOP
NOP
·
·
·
RT
000116 BM SUB1
000216 NOP
(PC) ← (SK0)
(SP) ← 7
Note : Returning to the BM instruction execution
address with the RT instruction, and the BM
instruction becomes the NOP instruction.
Fig. 6 Example of operation at subroutine call
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4518 Group
(8) Program counter (PC)
Program counter (PC) is used to specify a ROM address (page and
address). It determines a sequence in which instructions stored in
ROM are read. It is a binary counter that increments the number of
instruction bytes each time an instruction is executed. However,
the value changes to a specified address when branch instructions,
subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed.
Program counter consists of PC H (most significant bit to bit 7)
which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address
(address 127) of a page, it specifies address 0 of the next page
(Figure 7).
Make sure that the PCH does not specify after the last page of the
built-in ROM.
Program counter
p6 p5 p4 p3 p2 p1 p0
a6 a5 a4 a3 a2 a1 a0
PCH
Specifying page
PCL
Specifying address
Fig. 7 Program counter (PC) structure
Data pointer (DP)
Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0
(9) Data pointer (DP)
Data pointer (DP) is used to specify a RAM address and consists
of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure
8).
Register Y is also used to specify the port D bit position.
When using port D, set the port D bit position to register Y certainly
and execute the SD, RD, or SZD instruction (Figure 9).
• Note
Register Z of data pointer is undefined after system is released
from reset.
Also, registers Z, X and Y are undefined in the RAM back-up. After
system is returned from the RAM back-up, set these registers.
Register Y (4)
Register X (4)
Specifying
RAM digit
Specifying RAM file
Specifying RAM file group
Register Z (2)
Fig. 8 Data pointer (DP) structure
Specifying bit position
Set
D3
0
0
0
D2
1
Register Y (4)
page 18 of 157
D0
1
Port D output latch
Fig. 9 SD instruction execution example
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D1
4518 Group
PROGRAM MEMORY (ROM)
The program memory is a mask ROM. 1 word of ROM is composed
of 10 bits. ROM is separated every 128 words by the unit of page
(addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 10 shows the ROM map of M34518M8/E8.
Table 1 ROM size and pages
Part number
M34518M2
M34518M4
M34518M6
M34518M8/E8
ROM (PROM) size
(✕ 10 bits)
2048 words
4096 words
6144 words
8192 words
Pages
9 8 7
000016
007F16
008016
00FF16
010016
017F16
018016
6 5 4
3 2 1
0
Page 0
Interrupt address page
Page 1
Subroutine special page
Page 2
Page 3
16 (0 to 15)
32 (0 to 31)
48 (0 to 47)
64 (0 to 63)
A part of page 1 (addresses 008016 to 00FF16) is reserved for interrupt addresses (Figure 11). When an interrupt occurs, the
address (interrupt address) corresponding to each interrupt is set
in the program counter, and the instruction at the interrupt address
is executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt
address.
Page 2 (addresses 010016 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from
any page with the 1-word instruction (BM). Subroutines extending
from page 2 to another page can also be called with the BM instruction when it starts on page 2.
ROM pattern (bits 9 to 0) of all addresses can be used as data areas with the TABP p instruction.
1FFF16
Page 63
Fig. 10 ROM map of M34518M8/E8
008016
9
8 7 6 5 4 3 2 1 0
External 0 interrupt address
008216
External 1 interrupt address
008416
Timer 1 interrupt address
008616
Timer 2 interrupt address
008816
Timer 3 interrupt address
008A16
Timer 4 interrupt address
008C16
A/D interrupt address
008E16
Serial I/O interrupt address
00FF16
Fig. 11 Page 1 (addresses 008016 to 00FF16) structure
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4518 Group
DATA MEMORY (RAM)
Table 2 RAM size
1 word of RAM is composed of 4 bits, but 1-bit manipulation (with
the SB j, RB j, and SZB j instructions) is enabled for the entire
memory area. A RAM address is specified by a data pointer. The
data pointer consists of registers Z, X, and Y. Set a value to the
data pointer certainly when executing an instruction to access
RAM (also, set a value after system returns from RAM back-up).
Table 2 shows the RAM size. Figure 12 shows the RAM map.
Part number
M34518M2/M4
M34518M6/M8/E8
RAM size
256 words ✕ 4 bits (1024 bits)
384 words ✕ 4 bits (1536 bits)
• Note
Register Z of data pointer is undefined after system is released
from reset.
Also, registers Z, X and Y are undefined in the RAM back-up. After
system is returned from the RAM back-up, set these registers.
RAM 384 words ✕ 4 bits (1536 bits)
Register Z
Register Y
Register X
M34518M6
M34518M8/E8
Z=0, X=0 to 15
Z=1, X=0 to 7
M34518M2/M4
Z=0, X=0 to 15
1
1
... ... 15 0 ... ...
5 6 7
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Fig. 12 RAM map
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0
0
...
2 3
6 7
page 20 of 157
384 words
256 words
4518 Group
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an individual
address (interrupt address) according to each interrupt source. An
interrupt occurs when the following 3 conditions are satisfied.
• An interrupt activated condition is satisfied (request flag = “1”)
• Interrupt enable bit is enabled (“1”)
• Interrupt enable flag is enabled (INTE = “1”)
Table 3 shows interrupt sources. (Refer to each interrupt request
flag for details of activated conditions.)
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to
“1” with the EI instruction and disabled when INTE flag is cleared to
“0” with the DI instruction. When any interrupt occurs, the INTE flag
is automatically cleared to “0,” so that other interrupts are disabled
until the EI instruction is executed.
(2) Interrupt enable bit
Use an interrupt enable bit of interrupt control registers V1 and V2
to select the corresponding interrupt or skip instruction.
Table 4 shows the interrupt request flag, interrupt enable bit and
skip instruction.
Table 5 shows the interrupt enable bit function.
Table 3 Interrupt sources
Priority
Interrupt name
level
1
External 0 interrupt
2
External 1 interrupt
3
Timer 1 interrupt
Level change of
INT0 pin
Level change of
INT1 pin
Timer 1 underflow
4
Timer 2 interrupt
Timer 2 underflow
5
Timer 3 interrupt
Timer 3 underflow
6
Timer 4 interrupt
Timer 4 underflow
7
A/D interrupt
8
Serial I/O interrupt
Completion of
A/D conversion
Completion of serial
I/O transmit/receive
Interrupt name
External 0 interrupt
External 1 interrupt
Timer 1 interrupt
When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to “1.” Each interrupt
request flag is cleared to “0” when either;
• an interrupt occurs, or
• the next instruction is skipped with a skip instruction.
Each interrupt request flag is set when the activated condition is
satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set
until a clear condition is satisfied.
Accordingly, an interrupt occurs when the interrupt disable state is
released while the interrupt request flag is set.
If more than one interrupt request flag is set when the interrupt disable state is released, the interrupt priority level is as follows
shown in Table 3.
Timer 2 interrupt
Timer 3 interrupt
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Interrupt
address
Address 0
in page 1
Address 2
in page 1
Address 4
in page 1
Address 6
in page 1
Address 8
in page 1
Address A
in page 1
Address C
in page 1
Address E
in page 1
Table 4 Interrupt request flag, interrupt enable bit and skip instruction
(3) Interrupt request flag
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Activated condition
Timer 4 interrupt
A/D interrupt
Serial I/O interrupt
Interrupt
request flag
Skip instruction
Interrupt
enable bit
EXF0
EXF1
T1F
T2F
T3F
T4F
ADF
SIOF
SNZ0
SNZ1
SNZT1
SNZT2
SNZT3
SNZT4
SNZAD
SNZSI
V10
V11
V12
V13
V20
V21
V22
V23
Table 5 Interrupt enable bit function
Interrupt enable bit Occurrence of interrupt
Enabled
1
Disabled
0
Skip instruction
Invalid
Valid
4518 Group
(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is as follows (Figure 14).
• Program counter (PC)
An interrupt address is set in program counter. The address to be
executed when returning to the main routine is automatically
stored in the stack register (SK).
• Interrupt enable flag (INTE)
INTE flag is cleared to “0” so that interrupts are disabled.
• Interrupt request flag
Only the request flag for the current interrupt source is cleared to
“0.”
• Data pointer, carry flag, skip flag, registers A and B
The contents of these registers and flags are stored automatically
in the interrupt stack register (SDP).
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address is executed after branching a data store sequence to stack register.
Write the branch instruction to an interrupt service routine at an interrupt address.
Use the RTI instruction to return from an interrupt service routine.
Interrupt enabled by executing the EI instruction is performed after
executing 1 instruction (just after the next instruction is executed).
Accordingly, when the EI instruction is executed just before the RTI
instruction, interrupts are enabled after returning the main routine.
(Refer to Figure 13)
Main
routine
• Stack register (SK)
The address of main routine to be
....................................................................................................
executed when returning
• Interrupt enable flag (INTE)
.................................................................. 0 (Interrupt disabled)
• Interrupt request flag (only the flag for the current interrupt
source) ................................................................................... 0
• Data pointer, carry flag, registers A and B, skip flag
........ Stored in the interrupt stack register (SDP) automatically
Fig. 14 Internal state when interrupt occurs
Activated
condition
INT0 pin interrupt
waveform input
•
•
•
•
EI
R TI
Interrupt is
enabled
Request flag Enable bit
(state retained)
V10
Address 0
in page 1
EXF1
V11
Address 2
in page 1
T1F
V12
Address 4
in page 1
Timer 2
underflow
T2F
V13
Address 6
in page 1
Timer 3
underflow
T3F
V20
Address 8
in page 1
Timer 4
underflow
T4F
V21
Address A
in page 1
A/D conversion
completed
ADF
V22
Address C
in page 1
SIOF
V23
Address E
in page 1
INT1 pin interrupt
waveform input
Serial I/O
transmit/
receive
completed
: Interrupt enabled state
: Interrupt disabled state
Fig. 13 Program example of interrupt processing
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Enable flag
EXF0
Timer 1
underflow
Interrupt
service routine
Interrupt
occurs
• Program counter (PC)
............................................................... Each interrupt address
Fig. 15 Interrupt system diagram
INTE
4518 Group
(6) Interrupt control registers
• Interrupt control register V1
Interrupt enable bits of external 0, external 1, timer 1 and timer 2
are assigned to register V1. Set the contents of this register
through register A with the TV1A instruction. The TAV1 instruction
can be used to transfer the contents of register V1 to register A.
• Interrupt control register V2
The timer 3, timer 4, A/D and serial I/O interrupt enable bit is assigned to register V2. Set the contents of this register through
register A with the TV2A instruction. The TAV2 instruction can be
used to transfer the contents of register V2 to register A.
Table 6 Interrupt control registers
Interrupt control register V1
V13
Timer 2 interrupt enable bit
V12
Timer 1 interrupt enable bit
V11
External 1 interrupt enable bit
V10
External 0 interrupt enable bit
at reset : 00002
0
1
0
1
0
1
0
1
Interrupt control register V2
V23
Serial I/O interrupt enable bit
V22
A/D interrupt enable bit
V21
Timer 4 interrupt enable bit
V20
Timer 3 interrupt enable bit
at reset : 00002
0
1
0
1
0
1
0
1
(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt enable bits (V10–V1 3, V20–V23), and interrupt request flag are “1.”
The interrupt actually occurs 2 to 3 machine cycles after the cycle
in which all three conditions are satisfied. The interrupt occurs after
3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle instructions (Refer to
Figure 16).
page 23 of 157
R/W
TAV1/TV1A
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
Interrupt disabled (SNZ1 instruction is valid)
Interrupt enabled (SNZ1 instruction is invalid)
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
Note: “R” represents read enabled, and “W” represents write enabled.
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at RAM back-up : 00002
at RAM back-up : 00002
Interrupt disabled (SNZSI instruction is valid)
Interrupt enabled (SNZSI instruction is invalid)
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid)
Interrupt disabled (SNZT4 instruction is valid)
Interrupt enabled (SNZT4 instruction is invalid)
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid)
R/W
TAV2/TV2A
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Fig. 16 Interrupt sequence
page 24 of 157
Timer 1,
Timer 2,
Timer 3,
Timer 4,
A/D and
Serial I/O
interrupts
External
interrupt
T1
T2
T3
EI instruction execution cycle
T1
T2
T3
T2
T3
Interrupt enabled state
T1
T2
T1
T2
The program starts
from the interrupt
address.
Retaining level of system
clock for 4 periods or more
is necessary.
Interrupt disabled state
Flag cleared
T3
2 to 3 machine cycles
(Notes 1, 2)
Interrupt activated
condition is satisfied.
T1
Notes 1: The address is stacked to the last cycle.
2: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.
T1F,T2F,T3F,T4F,
ADF,SIOF
EXF0,EXF1
INT0,INT1
Interrupt enable
flag (INTE)
System clock
(STCK)
1 machine cycle
● When an interrupt request flag is set after its interrupt is enabled (Note 1)
4518 Group
4518 Group
EXTERNAL INTERRUPTS
The 4518 Group has the external 0 interrupt and external 1 interrupt.
An external interrupt request occurs when a valid waveform is input
to an interrupt input pin (edge detection).
The external interrupt can be controlled with the interrupt control
registers I1 and I2.
Table 7 External interrupt activated conditions
Name
External 0 interrupt
Input pin
Valid waveform
selection bit
I11
I12
Activated condition
P30/INT0
When the next waveform is input to P30/INT0 pin
• Falling waveform (“H”→“L”)
• Rising waveform (“L”→“H”)
• Both rising and falling waveforms
External 1 interrupt
P31/INT1
I21
I22
When the next waveform is input to P31/INT1 pin
• Falling waveform (“H”→“L”)
• Rising waveform (“L”→“H”)
• Both rising and falling waveforms
I12
Falling
(Note 1)
0
One-sided edge
detection circuit
I11
0
P30/INT0
External 0
interrupt
Period measurement
circuit input
Timer 1 count start
synchronous circuit
EXF0
1
Rising
I13
Both edges
detection circuit
1
(Note 2)
Level detection circuit
K20
K21
0
Key-on wakeup
(Note 3)
Edge detection circuit
1
Skip decision
(SNZI0 instruction)
I22
Falling
(Note 1)
0
One-sided edge
detection circuit
I21
0
P31/INT1
External 1
interrupt
EXF1
1
Rising
I23
Both edges
detection circuit
1
(Note 2)
Level detection circuit
K22
(Note 3)
Edge detection circuit
Timer 3 count start
synchronous circuit
K23
0
Key-on wakeup
1
Skip decision
(SNZI1 instruction)
This symbol represents a parasitic diode on the port.
Notes 1:
2: I12 (I22) = 0: “L” level detected
I12 (I22) = 1: “H” level detected
3: I12 (I22) = 0: Falling edge detected
I12 (I22) = 1: Rising edge detected
Fig. 17 External interrupt circuit structure
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4518 Group
(1) External 0 interrupt request flag (EXF0)
(2) External 1 interrupt request flag (EXF1)
External 0 interrupt request flag (EXF0) is set to “1” when a valid
waveform is input to P30/INT0 pin.
The valid waveforms causing the interrupt must be retained at their
level for 4 clock cycles or more of the system clock (Refer to Figure
16).
The state of EXF0 flag can be examined with the skip instruction
(SNZ0). Use the interrupt control register V1 to select the interrupt
or the skip instruction. The EXF0 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip
instruction.
External 1 interrupt request flag (EXF1) is set to “1” when a valid
waveform is input to P31/INT1 pin.
The valid waveforms causing the interrupt must be retained at their
level for 4 clock cycles or more of the system clock (Refer to Figure
16).
The state of EXF1 flag can be examined with the skip instruction
(SNZ1). Use the interrupt control register V1 to select the interrupt
or the skip instruction. The EXF1 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip
instruction.
• External 0 interrupt activated condition
External 0 interrupt activated condition is satisfied when a valid
waveform is input to P30/INT0 pin.
The valid waveform can be selected from rising waveform, falling
waveform or both rising and falling waveforms. An example of
how to use the external 0 interrupt is as follows.
• External 1 interrupt activated condition
External 1 interrupt activated condition is satisfied when a valid
waveform is input to P31/INT1 pin.
The valid waveform can be selected from rising waveform, falling
waveform or both rising and falling waveforms. An example of
how to use the external 1 interrupt is as follows.
➀ Set the bit 3 of register I1 to “1” for the INT0 pin to be in the input enabled state.
➁ Select the valid waveform with the bits 1 and 2 of register I1.
➂ Clear the EXF0 flag to “0” with the SNZ0 instruction.
➃ Set the NOP instruction for the case when a skip is performed
with the SNZ0 instruction.
➄ Set both the external 0 interrupt enable bit (V10) and the INTE
flag to “1.”
➀ Set the bit 3 of register I2 to “1” for the INT1 pin to be in the input enabled state.
➁ Select the valid waveform with the bits 1 and 2 of register I2.
➂ Clear the EXF1 flag to “0” with the SNZ1 instruction.
➃ Set the NOP instruction for the case when a skip is performed
with the SNZ1 instruction.
➄ Set both the external 1 interrupt enable bit (V1 1) and the INTE
flag to “1.”
The external 0 interrupt is now enabled. Now when a valid waveform is input to the P30/INT0 pin, the EXF0 flag is set to “1” and the
external 0 interrupt occurs.
The external 1 interrupt is now enabled. Now when a valid waveform is input to the P31/INT1 pin, the EXF1 flag is set to “1” and the
external 1 interrupt occurs.
Rev.3.01 2005.06.15
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page 26 of 157
4518 Group
(3) External interrupt control registers
• Interrupt control register I1
Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the
TI1A instruction. The TAI1 instruction can be used to transfer the
contents of register I1 to register A.
• Interrupt control register I2
Register I2 controls the valid waveform for the external 1 interrupt. Set the contents of this register through register A with the
TI2A instruction. The TAI2 instruction can be used to transfer the
contents of register I2 to register A.
Table 8 External interrupt control register
Interrupt control register I1
I13
I12
I11
I10
INT0 pin input control bit
Interrupt valid waveform for INT0 pin/
return level selection bit
INT0 pin edge detection circuit control bit
INT0 pin Timer 1 count start synchronous
circuit selection bit
at reset : 00002
0
1
0
1
0
1
0
1
Interrupt control register I2
I23
I22
I21
I20
INT1 pin input control bit (Note 2)
Interrupt valid waveform for INT1 pin/
return level selection bit (Note 2)
INT1 pin edge detection circuit control bit
INT1 pin Timer 3 count start synchronous
circuit selection bit
0
1
0
1
0
1
INT0 pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI0
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI0
instruction)
One-sided edge detected
Both edges detected
Timer 1 count start synchronous circuit not selected
Timer 1 count start synchronous circuit selected
at RAM back-up : state retained
page 27 of 157
R/W
TAI2/TI2A
INT1 pin input disabled
INT1 pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI1
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI1
instruction)
One-sided edge detected
Both edges detected
Timer 3 count start synchronous circuit not selected
Timer 3 count start synchronous circuit selected
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12, I13 I22 and I23 are changed, the external interrupt request flag (EXF0, EXF1) may be set.
Rev.3.01 2005.06.15
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R/W
TAI1/TI1A
INT0 pin input disabled
at reset : 00002
0
1
at RAM back-up : state retained
4518 Group
(4) Notes on External 0 interrupt
• Depending on the input state of the P30/INT0 pin, the external 0
interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to
Figure 18 ➀) and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction (refer to Figure 18 ➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 18 ➂).
• Depending on the input state of the P3 0/INT0 pin, the external 0
interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to
Figure 20➀) and then, change the bit 2 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction (refer to Figure 20➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 20➂).
•••
•••
➀ Note [1] on bit 3 of register I1
When the input of the INT0 pin is controlled with the bit 3 of register I1 in software, be careful about the following notes.
➂ Note on bit 2 of register I1
When the interrupt valid waveform of the P3 0 /INT0 pin is
changed with the bit 2 of register I1 in software, be careful about
the following notes.
LA
4
TV1A
LA
8
TI1A
NOP
SNZ0
LA
4
TV1A
LA
12
TI1A
NOP
SNZ0
•••
NOP
; (✕✕✕02)
; The SNZ0 instruction is valid ........... ➀
; (✕1✕✕2)
; Interrupt valid waveform is changed
........................................................... ➁
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... ➂
•••
NOP
; (✕✕✕02)
; The SNZ0 instruction is valid ........... ➀
; (1✕✕✕2)
; Control of INT0 pin input is changed
........................................................... ➁
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... ➂
✕ : these bits are not used here.
✕ : these bits are not used here.
Fig. 18 External 0 interrupt program example-1
➁ Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared to “0”, the RAM back-up
mode is selected and the input of INT0 pin is disabled, be careful
about the following notes.
•••
• When the input of INT0 pin is disabled (register I13 = “0”), set the
key-on wakeup function to be invalid (register K20 = “0”) before
system enters to the RAM back-up mode. (refer to Figure 19➀).
; (✕✕✕02)
; Input of INT0 key-on wakeup invalid .. ➀
; RAM back-up
•••
LA
0
TK2A
DI
EPOF
POF
✕ : these bits are not used here.
Fig. 19 External 0 interrupt program example-2
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page 28 of 157
Fig. 20 External 0 interrupt program example-3
4518 Group
(5) Notes on External 1 interrupt
➂ Note on bit 2 of register I2
When the interrupt valid waveform of the P3 1 /INT1 pin is
changed with the bit 2 of register I2 in software, be careful about
the following notes.
• Depending on the input state of the P31/INT1 pin, the external 1
interrupt request flag (EXF1) may be set when the bit 3 of register I2 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to
Figure 21➀) and then, change the bit 3 of register I2.
In addition, execute the SNZ1 instruction to clear the EXF1 flag to
“0” after executing at least one instruction (refer to Figure 21➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to Figure 21➂).
• Depending on the input state of the P31/INT1 pin, the external 1
interrupt request flag (EXF1) may be set when the bit 2 of register I2 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to
Figure 23➀) and then, change the bit 2 of register I2.
In addition, execute the SNZ1 instruction to clear the EXF1 flag to
“0” after executing at least one instruction (refer to Figure 23➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to Figure 23➂).
•••
•••
➀ Note [1] on bit 3 of register I2
When the input of the INT1 pin is controlled with the bit 3 of register I2 in software, be careful about the following notes.
LA
4
TV1A
LA
8
TI2A
NOP
SNZ1
LA
4
TV1A
LA
12
TI2A
NOP
SNZ1
•••
NOP
; (✕✕0✕2)
; The SNZ1 instruction is valid ........... ➀
; (✕1✕✕2)
; Interrupt valid waveform is changed
........................................................... ➁
; The SNZ1 instruction is executed
(EXF1 flag cleared)
........................................................... ➂
•••
NOP
; (✕✕0✕2)
; The SNZ1 instruction is valid ........... ➀
; (1✕✕✕2)
; Control of INT1 pin input is changed
........................................................... ➁
; The SNZ1 instruction is executed
(EXF1 flag cleared)
........................................................... ➂
✕ : these bits are not used here.
✕ : these bits are not used here.
Fig. 21 External 1 interrupt program example-1
➁ Note [2] on bit 3 of register I2
When the bit 3 of register I2 is cleared to “0”, the RAM back-up
mode is selected and the input of INT1 pin is disabled, be careful
about the following notes.
•••
• When the input of INT1 pin is disabled (register I23 = “0”), set the
key-on wakeup function to be invalid (register K22 = “0”) before
system enters to the RAM back-up mode. (refer to Figure 22➀).
; (✕0✕✕2)
; Input of INT1 key-on wakeup invalid .. ➀
; RAM back-up
•••
LA
0
TK2A
DI
EPOF
POF
✕ : these bits are not used here.
Fig. 22 External 1 interrupt program example-2
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page 29 of 157
Fig. 23 External 1 interrupt program example-3
4518 Group
TIMERS
The 4518 Group has the following timers.
• Programmable timer
The programmable timer has a reload register and enables the
frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt
request flag is set to “1,” new data is loaded from the reload register, and count continues (auto-reload function).
• Fixed dividing frequency timer
The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to “1” after every n
count of a count pulse.
FF16
n : Counter initial value
Count starts
Reload
Reload
The contents of counter
n
1st underflow
2nd underflow
0016
Time
n+1 count
n+1 count
Timer interrupt “1”
“0”
request flag
An interrupt occurs or
a skip instruction is executed.
Fig. 24 Auto-reload function
The 4518 Group timer consists of the following circuits.
• Prescaler : 8-bit programmable timer
• Timer 1 : 8-bit programmable timer
• Timer 2 : 8-bit programmable timer
• Timer 3 : 8-bit programmable timer
• Timer 4 : 8-bit programmable timer
• Watchdog timer : 16-bit fixed dividing frequency timer
(Timers 1, 2, 3, and 4 have the interrupt function, respectively)
Prescaler and timers 1, 2, 3, and 4 can be controlled with the timer
control registers PA, W1 to W6. The watchdog timer is a free
counter which is not controlled with the control register.
Each function is described below.
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page 30 of 157
4518 Group
Table 9 Function related timers
Prescaler
8-bit programmable
• Instruction clock (INSTCK)
Frequency
dividing ratio
1 to 256
Timer 1
binary down counter
8-bit programmable
• Instruction clock (INSTCK)
1 to 256
Circuit
Count source
Structure
(link to INT0 input)
• Prescaler output (ORCLK)
• XIN input
(period/pulse width
• CNTR0 input
binary down counter
Use of output signal
Control
register
PA
• Timer 1, 2, 3, amd 4 count sources
• Timer 2 count source
W1
• CNTR0 output
W2
• Timer 1 interrupt
W5
• Timer 3 count source
W2
measurement function)
Timer 2
8-bit programmable
binary down counter
• System clock (STCK)
1 to 256
• Prescaler output (ORCLK)
• CNTR0 output
• Timer 1 underflow
(T1UDF)
• Timer 2 interrupt
• PWM output (PWMOUT)
Timer 3
8-bit programmable
• PWM output (PWMOUT)
binary down counter
(link to INT1 input)
• Prescaler output (ORCLK)
1 to 256
• CNTR1 output control
• Timer 3 interrupt
W3
1 to 256
• Timer 2, 3 count source
W4
• Timer 2 underflow
(T2UDF)
• CNTR1 input
Timer 4
8-bit programmable
• XIN input
binary down counter
• Prescaler output (ORCLK)
Watchdog
(PWM output function)
• Instruction clock (INSTCK)
16-bit fixed dividing
timer
frequency
Rev.3.01 2005.06.15
REJ03B0008-0301
• CNTR1 output
• Timer 4 interrupt
65534
• System reset (count twice)
• WDF flag decision
page 31 of 157
4518 Group
MR3, MR2
11
Division circuit
Divided by 8
On-chip oscillator
Multiplexer
RC oscillation
Quartz-crystal
oscillation
Internal clock
generating circuit
(divided by 3)
01
Divided by 2
1
Ceramic resonance
XIN
10
Divided by 4
MR0
System clock (STCK)
00
Instruction clock
(INSTCK)
0
(CMCK,
CRCK,
CYCK)
(Note 1)
Prescaler (8)
PA0
ORCLK
Reload register RPS (8)
(TPSAB)
(TABPS)
(TPSAB)
Register B
W60
0
Port D6 output
W23
0
1/2
1
1/2
1
(TPSAB)
(TABPS)
Register A
T1UDF
T2UDF
W51, W50
On-chip oscillator
00
1/16
01
W62
0
D6/CNTR0
One-period
generation circuit
10
11
W52
1
I12
P30/INT0
0
One-sided edge
detection circuit
I11
0
Both edges
detection circuit
1
(Note 2)
I13
1
I10
1
S Q
I10
0
R
W13
W52
1
T1UDF
0
W11, W10 (Note 3)
INSTCK
ORCLK
XIN
00
W52
1
01
10
0
Timer 1 (8)
T1F
11
Reload register R1 (8)
W12
(T1AB)
STCK
ORCLK
T1UDF
PWMOUT
(TAB1)
W21, W20
00
(TR1AB)
(T1AB)
(T1AB)
(TAB1)
Timer 1 underflow signal (
T1UDF)
Register B Register A
01
10
Timer 2 (8)
T2F
11
Timer 2
interrupt
Reload register R2 (8)
W22
(T2AB)
(TAB2)
(T2AB)
(T2AB)
Register B Register A
TR1AB: This instruction is used to transfer the contents of
register A and register B to only reload register R1.
PWMOUT: PWM output signal (from timer 4 output unit)
Data is set automatically from each reload
register when timer underflows
(auto-reload function).
Fig. 25 Timer structure (1)
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REJ03B0008-0301
Timer 1
interrupt
page 32 of 157
(TAB2)
Timer 2 underflow signal (T2UDF)
Notes 1: When CMCK instruction is executed, ceramic resonance is selected.
When CRCK instruction is executed, RC oscillation is selected.
When CYCK instruction is executed, quartz-crystal oscillator is selected.
2: Timer 1 count start synchronous circuit is set by the valid edge of P30/INT0 pin
selected by bits 1 (I11) and 2 (I12) of register I1.
3: XIN cannot be used for the count source when bit 1 (MR1) of register MR is set
to “1” and f(XIN) oscillation is stopped.
4518 Group
I22
P31/INT1
0
I23
1
One-sided edge
detection circuit
I21
0
Both edges
detection circuit
1
(Note 4)
S Q
I20
I20
1
0
R
W33
T3UDF
W31, W30
00
PWMOUT
Timer 3 (8)
01
ORCLK
10
T2UDF
Reload register R3 (8)
11
W63
0
D7/CNTR1
(T3AB)
(TAB3)
W32
(TR3AB)
(T3AB)
(T3AB)
Register B Register A
1
W43
0
Timer 3
interrupt
T3F
(TAB3)
Timer 3
underflow signal
(T3UDF)
Port D7 output
1
T3UDF
Q D
PWMOD
W32
W61
R T
Register B Register A
(T4HAB)
W40
0
XIN
ORCLK
1/2
T Q
Reload register R4H (8)
(Note 3)
Reload control circuit
“H” interval expansion
Timer 4 (8)
1
W42
1
T4F
0
W41
R
PWMOUT
W43
Timer 4
interrupt
(T4R4L)
Reload register R4L (8)
(T4AB)
(TAB4)
(T4AB)
(T4AB)
(TAB4)
Register B Register A
INSTCK
Watchdog timer
(Note 5)
1 - - - - - - - - - - - - - - 16
S
Q
WDF1
WRST instruction
R
RESET signal
S
(Note 7)
Q
WEF
DWDT instruction R
+
(Note 6)
WRST instruction
D
Q
T
R
Watchdog reset signal
RESET signal
TR3AB: This instruction is used to transfer the contents of
Notes 3: XIN cannot be used for the count source when bit 1 (MR1) of
register A and register B to only reload register R3.
register MR is set to “1” and f(XIN) oscillation is stopped.
T4R4L: This instruction is used to transfer the contents of
reload register R4L to timer 4.
4: Timer 3 count start synchronous circuit is set by the valid edge
INSTCK: Instruction clock (system clock divided by 3)
of P31/INT1 pin selected by bits 1 (I21) and 2 (I22) of register I2.
ORCLK: Prescaler output (instruction clock divided by 1 to 256)
Data is set automatically from each reload
register when timer underflows
(auto-reload function).
Fig. 26 Timer structure (2)
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page 33 of 157
5: Flag WDF1 is cleared to “0” and the next instruction is skipped
when the WRST instruction is executed while flag WDF1 = “1”.
The next instruction is not skipped even when the WRST
instruction is executed while flag WDF1 = “0”.
6: Flag WEF is cleared to “0” and watchdog timer reset does not
occur when the DWDT instruction and WRST instruction are
executed continuously.
7: The WEF flag is set to “1” at system reset or RAM back-up
mode.
4518 Group
Table 10 Timer related registers
Timer control register PA
PA0
Prescaler control bit
0
1
Timer control register W1
W13
Timer 1 count auto-stop circuit selection
bit (Note 2)
W12
Timer 1 control bit
W11
Timer 1 count source selection bits
W10
CNTR0 output signal selection bit
W22
Timer 2 control bit
W21
Timer 2 count source selection bits
W20
Timer 3 count auto-stop circuit selection
bit (Note 3)
W32
Timer 3 control bit
W31
Timer 3 count source selection bits
W30
at RAM back-up : state retained
R/W
TAW1/TW1A
0
1
0
1
Timer 1 count auto-stop circuit not selected
Timer 1 count auto-stop circuit selected
Stop (state retained)
Operating
W11 W10
Count source
0
Instruction clock (INSTCK)
0
0
Prescaler output (ORCLK)
1
1
XIN input
0
1
CNTR0 input
1
at reset : 00002
at RAM back-up : state retained
Timer 1 underflow signal divided by 2 output
Timer 2 underflow signal divided by 2 output
Stop (state retained)
Operating
W21 W20
Count source
0
System clock (STCK)
0
0
Prescaler output (ORCLK)
1
1
Timer 1 underflow signal (T1UDF)
0
1
PWM signal (PWMOUT)
1
at reset : 00002
at RAM back-up : state retained
0
1
0
1
Timer 3 count auto-stop circuit not selected
Timer 3 count auto-stop circuit selected
Stop (state retained)
Operating
W31 W30
Count source
0
PWM signal (PWMOUT)
0
0
Prescaler output (ORCLK)
1
1
Timer 2 underflow signal (T2UDF)
0
1
CNTR1 input
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”).
3: This function is valid only when the timer 3 count start synchronous circuit is selected (I20=“1”).
Rev.3.01 2005.06.15
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page 34 of 157
R/W
TAW2/TW2A
0
1
0
1
Timer control register W3
W33
W
TPAA
Stop (state initialized)
Operating
at reset : 00002
Timer control register W2
W23
at RAM back-up : 02
at reset : 02
R/W
TAW3/TW3A
4518 Group
Timer control register W4
W43
D7/CNTR1 pin function selection bit
W42
PWM signal
“H” interval expansion function control bit
W41
Timer 4 control bit
W40
Timer 4 count source selection bit
at reset : 00002
0
1
0
1
0
1
0
1
Timer control register W5
W53
Not used
W52
Period measurement circuit control bit
W51
Signal for period measurement selection
bits
W50
W63
CNTR1 pin input count edge selection bit
0
1
0
1
W62
CNTR0 pin input count edge selection bit
W61
CNTR1 output auto-control circuit
selection bit
W60
D6/CNTR0 pin function selection bit
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page 35 of 157
R/W
TAW5/TW5A
Stop
Operating
Count source
On-chip oscillator (f(RING/16))
CNTR0 pin input
INT0 pin input
Not available
at reset : 00002
Note: “R” represents read enabled, and “W” represents write enabled.
at RAM back-up : state retained
This bit has no function, but read/write is enabled.
W51 W50
0
0
0
1
1
0
1
1
0
1
0
1
0
1
0
1
R/W
TAW4/TW4A
D7 (I/O) / CNTR1 (input)
CNTR1 (I/O) / D7 (input)
PWM signal “H” interval expansion function invalid
PWM signal “H” interval expansion function valid
Stop (state retained)
Operating
XIN input
Prescaler output (ORCLK) divided by 2
at reset : 00002
Timer control register W6
at RAM back-up : 00002
at RAM back-up : state retained
Falling edge
Rising edge
Falling edge
Rising edge
CNTR1 output auto-control circuit not selected
CNTR1 output auto-control circuit selected
D6 (I/O) / CNTR0 (input)
CNTR0 (I/O) /D6 (input)
R/W
TAW6/TW6A
4518 Group
(1) Timer control registers
(2) Prescaler
• Timer control register PA
Register PA controls the count operation of prescaler. Set the
contents of this register through register A with the TPAA instruction.
• Timer control register W1
Register W1 controls the selection of timer 1 count auto-stop circuit, and the count operation and count source of timer 1. Set the
contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents
of register W1 to register A.
• Timer control register W2
Register W2 controls the selection of CNTR0 output, and the
count operation and count source of timer 2. Set the contents of
this register through register A with the TW2A instruction. The
TAW2 instruction can be used to transfer the contents of register
W2 to register A.
• Timer control register W3
Register W3 controls the selection of the count operation and
count source of timer 3 count auto-stop circuit. Set the contents
of this register through register A with the TW3A instruction. The
TAW3 instruction can be used to transfer the contents of register
W3 to register A.
• Timer control register W4
Register W4 controls the D7/CNTR1 output, the expansion of “H”
interval of PWM output, and the count operation and count
source of timer 4. Set the contents of this register through register A with the TW4A instruction. The TAW4 instruction can be
used to transfer the contents of register W4 to register A.
• Timer control register W5
Register W5 controls the period measurement circuit and target
signal for period measurement. Set the contents of this register
through register A with the TW5A instruction. The TAW5 instruction can be used to transfer the contents of register W5 to
register A.
• Timer control register W6
Register W6 controls the count edges of CNTR0 pin and CNTR1
pin, selection of CNTR1 output auto-control circuit and the D6/
CNTR0 pin function. Set the contents of this register through register A with the TW6A instruction. The TAW6 instruction can be
used to transfer the contents of register W6 to register A..
Prescaler is an 8-bit binary down counter with the prescaler reload
register PRS. Data can be set simultaneously in prescaler and the
reload register RPS with the TPSAB instruction. Data can be read
from reload register RPS with the TABPS instruction.
Stop counting and then execute the TPSAB or TABPS instruction
to read or set prescaler data.
Prescaler starts counting after the following process;
➀ set data in prescaler, and
➁ set the bit 0 of register PA to “1.”
When a value set in reload register RPS is n, prescaler divides the
count source signal by n + 1 (n = 0 to 255).
Count source for prescaler is the instruction clock (INSTCK).
Once count is started, when prescaler underflows (the next count
pulse is input after the contents of prescaler becomes “0”), new
data is loaded from reload register RPS, and count continues
(auto-reload function).
The output signal (ORCLK) of prescaler can be used for timer 1, 2,
3, and 4 count sources.
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(3) Timer 1 (interrupt function)
Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). Data can be set simultaneously in timer 1 and the reload
register (R1) with the T1AB instruction. Data can be written to reload register (R1) with the TR1AB instruction. Data can be read
from timer 1 with the TAB1 instruction.
Stop counting and then execute the T1AB or TAB1 instruction to
read or set timer 1 data.
When executing the TR1AB instruction to set data to reload register R1 while timer 1 is operating, avoid a timing when timer 1
underflows.
Timer 1 starts counting after the following process;
➀ set data in timer 1
➁ set count source by bits 0 and 1 of register W1, and
➂ set the bit 2 of register W1 to “1.”
When a value set in reload register R1 is n, timer 1 divides the
count source signal by n + 1 (n = 0 to 255).
Once count is started, when timer 1 underflows (the next count
pulse is input after the contents of timer 1 becomes “0”), the timer
1 interrupt request flag (T1F) is set to “1,” new data is loaded from
reload register R1, and count continues (auto-reload function).
INT0 pin input can be used as the start trigger for timer 1 count operation by setting the bit 0 of register I1 to “1.”
Also, in this time, the auto-stop function by timer 1 underflow can
be performed by setting the bit 3 of register W1 to “1.”
Timer 1 underflow signal divided by 2 can be output from CNTR0
pin by clearing bit 3 of register W2 to “0” and setting bit 0 of register W6 to “1”.
The period measurement circuit starts operating by setting bit 2 of
register W5 to “1” and timer 1 is used to count the one-period of the
target signal for the period measurement. In this time, the timer 1
interrupt request flag (T1F) is not set by the timer 1 underflow signal, it is the flag for detecting the completion of period
measurement.
4518 Group
(4) Timer 2 (interrupt function)
(6) Timer 4 (interrupt function)
Timer 2 is an 8-bit binary down counter with the timer 2 reload register (R2). Data can be set simultaneously in timer 2 and the reload
register (R2) with the T2AB instruction. Data can be read from
timer 2 with the TAB2 instruction. Stop counting and then execute
the T2AB or TAB2 instruction to read or set timer 2 data.
Timer 2 starts counting after the following process;
➀ set data in timer 2,
➁ select the count source with the bits 0 and 1 of register W2, and
➂ set the bit 2 of register W2 to “1.”
Timer 4 is an 8-bit binary down counter with two timer 4 reload registers (R4L, R4H). Data can be set simultaneously in timer 4 and
the reload register R4L with the T4AB instruction. Data can be set
in the reload register R4H with the T4HAB instruction. The contents
of reload register R4L set with the T4AB instruction can be set to
timer 4 again with the T4R4L instruction. Data can be read from
timer 4 with the TAB4 instruction.
Stop counting and then execute the T4AB or TAB4 instruction to
read or set timer 4 data.
When executing the T4HAB instruction to set data to reload register R4H while timer 4 is operating, avoid a timing when timer 4
underflows.
Timer 4 starts counting after the following process;
➀ set data in timer 4
➁ set count source by bit 0 of register W4, and
➂ set the bit 1 of register W4 to “1.”
When a value set in reload register R2 is n, timer 2 divides the
count source signal by n + 1 (n = 0 to 255).
Once count is started, when timer 2 underflows (the next count
pulse is input after the contents of timer 2 becomes “0”), the timer
2 interrupt request flag (T2F) is set to “1,” new data is loaded from
reload register R2, and count continues (auto-reload function).
Timer 2 underflow signal divided by 2 can be output from CNTR0
pin by setting bit 3 of register W2 to “1” and setting bit 0 of register
W6 to “1”.
(5) Timer 3 (interrupt function)
Timer 3 is an 8-bit binary down counter with the timer 3 reload register (R3). Data can be set simultaneously in timer 3 and the reload
register (R3) with the T3AB instruction. Data can be written to reload register (R3) with the TR3AB instruction. Data can be read
from timer 3 with the TAB3 instruction.
Stop counting and then execute the T3AB or TAB3 instruction to
read or set timer 3 data.
When executing the TR3AB instruction to set data to reload register R3 while timer 3 is operating, avoid a timing when timer 3
underflows.
Timer 3 starts counting after the following process;
➀ set data in timer 3
➁ set count source by bits 0 and 1 of register W3, and
➂ set the bit 2 of register W3 to “1.”
When a value set in reload register R3 is n, timer 3 divides the
count source signal by n + 1 (n = 0 to 255).
Once count is started, when timer 3 underflows (the next count
pulse is input after the contents of timer 3 becomes “0”), the timer
3 interrupt request flag (T3F) is set to “1,” new data is loaded from
reload register R3, and count continues (auto-reload function).
INT1 pin input can be used as the start trigger for timer 3 count operation by setting the bit 0 of register I2 to “1.”
Also, in this time, the auto-stop function by timer 3 underflow can
be performed by setting the bit 3 of register W3 to “1.”
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When a value set in reload register R4L is n, timer 4 divides the
count source signal by n + 1 (n = 0 to 255).
Once count is started, when timer 4 underflows (the next count
pulse is input after the contents of timer 4 becomes “0”), the timer
4 interrupt request flag (T4F) is set to “1,” new data is loaded from
reload register R4L, and count continues (auto-reload function).
The PWM signal generated by timer 4 can be output from CNTR1
pin by setting bit 3 of the timer control register W4 to “1”.
Timer 4 can control the PWM output to CNTR1 pin with timer 3 by
setting bit 1 of the timer control register W6 to “1”.
4518 Group
When a period measurement circuit is used, clear bit 0 of register I1 to “0”, and set a timer 1 count start synchronous circuit to
be “not selected”.
Start timer operation immediately after operation of a period
measurement circuit is started.
When the target edge for measurement is input until timer operation is started from the operation of period measurement circuit is
started, the count operation is not executed until the timer operation becomes valid. Accordingly, be careful of count data.
When data is read from timer, stop the timer and clear bit 2 of
register W5 to “0” to stop the period measurement circuit, and
then execute the data read instruction.
Depending on the state of timer 1, the timer 1 interrupt request
flag (T1F) may be set to “1” when the period measurement circuit is stopped by clearing bit 2 of register W5 to “0”. In order to
avoid the occurrence of an unexpected interrupt, clear the bit 2 of
register V1 to “0” (refer to Figure 27➀) and then, stop the bit 2 of
register W5 to “0” to stop the period measurement circuit.
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•••
Timer 1 has the period measurement circuit which performs timer
count operation synchronizing with one cycle of the signal divided by 16 of an on-chip oscillator, D6/CNTR0 pin input, or P30/
INT0 pin input (one cycle, “H”, or “L” pulse width at the case of a
P30/INT0 pin input).
When the target signal for period measurement is set by bits 0
and 1 of register W5, a period measurement circuit is started by
setting the bit 2 of register W5 to “1”.
Then, if a XIN input is set as the count source of a timer 1 and the
bit 2 of register W1 is set to “1”, timer 1 starts operation.
Timer 1 starts operation synchronizing with the falling edge of the
target signal for period measurement, and stops count operation
synchronizing with the next falling edge (one-period generation
circuit).
When selecting D6/CNTR0 pin input as target signal for period
measurement, the period measurement synchronous edge can
be changed into a rising edge by setting the bit 2 of register W6
to “1”.
When selecting P3 0/INT0 pin input as target signal for period
measurement, period measurement synchronous edge can be
changed into a rising edge by setting the bit 2 of register I1 to “1”.
A timer 1 interrupt request flag (T1F) is set to “1” after completing
measurement operation.
When a period measurement circuit is set to be operating, timer
1 interrupt request flag (T1F) is not set by timer 1 underflow signal, but turns into a flag which detects the completion of period
measurement.
In addition, a timer 1 underflow signal can be used as timer 2
count source.
Once period measurement operation is completed, even if period
measurement valid edge is input next, timer 1 is in a stop state
and measurement data is held.
When a period measurement circuit is used again, stop a period
measurement circuit at once by setting the bit 2 of register W5 to
“0”, and change a period measurement circuit into a state of operation by setting the bit 2 of register W5 to “1” again.
In addition, execute the SNZT1 instruction to clear the T1F flag
after executing at least one instruction (refer to Figure 27➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZT1 instruction (refer to Figure 27➂).
LA
0
TV1A
LA
0
TW5A
NOP
SNZT1
NOP
; (✕0✕✕2)
; The SNZT1 instruction is valid ........ ➀
; (✕0✕✕2)
; Period measurement circuit stop
........................................................... ➁
; The SNZT1 instruction is executed
(T1F flag cleared)
........................................................... ➂
•••
(7) Period measurement function (Timer 1,
period measurement circuit)
✕ : these bits are not used here.
Fig. 27 Period measurement circuit program example
When a period measurement circuit is used, select the sufficiently higher-speed frequency than the signal for measurement
for the count source of a timer 1.
When the target signal for period measurement is D6/CNTR0 pin
input, do not select D6/CNTR0 pin input as timer 1 count source.
(The XIN input is recommended as timer 1 count source at the
time of period measurement circuit use.)
(8) Pulse width measurement function (timer
1, period measurement circuit)
A period measurement circuit can measure “H” pulse width (from
rising to falling) or “L” pulse width (from falling to rising) of P30/
INT0 pin input (pulse width measurement function) when the following is set;
• Set the bit 0 of register W5 to “0”, and set a bit 1 to “1” (target
for period measurement circuit: 30/INT0 pin input).
• Set the bit 1 of register I1 to “1” (INT0 pin edge detection circuit:
both edges detection)
The measurement pulse width (“H” or “L”) is decided by the period measurement circuit and the P30/INT0 pin input level at the
start time of timer operation.
At the time of the start of a period measurement circuit and timer
operation, “L” pulse width (from falling to rising) when the input
level of P30/INT0 pin is “H” or “H” pulse width (from rising to falling) when its level is “L” is measured.
When the input of P30/INT0 pin is selected as the target for measurement, set the bit 3 of register I1 to “1”, and set the input of
INT0 pin to be enabled.
4518 Group
(9) Count start synchronization circuit (timer 1,
timer 3)
(11) Timer input/output pin
(D6/CNTR0 pin, D7/CNTR1 pin)
Timer 1 and timer 3 have the count start synchronous circuit which
synchronizes the input of INT0 pin and INT1 pin, and can start the
timer count operation.
Timer 1 count start synchronous circuit function is selected by setting the bit 0 of register I1 to “1” and the control by INT0 pin input
can be performed.
Timer 3 count start synchronous circuit function is selected by setting the bit 0 of register I2 to “1” and the control by INT1 pin input
can be performed.
When timer 1 or timer 3 count start synchronous circuit is used, the
count start synchronous circuit is set, the count source is input to
each timer by inputting valid waveform to INT0 pin or INT1 pin.
The valid waveform of INT0 pin or INT1 pin to set the count start
synchronous circuit is the same as the external interrupt activated
condition.
Once set, the count start synchronous circuit is cleared by clearing
the bit I10 or I20 to “0” or reset.
However, when the count auto-stop circuit is selected, the count
start synchronous circuit is cleared (auto-stop) at the timer 1 or
timer 3 underflow.
CNTR0 pin is used to input the timer 1 count source and output the
timer 1 and timer 2 underflow signal divided by 2.
CNTR1 pin is used to input the timer 3 count source and output the
PWM signal generated by timer 4.
The D6/CNTR0 pin function can be selected by bit 0 of register W6.
The selection of D7/CNTR1 output signal can be controlled by bit 3
of register W4.
When the CNTR0 input is selected for timer 1 count source, timer
1 counts the rising or falling waveform of CNTR0 input. The count
edge is selected by the bit 2 of register W6.
When the CNTR1 input is selected for timer 3 count source, timer
3 counts the rising or falling waveform of CNTR1 input. The count
edge is selected by the bit 3 of register W6.
(10) Count auto-stop circuit (timer 1, timer 3)
Timer 1 has the count auto-stop circuit which is used to stop timer
1 automatically by the timer 1 underflow when the count start synchronous circuit is used.
The count auto-stop cicuit is valid by setting the bit 3 of register W1
to “1”. It is cleared by the timer 1 underflow and the count source to
timer 1 is stopped.
This function is valid only when the timer 1 count start synchronous
circuit is selected.
Timer 3 has the count auto-stop circuit which is used to stop timer
3 automatically by the timer 3 underflow when the count start synchronous circuit is used.
The count auto-stop cicuit is valid by setting the bit 3 of register W3
to “1”. It is cleared by the timer 3 underflow and the count source to
timer 3 is stopped.
This function is valid only when the timer 3 count start synchronous
circuit is selected.
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(12) PWM output function (D7/CNTR1, timer 3,
timer 4)
When bit 3 of register W4 is set to “1”, timer 4 reloads data from reload register R4L and R4H alternately each underflow.
Timer 4 generates the PWM signal (PWMOUT) of the “L” interval
set as reload register R4L, and the “H” interval set as reload register R4H. The PWM signal (PWMOUT) is output from CNTR1 pin.
When bit 2 of register W4 is set to “1” at this time, the interval
(PWM signal “H” interval) set to reload register R4H for the counter
of timer 4 is extended for a half period of count source.
In this case, when a value set in reload register R4H is n, timer 4
divides the count source signal by n + 1.5 (n = 1 to 255).
When this function is used, set “1” or more to reload register R4H.
When bit 1 of register W6 is set to “1”, the PWM signal output to
CNTR1 pin is switched to valid/invalid each timer 3 underflow.
However, when timer 3 is stopped (bit 2 of register W3 is cleared to
“0”), this function is canceled.
Even when bit 1 of a register W4 is cleared to “0” in the “H” interval
of PWM signal, timer 4 does not stop until it next timer 4 underflow.
When clearing bit 1 of register W4 to “0” to stop timer 4 at the use
of PWM output function, avoid a timing when timer 4 underflows.
4518 Group
(14) Precautions
Note the following for the use of timers.
• Prescaler
Stop counting and then execute the TABPS instruction to read
from prescaler data.
Stop counting and then execute the TPSAB instruction to set
prescaler data.
• Timer count source
Stop timer 1, 2, 3 and 4 counting to change its count source.
•••
Each timer interrupt request flag is set to “1” when each timer
underflows. The state of these flags can be examined with the skip
instructions (SNZT1, SNZT2, SNZT3, SNZT4).
Use the interrupt control register V1, V2 to select an interrupt or a
skip instruction.
An interrupt request flag is cleared to “0” when an interrupt occurs
or when the next instruction is skipped with a skip instruction. The
timer 1 interrupt request flag (T1F) is not set by the timer 1 underflow signal, it is the flag for detecting the completion of period
measurement.
Depending on the state of timer 1, the timer 1 interrupt request
flag (T1F) may be set to “1” when the period measurement circuit is stopped by clearing bit 2 of register W5 to “0”. In order to
avoid the occurrence of an unexpected interrupt, clear the bit 2 of
register V1 to “0” (refer to Figure 28➀) and then, stop the bit 2 of
register W5 to “0” to stop the period measurement circuit.
In addition, execute the SNZT1 instruction to clear the T1F flag
after executing at least one instruction (refer to Figure 28➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZT1 instruction (refer to Figure 28➂).
LA
0
TV1A
LA
0
TW5A
NOP
SNZT1
NOP
; (✕0✕✕2)
; The SNZT1 instruction is valid ........ ➀
; (✕0✕✕2)
; Period measurement circuit stop
........................................................... ➁
; The SNZT1 instruction is executed
(T1F flag cleared)
........................................................... ➂
•••
(13) Timer interrupt request flags
(T1F, T2F, T3F, T4F)
✕ : these bits are not used here.
Fig. 28 Period measurement circuit program example
• Reading the count value
Stop timer 1, 2, 3 or 4 counting and then execute the data read
instruction (TAB1, TAB2, TAB3, TAB4) to read its data.
• Writing to the timer
Stop timer 1, 2, 3 or 4 counting and then execute the data write
instruction (T1AB, T2AB, T3AB, T4AB) to write its data.
• Writing to reload register R1, R3, R4H
When writing data to reload register R1, reload register R3 or reload register R4H while timer 1, timer 3 or timer 4 is operating,
avoid a timing when timer 1, timer 3 or timer 4 underflows.
• Timer 4
Avoid a timing when timer 4 underflows to stop timer 4 at the use
of PWM output function.
When “H” interval extension function of the PWM signal is set to
be “valid”, set “1” or more to reload register R4H.
• Period measurement function
When a period measurement circuit is used, clear bit 0 of register I1 to “0”, and set a timer 1 count start synchronous circuit to
be “not selected”.
Start timer operation immediately after operation of a period
measurement circuit is started.
When the target edge for measurement is input until timer operation is started from the operation of period measurement circuit is
started, the count operation is not executed until the timer operation becomes valid. Accordingly, be careful of count data.
When data is read from timer, stop the timer and clear bit 2 of
register W5 to “0” to stop the period measurement circuit, and
then execute the data read instruction.
Rev.3.01 2005.06.15
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While a period measurement circuit is operating, the timer 1 interrupt request flag (T1F) is not set by the timer 1 underflow
signal, it is the flag for detecting the completion of period measurement.
When a period measurement circuit is used, select the sufficiently higher-speed frequency than the signal for measurement
for the count source of a timer 1.
When the target signal for period measurement is D6/CNTR0 pin
input, do not select D6/CNTR0 pin input as timer 1 count source.
(The XIN input is recommended as timer 1 count source at the
time of period measurement circuit use.)
When the input of P30/INT0 pin is selected for measurement, set
the bit 3 of a register I1 to “1”, and set the input of INT0 pin to be
enabled.
4518 Group
• Prescaler, Timer 1, Timer 2 and Timer 3 count start timing and
count time when operation starts
Count starts from the first rising edge of the count source (2) after Prescaler, Timer 1, Timer 2 and Timer 3 operations start (1).
Time to first underflow (3) is shorter (for up to 1 period of the
count source) than time among next underflow (4) by the timing
to start the timer and count source operations after count starts.
AA
A
(2)
Count Source
Timer value
3
2
1
0
3
2
1
0
3
2
Timer Underflow signal
(3)
(4)
(1) Timer Start
Fig. 29 Timer count start timing and count time when operation starts (Prescaler, Timer 1, Timer 2 and Timer 3)
• Timer 4 count start timing and count time when operation starts
Count starts from the rising edge (2) after the first falling edge of
the count source, after Timer 4 operations start (1).
Time to first underflow (3) is different from time among next underflow (4) by the timing to start the timer and count source
operations after count starts.
A
A
A
(2)
Count Source
Timer Value
3
2
1
0
3
2
1
0
3
Timer Underflow Signal
(3)
(4)
(1) Timer Start
Fig. 30 Timer count start timing and count time when operation starts (Timer 4)
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4518 Group
● CNTR1 output: invalid (W43 = “0”)
Timer 4 count source
Timer 4 count value
0316
0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016
(R4L)
(Reload
register)
(R4L)
(R4L)
(R4L)
(R4L)
Timer 4 underflow signal
PWM signal (output invalid)
PWM signal “L”
fixed
Timer 4 start
● CNTR1 output: valid (W43 = “1”)
PWM signal “H” interval extension function: invalid (W42 = “0”)
Timer 4 count source
Timer 4 count value
0316
0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116
(R4L)
(Reload
register)
(R4H)
(R4L)
(R4H)
(R4L)
(R4H)
Timer 4 underflow signal
3 clock
PWM
signal
3 clock
PWM period 7 clock
PWM period 7 clock
Timer 4 start
● CNTR1 output: valid (W43 = “1”)
PWM signal “H” interval extension function: valid (W42 = “1”) (Note)
Timer 4 count source
Timer 4 count value
0316
0216 0116 0016
0216
0116 0016 0316 0216 0116 0016
0216
0116 0016 0316 0216 0116 0016 0216
(R4L)
(Reload
register)
(R4H)
(R4L)
(R4H)
(R4L)
Timer 4 underflow signal
3.5 clock
PWM
signal
Timer 4 start
PWM period 7.5 clock
Note: At PWM signal “H” interval extension function: valid, set “0116” or more to reload register R4H.
Fig. 31 Timer 4 operation (reload register R4L: “0316”, R4H: “0216”)
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3.5 clock
PWM period 7.5 clock
(R4H)
4518 Group
CNTR1 output auto-control circuit by timer 3 is selected.
● CNTR1 output: valid (W43 = “1”)
CNTR1 output auto-control circuit selected (W61 = “1”)
PWM
signal
Timer 3 underflow signal
Timer 3 start
CNTR1 output
CNTR1 output start
● CNTR1 output auto-control function
PWM
signal
Timer 3 underflow signal
Timer 3 start
➀
➁
Timer 3
stop
➂
Register W61
CNTR1 output
CNTR1 output start
➀
➁
➂
When the CNTR1 output auto-control function is set to be invalid while the CNTR1 output is invalid,
the CNTR1 output invalid state is retained.
When the CNTR1 output auto-control function is set to be invalid while the CNTR1 output is valid,
the CNTR1 output valid state is retained.
When timer 3 is stopped, the CNTR1 output auto-control function becomes invalid.
Fig. 32 CNTR1 output auto-control function by timer 3
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CNTR1 output stop
4518 Group
●Waveform extension function of CNTR1 output “H” interval: Invalid (W42 = “0”),
CNTR1 output: valid (W43 = “1”),
Count source: XIN input selected (W40 = “0”),
Reload register R4L: “0316”
Reload register R4H: “0216”
Timer 4 count start timing
Machine cycle
Mi
Mi+1
Mi+2
TW4A instruction execution cycle (W41) ← 1
System clock
f(STCK)=f(XIN)/4
XIN input
(count source selected)
Register W41
Timer 4 count value
(Reload register)
0316
0216 0116 0016 0216 0116 0016 0316 0216 0116
(R4L)
(R4H)
(R4L)
Timer 4
underflow signal
PWM signal
Timer 4 count start timing
Timer 4 count stop timing
Machine cycle
Mi
Mi+1
Mi+2
TW4A instruction execution cycle (W41) ← 0
System clock
f(STCK)=f(XIN)/4
XIN input
(count source selected)
Register W41
Timer 4 count value
(Reload register)
0216 0116 0016 0216 0116 0016 0316 0216 0116 0016
(R4H)
(R4L)
0216
(R4H)
Timer 4
underflow signal
(Note 1)
PWM signal
Timer 4 count stop timing
Notes 1: In order to stop timer 4 at CNTR1 output valid (W43 = “1”), avoid a timing when timer 4 underflows.
If these timings overlap, a hazard may occur in a CNTR1 output waveform.
2: At CNTR1 output valid, timer 4 stops after “H” interval of PWM signal set by reload register R4H is output.
Fig. 33 Timer 4 count start/stop timing
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4518 Group
WATCHDOG TIMER
Watchdog timer provides a method to reset the system when a program run-away occurs. Watchdog timer consists of timer
WDT(16-bit binary counter), watchdog timer enable flag (WEF),
and watchdog timer flags (WDF1, WDF2).
The timer WDT downcounts the instruction clocks as the count
source from “FFFF16” after system is released from reset.
After the count is started, when the timer WDT underflow occurs
(after the count value of timer WDT reaches “000016,” the next
count pulse is input), the WDF1 flag is set to “1.”
If the WRST instruction is never executed until the timer WDT underflow occurs (until timer WDT counts 65534), WDF2 flag is set to
“1,” and the RESET pin outputs “L” level to reset the microcomputer.
Execute the WRST instruction at each period of 65534 machine
cycle or less by software when using watchdog timer to keep the
microcomputer operating normally.
When the WEF flag is set to “1” after system is released from reset,
the watchdog timer function is valid.
When the DWDT instruction and the WRST instruction are executed continuously, the WEF flag is cleared to “0” and the
watchdog timer function is invalid.
The WEF flag is set to "1" at system reset or RAM back-up mode.
The WRST instruction has the skip function. When the WRST instruction is executed while the WDF1 flag is “1”, the WDF1 flag is
cleared to “0” and the next instruction is skipped.
When the WRST instruction is executed while the WDF1 flag is “0”,
the next instruction is not skipped.
The skip function of the WRST instruction can be used even when
the watchdog timer function is invalid.
FFFF 1 6
Value of 16-bit timer (WDT)
000016
➁
WDF1 flag
➁
65534 count
(Note)
➃
WDF2 flag
RESET pin output
➀ Reset
released
➂ WRST instruction
executed
(skip executed)
➄ System reset
➀ After system is released from reset (= after program is started), timer WDT starts count down.
➁ When timer WDT underflow occurs, WDF1 flag is set to “1.”
➂ When the WRST instruction is executed, WDF1 flag is cleared to “0,” the next instruction is skipped.
➃ When timer WDT underflow occurs while WDF1 flag is “1,” WDF2 flag is set to “1” and the
watchdog reset signal is output.
➄ The output transistor of RESET pin is turned “ON” by the watchdog reset signal and system reset is
executed.
Note: The number of count is equal to the number of cycle because the count source of watchdog timer
is the instruction clock.
Fig. 34 Watchdog timer function
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; WDF1 flag cleared
•••
WRST
; Watchdog timer function enabled/disabled
; WEF and WDF1 flags cleared
•••
DI
DWDT
WRST
•••
Fig. 35 Program example to start/stop watchdog timer
WRST
; WDF1 flag cleared
NOP
DI
; Interrupt disabled
EPOF
; POF instruction enabled
POF
↓
Oscillation stop
•••
When the watchdog timer is used, clear the WDF1 flag at the period of 65534 machine cycles or less with the WRST instruction.
When the watchdog timer is not used, execute the DWDT instruction and the WRST instruction continuously (refer to Figure 35).
The watchdog timer is not stopped with only the DWDT instruction.
The contents of WDF1 flag and timer WDT are initialized at the
RAM back-up mode.
When using the watchdog timer and the RAM back-up mode, initialize the WDF1 flag with the WRST instruction just before the
microcomputer enters the RAM back-up state (refer to Figure 36).
The watchdog timer function is valid after system is returned from
the RAM back-up. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously
every system is returned from the RAM back-up, and stop the
watchdog timer function.
•••
4518 Group
Fig. 36 Program example to enter the mode when using the
watchdog timer
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4518 Group
A/D CONVERTER (Comparator)
Table 11 A/D converter characteristics
Characteristics
Parameter
Conversion format Successive comparison method
The 4518 Group has a built-in A/D conversion circuit that performs
conversion by 10-bit successive comparison method. Table 11
shows the characteristics of this A/D converter. This A/D converter
can also be used as an 8-bit comparator to compare analog voltages input from the analog input pin with preset values.
Resolution
10 bits
Relative accuracy Linearity error: ±2LSB (2.7 V ≤ VDD ≤ 5.5V)
Differential non-linearity error: ±0.9LSB (2.2 V
≤ VDD ≤ 5.5V)
Conversion speed 31 µs (f(X IN ) = 6 MHz, STCK = f(XIN) (XIN
through-mode), ADCK = INSTCK/6)
Analog input pin
4
Register B (4)
Register A (4)
4
TAQ1
TQ1A
4
IAP6
(P60–P63)
OP6A
(P60–P63)
Q13 Q12 Q11 Q10
4
TAQ2
TQ2A
4
Division circuit
Divided by 48
3
Q32
Divided by 24
0
Divided by 12
Divided by 6
P62/AIN2
P63/AIN3
4-channel multi-plexed analog switch
P61/AIN1
4
2
8
TALA
TABAD
8
TADAB
Q31, Q30
11
A/D conversion clock
(ADCK)
10
01
00
Q13
0
P60/AIN0
4
4
Q33 Q32 Q31 Q30
Q23 Q22 Q21 Q20
Instruction clock
On-chip oscillator
1
clock
TAQ3
TQ3A
A/D control circuit
1
ADF
(1)
A/D
interrupt
1
Comparator
0
Q13
Successive comparison
register (AD) (10)
10
DAC
operation
signal
0
Q13
8
10
0
1
1
1
Q13
8
DA converter
8
8
VDD
(Note 1)
VSS
Comparator register (8)
(Note 2)
Notes 1: This switch is turned ON only when A/D converter is operating and generates the comparison voltage.
2: Writing/reading data to the comparator register is possible only in the comparator mode (Q13=1).
The value of the comparator register is retained even when the mode is switched to the A/D conversion
mode (Q13=0) because it is separated from the successive comparison register (AD). Also, the resolution
in the comparator mode is 8 bits because the comparator register consists of 8 bits.
Fig. 37 A/D conversion circuit structure
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4518 Group
Table 12 A/D control registers
A/D control register Q1
Q13
A/D operation mode selection bit
Q12
Q11
Analog input pin selection bits
Q10
at reset : 00002
A/D conversion mode
Comparator mode
Q12 Q11 Q10
0
0
0 AIN0
0
0
1 AIN1
0
1
0 AIN2
0
1
1 AIN3
1
0
0 Not available
1
0
1 Not available
1
1
0 Not available
1
1
1 Not available
A/D control register Q2
Q23
Not used
Q22
P62/AIN2, P63/AIN3 pin function selection bit
Q21
P61/AIN1 pin function selection bit
Q20
P60/AIN0 pin function selection bit
at reset : 00002
0
1
0
1
0
1
0
1
Not used
Q32
A/D converter operation clock selection bit
Q31
Q30
A/D converter operation clock division
ratio selection bits
0
1
0
1
Note: “R” represents read enabled, and “W” represents write enabled.
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Analog input pins
at RAM back-up : state retained
R/W
TAQ2/TQ2A
P62, P63
AIN2, AIN3
P61
AIN1
P60
AIN0
at reset : 00002
Q31
0
0
1
1
R/W
TAQ1/TQ1A
This bit has no function, but read/write is enabled.
A/D control register Q3
Q33
at RAM back-up : state retained
at RAM back-up : state retained
This bit has no function, but read/write is enabled.
Instruction clock (INSTCK)
On-chip oscillator (f(RING))
Division ratio
Q30
0 Frequency divided by 6
1 Frequency divided by 12
0 Frequency divided by 24
1 Frequency divided by 48
R/W
TAQ3/TQ3A
4518 Group
(1) A/D control register
(4) A/D conversion completion flag (ADF)
• A/D control register Q1
Register Q1 controls the selection of A/D operation mode and the
selection of analog input pins. Set the contents of this register
through register A with the TQ1A instruction. The TAQ1 instruction can be used to transfer the contents of register Q1 to register
A.
• A/D control register Q2
Register Q2 controls the selection of P60/AIN0–P63/AIN3. Set the
contents of this register through register A with the TQ2A instruction. The TAQ2 instruction can be used to transfer the contents of
register Q2 to register A.
• A/D control register Q3
Register Q3 controls the selection of A/D converter operation
clock. Set the contents of this register through register A with the
TQ3A instruction. The TAQ3 instruction can be used to transfer
the contents of register Q3 to register A.
A/D conversion completion flag (ADF) is set to “1” when A/D conversion completes. The state of ADF flag can be examined with the
skip instruction (SNZAD). Use the interrupt control register V2 to
select the interrupt or the skip instruction.
The ADF flag is cleared to “0” when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
(2) Operating at A/D conversion mode
The A/D conversion mode is set by setting the bit 3 of register Q1 to “0.”
(3) Successive comparison register AD
Register AD stores the A/D conversion result of an analog input in
10-bit digital data format. The contents of the high-order 8 bits of
this register can be stored in register B and register A with the
TABAD instruction. The contents of the low-order 2 bits of this register can be stored into the high-order 2 bits of register A with the
TALA instruction. However, do not execute these instructions during A/D conversion.
When the contents of register AD is n, the logic value of the comparison voltage Vref generated from the built-in DA converter can
be obtained with the reference voltage VDD by the following formula:
(5) A/D conversion start instruction (ADST)
A/D conversion starts when the ADST instruction is executed. The
conversion result is automatically stored in the register AD.
(6) Operation description
A/D conversion is started with the A/D conversion start instruction
(ADST). The internal operation during A/D conversion is as follows:
➀ When the A/D conversion starts, the register AD is cleared to
“00016.”
➁ Next, the topmost bit of the register AD is set to “1,” and the comparison voltage V ref is compared with the analog input voltage
VIN.
➂ When the comparison result is Vref < VIN, the topmost bit of the
register AD remains set to “1.” When the comparison result is Vref
> VIN, it is cleared to “0.”
The 4518 Group repeats this operation to the lowermost bit of the
register AD to convert an analog value to a digital value. A/D conversion stops after 2 machine cycles + A/D conversion clock (31 µs
when f(XIN) = 6.0 MHz in XIN through mode, f(ADCK) = f(INSTCK)/
6) from the start, and the conversion result is stored in the register
AD. An A/D interrupt activated condition is satisfied and the ADF
flag is set to “1” as soon as A/D conversion completes (Figure 38).
Logic value of comparison voltage Vref
Vref =
V DD
✕n
1024
n: The value of register AD (n = 0 to 1023)
Table 13 Change of successive comparison register AD during A/D conversion
At starting conversion
-------------
1st comparison
2nd comparison
3rd comparison
After 10th comparison
completes
✼1: 1st comparison result
✼3: 3rd comparison result
✼9: 9th comparison result
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Comparison voltage (Vref) value
Change of successive comparison register AD
1
✼1
✼1
0
1
✼2
0
0
-----
0
0
0
-------------
2
-------------
VDD
-----
-------------
0
0
0
2
-------------
1
-----
-------------
0
0
0
VDD
-------------
✼2
✼3
-----
-------------
✼8
✼2: 2nd comparison result
✼8: 8th comparison result
✼A: 10th comparison result
page 49 of 157
✼9
✼A
VDD
±
4
VDD
2
A/D conversion result
✼1
VDD
2
VDD
±
±
VDD
±
4
○
○
○
○
±
8
VDD
1024
4518 Group
(7) A/D conversion timing chart
Figure 38 shows the A/D conversion timing chart.
ADST instruction
2 machine cycles + 10/f(ADCK)
A/D conversion
completion flag (ADF)
DAC operation signal
Fig. 38 A/D conversion timing chart
(8) How to use A/D conversion
How to use A/D conversion is explained using as example in which
the analog input from P60/AIN0 pin is A/D converted, and the highorder 4 bits of the converted data are stored in address M(Z, X, Y)
= (0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1),
and the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM.
The A/D interrupt is not used in this example.
Instruction clock/6 is selected as the A/D converter operation clock.
(Bit 3)
✕
✕
✕
1
(Bit 3)
(Bit 0)
0
0
0
page 50 of 157
A/D control register Q1
A IN0 pin selected
A/D conversion mode
(Bit 3)
✕
(Bit 0)
0
0
0
A/D control register Q3
Frequency divided by 6
Instruction clock
✕: Set an arbitrary value.
Fig. 39 Setting registers
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A/D control register Q2
A IN0 pin function selected
0
➀ Select the AIN0 pin function with the bit 0 of the register Q2. Select the A IN0 pin function and A/D conversion mode with the
register Q1. Also, the instruction clock divided by 6 is selected
with the register Q3. (refer to Figure 39)
➁ Execute the ADST instruction and start A/D conversion.
➂ Examine the state of ADF flag with the SNZAD instruction to determine the end of A/D conversion.
➃ Transfer the low-order 2 bits of converted data to the high-order
2 bits of register A (TALA instruction).
➄ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2).
➅ Transfer the high-order 8 bits of converted data to registers A
and B (TABAD instruction).
➆ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1).
➇ Transfer the contents of register B to register A, and then, store
into M(Z, X, Y) = (0, 0, 0).
(Bit 0)
4518 Group
(9) Operation at comparator mode
The A/D converter is set to comparator mode by setting bit 3 of the
register Q1 to “1.”
Below, the operation at comparator mode is described.
(10) Comparator register
In comparator mode, the built-in DA comparator is connected to the
8-bit comparator register as a register for setting comparison voltages. The contents of register B is stored in the high-order 4 bits of
the comparator register and the contents of register A is stored in
the low-order 4 bits of the comparator register with the TADAB instruction.
When changing from A/D conversion mode to comparator mode,
the result of A/D conversion (register AD) is undefined.
However, because the comparator register is separated from register AD, the value is retained even when changing from comparator
mode to A/D conversion mode. Note that the comparator register
can be written and read at only comparator mode.
If the value in the comparator register is n, the logic value of comparison voltage Vref generated by the built-in DA converter can be
determined from the following formula:
Logic value of comparison voltage Vref
Vref =
VDD
256
✕n
n: The value of register AD (n = 0 to 255)
(12) Comparator operation start instruction
(ADST instruction)
In comparator mode, executing ADST starts the comparator operating.
The comparator stops 2 machine cycles + A/D conversion clock
f(ADCK) 1 clock after it has started (4 µs at f(XIN) = 6.0 MHz in XIN
through mode, f(ADCK) = f(INSTCK)/6). When the analog input
voltage is lower than the comparison voltage, the ADF flag is set to
“1.”
(13) Notes for the use of A/D conversion
• TALA instruction
When the TALA instruction is executed, the low-order 2 bits of
register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is “0.”
• Operation mode of A/D converter
Do not change the operating mode (both A/D conversion mode
and comparator mode) of A/D converter with the bit 3 of register
Q1 while the A/D converter is operating.
Clear the bit 2 of register V2 to “0” to change the operating mode
of the A/D converter from the comparator mode to A/D conversion mode.
The A/D conversion completion flag (ADF) may be set when the
operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a
value to the register Q1, and execute the SNZAD instruction to
clear the ADF flag.
(11) Comparison result store flag (ADF)
In comparator mode, the ADF flag, which shows completion of A/D
conversion, stores the results of comparing the analog input voltage with the comparison voltage. When the analog input voltage is
lower than the comparison voltage, the ADF flag is set to “1.” The
state of ADF flag can be examined with the skip instruction
(SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction.
The ADF flag is cleared to “0” when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
ADST instruction
2 machine cycles + 1/f(ADCK)
Comparison result
store flag(ADF)
DAC operation signal
→
Comparator operation completed.
(The value of ADF is determined)
Fig. 40 Comparator operation timing chart
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4518 Group
(14) Definition of A/D converter accuracy
The A/D conversion accuracy is defined below (refer to Figure 41).
• Relative accuracy
➀ Zero transition voltage (V0T)
This means an analog input voltage when the actual A/D conversion output data changes from “0” to “1.”
➁ Full-scale transition voltage (VFST)
This means an analog input voltage when the actual A/D conversion output data changes from “1023” to “1022.”
➂ Linearity error
This means a deviation from the line between V0T and VFST of
a converted value between V0T and VFST.
➃ Differential non-linearity error
This means a deviation from the input potential difference required to change a converter value between V0T and VFST by 1
LSB at the relative accuracy.
Vn: Analog input voltage when the output data changes from “n” to
“n+1” (n = 0 to 1022)
• 1LSB at relative accuracy →
VFST–V0T
(V)
1022
• 1LSB at absolute accuracy →
VDD
1024
(V)
• Absolute accuracy
This means a deviation from the ideal characteristics between 0
to VDD of actual A/D conversion characteristics.
Output data
Full-scale transition voltage (VFST)
1023
1022
Differential non-linearity error = b–a [LSB]
a
Linearity error = c [LSB]
a
b
a
n+1
n
Actual A/D conversion
characteristics
c
a: 1LSB by relative accuracy
b: Vn+1–Vn
c: Difference between ideal Vn
and actual Vn
Ideal line of A/D conversion
between V0–V1022
1
0
V0
V1
Zero transition voltage (V0T)
Fig. 41 Definition of A/D conversion accuracy
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Vn
Vn+1
V1022
VDD
Analog voltage
4518 Group
SERIAL INTERFACE
Table 14 Serial I/O pins
The 4518 Group has a built-in clock synchronous serial I/O which
can serially transmit or receive 8-bit data.
Serial I/O consists of;
• serial I/O register SI
• serial I/O control register J1
• serial I/O transmit/receive completion flag (SIOF)
• serial I/O counter
Registers A and B are used to perform data transfer with internal
CPU, and the serial I/O pins are used for external data transfer.
The pin functions of the serial I/O pins can be set with the register
J1.
1/8
1/4
1/2
INSTCK
Pin
P20/SCK
P21/SOUT
P22/SIN
Pin function when selecting serial I/O
Clock I/O (SCK)
Serial data output (SOUT)
Serial data input (SIN)
Note: Even when the SCK, S OUT, SIN pin functions are used, the input of
P20, P21, P22 are valid.
J13J12
00
01
10
Synchronous
circuit
Serial I/O counter (3)
SIOF
Serial I/O
interrupt
11
P20/SCK
P21/SOUT
P22/SIN
SCK
Q
S
SST
instruction
R
Internal reset signal
SOUT
SIN
MSB Serial I/O register (8) LSB
TABSI
TSIAB
Register B (4)
TABSI
Register A (4)
J11 J10
Fig. 42 Serial I/O structure
Table 15 Serial I/O control register
Serial I/O control register J1
J13
J12
J11
J10
at reset : 00002
at RAM back-up : state retained
J13 J12
Synchronous clock
0 Instruction clock (INSTCK) divided by 8
0
Serial I/O synchronous clock selection bits 0
1 Instruction clock (INSTCK) divided by 4
0 Instruction clock (INSTCK) divided by 2
1
1 External clock (SCK input)
1
J11 J10
Port function
0 P20, P21,P22 selected/SCK, SOUT, SIN not selected
0
Serial I/O port function selection bits
1 SCK, SOUT, P22 selected/P20, P21, SIN not selected
0
0 SCK, P21, SIN selected/P20, SOUT, P22 not selected
1
1 SCK, SOUT, SIN selected/P20, P21,P22 not selected
1
Note: “R” represents read enabled, and “W” represents write enabled.
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R/W
TAJ1/TJ1A
4518 Group
At transmit (D7–D0: transfer data)
At receive
SIN pin
Serial I/O register (SI)
SOUT pin
SOUT pin
SIN pin
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
*D
7 D6 D5 D4 D3 D2 D1
* ** * * ** *
Transfer data set
Transfer start
* *D
7 D6 D5 D4 D3 D2
* ** * * ** *
Serial I/O register (SI)
* ** * * ** *
D0
** * * ** *
D1 D0
Transfer complete
* * * ** *
D7 D6 D5 D4 D3 D2 D1 D0
Fig. 43 Serial I/O register state when transferring
(1) Serial I/O register SI
(3) Serial I/O start instruction (SST)
Serial I/O register SI is the 8-bit data transfer serial/parallel conversion register. Data can be set to register SI through registers A and
B with the TSIAB instruction. The contents of register A is transmitted to the low-order 4 bits of register SI, and the contents of
register B is transmitted to the high-order 4 bits of register SI.
During transmission, each bit data is transmitted LSB first from the
lowermost bit (bit 0) of register SI, and during reception, each bit
data is received LSB first to register SI starting from the topmost bit
(bit 7).
When register SI is used as a work register without using serial I/O,
do not select the SCK pin.
When the SST instruction is executed, the SIOF flag is cleared to
“0” and then serial I/O transmission/reception is started.
(2) Serial I/O transmit/receive completion flag
(SIOF)
Serial I/O transmit/receive completion flag (SIOF) is set to “1” when
serial data transmission or reception completes. The state of SIOF
flag can be examined with the skip instruction (SNZSI). Use the interrupt control register V2 to select the interrupt or the skip
instruction.
The SIOF flag is cleared to “0” when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
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(4) Serial I/O control register J1
Register J1 controls the synchronous clock, P2 0/S CK, P21/S OUT
and P22/SIN pin function. Set the contents of this register through
register A with the TJ1A instruction. The TAJ1 instruction can be
used to transfer the contents of register J1 to register A.
4518 Group
(5) How to use serial I/O
Figure 44 shows the serial I/O connection example. Serial I/O interrupt is not used in this example. In the actual wiring, pull up the
wiring between each pin with a resistor. Figure 44 shows the data
transfer timing and Table 16 shows the data transfer sequence.
Master (clock control)
Slave (external clock)
SRDY signal
D3
(Bit 3)
0
0
1
(Bit 0)
1
D3
SCK
SCK
SOUT
SIN
SIN
SOUT
(Bit 0)
(Bit 3)
Serial I/O control
register J1
Serial I/O port
SCK,SOUT,SIN
1
1
1
Serial I/O control
register J1
Serial I/O port
SCK,SOUT,SIN
1
Instruction clock/8 selected
as synchronous clock
(Bit 0)
(Bit 3)
✕
0
External clock selected
as synchronous clock
✕
✕
(Bit 0)
(Bit 3)
Interrupt control
register V2
0
✕
✕
Interrupt control
register V2
✕
Serial I/O interrupt
enable bit
Serial I/O interrupt
enable bit
(SNZSI instruction valid)
(SNZSI instruction valid)
✕: Set an arbitrary value.
Fig. 44 Serial I/O connection example
Master
SOUT
M7’
SI N
M0
S7 ’
M1
S0
M2
S1
M3
S2
M4
S3
M5
S4
M6
S5
M7
S6
S7
SST instruction
SCK
Slave
SST instruction
SRDY signal
SOUT
S0
S7 ’
SI N
M7’
S2
S1
M0
M1
M0–M7: Contents of master serial I/O register
S0–S7: Contents of slave serial I/O register
Rising of SCK: Serial input
Falling of SCK: Serial output
Fig. 45 Timing of serial I/O data transfer
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S3
M2
S4
M3
S5
M4
S6
M5
S7
M6
M7
4518 Group
Table 16 Processing sequence of data transfer from master to slave
Slave (reception)
Master (transmission)
[Initial setting]
[Initial setting]
• Setting the serial I/O mode register J1 and interrupt control register V2 shown in Figure 44.
• Setting serial I/O mode register J1, and interrupt control register V2 shown in
Figure 44.
TJ1A and TV2A instructions
• Setting the port received the reception enable
signal (SRDY) to the input mode.
TJ1A and TV2A instructions
• Setting the port transmitted the reception enable signal (SRDY) and outputting
“H” level (reception impossible).
(Port D3 is used in this example)
SD instruction
* [Transmission enable state]
• Storing transmission data to serial I/O register SI.
TSIAB instruction
(Port D3 is used in this example)
SD instruction
*[Reception enable state]
• The SIOF flag is cleared to “0.”
SST instruction
• “L” level (reception possible) is output from port D3.
RD instruction
[Transmission]
•Check port D3 is “L” level.
[Reception]
SZD instruction
•Serial transfer starts.
SST instruction
•Check transmission completes.
• Check reception completes.
SNZSI instruction
•Wait (timing when continuously transferring)
SNZSI instruction
• “H” level is output from port D3.
SD instruction
[Data processing]
1-byte data is serially transferred on this process. Subsequently, data
can be transferred continuously by repeating the process from *.
When an external clock is selected as a synchronous clock, the
clock is not controlled internally. Control the clock externally because serial transfer is performed as long as clock is externally
input. (Unlike an internal clock, an external clock is not stopped
when serial transfer is completed.) However, the SIOF flag is set to
“1” when the clock is counted 8 times after executing the SST instruction. Be sure to set the initial level of the external clock to “H.”
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4518 Group
RESET FUNCTION
System reset is performed by applying “L” level to RESET pin for
1 machine cycle or more when the following condition is satisfied;
the value of supply voltage is the minimum value or more of the
recommended operating conditions.
Then when “H” level is applied to RESET pin, software starts from
address 0 in page 0.
f(RING)
RESET
On-chip oscillator (internal oscillator)
is counted 120 to 144 times.
Program starts
(address 0 in page 0)
Note: The number of clock cycles depends on the internal state of
the microcomputer when reset is performed.
Fig. 46 Reset release timing
=
Reset input
On-chip oscillator (internal oscillator) is
1 machine cycle or more
0.85VDD
counted 120 to 144 times.
Program starts
(address 0 in page 0)
RESET
0.3VDD
(Note)
Note: Keep the value of supply voltage to the minimum value
or more of the recommended operating conditions.
Fig. 47 RESET pin input waveform and reset operation
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4518 Group
(1) Power-on reset
Reset can be automatically performed at power on (power-on reset) by the built-in power-on reset circuit. When the built-in
power-on reset circuit is used, the time for the supply voltage to
rise from 0 V until the value of supply voltage reaches the minimum
operating voltage must be set to 100 µs or less.
If the rising time exceeds 100 µs, connect a capacitor between the
RESET pin and VSS at the shortest distance, and input “L” level to
RESET pin until the value of supply voltage reaches the minimum
operating voltage.
100 µs or less
Pull-up transistor
VDD (Note 3)
Power-on reset circuit output
(Note 1)
(Note 2)
Internal reset signal
RESET pin
Power-on reset circuit
(Note 1)
Voltage drop detection circuit
Internal reset signal
Watchdog reset signal
WEF
Reset
state
SRST instruction
Power-on
Reset released
Notes 1:
This symbol represents a parasitic diode.
2: Applied potential to RESET pin must be VDD or less.
3: Keep the value of supply voltage to the minimum value
or more of the recommended operating conditions.
Fig. 48 Structure of reset pin and its peripherals,, and power-on reset operation
Table 1 Port state at reset
Name
State
Function
D0–D5
D0–D5
High-impedance (Notes 1, 2)
D6/CNTR0
D7/CNTR1
D6
High-impedance (Notes 1, 2)
High-impedance (Notes 1, 2)
P00–P03
D7
P00–P03
P10–P13
P10–P13
High-impedance (Notes 1, 2, 3)
P20/SCK, P21/SOUT, P22/SIN
P20–P22
High-impedance (Note 1)
P30/INT0, P31/INT1
P30, P31
High-impedance (Note 1)
P60/AIN0–P63/AIN3
P60–P63
High-impedance (Note 1)
Notes 1: Output latch is set to “1.”
2: Output structure is N-channel open-drain.
3: Pull-up transistor is turned OFF.
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High-impedance (Notes 1, 2, 3)
4518 Group
(2) Internal state at reset
Figure 49 and 50 show internal state at reset (they are the same after system is released from reset). The contents of timers, registers,
flags and RAM except shown in Figure are undefined, so set the
initial value to them.
• Program counter (PC) ..........................................................................................................
0 0 0 0 0 0
Address 0 in page 0 is set to program counter.
0
• Interrupt enable flag (INTE) .................................................................................................. 0
(Interrupt disabled)
0
0
0
0
0
0
0
• Power down flag (P) ............................................................................................................. 0
• External 0 interrupt request flag (EXF0) .............................................................................. 0
• External 1 interrupt request flag (EXF1) .............................................................................. 0
• Interrupt control register V1 ..................................................................................................
0 0 0 0
• Interrupt control register V2 ..................................................................................................
0 0 0 0
• Interrupt control register I1 ...................................................................................................
0 0 0 0
(Interrupt disabled)
(Interrupt disabled)
• Interrupt control register I2 ...................................................................................................
0 0 0 0
• Timer 1 interrupt request flag (T1F) ..................................................................................... 0
• Timer 2 interrupt request flag (T2F) ..................................................................................... 0
• Timer 3 interrupt request flag (T3F) ..................................................................................... 0
• Timer 4 interrupt request flag (T4F) ..................................................................................... 0
• Watchdog timer flags (WDF1, WDF2) .................................................................................. 0
• Watchdog timer enable flag (WEF) ...................................................................................... 1
• Timer control register PA ...................................................................................................... 0
• Timer control register W1 .....................................................................................................
0 0 0 0
• Timer control register W2 .....................................................................................................
0 0 0 0
• Timer control register W3 .....................................................................................................
0 0 0 0
(Prescaler stopped)
(Timer 1 stopped)
(Timer 2 stopped)
(Timer 3 stopped)
• Timer control register W4 .....................................................................................................
0 0 0 0
(Timer 4 stopped)
• Timer control register W5 .....................................................................................................
0 0 0 0
(Period measurement circuit stopped)
• Timer control register W6 .....................................................................................................
0 0 0 0
• Clock control register MR .....................................................................................................
1 1 1 1
• Clock control register RG ..................................................................................................... 0
(On-chip oscillator operating)
• Serial I/O transmit/receive completion flag (SIOF) .............................................................. 0
• Serial I/O mode register J1 ..................................................................................................
0 0 0 0
(External clock selected,
serial I/O port not selected)
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Serial I/O register SI .............................................................................................................
• A/D conversion completion flag (ADF) ................................................................................. 0
• A/D control register Q1 .........................................................................................................
0 0 0 0
• A/D control register Q2 .........................................................................................................
0 0 0 0
• A/D control register Q3 .........................................................................................................
0 0 0 0
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Successive comparison register AD ....................................................................................
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Comparator register ..............................................................................................................
• Key-on wakeup control register K0 ......................................................................................
0 0 0 0
• Key-on wakeup control register K1 ......................................................................................
0 0 0 0
• Key-on wakeup control register K2 ......................................................................................
0 0 0 0
• Pull-up control register PU0 .................................................................................................
0 0 0 0
• Pull-up control register PU1 .................................................................................................
0 0 0 0
“✕” represents undefined.
Fig. 49 Internal state at reset 1
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4518 Group
• Port output structure control register FR0 ...........................................................................
0 0 0 0
• Port output structure control register FR1 ...........................................................................
0 0 0 0
• Port output structure control register FR2 ...........................................................................
0 0 0 0
• Carry flag (CY) ......................................................................................................................
0
• Register A .............................................................................................................................
0 0 0 0
• Register B .............................................................................................................................
0 0 0 0
• Register D .............................................................................................................................
✕ ✕ ✕
• Register E .............................................................................................................................
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Register X .............................................................................................................................
0 0 0 0
• Register Y .............................................................................................................................
0 0 0 0
• Register Z .............................................................................................................................
✕ ✕
• Stack pointer (SP) ................................................................................................................
1 1 1
• Operation source clock .......................................................... On-chip oscillator (operating)
• Ceramic resonator circuit .............................................................................................. Stop
• RC oscillation circuit ...................................................................................................... Stop
• Quartz-crystal oscillation circuit .................................................................................... Stop
“✕” represents undefined.
Fig. 50 Internal state at reset 2
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4518 Group
VOLTAGE DROP DETECTION CIRCUIT
The built-in voltage drop detection circuit is designed to detect a
drop in voltage and to reset the microcomputer if the supply voltage
drops below a set value.
VDCE
VRST +
VRST -
Voltage drop detection circuit
Reset signal
–
+
Voltage drop detection circuit
Fig. 51 Voltage drop detection reset circuit
VDD
+
VRST (reset release voltage)
VRST -(reset voltage)
Voltage drop detection circuit
Reset signal
Microcomupter starts operation after
on-chip oscillator (internal oscillator)
clock is counted 120 to 144 times.
RESET pin
Note: Detection voltage hysteresis of voltage drop detection circuit is 0.2 V (Typ).
Fig. 52 Voltage drop detection circuit operation waveform
Table 17 Voltage drop detection circuit operation state
VDCE pin
“L”
“H”
At CPU operating
Invalid
Valid
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At RAM back-up
Invalid
Valid
4518 Group
RAM BACK-UP MODE
Table 18 Functions and states retained at RAM back-up
The 4518 Group has the RAM back-up mode.
When the EPOF and POF instructions are executed continuously,
system enters the RAM back-up state. The POF instruction is
equal to the NOP instruction when the EPOF instruction is not executed before the POF instruction.
As oscillation stops retaining RAM, the function of reset circuit and
states at RAM back-up mode, current dissipation can be reduced
without losing the contents of RAM. Table 18 shows the function
and states retained at RAM back-up. Figure 53 shows the state
transition.
Function
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
RAM back-up
✕
Contents of RAM
O
Interrupt control registers V1, V2
✕
Interrupt control registers I1, I2
O
Selection of oscillation circuit
Clock control register MR
O
Timer 1 function
✕
(Note 3)
Timer 2 function
(Note 3)
(1) Identification of the start condition
Timer 3 function
(Note 3)
Warm start (return from the RAM back-up state) or cold start (return from the normal reset state) can be identified by examining the
state of the RAM back-up flag (P) with the SNZP instruction.
Timer 4 function
Watchdog timer function
Timer control register PA, W4
(Note 3)
✕ (Note 4)
Timer control registers W1 to W3, W5, W6
✕
O
(2) Warm start condition
Serial I/O function
✕
When the external wakeup signal is input after the system enters
the RAM back-up state by executing the EPOF and POF instructions continuously, the CPU starts executing the program from
address 0 in page 0. In this case, the P flag is “1.”
Serial I/O mode register J1
O
A/D conversion function
✕
(3) Cold start condition
The CPU starts executing the program from address 0 in page 0
when;
• reset pulse is input to RESET pin, or
• reset by watchdog timer is performed, or
• voltage drop detection circuit detects the voltage drop, or
• SRST instruction is executed.
In this case, the P flag is “0.”
A/D control registers Q1 to Q3
Voltage drop detection circuit
Port level
O
O (Note 5)
O
Key-on wakeup control register K0 to K2
O
Pull-up control registers PU0, PU1
O
Port output direction registers FR0 to FR2
O
External 0 interrupt request flag (EXF0)
External 1 interrupt request flag (EXF1)
✕
Timer 1 interrupt request flag (T1F)
✕
(Note 3)
Timer 2 interrupt request flag (T2F)
(Note 3)
Timer 3 interrupt request flag (T3F)
(Note 3)
Timer 4 interrupt request flag (T4F)
(Note 3)
A/D conversion completion flag (ADF)
Serial I/O transmission/reception completion flag
✕
✕
(SIOF)
Interrupt enable flag (INTE)
✕
Watchdog timer flags (WDF1, WDF2)
✕ (Note 4)
Watchdog timer enable flag (WEF)
✕ (Note 4)
Notes 1:“O” represents that the function can be retained, and “✕” represents that the function is initialized.
Registers and flags other than the above are undefined at RAM
back-up, and set an initial value after returning.
2: The stack pointer (SP) points the level of the stack register and is
initialized to “7” at RAM back-up.
3: The state of the timer is undefined.
4: Initialize the watchdog timer with the WRST instruction, and then
execute the POF instruction.
5: The valid/invalid of the voltage drop detection circuit can be controlled only by VDCE pin.
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4518 Group
(4) Return signal
An external wakeup signal is used to return from the RAM back-up
mode because the oscillation is stopped. Table 19 shows the return
condition for each return source.
(5) Related registers
• Key-on wakeup control register K0
Register K0 controls the ports P0 and P1 key-on wakeup function. Set the contents of this register through register A with the
TK0A instruction. In addition, the TAK0 instruction can be used to
transfer the contents of register K0 to register A.
• Key-on wakeup control register K1
Register K1 controls the return condition and valid waveform/
level selection for port P0. Set the contents of this register
through register A with the TK1A instruction. In addition, the
TAK1 instruction can be used to transfer the contents of register
K1 to register A.
• Key-on wakeup control register K2
Register K2 controls the INT0 and INT1 key-on wakeup functions
and return condition function. Set the contents of this register
through register A with the TK2A instruction. In addition, the
TAK2 instruction can be used to transfer the contents of register
K2 to register A.
• Pull-up control register PU0
Register PU0 controls the ON/OFF of the port P0 pull-up transistor. Set the contents of this register through register A with the
TPU0A instruction. In addition, the TAPU0 instruction can be
used to transfer the contents of register PU0 to register A.
• Pull-up control register PU1
Register PU1 controls the ON/OFF of the port P1 pull-up transistor. Set the contents of this register through register A with the
TPU1A instruction. In addition, the TAPU1 instruction can be
used to transfer the contents of register PU0 to register A.
• External interrupt control register I1
Register I1 controls the valid waveform of external 0 interrupt, input control of INT0 pin, and return input level. Set the contents of
this register through register A with the TI1A instruction. In addition, the TAI1 instruction can be used to transfer the contents of
register I1 to register A.
• External interrupt control register I2
Register I2 controls the valid waveform of external 1 interrupt, input control of INT1 pin, and return input level. Set the contents of
this register through register A with the TI2A instruction. In addition, the TAI2 instruction can be used to transfer the contents of
register I2 to register A.
Table 19 Return source and return condition
External wakeup signal
Return source
Return condition
Remarks
The key-on wakeup function can be selected with 2 port units. Select the return level (“L” level or “H” level), and return condition (return by level or
edge) with the register K1 according to the external state before going into
the RAM back-up state.
Ports P1 0 –P1 3 Return by an external “L” level in- The key-on wakeup function can be selected with 2 port units. Set the port
using the key-on wakeup function to “H” level before going into the RAM
put.
back-up state.
Ports P0 0 –P0 3 Return by an external “H” level or
“L” level input, or rising edge
(“L”→“H”) or falling edge
(“H”→“L”).
INT0
INT1
Return by an external “H” level or Select the return level (“L” level or “H” level) with the registers I1 and I2 ac“L” level input, or rising edge cording to the external state, and return condition (return by level or edge)
( “ L ” → “ H ” ) o r f a l l i n g e d g e with the register K2 before going into the RAM back-up state.
(“H”→“L”).
The external interrupt request flags
(EXF0, EXF1) are not set.
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4518 Group
(Note 5)
Key-on wakeup
A
E
RAM back-up mode
Operation state
Reset
• Operation source clock:
f(RING)
• f(XIN): Stop
(Note 1)
POF instruction
execution
(Note 4)
MR1←1
(Note 2) MR1←0
B
Operation state
• Operation source clock:
f(RING)
• f(XIN): Operating
(Note 3) MR0←0
POF instruction
execution
(Note 4)
MR0←1
C
Operation state
• Operation source clock:
f(XIN)
• f(RING): Operating
RG0←0
RG0←1
POF instruction
execution
(Note 4)
D
Operation state
• Operation source clock:
f(XIN)
• f(RING): Stop
POF instruction
execution
(Note 4)
f(RING): stop
f(XIN): stop
Notes 1: Microcomputer starts its operation after counting f(RING) 120 to 144 times.
2: The f(XIN) oscillation circuit (ceramic resonance, RC oscillation or quartz-crystal oscillation) selected by the CMCK, CRCK or CYCK
instruction starts oscillatng (the start of oscillation and the operation source clock is not switched by these instructions).
The start/stop of oscillation and the operation source is switched by register MR.
Surely, select the f(XIN) oscillation circuit by executing the CMCK, CRCK or CYCK instruction before clearing MR1 to “0”.
MR1 cannot be cleared to “0” when the oscillation circuit is not selected.
3: Generate the wait time by software until the oscillation is stabilized, and then, switch the system clock.
4: Continuous execution of the EPOF instruction and the POF instruction is required to go into the RAM back-up state.
5: System returns to state A certainly when returning from the RAM back-up mode.
However, the selected contents (CMCK, CRCK, CYCK instruction execution state) of f(XIN) oscillation circuit is retained.
Fig. 53 State transition
POF
EPOF
instruction + instruction
Reset input
Power down flag P
S
Q
R
Program start
P = “1”
?
No
● Set source
•••••••
EPOF instruction + POF instruction
Yes
Warm start
Cold start
● Clear source • • • • • • Reset input
Fig. 54 Set source and clear source of the P flag
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Fig. 55 Start condition identified example using the SNZP instruction
4518 Group
Table 20 Key-on wakeup control register, pull-up control register
Key-on wakeup control register K0
K03
K02
K01
K00
Pins P12 and P13 key-on wakeup
at reset : 00002
control bit
0
1
Pins P10 and P11 key-on wakeup
0
Key-on wakeup used
Key-on wakeup not used
control bit
Pins P02 and P03 key-on wakeup
1
Key-on wakeup used
0
Key-on wakeup not used
control bit
1
Key-on wakeup used
Pins P00 and P01 key-on wakeup
0
1
Key-on wakeup not used
control bit
Key-on wakeup control register K1
K13
K12
K11
K10
at RAM back-up : state retained
Ports P02 and P03 return condition selection
0
1
Ports P02 and P03 valid waveform/
level selection bit
0
Falling waveform/“L” level
1
Rising waveform/“H” level
Ports P01 and P00 return condition selection
0
Return by level
bit
Return by edge
Ports P01 and P00 valid waveform/
1
0
level selection bit
1
K22
INT1 pin key-on wakeup contro bit
K21
INT0 pin return condition selection bit
K20
Key-on wakeup used
bit
INT1 pin return condition selection bit
INT0 pin key-on wakeup contro bit
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R/W
TAK1/TK1A
Return by level
Return by edge
Falling waveform/“L” level
Rising waveform/“H” level
at reset : 00002
at RAM back-up : state retained
0
Return by level
1
Return by edge
0
Key-on wakeup not used
1
0
Key-on wakeup used
1
0
Return by edge
Key-on wakeup not used
1
Key-on wakeup used
Note: “R” represents read enabled, and “W” represents write enabled.
R/W
TAK0/TK0A
Key-on wakeup not used
at reset : 00002
Key-on wakeup control register K2
K23
at RAM back-up : state retained
Return by level
R/W
TAK2/TK2A
4518 Group
Table 21 Key-on wakeup control register, pull-up control register
Pull-up control register PU0
PU03
PU02
PU01
PU00
at reset : 00002
P03 pin pull-up transistor
0
Pull-up transistor OFF
control bit
1
P02 pin pull-up transistor
0
Pull-up transistor ON
Pull-up transistor OFF
control bit
P01 pin pull-up transistor
1
Pull-up transistor ON
0
Pull-up transistor OFF
control bit
Pull-up transistor ON
P00 pin pull-up transistor
1
0
control bit
1
Pull-up transistor ON
Pull-up control register PU1
PU13
PU12
PU11
PU10
P13 pin pull-up transistor
0
Pull-up transistor OFF
control bit
P12 pin pull-up transistor
1
Pull-up transistor ON
0
Pull-up transistor OFF
control bit
1
P11 pin pull-up transistor
0
Pull-up transistor ON
Pull-up transistor OFF
control bit
1
0
Pull-up transistor ON
P10 pin pull-up transistor
control bit
1
Pull-up transistor ON
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R/W
TAPU0/
TPU0A
at RAM back-up : state retained
R/W
TAPU1/
TPU1A
Pull-up transistor OFF
at reset : 00002
Note: “R” represents read enabled, and “W” represents write enabled.
at RAM back-up : state retained
Pull-up transistor OFF
4518 Group
CLOCK CONTROL
The CMCK, CRCK, and CYCK instructions can be used only to select main clock (f(XIN)). In this time, the start of oscillation and the
switch of system clock are not performed.
The oscillation start/stop of main clock f(XIN) is controlled by bit 1
of register MR. The system clock is selected by bit 0 of register
MR. The oscillation start/stop of on-chip oscillator is controlled by
register RG.
The oscillation circuit by the CMCK, CRCK or CYCK instruction
can be selected only at once.
The oscillation circuit corresponding to the first executed one of
these instructions is valid.
Execute the main clock (f(XIN)) selection instruction (CMCK, CRCK
or CYCK instruction) in the initial setting routine of program (executing it in address 0 in page 0 is recommended).
When the CMCK, CRCK, and CYCK instructions are never executed, main clock (f(X IN)) cannot be used and system can be
operated only by on-chip oscillator.
The no operated clock source (f(RING)) or (f(XIN)) cannot be used
for the system clock. Also, the clock source (f(RING) or f(XIN)) selected for the system clock cannot be stopped.
The clock control circuit consists of the following circuits.
• On-chip oscillator (internal oscillator)
• Ceramic resonator
• RC oscillation circuit
• Quartz-crystal oscillation circuit
• Multi-plexer (clock selection circuit)
• Frequency divider
• Internal clock generating circuit
The system clock and the instruction clock are generated as the
source clock for operation by these circuits.
Figure 56 shows the structure of the clock control circuit.
The 4518 Group operates by the on-chip oscillator clock (f(RING))
which is the internal oscillator after system is released from reset.
Also, the ceramic resonator, the RC oscillation or quartz-crystal oscillator can be used for the main clock (f(XIN)) of the 4518 Group.
The CMCK instruction, CRCK instruction or CYCK instruction is executed to select the ceramic resonator, RC oscillator or
quartz-crystal oscillator respectively.
Division circuit
Divided by 8
MR3, MR2
11
System clock (STCK)
10
MR0
1
On-chip oscillator
(internal oscillator)
Divided by 4
Divided by 2
Internal clock
generating circuit
(divided by 3)
01
00
0
RG0
S
XIN
XOUT
Ceramic
resonance
Multiplexer
R Q
Q S
RC oscillation
R
Q S
Quartz-crystal
oscillation
MR1
R
page 67 of 157
CYCK instruction
R
Internal reset signal
Key-on wakeup signal
Q S
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CRCK instruction
R
Q S
Fig. 56 Clock control circuit structure
CMCK instruction
EPOF instruction +
POF instruction
Instruction clock
(INSTCK)
4518 Group
(1) Main clock generating circuit (f(XIN))
The ceramic resonator, RC oscillation or quartz-crystal oscillator
can be used for the main clock of this MCU.
After system is released from reset, the MCU starts operation by
the clock output from the on-chip oscillator which is the internal oscillator.
When the ceramic resonator is used, execute the CMCK instruction. When the RC oscillation is used, execute the CRCK
instruction. When the quartz-crystal oscillator is used, execute the
CYCK instruction. The oscillation start/stop of main clock f(XIN) is
controlled by bit 1 of register MR. The system clock is selected by
bit 0 of register MR. The oscillation circuit by the CMCK, CRCK or
CYCK instruction can be selected only at once. The oscillation circuit corresponding to the first executed one of these instructions is
valid.
Execute the CMCK, CRCK or CYCK instruction in the initial setting
routine of program (executing it in address 0 in page 0 is recommended). Also, when the CMCK, CRCK or CYCK instruction is not
executed in program, this MCU operates by the on-chip oscillator.
Reset
On-chip oscillator operation
CMCK instruction
• Main clock: ceramic resonance
• On-chip oscillator: operating
• System clock: on-chip oscillator clock
CRCKinstruction
• Main clock: RC oscillation circuit
• On-chip oscillator: operating
• System clock: on-chip oscillator clock
CYCK instruction
• Main clock: Quartz-crystal circuit
• On-chip oscillator: operating
• System clock: on-chip oscillator clock
• Set the main clock (f(XIN)) oscillation by bit 1 of register MR.
• Switch the system clock by bit 0 of register MR.
Also, when system clock is switched after main clock oscillation is started,
generate the oscillation stabilizing wait time by program if necessary.
• Set the on-chip oscillator clock oscillation by register RG.
Fig. 57 Switch to ceramic resonance/RC oscillation/quartz-crystal oscillation
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4518 Group
(2) On-chip oscillator operation
When the MCU operates by the on-chip oscillator as the main clock
(f(X IN )) without using the ceramic resonator, RC oscillator or
quartz-crystal oscillation, leave XIN pin and XOUT pin open (Figure
58).
The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range.
Be careful that variable frequencies when designing application
products.
M34518
not use the CMCK, CRCK and
* Do
CYCK instructions in program.
XIN
XOUT
Open
Open
Fig. 58 Handling of XIN and XOUT when operating on-chip oscillator
M34518
(3) Ceramic resonator
When the ceramic resonator is used as the main clock (f(X IN)),
connect the ceramic resonator and the external circuit to pins XIN
and XOUT at the shortest distance. Then, execute the CMCK instruction. A feedback resistor is built in between pins XIN and XOUT
(Figure 59).
XIN
Execute the CMCK instruction in program.
XOUT
Note: Externally connect a damping
resistor Rd depending on the
oscillation frequency.
Rd
(A feedback resistor is built-in.)
Use the resonator manufacturer’s recommended value
COUT
because constants such as capacitance depend on the
resonator.
CIN
(4) RC oscillation
When the RC oscillation is used as the main clock (f(XIN)), connect
the XIN pin to the external circuit of resistor R and the capacitor C
at the shortest distance and leave XOUT pin open. Then, execute
the CRCK instruction (Figure 60).
The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency
limits.
*
Fig. 59 Ceramic resonator external circuit
M34518
XIN
R
XOUT
(5) Quartz-crystal oscillator
When a quartz-crystal oscillator is used as the main clock (f(XIN)),
connect this external circuit and a quartz-crystal oscillator to pins
XIN and XOUT at the shortest distance. Then, execute the CYCK instruction. A feedback resistor is built in between pins XIN and XOUT
(Figure 61).
Open
C
Fig. 60 External RC oscillation circuit
(6) External clock
the CYCK instruction
* Execute
in program.
M34518
When the external clock signal for the main clock (f(XIN)) is used,
connect the clock source to XIN pin and XOUT pin open. In program,
after the CMCK instruction is executed, set main clock (f(XIN)) oscillation start to be enabled (MR1=0).
For this product, when RAM back-up mode and main clock (f(XIN))
stop (MR1=1), XIN pin is fixed to “H” in order to avoid the through
current by floating of internal logic. The XIN pin is fixed to “H” until
main clock (f(XIN)) oscillation starts to be valid (MR 1=0) by the
CMCK instruction from reset state. Accordingly, when an external
clock is used, connect a 1 kΩ or more resistor to XIN pin in series
to limit of current by competitive signal.
the CRCK
* Execute
instruction in program.
XIN
XOUT
Note: Externally connect a damping
resistor Rd depending on the
oscillation frequency.
(A feedback resistor is built-in.)
Use the quartz-crystal manuCOUT
facturer’s recommended value
because constants such as capacitance depend on the
resonator.
Rd
CIN
Fig. 61 External quartz-crystal circuit
the CMCK instruction in
* Execute
program, and set the main clock
M34518
XIN
f(XIN) to be enabled (MR1=0)
XOUT
VDD
Open
R
1kΩ or more
VSS
External oscillation circuit
Fig. 62 External clock input circuit
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page 69 of 157
4518 Group
(7) Clock control register MR
(8) Clock control register RG
Register MR controls system clock. Set the contents of this register
through register A with the TMRA instruction. In addition, the TAMR
instruction can be used to transfer the contents of register MR to
register A.
Register RG controls start/stop of on-chip oscillator. Set the contents of this register through register A with the TRGA instruction.
Table 22 Clock control registers
Clock control register MR
MR3
Operation mode selection bits
MR2
MR1
Main clock f(XIN) oscillation circuit control bit
MR0
System clock oscillation source selection bit
at reset : 11112
MR3 MR2
0
0
0
1
1
0
1
1
On-chip oscillator (f(RING)) control bit
Frequency divided by 8 mode
Main clock (f(XIN)) oscillation stop
Main clock (f(XIN))
1
Main clock (f(RING))
at reset : 02
ROM ORDERING METHOD
1.Mask ROM Order Confirmation Form✽
2.Mark Specification Form✽
3.Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk.
✽ For the mask ROM confirmation and the mark specifications, refer to the “Renesas Technology Corp.” Homepage
(http://www.renesas.com/en/rom).
page 70 of 157
Frequency divided by 4 mode
Main clock (f(XIN)) oscillation enabled
Note: “R” represents read enabled, and “W” represents write enabled.
Rev.3.01 2005.06.15
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Frequency divided by 2 mode
1
0
0
1
R/W
TAMR/
TMRA
Operation mode
Through mode (frequency not divided)
0
Clock control register RG
RG0
at RAM back-up : 11112
at RAM back-up : 02
On-chip oscillator (f(RING)) oscillation enabled
On-chip oscillator (f(RING)) oscillation stop
W
TRGA
4518 Group
LIST OF PRECAUTIONS
➀Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
• connect a bypass capacitor (approx. 0.1 µF) between pins VDD
and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use relatively thick wire.
In the One Time PROM version, CNVSS pin is also used as VPP
pin. Accordingly, when using this pin, connect this pin to VSS
through a resistor about 5 kΩ (connect this resistor to CNVSS/
VPP pin as close as possible).
➁Register initial values 1
The initial value of the following registers are undefined after system is released from reset. After system is released from reset,
set initial values.
• Register Z (2 bits)
• Register D (3 bits)
• Register E (8 bits)
➂Register initial values 2
The initial value of the following registers are undefined at RAM backup. After system is returned from RAM back-up, set initial values.
• Register Z (2 bits)
• Register X (4 bits)
• Register Y (4 bits)
• Register D (3 bits)
• Register E (8 bits)
➃ Stack registers (SKS)
Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack
registers is used respectively when using an interrupt service
routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these
operations together.
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➄ Multifunction
• The input/output of P30 and P3 1 can be used even when INT0
and INT1 are selected.
• The input of ports P2 0–P22 can be used even when S IN, S OUT
and SCK are selected.
• The input/output of D6 can be used even when CNTR0 (input) is
selected.
• The input of D6 can be used even when CNTR0 (output) is selected.
• The input/output of D7 can be used even when CNTR1 (input) is
selected.
• The input of D7 can be used even when CNTR1 (output) is selected.
➅ Prescaler
Stop counting and then execute the TABPS instruction to read
from prescaler data.
Stop counting and then execute the TPSAB instruction to set
prescaler data.
➆ Timer count source
Stop timer 1, 2, 3 and 4 counting to change its count source.
➇Reading the count value
Stop timer 1, 2, 3 or 4 counting and then execute the data read
instruction (TAB1, TAB2, TAB3, TAB4) to read its data.
➈Writing to the timer
Stop timer 1, 2, 3 or 4 counting and then execute the data write
instruction (T1AB, T2AB, T3AB, T4AB) to write its data.
10
Writing to reload register R1, R3, R4H
When writing data to reload register R1, reload register R3 or reload register R4H while timer 1, timer 3 or timer 4 is operating,
avoid a timing when timer 1, timer 3 or timer 4 underflows.
11
Timer 4
Avoid a timing when timer 4 underflows to stop timer 4 at the use
of PWM output function.
When “H” interval extension function of the PWM signal is set to
be “valid”, set “1” or more to reload register R4H.
4518 Group
Watchdog timer
• The watchdog timer function is valid after system is released
from reset. When not using the watchdog timer function, execute
the DWDT instruction and the WRST instruction continuously,
and clear the WEF flag to “0” to stop the watchdog timer function.
• The watchdog timer function is valid after system is returned
from the RAM back-up state. When not using the watchdog timer
function, execute the DWDT instruction and the WRST instruction continuously every system is returned from the RAM
back-up state, and stop the watchdog timer function.
• When the watchdog timer function and RAM back-up function are
used at the same time, execute the WRST instruction before
system enters into the RAM back-up state and initialize the flag
12
13
Prescaler, Timer 1, Timer 2 and Timer 3 count start timing and
count time when operation starts
Count starts from the first rising edge of the count source (2) after Prescaler, Timer 1, Timer 2 and Timer 3 operations start (1).
Time to first underflow (3) is shorter (for up to 1 period of the
count source) than time among next underflow (4) by the timing
to start the timer and count source operations after count starts.
AA
A
(2)
Count Source
Timer value
3
2
1
0
3
2
1
0
3
2
Timer Underflow signal
(3)
(4)
(1) Timer Start
Fig. 63 Timer count start timing and count time when operation starts (Prescaler, Timer 1, Timer 2 and Timer 3)
14
Timer 4 count start timing and count time when operation starts
Count starts from the rising edge (2) after the first falling edge of
the count source, after Timer 4 operations start (1).
Time to first underflow (3) is different from time among next underflow (4) by the timing to start the timer and count source
operations after count starts.
AA
A
(2)
Count Source
Timer Value
3
2
1
0
3
2
1
0
3
Timer Underflow Signal
(3)
(4)
(1) Timer Start
Fig. 64 Timer count start timing and count time when operation starts (Timer 4)
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Period measurement circuit
When a period measurement circuit is used, clear bit 0 of register I1 to “0”, and set a timer 1 count start synchronous circuit to
be “not selected”.
Start timer operation immediately after operation of a period
measurement circuit is started.
When the edge for measurement is input until timer operation is
started from the operation of period measurement circuit is
started, the count operation is not executed until the timer operation becomes valid. Accordingly, be careful of count data.
When data is read from timer, stop the timer and clear bit 2 of
register W5 to “0” to stop the period measurement circuit, and
then execute the data read instruction.
Depending on the state of timer 1, the timer 1 interrupt request
flag (T1F) may be set to “1” when the period measurement circuit is stopped by clearing bit 2 of register W5 to “0”. In order to
avoid the occurrence of an unexpected interrupt, clear the bit 2
of register V1 to “0” (refer to Figure 65➀) and then, stop the bit 2
of register W5 to “0” to stop the period measurement circuit.
In addition, execute the SNZT1 instruction to clear the T1F flag
after executing at least one instruction (refer to Figure 65➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZT1 instruction (refer to Figure 65➂).
While a period measurement circuit is operating, the timer 1 interrupt request flag (T1F) is not set by the timer 1 underflow
signal, it is the flag for detecting the completion of period measurement.
When a period measurement circuit is used, select the sufficiently higher-speed frequency than the signal for measurement
for the count source of a timer 1.
When the signal for period measurement is D6/CNTR0 pin input,
do not select D6/CNTR0 pin input as timer 1 count source.
(The X IN input is recommended as timer 1 count source at the
time of period measurement circuit use.)
When the input of P30/INT0 pin is selected for measurement, set
the bit 3 of a register I1 to “1”, and set the input of INT0 pin to be
enabled.
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LA
0
TV1A
LA
0
TW5A
NOP
SNZT1
NOP
; (✕0✕✕2)
; The SNZT1 instruction is valid ........ ➀
; (✕0✕✕2)
; Period measurement circuit stop
........................................................... ➁
; The SNZT1 instruction is executed
(T1F flag cleared)
........................................................... ➂
•••
15
•••
4518 Group
✕ : these bits are not used here.
Fig. 65 Period measurement circuit program example
4518 Group
P30/INT0 pin
❶ Note [1] on bit 3 of register I1
When the input of the INT0 pin is controlled with the bit 3 of register I1 in software, be careful about the following notes.
❸ Note on bit 2 of register I1
When the interrupt valid waveform of the P3 0 /INT0 pin is
changed with the bit 2 of register I1 in software, be careful about
the following notes.
• Depending on the input state of the P30/INT0 pin, the external 0
interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to
Figure 66 ➀) and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction (refer to Figure 66 ➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 66 ➂).
• Depending on the input state of the P3 0/INT0 pin, the external 0
interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to
Figure 68➀) and then, change the bit 2 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction (refer to Figure 68➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 68➂).
•••
NOP
; (✕✕✕02)
; The SNZ0 instruction is valid ........... ➀
; (1✕✕✕2)
; Control of INT0 pin input is changed
........................................................... ➁
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... ➂
✕ : these bits are not used here.
LA
4
TV1A
LA
12
TI1A
NOP
SNZ0
NOP
; (✕✕✕02)
; The SNZ0 instruction is valid ........... ➀
; (✕1✕✕2)
; Interrupt valid waveform is changed
........................................................... ➁
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... ➂
•••
LA
4
TV1A
LA
8
TI1A
NOP
SNZ0
•••
•••
16
Fig. 66 External 0 interrupt program example-1
✕ : these bits are not used here.
❷ Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared to “0”, the RAM back-up
mode is selected and the input of INT0 pin is disabled, be careful
about the following notes.
•••
• When the input of INT0 pin is disabled (register I13 = “0”), set the
key-on wakeup function to be invalid (register K20 = “0”) before
system enters to the RAM back-up mode. (refer to Figure 67➀).
; (✕✕✕02)
; Input of INT0 key-on wakeup invalid .. ➀
; RAM back-up
•••
LA
0
TK2A
DI
EPOF
POF
✕ : these bits are not used here.
Fig. 67 External 0 interrupt program example-2
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Fig. 68 External 0 interrupt program example-3
4518 Group
❸ Note on bit 2 of register I2
When the interrupt valid waveform of the P3 1 /INT1 pin is
changed with the bit 2 of register I2 in software, be careful about
the following notes.
• Depending on the input state of the P31/INT1 pin, the external 1
interrupt request flag (EXF1) may be set when the bit 3 of register I2 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to
Figure 69➀) and then, change the bit 3 of register I2.
In addition, execute the SNZ1 instruction to clear the EXF1 flag to
“0” after executing at least one instruction (refer to Figure 69➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to Figure 69➂).
• Depending on the input state of the P31/INT1 pin, the external 1
interrupt request flag (EXF1) may be set when the bit 2 of register I2 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to
Figure 71➀) and then, change the bit 2 of register I2.
In addition, execute the SNZ1 instruction to clear the EXF1 flag to
“0” after executing at least one instruction (refer to Figure 71➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to Figure 71➂).
•••
•••
17 P31/INT1 pin
❶ Note [1] on bit 3 of register I2
When the input of the INT1 pin is controlled with the bit 3 of register I2 in software, be careful about the following notes.
LA
4
TV1A
LA
8
TI2A
NOP
SNZ1
LA
4
TV1A
LA
12
TI2A
NOP
SNZ1
•••
NOP
; (✕✕0✕2)
; The SNZ1 instruction is valid ........... ➀
; (✕1✕✕2)
; Interrupt valid waveform is changed
........................................................... ➁
; The SNZ1 instruction is executed
(EXF1 flag cleared)
........................................................... ➂
•••
NOP
; (✕✕0✕2)
; The SNZ1 instruction is valid ........... ➀
; (1✕✕✕2)
; Control of INT1 pin input is changed
........................................................... ➁
; The SNZ1 instruction is executed
(EXF1 flag cleared)
........................................................... ➂
✕ : these bits are not used here.
✕ : these bits are not used here.
Fig. 69 External 1 interrupt program example-1
❷ Note [2] on bit 3 of register I2
When the bit 3 of register I2 is cleared to “0”, the RAM back-up
mode is selected and the input of INT1 pin is disabled, be careful
about the following notes.
•••
• When the input of INT1 pin is disabled (register I23 = “0”), set the
key-on wakeup function to be invalid (register K22 = “0”) before
system enters to the RAM back-up mode. (refer to Figure 70➀).
; (✕0✕✕2)
; Input of INT1 key-on wakeup invalid .. ➀
; RAM back-up
•••
LA
0
TK2A
DI
EPOF
POF
✕ : these bits are not used here.
Fig. 70 External 1 interrupt program example-2
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Fig. 71 External 1 interrupt program example-3
4518 Group
19
A/D converter-2
Each analog input pin is equipped with a capacitor which is used
to compare the analog voltage. Accordingly, when the analog voltage is input from the circuit with high-impedance and, charge/
discharge noise is generated and the sufficient A/D accuracy may
not be obtained. Therefore, reduce the impedance or, connect a
capacitor (0.01 µF to 1 µF) to analog input pins (Figure 73).
When the overvoltage applied to the A/D conversion circuit may
occur, connect an external circuit in order to keep the voltage
within the rated range as shown the Figure 74. In addition, test
the application products sufficiently.
Sensor
AI N
•••
18 A/D converter-1
• When the TALA instruction is executed, the low-order 2 bits of
register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is “0.”
• Do not change the operating mode (both A/D conversion mode
and comparator mode) of A/D converter with the bit 3 of register
Q1 while the A/D converter is operating.
• Clear the bit 2 of register V2 to “0” to change the operating mode of
the A/D converter from the comparator mode to A/D conversion mode.
• The A/D conversion completion flag (ADF) may be set when the
operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a
value to the register Q1, and execute the SNZAD instruction to
clear the ADF flag.
LA
8
TV2A
LA
0
TQ1A
; (✕0✕✕2)
; The SNZAD instruction is valid ........ ➀
; (0✕✕✕2)
; Operation mode of A/D converter is
changed from comparator mode to A/D
conversion mode.
Apply the voltage withiin the specifications
to an analog input pin.
Fig. 73 Analog input external circuit example-1
•••
SNZAD
NOP
About 1kΩ
✕ : these bits are not used here.
Sensor
AIN
Fig. 72 A/D converter program example-3
Fig. 74 Analog input external circuit example-2
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4518 Group
20
POF instruction
When the POF instruction is executed continuously after the
EPOF instruction, system enters the RAM back-up state.
Note that system cannot enter the RAM back-up state when executing only the POF instruction.
Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction and the POF instruction
continuously.
21
Program counter
Make sure that the PC does not specify after the last page of the
built-in ROM.
22
Power-on reset
When the built-in power-on reset circuit is used, the time for the
supply voltage to rise from 0 V to the value of supply voltage or
more must be set to 100 µs or less. If the rising time exceeds
100 µs, connect a capacitor between the RESET pin and VSS at
the shortest distance, and input “L” level to RESET pin until the
value of supply voltage reaches the minimum operating voltage.
23
Clock control
Execute the main clock (f(X IN)) selection instruction (CMCK,
CRCK or CYCK instruction) in the initial setting routine of program (executing it in address 0 in page 0 is recommended).
The oscillation circuit by the CMCK, CRCK or CYCK instruction
can be selected only at once. The oscillation circuit corresponding to the first executed one of these instructions is valid.
The CMCK, CRCK, and CYCK instructions can be used only to
select main clock (f(XIN)). In this time, the start of oscillation and
the switch of system clock are not performed.
When the CMCK, CRCK, and CYCK instructions are never executed, main clock (f(XIN)) cannot be used and system can be
operated only by on-chip oscillator.
The no operated clock source (f(RING)) or (f(XIN)) cannot be
used for the system clock. Also, the clock source (f(RING) or
f(XIN)) selected for the system clock cannot be stopped.
24
On-chip oscillator
The clock frequency of the on-chip oscillator depends on the
supply voltage and the operation temperature range.
Be careful that variable frequencies when designing application
products.
When considering the oscillation stabilize wait time at the switch
of clock, be careful that the variable frequency of the on-chip
oscillator clock.
Rev.3.01 2005.06.15
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page 77 of 157
25
External clock
When the external clock signal for the main clock (f(XIN)) is used,
connect the clock source to XIN pin and XOUT pin open. In program, after the CMCK instruction is executed, set main clock
(f(XIN)) oscillation start to be enabled (MR1=0).
For this product, when RAM back-up mode and main clock
(f(XIN)) stop (MR1=1), XIN pin is fixed to “H” in order to avoid the
through current by floating of internal logic. The XIN pin is fixed to
“H” until main clock (f(XIN)) oscillation start to be valid (MR1=0)
by the CMCK instruction from reset state. Accordingly, when an
external clock is used, connect a 1 kΩ or more resistor to XIN pin
in series to limit of current by competitive signal.
26
Electric Characteristic Differences Between Mask ROM and One
Time PROM Version MCU
There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between Mask ROM and
One Time PROM version MCUs due to the difference in the
manufacturing processes.
When manufacturing an application system with the One time
PROM version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial
samples of the Mask ROM version.
27
Note on Power Source Voltage
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and
may perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the supply voltage is less than the
recommended operating conditions and design a system not to
cause errors to the system by this unstable operation.
4518 Group
CONTROL REGISTERS
Interrupt control register V1
V13
Timer 2 interrupt enable bit
V12
Timer 1 interrupt enable bit
V11
External 1 interrupt enable bit
V10
External 0 interrupt enable bit
at reset : 00002
0
1
0
1
0
1
0
1
Interrupt control register V2
V23
Serial I/O interrupt enable bit
V22
A/D interrupt enable bit
V21
Timer 4 interrupt enable bit
V20
Timer 3 interrupt enable bit
0
1
0
1
0
1
0
1
I12
I11
I10
INT0 pin input control bit (Note 2)
Interrupt valid waveform for INT0 pin/
return level selection bit (Note 2)
INT0 pin edge detection circuit control bit
INT0 pin Timer 1 count start synchronous
circuit selection bit
0
1
0
1
0
1
Interrupt control register I2
I23
I22
I21
I20
INT1 pin input control bit (Note 2)
Interrupt valid waveform for INT1 pin/
return level selection bit (Note 2)
INT1 pin edge detection circuit control bit
INT1 pin Timer 3 count start synchronous
circuit selection bit
at RAM back-up : 00002
0
1
0
1
0
1
at RAM back-up : state retained
INT0 pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI0
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI0
instruction)
One-sided edge detected
Both edges detected
Timer 1 count start synchronous circuit not selected
Timer 1 count start synchronous circuit selected
at RAM back-up : state retained
page 78 of 157
R/W
TAI2/TI2A
INT1 pin input disabled
INT1 pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI1
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI1
instruction)
One-sided edge detected
Both edges detected
Timer 3 count start synchronous circuit not selected
Timer 3 count start synchronous circuit selected
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12, I13 I22 and I23 are changed, the external interrupt request flag (EXF0, EXF1) may be set to "1".
Rev.3.01 2005.06.15
REJ03B0008-0301
R/W
TAI1/TI1A
INT0 pin input disabled
at reset : 00002
0
1
R/W
TAV2/TV2A
Interrupt disabled (SNZSI instruction is valid)
Interrupt enabled (SNZSI instruction is invalid)
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid)
Interrupt disabled (SNZT4 instruction is valid)
Interrupt enabled (SNZT4 instruction is invalid)
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid)
at reset : 00002
0
1
R/W
TAV1/TV1A
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
Interrupt disabled (SNZ1 instruction is valid)
Interrupt enabled (SNZ1 instruction is invalid)
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
at reset : 00002
Interrupt control register I1
I13
at RAM back-up : 00002
4518 Group
Clock control register MR
MR3
Operation mode selection bits
MR2
MR1
Main clock f(XIN) oscillation circuit control bit
MR0
System clock oscillation source selection bit
at reset : 11112
MR3 MR2
0
0
0
1
1
0
1
1
On-chip oscillator (f(RING)) control bit
Prescaler control bit
Timer 1 count auto-stop circuit selection
bit
(Note 2)
W12
Timer 1 control bit
W11
Timer 1 count source selection bits
W10
1
Main clock (f(RING))
CNTR0 output signal selection bit
W22
Timer 2 control bit
W21
Timer 2 count source selection bits
W20
at RAM back-up : 02
at reset : 02
0
1
On-chip oscillator (f(RING)) oscillation stop
at RAM back-up : 02
W
TPAA
at RAM back-up : state retained
R/W
TAW1/TW1A
Stop (state initialized)
Operating
at reset : 00002
0
1
0
1
Timer 1 count auto-stop circuit not selected
Timer 1 count auto-stop circuit selected
Stop (state retained)
Operating
W11 W10
Count source
0
Instruction clock (INSTCK)
0
0
Prescaler output (ORCLK)
1
1
XIN input
0
1
CNTR0 input
1
at reset : 00002
at RAM back-up : state retained
0
1
0
1
Timer 1 underflow signal divided by 2 output
Timer 2 underflow signal divided by 2 output
Stop (state retained)
Operating
W21 W20
Count source
0
System clock (STCK)
0
0
Prescaler output (ORCLK)
1
1
Timer 1 underflow signal (T1UDF)
0
1
PWM signal (PWMOUT)
1
Note 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”).
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W
TRGA
On-chip oscillator (f(RING)) oscillation enabled
at reset : 02
Timer control register W2
W23
Frequency divided by 8 mode
Main clock (f(XIN)) oscillation stop
Main clock (f(XIN))
Timer control register W1
W13
Frequency divided by 4 mode
Main clock (f(XIN)) oscillation enabled
Timer control register PA
PA0
Frequency divided by 2 mode
1
0
0
1
R/W
TAMR/
TMRA
Operation mode
Through mode (frequency not divided)
0
Clock control register RG
RG0
at RAM back-up : 11112
R/W
TAW2/TW2A
4518 Group
Timer control register W3
W33
Timer 3 count auto-stop circuit selection
bit (Note 2)
W32
Timer 3 control bit
W31
Timer 3 count source selection bits
W30
at reset : 00002
D7/CNTR1 pin function selection bit
W42
PWM signal
“H” interval expansion function control bit
W41
Timer 4 control bit
W40
Timer 4 count source selection bit
Timer 3 count auto-stop circuit not selected
Timer 3 count auto-stop circuit selected
Stop (state retained)
Operating
W31 W30
Count source
0
PWM signal (PWMOUT)
0
0
Prescaler output (ORCLK)
1
1
Timer 2 underflow signal (T2UDF)
0
1
CNTR1 input
1
Not used
W52
Period measurement circuit control bit
W51
Signal for period measurement selection
bits
W50
0
1
0
1
0
1
0
1
CNTR1 pin input count edge selection bit
W62
CNTR0 pin input count edge selection bit
W61
CNTR1 output auto-control circuit
selection bit
W60
D6/CNTR0 pin function selection bit
Prescaler output (ORCLK) divided by 2
0
1
0
1
at RAM back-up : state retained
Stop
Operating
Count source
On-chip oscillator (f(RING/16))
CNTR0 pin input
INT0 pin input
Not available
at reset : 00002
at RAM back-up : state retained
Falling edge
Rising edge
Falling edge
Rising edge
CNTR1 output auto-control circuit not selected
CNTR1 output auto-control circuit selected
D6 (I/O) / CNTR0 (input)
CNTR0 (I/O) /D6 (input)
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the timer 3 count start synchronous circuit is selected (I20=“1”).
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R/W
TAW5/TW5A
This bit has no function, but read/write is enabled.
W51 W50
0
0
0
1
1
0
1
1
0
1
0
1
0
1
0
1
R/W
TAW4/TW4A
D7 (I/O) / CNTR1 (input)
CNTR1 (I/O) / D7 (input)
PWM signal “H” interval expansion function invalid
PWM signal “H” interval expansion function valid
Stop (state retained)
Operating
XIN input
at reset : 00002
Timer control register W6
W63
at RAM back-up : 00002
at reset : 00002
Timer control register W5
W53
R/W
TAW3/TW3A
0
1
0
1
Timer control register W4
W43
at RAM back-up : state retained
R/W
TAW6/TW6A
4518 Group
Serial I/O control register J1
J13
J12
J11
J10
at reset : 00002
A/D operation mode selection bit
Q12
Q11
Analog input pin selection bits
Q10
at reset : 00002
A/D conversion mode
Comparator mode
Q12 Q11 Q10
0
0
0 AIN0
0
0
1 AIN1
0
1
0 AIN2
0
1
1 AIN3
1
0
0 Not available
1
0
1 Not available
1
1
0 Not available
1
1
1 Not available
A/D control register Q2
Q23
Not used
Q22
P62/AIN2, P63/AIN3 pin function selection bit
Q21
P61/AIN1 pin function selection bit
Q20
P60/AIN0 pin function selection bit
at reset : 00002
0
1
0
1
0
1
0
1
Q33
Not used
Q32
A/D converter operation clock selection bit
Q31
A/D converter operation clock division
ratio selection bits
0
1
0
1
Note: “R” represents read enabled, and “W” represents write enabled.
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R/W
TAQ1/TQ1A
Analog input pins
at RAM back-up : state retained
R/W
TAQ2/TQ2A
P62, P63
AIN2, AIN3
P61
AIN1
P60
AIN0
at reset : 00002
Q31
0
0
1
1
at RAM back-up : state retained
This bit has no function, but read/write is enabled.
A/D control register Q3
Q30
R/W
TAJ1/TJ1A
Synchronous clock
J13 J12
0 Instruction clock (INSTCK) divided by 8
0
Serial I/O synchronous clock selection bits 0
1 Instruction clock (INSTCK) divided by 4
0 Instruction clock (INSTCK) divided by 2
1
1 External clock (SCK input)
1
Port function
J11 J10
0 P20, P21,P22 selected/SCK, SOUT, SIN not selected
0
Serial I/O port function selection bits
1 SCK, SOUT, P22 selected/P20, P21, SIN not selected
0
0 SCK, P21, SIN selected/P20, SOUT, P22 not selected
1
1 SCK, SOUT, SIN selected/P20, P21,P22 not selected
1
A/D control register Q1
Q13
at RAM back-up : state retained
at RAM back-up : state retained
This bit has no function, but read/write is enabled.
Instruction clock (INSTCK)
On-chip oscillator (f(RING))
Division ratio
Q30
0 Frequency divided by 6
1 Frequency divided by 12
0 Frequency divided by 24
1 Frequency divided by 48
R/W
TAQ3/TQ3A
4518 Group
Key-on wakeup control register K0
K03
K02
K01
K00
at reset : 00002
Pins P12 and P13 key-on wakeup
0
Key-on wakeup not used
control bit
Pins P10 and P11 key-on wakeup
1
Key-on wakeup used
0
Key-on wakeup not used
control bit
1
Key-on wakeup used
Pins P02 and P03 key-on wakeup
Key-on wakeup not used
control bit
0
1
Pins P00 and P01 key-on wakeup
0
Key-on wakeup used
Key-on wakeup not used
control bit
1
Key-on wakeup used
Key-on wakeup control register K1
K13
K12
K11
K10
at reset : 00002
K22
K21
K20
at RAM back-up : state retained
Ports P02 and P03 return condition selection
bit
0
Return by level
1
Return by edge
Ports P02 and P03 valid waveform/
0
Falling waveform/“L” level
level selection bit
Rising waveform/“H” level
Ports P01 and P00 return condition selection
1
0
bit
1
Ports P01 and P00 valid waveform/
level selection bit
0
Falling waveform/“L” level
1
Rising waveform/“H” level
INT1 pin return condition selection bit
INT1 pin key-on wakeup contro bit
INT0 pin return condition selection bit
INT0 pin key-on wakeup contro bit
Rev.3.01 2005.06.15
REJ03B0008-0301
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at RAM back-up : state retained
0
Return by level
1
Return by edge
0
1
Key-on wakeup not used
0
Key-on wakeup used
Return by level
1
Return by edge
0
Key-on wakeup not used
1
Key-on wakeup used
Note: “R” represents read enabled, and “W” represents write enabled.
R/W
TAK0/TK0A
R/W
TAK1/TK1A
Return by level
Return by edge
at reset : 00002
Key-on wakeup control register K2
K23
at RAM back-up : state retained
R/W
TAK2/TK2A
4518 Group
Pull-up control register PU0
PU03
PU02
PU01
PU00
at reset : 00002
P03 pin pull-up transistor
0
Pull-up transistor OFF
control bit
P02 pin pull-up transistor
1
Pull-up transistor ON
0
Pull-up transistor OFF
control bit
Pull-up transistor ON
P01 pin pull-up transistor
1
0
control bit
1
P00 pin pull-up transistor
0
Pull-up transistor ON
Pull-up transistor OFF
control bit
1
Pull-up transistor ON
PU13
PU12
PU11
PU10
P13 pin pull-up transistor
0
Pull-up transistor OFF
control bit
1
P12 pin pull-up transistor
0
Pull-up transistor ON
Pull-up transistor OFF
control bit
1
0
Pull-up transistor ON
control bit
P10 pin pull-up transistor
1
Pull-up transistor ON
0
Pull-up transistor OFF
control bit
1
Pull-up transistor ON
P11 pin pull-up transistor
Note: “R” represents read enabled, and “W” represents write enabled.
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R/W
TAPU0/
TPU0A
at RAM back-up : state retained
R/W
TAPU1/
TPU1A
Pull-up transistor OFF
at reset : 00002
Pull-up control register PU1
at RAM back-up : state retained
Pull-up transistor OFF
4518 Group
Port output structure control register FR0
FR03
FR02
FR01
FR00
Ports P12, P13 output structure selection
at reset : 00002
0
1
N-channel open-drain output
Ports P10, P11 output structure selection
bit
0
N-channel open-drain output
1
CMOS output
Ports P02, P03 output structure selection
0
bit
1
N-channel open-drain output
CMOS output
Ports P00, P01 output structure selection
0
1
bit
bit
FR13
Port D3 output structure selection bit
FR12
Port D2 output structure selection bit
FR10
Port D1 output structure selection bit
Port D0 output structure selection bit
FR23
Port D7/CNTR1 output structure selection bit
FR22
Port D6/CNTR0 output structure selection bit
FR21
Port D5 output structure selection bit
FR20
Port D4 output structure selection bit
page 84 of 157
CMOS output
at RAM back-up : state retained
N-channel open-drain output
1
0
CMOS output
1
CMOS output
0
N-channel open-drain output
1
0
CMOS output
N-channel open-drain output
1
CMOS output
at RAM back-up : state retained
0
N-channel open-drain output
1
CMOS output
N-channel open-drain output
0
W
TFR1A
N-channel open-drain output
at reset : 00002
1
0
CMOS output
1
CMOS output
0
N-channel open-drain output
1
CMOS output
Note: “R” represents read enabled, and “W” represents write enabled.
Rev.3.01 2005.06.15
REJ03B0008-0301
N-channel open-drain output
0
Port output structure control register FR2
W
TFR0A
CMOS output
at reset : 00002
Port output structure control register FR1
FR11
at RAM back-up : state retained
N-channel open-drain output
W
TFR2A
4518 Group
INSTRUCTIONS
SYMBOL
The 4518 Group has the 148 instructions. Each instruction is described as follows;
(1) Index list of instruction function
(2) Machine instructions (index by alphabet)
(3) Machine instructions (index by function)
(4) Instruction code table
The symbols shown below are used in the following list of instruction function and the machine instructions.
Symbol
A
B
DR
E
V1
V2
I1
I2
MR
RG
PA
W1
W2
W3
W4
W5
W6
J1
Q1
Q2
Q3
PU0
PU1
FR0
FR1
FR2
K0
K1
K2
X
Y
Z
DP
PC
PCH
PCL
SK
SP
CY
RPS
R1
R2
R3
R4L
R4H
Contents
Register A (4 bits)
Register B (4 bits)
Register DR (3 bits)
Register E (8 bits)
Interrupt control register V1 (4 bits)
Interrupt control register V2 (4 bits)
Interrupt control register I1 (4 bits)
Interrupt control register I2 (4 bits)
Clock control register MR (4 bits)
Clock control register RG (1 bit)
Timer control register PA (1 bit)
Timer control register W1 (4 bits)
Timer control register W2 (4 bits)
Timer control register W3 (4 bits)
Timer control register W4 (4 bits)
Timer control register W5 (4 bits)
Timer control register W6 (4 bits)
Serial I/O control register J1 (4 bits)
A/D control register Q1 (4 bits)
A/D control register Q2 (4 bits)
A/D control register Q3 (4 bits)
Pull-up control register PU0 (4 bits)
Pull-up control register PU1 (4 bits)
Port output format control register FR0 (4 bits)
Port output format control register FR1 (4 bits)
Port output format control register FR2 (4 bits)
Key-on wakeup control register K0 (4 bits)
Key-on wakeup control register K1 (4 bits)
Key-on wakeup control register K2 (4 bits)
Register X (4 bits)
Register Y (4 bits)
Register Z (2 bits)
Data pointer (10 bits)
(It consists of registers X, Y, and Z)
Program counter (14 bits)
High-order 7 bits of program counter
Low-order 7 bits of program counter
Stack register (14 bits ✕ 8)
Stack pointer (3 bits)
Carry flag
Prescaler reload register (8 bits)
Timer 1 reload register (8 bits)
Timer 2 reload register (8 bits)
Timer 3 reload register (8 bits)
Timer 4 reload register (8 bits)
Timer 4 reload register (8 bits)
Symbol
PS
T1
T2
T3
T4
T1F
T2F
T3F
T4F
WDF1
WEF
INTE
EXF0
EXF1
P
ADF
SIOF
Contents
Prescaler
Timer 1
Timer 2
Timer 3
Timer 4
Timer 1 interrupt request flag
Timer 2 interrupt request flag
Timer 3 interrupt request flag
Timer 4 interrupt request flag
Watchdog timer flag
Watchdog timer enable flag
Interrupt enable flag
External 0 interrupt request flag
External 1 interrupt request flag
Power down flag
A/D conversion completion flag
Serial I/O transmit/receive completion flag
D
P0
P1
P2
P3
P6
Port D (8 bits)
Port P0 (4 bits)
Port P1 (4 bits)
Port P2 (3 bits)
Port P3 (2 bits)
Port P6 (4 bits)
x
y
z
p
n
i
j
A 3A 2A 1A 0
Hexadecimal variable
Hexadecimal variable
Hexadecimal variable
Hexadecimal variable
Hexadecimal constant
Hexadecimal constant
Hexadecimal constant
Binary notation of hexadecimal variable A
(same for others)
←
↔
?
( )
—
M(DP)
a
p, a
Direction of data movement
Data exchange between a register and memory
Decision of state shown before “?”
Contents of registers and memories
Negate, Flag unchanged after executing instruction
RAM address pointed by the data pointer
Label indicating address a6 a5 a4 a3 a2 a1 a0
Label indicating address a6 a5 a4 a3 a2 a1 a0
in page p5 p4 p3 p2 p1 p0
Hex. C + Hex. number x
C
+
x
Note : Some instructions of the 4518 Group has the skip function to unexecute the next described instruction. The 4518 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip
is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped.
Rev.3.01 2005.06.15
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4518 Group
INDEX LIST OF INSTRUCTION FUNCTION
Function
TAB
(A) ← (B)
TBA
(B) ← (A)
TAY
(A) ← (Y)
TYA
(Y) ← (A)
TEAB
(E7–E4) ← (B)
GroupMnemonic
ing
XAMI j
RAM to register transfer
GroupMnemonic
ing
Register to register transfer
(E3–E0) ← (A)
Function
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
TMA j
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
LA n
(A) ← n
n = 0 to 15
TABP p
(SP) ← (SP) + 1
(B) ← (E7–E4)
TABE
(A) ← (E3–E0)
(SK(SP)) ← (PC)
TDA
TAD
(DR2–DR0) ← (A2–A0)
(PCH) ← p
(A2–A0) ← (DR2–DR0)
(PCL) ← (DR2–DR0, A3–A0)
(DR2) ← 0
(A3) ← 0
(DR1, DR0) ← (ROM(PC))9, 8
(B) ← (ROM(PC))7–4
TAZ
(A1, A0) ← (Z1, Z0)
(A) ← (ROM(PC))3–0
(A3, A2) ← 0
(PC) ← (SK(SP))
(A) ← (X)
TASP
(A2–A0) ← (SP2–SP0)
(A3) ← 0
LXY x, y
(X) ← x x = 0 to 15
RAM addresses
(Y) ← y y = 0 to 15
LZ z
(Z) ← z z = 0 to 3
INY
(Y) ← (Y) + 1
DEY
(Y) ← (Y) – 1
TAM j
(A) ← (M(DP))
(X) ← (X)EXOR(j)
AM
(A) ← (A) + (M(DP))
AMC
(A) ← (A) + (M(DP)) + (CY)
(CY) ← Carry
An
(A) ← (A) + n
n = 0 to 15
AND
(A) ← (A) AND (M(DP))
OR
(A) ← (A) OR (M(DP))
SC
(CY) ← 1
RC
(CY) ← 0
SZC
(CY) = 0 ?
CMA
(A) ← (A)
RAR
→ CY → A3A2A1A0
RAM to register transfer
j = 0 to 15
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
XAM j
j = 0 to 15
XAMD j
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1
Note: p
p
p
p
Arithmetic operation
(SP) ← (SP) – 1
TAX
is
is
is
is
0
0
0
0
to
to
to
to
15
31
47
63
for
for
for
for
M34518M2,
M34518M4,
M34518M6,
M34518M8/E8.
Rev.3.01 2005.06.15
REJ03B0008-0301
page 86 of 157
4518 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Bit operation
GroupMnemonic
ing
Function
SB j
(Mj(DP)) ← 1
j = 0 to 3
RB j
(Mj(DP)) ← 0
GroupMnemonic
ing
j = 0 to 3
SZB j
(Mj(DP)) = 0 ?
j = 0 to 3
SEAM
(A) = (M(DP)) ?
SEA n
(A) = n ?
DI
(INTE) ← 0
EI
(INTE) ← 1
SNZ0
V10 = 0: (EXF0) = 1 ?
After skipping, (EXF0) ← 0
V10 = 1: NOP
SNZ1
Comparison
operation
Function
V11 = 0: (EXF1) = 1 ?
After skipping, (EXF1) ← 0
V11 = 1: NOP
SNZI0
n = 0 to 15
I12 = 1 : (INT0) = “H” ?
(PCL) ← a6–a0
BL p, a
(PCH) ← p
(PCL) ← a6–a0
BLA p
BM a
Interrupt operation
Branch operation
I12 = 0 : (INT0) = “L” ?
Ba
SNZI1
I22 = 1 : (INT1) = “H” ?
I22 = 0 : (INT1) = “L” ?
TAV1
(A) ← (V1)
(PCL) ← (DR2–DR0, A3–A0)
TV1A
(V1) ← (A)
(SP) ← (SP) + 1
TAV2
(A) ← (V2)
TV2A
(V2) ← (A)
TAI1
(A) ← (I1)
TI1A
(I1) ← (A)
(PCL) ← a6–a0
TAI2
(A) ← (I2)
(SP) ← (SP) + 1
TI2A
(I2) ← (A)
TPAA
(PA0) ← (A0)
TAW1
(A) ← (W1)
TW1A
(W1) ← (A)
TAW2
(A) ← (W2)
TW2A
(W2) ← (A)
TAW3
(A) ← (W3)
TW3A
(W3) ← (A)
(PCH) ← p
(SK(SP)) ← (PC)
Subroutine operation
(PCH) ← 2
(PCL) ← a6–a0
BML p, a
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
BMLA p
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
RTI
(PC) ← (SK(SP))
RT
(PC) ← (SK(SP))
Return operation
(SP) ← (SP) – 1
RTS
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Timer operation
(SP) ← (SP) – 1
Note: p is 0 to 15 for M34518M2, p is 0 to 31 for M34518M4, p is 0 to 47 for M34518M6 and p is 0 to 63 for M34518M8/E8.
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4518 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Function
TAW4
(A) ← (W4)
TW4A
(W4) ← (A)
TAW5
(A) ← (W5)
TW5A
(W5) ← (A)
TAW6
(A) ← (W6)
TW6A
(W6) ← (A)
TABPS
(B) ← (TPS7–TPS4)
(A) ← (TPS3–TPS0)
TPSAB
GroupMnemonic
ing
Timer operation
Grouping Mnemonic
Function
T4HAB
(R4H7–R4H4) ← (B)
(R4H3–R4H0) ← (A)
TR1AB
(R17–R14) ← (B) (R13–R10) ← (A)
TR3AB
(R37–R34) ← (B) (R33–R30) ← (A)
T4R4L
(T47–T44) ← (R4L7–R4L4)
SNZT1
V12 = 0: (T1F) = 1 ?
After skipping, (T1F) ← 0
V12 = 1: NOP
SNZT2
V13 = 0: (T2F) = 1 ?
After skipping, (T2F) ← 0
V13 = 1: NOP
SNZT3
V20 = 0: (T3F) = 1 ?
After skipping, (T3F) ← 0
V20 = 1: NOP
SNZT4
V21 = 0: (T4F) = 1 ?
After skipping, (T4F) ← 0
V21 = 1: NOP
IAP0
(A) ← (P0)
(RPS7–RPS4) ← (B)
(TPS7–TPS4) ← (B)
(RPS3–RPS0) ← (A)
(TPS3–TPS0) ← (A)
TAB1
(B) ← (T17–T14)
Timer operation
(A) ← (T13–T10)
T1AB
(R17–R14) ← (B)
(T17–T14) ← (B)
(R13–R10) ← (A)
(T13–T10) ← (A)
TAB2
T2AB
OP0A
(P0) ← (A)
(B) ← (T27–T24)
(A) ← (T23–T20)
IAP1
(A) ← (P1)
(R27–R24) ← (B)
OP1A
(P1) ← (A)
IAP2
(A2–A0) ← (P22–P20) (A3) ← 0
OP2A
(P22–P20) ← (A2–A0)
IAP3
(A) ← (P3)
OP3A
(P3) ← (A)
IAP6
(A) ← (P6)
OP6A
(P6) ← (A)
(T27–T24) ← (B)
(T23–T20) ← (A)
TAB3
(B) ← (T37–T34)
(A) ← (T33–T30)
T3AB
(R37–R34) ← (B)
(T37–T34) ← (B)
(R33–R30) ← (A)
(T33–T30) ← (A)
TAB4
(B) ← (T47–T44)
(A) ← (T43–T40)
T4AB
(R4L7–R4L4) ← (B)
(T47–T44) ← (B)
(R4L3–R4L0) ← (A)
(T43–T40) ← (A)
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Input/Output operation
(R23–R20) ← (A)
4518 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Grouping Mnemonic
Function
GroupMnemonic
ing
Function
CLD
(D) ← 1
TABSI
(B) ← (SI7–SI4) (A) ← (SI3–SI0)
RD
(D(Y)) ← 0
TSIAB
(SI7–SI4) ← (B) (SI3–SI0) ← (A)
SST
(SIOF) ← 0
SD
(D(Y)) ← 1
(Y) = 0 to 7
SZD
(D(Y)) = 0 ?
Clock operation
Serial I/O starting
SNZSI
V23=0: (SIOF)=1?
After skipping, (SIOF) ← 0
V23=1: NOP
TAPU0
(A) ← (PU0)
TAJ1
(A) ← (J1)
TPU0A
(PU0) ← (A)
TJ1A
(J1) ← (A)
TAPU1
(A) ← (PU1)
TABAD
In A/D conversion mode ,
(B) ← (AD9–AD6)
TPU1A
(PU1) ← (A)
(A) ← (AD5–AD2)
TAK0
(A) ← (K0)
In comparator mode,
(B) ← (AD7–AD4)
(A) ← (AD3–AD0)
TK0A
(K0) ← (A)
TAK1
(A) ← (K1)
TK1A
(K1) ← (A)
TAK2
(A) ← (K2)
TK2A
(K2) ← (A)
TFR0A
(FR0) ← (A)
TFR1A
(FR1) ← (A)
TFR2A
(FR2) ← (A)
TAQ1
(A) ← (Q1)
CMCK
Ceramic resonator selected
TQ1A
(Q1) ← (A)
CRCK
RC oscillator selected
TAQ2
(A) ← (Q2)
CYCK
Quartz-crystal oscillator selected
TQ2A
(Q2) ← (A)
TRGA
(RG0) ← (A0)
TAQ3
(A) ← (Q3)
TAMR
(A) ← (MR)
TQ3A
(Q3) ← (A)
TMRA
(MR) ← (A)
TALA
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(A3, A2) ← (AD1, AD0)
(A1, A0) ← 0
A/D operation
Input/Output operation
(Y) = 0 to 7
Serial I/O operation
(Y) = 0 to 7
TADAB
(AD7–AD4) ← (B)
(AD3–AD0) ← (A)
ADST
(ADF) ← 0
A/D conversion starting
SNZAD
V21 = 0: (ADF) = 1 ?
After skipping, (ADF) ← 0
V21=1: NOP
4518 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Other operation
GroupMnemonic
ing
Function
NOP
(PC) ← (PC) + 1
POF
Transition to RAM back-up mode
EPOF
POF instruction valid
SNZP
(P) = 1 ?
DWDT
Stop of watchdog timer function enabled
WRST
(WDF1) = 1 ?
After skipping, (WDF1) ← 0
SRST
System reset occurrence
Rev.3.01 2005.06.15
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page 90 of 157
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET)
A n (Add n and accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
1
1
0
n
n
n
n
2
0
6
n
16
(A) ← (A) + n
n = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
Overflow = 0
Grouping:
Arithmetic operation
Description: Adds the value n in the immediate field to
register A, and stores a result in register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no
overflow as the result of operation.
Executes the next instruction when there is
overflow as the result of operation.
ADST (A/D conversion STart)
Instruction
code
Operation:
D0
D9
1
0
1
0
0
1
1
1
1
1
2
2
9
F
16
(ADF) ← 0
Q13 = 0: A/D conversion starting
Q13 = 1: Comparator operation starting
(Q13 : bit 3 of A/D control register Q1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: Clears (0) to A/D conversion completion
flag ADF, and the A/D conversion at the A/D
conversion mode (Q13 = 0) or the comparator operation at the comparator mode (Q13
= 1) is started.
AM (Add accumulator and Memory)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
1
0
1
0
2
0
0
A
16
(A) ← (A) + (M(DP))
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Arithmetic operation
Description: Adds the contents of M(DP) to register A.
Stores the result in register A. The contents
of carry flag CY remains unchanged.
AMC (Add accumulator, Memory and Carry)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
1
(A) ← (A) + (M(DP)) + (CY)
(CY) ← Carry
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0
1
1
2
0
0
B
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
0/1
–
Grouping:
Arithmetic operation
Description: Adds the contents of M(DP) and carry flag
CY to register A. Stores the result in register A and carry flag CY.
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
AND (logical AND between accumulator and memory)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
1
0
0
0
2
0
1
8
16
(A) ← (A) AND (M(DP))
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Arithmetic operation
Description: Takes the AND operation between the contents of register A and the contents of
M(DP), and stores the result in register A.
B a (Branch to address a)
Instruction
code
Operation:
D9
0
D0
1
1
a6 a5 a4 a3 a2 a1 a0
2
1
8
+a
a
16
(PCL) ← a6 to a0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Branch operation
Description: Branch within a page : Branches to address
a in the identical page.
Note:
Specify the branch address within the page
including this instruction.
BL p, a (Branch Long to address a in page p)
Instruction
code
D9
0
1
Operation:
D0
0
0
1
1
1
p4 p3 p2 p1 p0
2
p5 a6 a5 a4 a3 a2 a1 a0 2
0
E
+p
p
2
p
+a
a 16
16
(PCH) ← p
(PCL) ← a6 to a0
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
Grouping:
Branch operation
Description: Branch out of a page : Branches to address
a in page p.
Note:
p is 0 to 15 for M34518M2, p is 0 to 31 for
M34518M4, p is 0 to 47 for M34518M6 and
p is 0 to 63 for M34518M8E8.
BLA p (Branch Long to address (D) + (A) in page p)
Instruction
code
Operation:
D9
D0
0
0
0
0
0
1
0
1
0
p5 p4 0
0
p3 p2 p1 p0 2
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
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0
0
0
2
0
1
0
2
p
p 16
16
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
Grouping:
Branch operation
Description: Branch out of a page : Branches to address
(DR2 DR 1 DR 0 A3 A2 A 1 A0 )2 specified by
registers D and A in page p.
Note:
p is 0 to 15 for M34518M2, p is 0 to 31 for
M34518M4, p is 0 to 47 for M34518M6 and
p is 0 to 63 for M34518M8E8.
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
BM a (Branch and Mark to address a in page 2)
Instruction
code
Operation:
D9
0
D0
1
0
a6 a5 a4 a3 a2 a1 a0
2
1
a
a
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
(PCL) ← a6–a0
Grouping:
Subroutine call operation
Description: Call the subroutine in page 2 : Calls the
subroutine at address a in page 2.
Note:
Subroutine extending from page 2 to another page can also be called with the BM
instruction when it starts on page 2.
Be careful not to over the stack because the
maximum level of subroutine nesting is 8.
BML p, a (Branch and Mark Long to address a in page p)
Instruction
code
0
1
Operation:
D0
D9
0
0
1
1
0
p4 p3 p2 p1 p0
2
p5 a6 a5 a4 a3 a2 a1 a0 2
0
C
+p
p
2
p
+a
a 16
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
16
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← a6–a0
Grouping:
Subroutine call operation
Description: Call the subroutine : Calls the subroutine at
address a in page p.
Note:
p is 0 to 15 for M34518M2, p is 0 to 31 for
M34518M4, p is 0 to 47 for M34518M6 and
p is 0 to 63 for M34518M8E8.
Be careful not to over the stack because the
maximum level of subroutine nesting is 8.
BMLA p (Branch and Mark Long to address (D) + (A) in page p)
Instruction
code
Operation:
D9
D0
0
0
0
0
1
1
0
0
0
0
1
0
p5 p4 0
0
p3 p2 p1 p0 2
2
0
3
0
2
p
p 16
16
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
Grouping:
Subroutine call operation
Description: Call the subroutine : Calls the subroutine at
address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p.
Note:
p is 0 to 15 for M34518M2, p is 0 to 31 for
M34518M4, p is 0 to 47 for M34518M6 and
p is 0 to 63 for M34518M8E8.
Be careful not to over the stack because the
maximum level of subroutine nesting is 8.
CLD (CLear port D)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
0
(D) ← 1
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0
0
1
2
0
1
1
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Sets (1) to port D.
page 93 of 157
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
CMA (CoMplement of Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
1
1
0
0
2
0
1
C 16
(A) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Arithmetic operation
Description: Stores the one’s complement for register
A’s contents in register A.
CMCK (Clock select: ceraMic oscillation ClocK)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
1
1
0
1
0
2
2
9
A
16
Ceramic oscillation circuit selected
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Clock control operation
Description: Selects the ceramic oscillation circuit for
main clock f(XIN).
CRCK (Clock select: Rc oscillation ClocK)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
1
1
0
1
1
2
2
9
B 16
RC oscillation circuit selected
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Clock control operation
Description: Selects the RC oscillation circuit for main
clock f(XIN).
CYCK (Clock select: crYstal oscillation ClocK)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
1
1
1
0
1
Quartz-crystal oscillation circuit selected
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REJ03B0008-0301
page 94 of 157
2
2
9
D
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Clock control operation
Description: Selects the quartz-crystal oscillation circuit
for main clock f(XIN).
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
DEY (DEcrement register Y)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
0
1
1
1
2
0
1
7 16
(Y) ← (Y) – 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 15
Grouping:
RAM addresses
Description: Subtracts 1 from the contents of register Y.
As a result of subtraction, when the contents of register Y is 15, the next instruction
is skipped. When the contents of register Y
is not 15, the next instruction is executed.
DI (Disable Interrupt)
Instruction
code
Operation:
D0
D9
0
0
0
0
0
0
0
1
0
0
2
0
0
4
16
(INTE) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt control operation
Description: Clears (0) to interrupt enable flag INTE, and
disables the interrupt.
Note:
Interrupt is disabled by executing the DI instruction after executing 1 machine cycle.
DWDT (Disable WatchDog Timer)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
1
1
1
0
0
2
2
9
C
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Stops the watchdog timer function by the
WRST instruction after executing the
DWDT instruction.
Stop of watchdog timer function enabled
EI (Enable Interrupt)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
(INTE) ← 1
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REJ03B0008-0301
1
0
1
2
0
0
5
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt control operation
Description: Sets (1) to interrupt enable flag INTE, and
enables the interrupt.
Note:
Interrupt is enabled by executing the EI instruction after executing 1 machine cycle.
page 95 of 157
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
EPOF (Enable POF instruction)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
1
0
1
1
2
0
5
B 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Makes the immediate after POF instruction
valid by executing the EPOF instruction.
POF instruction valid
IAP0 (Input Accumulator from port P0)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
0
0
0
0
0 2
2
6
0 16
(A) ← (P0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the input of port P0 to register A.
IAP1 (Input Accumulator from port P1)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
0
0
0
0
1
2
2
6
1 16
(A) ← (P1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the input of port P1 to register A.
IAP2 (Input Accumulator from port P2)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
0
0
(A2–A0) ← (P22–P20)
(A3) ← 0
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page 96 of 157
0
1
0
2
2
6
2 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the input of port P2 to register A.
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
IAP3 (Input Accumulator from port P3)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
0
0
0
1
1
2
2
6
3
16
(A) ← (P3)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the input of port P3 to register A.
IAP6 (Input Accumulator from port P6)
Instruction
code
Operation:
D0
D9
1
0
0
1
1
0
0
1
1
0
2
2
6
6
16
(A) ← (P6)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the input of port P6 to register A.
INY (INcrement register Y)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
0
0
1
1
2
0
1
3
16
(Y) ← (Y) + 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 0
Grouping:
RAM addresses
Description: Adds 1 to the contents of register Y. As a result of addition, when the contents of
register Y is 0, the next instruction is
skipped. When the contents of register Y is
not 0, the next instruction is executed.
LA n (Load n in Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
1
1
1
n
(A) ← n
n = 0 to 15
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REJ03B0008-0301
n
n
n
2
0
7
n
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
Continuous
description
Grouping:
Arithmetic operation
Description: Loads the value n in the immediate field to
register A.
When the LA instructions are continuously
coded and executed, only the first LA instruction is executed and other LA
instructions coded continuously are
skipped.
page 97 of 157
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
LXY x, y (Load register X and Y with x and y)
Instruction
code
Operation:
D9
1
D0
1
x3 x2 x1 x0 y3 y2 y1 y0
2
3
x
y 16
(X) ← x x = 0 to 15
(Y) ← y y = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
Continuous
description
Grouping:
RAM addresses
Description: Loads the value x in the immediate field to
register X, and the value y in the immediate
field to register Y. When the LXY instructions are continuously coded and executed,
only the first LXY instruction is executed
and other LXY instructions coded continuously are skipped.
LZ z (Load register Z with z)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
0
1
0
z1 z0
2
0
4
8
+z 16
(Z) ← z z = 0 to 3
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
RAM addresses
Description: Loads the value z in the immediate field to
register Z.
NOP (No OPeration)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
0
0
0
2
0
0
0
16
(PC) ← (PC) + 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: No operation; Adds 1 to program counter
value, and others remain unchanged.
OP0A (Output port P0 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
0
(P0) ← (A)
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0
0
0
2
2
2
0
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Outputs the contents of register A to port
P0.
page 98 of 157
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
OP1A (Output port P1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
0
0
0
1
2
2
2
1
16
(P1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Outputs the contents of register A to port
P1.
OP2A (Output port P2 from Accumulator)
Instruction
code
Operation:
D0
D9
1
0
0
0
1
0
0
0
1
0
2
2
2
2
16
(P2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Outputs the contents of register A to port
P2.
OP3A (Output port P3 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
0
0
1
1
2
2
2
3
16
(P3) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Outputs the contents of register A to port
P3.
OP6A (Output port P6 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
0
(P6) ← (A)
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1
1
0
2
2
2
6
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Outputs the contents of register A to port
P6.
page 99 of 157
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
OR (logical OR between accumulator and memory)
Instruction
code
Operation:
D9
D0
0
0
0
0
0
1
1
0
0
1 2
0
1
9 16
(A) ← (A) OR (M(DP))
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Arithmetic operation
Description: Takes the OR operation between the contents of register A and the contents of
M(DP), and stores the result in register A.
POF (Power OFf)
Instruction
code
Operation:
D9
D0
0
0
0
0
0
0
0
0
1
0
2
0
0
2 16
Transition to RAM back-up mode
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Puts the system in RAM back-up state by
executing the POF instruction after executing the EPOF instruction.
Note:
If the EPOF instruction is not executed before
executing this instruction, this instruction is
equivalent to the NOP instruction.
RAR (Rotate Accumulator Right)
Instruction
code
D9
D0
0
0
0
0
0
1
1
1
0
1
2
0
1
D
16
→ CY → A3A2A1A0
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
0/1
–
Grouping:
Arithmetic operation
Description: Rotates 1 bit of the contents of register A including the contents of carry flag CY to the
right.
RB j (Reset Bit)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
0
1
(Mj(DP)) ← 0
j = 0 to 3
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1
j
j
2
0
4
C
+j 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Bit operation
Description: Clears (0) the contents of bit j (bit specified
by the value j in the immediate field) of
M(DP).
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
RC (Reset Carry flag)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
1
1
0
2
0
0
6
16
(CY) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
0
–
Grouping:
Arithmetic operation
Description: Clears (0) to carry flag CY.
RD (Reset port D specified by register Y)
Instruction
code
Operation:
D0
D9
0
0
0
0
0
1
0
1
0
0
2
0
1
4
16
(D(Y)) ← 0
However,
(Y) = 0 to 7
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Clears (0) to a bit of port D specified by register Y.
RT (ReTurn from subroutine)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
0
0
1
0
0
2
0
4
4
16
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
2
–
–
Grouping:
Return operation
Description: Returns from subroutine to the routine
called the subroutine.
RTI (ReTurn from Interrupt)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
0
0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
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1
1
0
2
0
4
6 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Return operation
Description: Returns from interrupt service routine to
main routine.
Returns each value of data pointer (X, Y, Z),
carry flag, skip status, NOP mode status by
the continuous description of the LA/LXY instruction, register A and register B to the
states just before interrupt.
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
RTS (ReTurn from subroutine and Skip)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
0
0
1
0
1
2
0
4
5 16
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
2
–
Skip at uncondition
Grouping:
Return operation
Description: Returns from subroutine to the routine
called the subroutine, and skips the next instruction at uncondition.
SB j (Set Bit)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
1
1
j
j
2
0
5
C
+j 16
(Mj(DP)) ← 1
j = 0 to 3
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Bit operation
Description: Sets (1) the contents of bit j (bit specified by
the value j in the immediate field) of M(DP).
SC (Set Carry flag)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
1
1
1
2
0
0
7
16
(CY) ← 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
1
–
Grouping:
Arithmetic operation
Description: Sets (1) to carry flag CY.
SD (Set port D specified by register Y)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
0
(D(Y)) ← 1
(Y) = 0 to 7
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1
0
1
2
0
1
5
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Sets (1) to a bit of port D specified by register Y.
page 102 of 157
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SEA n (Skip Equal, Accumulator with immediate data n)
Instruction
code
D9
0
0
Operation:
D0
0
0
0
0
0
1
1
1
0
1
0
n
1
n
0
n
1
2
n 2
0
0
2
7
(A) = n ?
n = 0 to 15
5
16
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
(A) = n
n 16
Grouping:
Comparison operation
Description: Skips the next instruction when the contents of register A is equal to the value n in
the immediate field.
Executes the next instruction when the contents of register A is not equal to the value n
in the immediate field.
SEAM (Skip Equal, Accumulator with Memory)
Instruction
code
Operation:
D0
D9
0
0
0
0
1
0
0
1
1
0
2
0
2
6
16
(A) = (M(DP)) ?
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(A) = (M(DP))
Grouping:
Comparison operation
Description: Skips the next instruction when the contents of register A is equal to the contents of
M(DP).
Executes the next instruction when the contents of register A is not equal to the
contents of M(DP).
SNZ0 (Skip if Non Zero condition of external 0 interrupt request flag)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
1
1
0
0
0
2
0
3
8
16
V10 = 0: (EXF0) = 1 ?
After skipping, (EXF0) ← 0
V10 = 1: SNZ0 = NOP
(V10 : bit 0 of the interrupt control register V1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V10 = 0: (EXF0) = 1
Grouping:
Interrupt operation
Description: When V10 = 0 : Skips the next instruction
when external 0 interrupt request flag EXF0
is “1.” After skipping, clears (0) to the EXF0
flag. When the EXF0 flag is “0,” executes
the next instruction.
When V10 = 1 : This instruction is equivalent to the NOP instruction.
SNZ1 (Skip if Non Zero condition of external 1 interrupt request flag)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
1
1
0
0
1
2
V11 = 0: (EXF1) = 1 ?
After skipping, (EXF1) ← 0
V11 = 1: SNZ1 = NOP
(V11 : bit 1 of the interrupt control register V1)
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0
3
9
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V11 = 0: (EXF1) = 1
Grouping:
Interrupt operation
Description: When V11 = 0 : Skips the next instruction
when external 1 interrupt request flag EXF1
is “1.” After skipping, clears (0) to the EXF1
flag. When the EXF1 flag is “0,” executes
the next instruction.
When V11 = 1 : This instruction is equivalent to the NOP instruction.
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SNZAD (Skip if Non Zero condition of A/D conversion completion flag)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
0
0
1
1
1
2
2
8
7
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V22 = 0: (ADF) = 1
16
V22 = 0: (ADF) = 1 ?
After skipping, (ADF) ← 0
V22 = 1: SNZAD = NOP
(V22 : bit 2 of the interrupt control register V2)
Grouping:
A/D conversion operation
Description: When V22 = 0 : Skips the next instruction
when A/D conversion completion flag ADF
is “1.” After skipping, clears (0) to the ADF
flag. When the ADF flag is “0,” executes the
next instruction.
When V2 2 = 1 : This instruction is equivalent to the NOP instruction.
SNZI0 (Skip if Non Zero condition of external 0 Interrupt input pin)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
1
1
0
1
0
2
0
3
A 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
I12 = 0 : (INT0) = “L”
I12 = 1 : (INT0) = “H”
Grouping:
Interrupt operation
Description: When I1 2 = 0 : Skips the next instruction
when the level of INT0 pin is “L.” Executes
the next instruction when the level of INT0
pin is “H.”
When I1 2 = 1 : Skips the next instruction
when the level of INT0 pin is “H.” Executes
the next instruction when the level of INT0
pin is “L.”
I12 = 0 : (INT0) = “L” ?
I12 = 1 : (INT0) = “H” ?
(I12 : bit 2 of the interrupt control register I1)
SNZI1 (Skip if Non Zero condition of external 1 Interrupt input pin)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
1
1
0
1
1
2
0
3
B 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
I22 = 0 : (INT1) = “L”
I22 = 1 : (INT1) = “H”
Grouping:
Interrupt operation
Description: When I2 2 = 0 : Skips the next instruction
when the level of INT1 pin is “L.” Executes
the next instruction when the level of INT1
pin is “H.”
When I2 2 = 1 : Skips the next instruction
when the level of INT1 pin is “H.” Executes
the next instruction when the level of INT1
pin is “L.”
I22 = 0 : (INT1) = “L” ?
I22 = 1 : (INT1) = “H” ?
(I22 : bit 2 of the interrupt control register I2)
SNZP (Skip if Non Zero condition of Power down flag)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
(P) = 1 ?
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0
1
1
2
0
0
3
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(P) = 1
Grouping:
Other operation
Description: Skips the next instruction when the P flag is
“1”.
After skipping, the P flag remains unchanged.
Executes the next instruction when the P
flag is “0.”
page 104 of 157
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SNZSI (Skip if Non Zero condition of Serial I/o interrupt request flag)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
0
1
0
0
0
2
2
8
8
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V23 = 0: (SIOF) = 1
16
V23 = 0: (SIOF) = 1 ?
After skipping, (SIOF) ← 0
V23 = 1: SNZSI = NOP
(V23 = bit 3 of interrupt control register V2)
Grouping:
Serial I/O operation
Description: When V23 = 0 : Skips the next instruction
when serial I/O interrupt request flag SIOF
is “1.” After skipping, clears (0) to the SIOF
flag. When the SIOF flag is “0,” executes
the next instruction.
When V2 3 = 1 : This instruction is equivalent to the NOP instruction.
SNZT1 (Skip if Non Zero condition of Timer 1 interrupt request flag)
Instruction
code
Operation:
D0
D9
1
0
1
0
0
0
0
0
0
0
2
2
8
0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V12 = 0: (T1F) = 1
16
V12 = 0: (T1F) = 1 ?
After skipping, (T1F) ← 0
V12 = 1: SNZT1 = NOP
(V12 = bit 2 of interrupt control register V1)
Grouping:
Timer operation
Description: When V12 = 0 : Skips the next instruction
when timer 1 interrupt request flag T1F is
“1.” After skipping, clears (0) to the T1F
flag. When the T1F flag is “0,” executes the
next instruction.
When V12 = 1 : This instruction is equivalent to the NOP instruction.
SNZT2 (Skip if Non Zero condition of Timer 2 interrupt request flag)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
0
0
0
0
1
2
2
8
1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V13 = 0: (T2F) = 1
16
V13 = 0: (T2F) = 1 ?
After skipping, (T2F) ← 0
V13 = 1: SNZT2 = NOP
(V13 = bit 3 of interrupt control register V1)
Grouping:
Timer operation
Description: When V13 = 0 : Skips the next instruction
when timer 2 interrupt request flag T2F is
“1.” After skipping, clears (0) to the T2F
flag. When the T2F flag is “0,” executes the
next instruction.
When V13 = 1 : This instruction is equivalent to the NOP instruction.
SNZT3 (Skip if Non Zero condition of Timer 3 interrupt request flag)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
0
0
0
1
0
V20 = 0: (T3F) = 1 ?
After skipping, (T3F) ← 0
V20 = 1: SNZT3 = NOP
(V20 = bit 0 of interrupt control register V2)
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2
2
8
2
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V20 = 0: (T3F) = 1
Grouping:
Timer operation
Description: When V20 = 0 : Skips the next instruction
when timer 3 interrupt request flag T3F is
“1.” After skipping, clears (0) to the T3F
flag. When the T3F flag is “0,” executes the
next instruction.
When V20 = 1 : This instruction is equivalent to the NOP instruction.
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SNZT4 (Skip if Non Zero condition of Timer 4 inerrupt request flag)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
0
0
0
1
1
2
2
8
3 16
V21 = 0: (T4F) = 1 ?
After skipping, (T4F) ← 0
V21 = 1: SNZT4 = NOP
(V21 = bit 1 of interrupt control register V2)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V21 = 0: (T4F) = 1
Grouping:
Timer operation
Description: When V21 = 0 : Skips the next instruction
when timer 4 interrupt request flag T4F is
“1.” After skipping, clears (0) to the T4F
flag. When the T4F flag is “0,” executes the
next instruction.
When V21 = 1 : This instruction is equivalent to the NOP instruction.
SRST (System ReSeT)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
0
0
1
2
0
0
1
16
System reset occurrence
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: System reset occurs.
SST (Serial i/o transmission/reception STart)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
1
1
1
1
0
2
2
9
E
16
(SIOF) ← 0
Serial I/O transmission/reception start
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Serial I/O operation
Description: Clears (0) to SIOF flag and starts serial I/O.
SZB j (Skip if Zero, Bit)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
0
0
(Mj(DP)) = 0 ?
j = 0 to 3
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0
j
j
2
0
2
j
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Mj(DP)) = 0
j = 0 to 3
Grouping:
Bit operation
Description: Skips the next instruction when the contents of bit j (bit specified by the value j in
the immediate field) of M(DP) is “0.”
Executes the next instruction when the contents of bit j of M(DP) is “1.”
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SZC (Skip if Zero, Carry flag)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
0
1
1
1
1
2
0
2
F 16
(CY) = 0 ?
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(CY) = 0
Grouping:
Arithmetic operation
Description: Skips the next instruction when the contents of carry flag CY is “0.”
After skipping, the CY flag remains unchanged.
Executes the next instruction when the contents of the CY flag is “1.“
SZD (Skip if Zero, port D specified by register Y)
Instruction
code
Operation:
D0
D9
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
1
0
1
1 2
2
0
2
4 16
0
2
B 16
Number of
words
Number of
cycles
Flag CY
2
2
–
Skip condition
(D(Y)) = 0
(Y) = 0 to 7
Grouping:
Input/Output operation
Description: Skips the next instruction when a bit of port
D specified by register Y is “0.” Executes the
next instruction when the bit is “1.”
(D(Y)) = 0 ?
(Y) = 0 to 7
T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
0
0
0
0
2
2
3
0
16
(T17–T14) ← (B)
(R17–R14) ← (B)
(T13–T10) ← (A)
(R13–R10) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 1 and timer 1 reload register R1. Transfers the contents of
register A to the low-order 4 bits of timer 1
and timer 1 reload register R1.
T2AB (Transfer data to timer 2 and register R2 from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
0
(T27–T24) ← (B)
(R27–R24) ← (B)
(T23–T20) ← (A)
(R23–R20) ← (A)
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0
0
1
2
2
3
1
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 2 and timer 2 reload register R2. Transfers the contents of
register A to the low-order 4 bits of timer 2
and timer 2 reload register R2.
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
T3AB (Transfer data to timer 3 and register R3 from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
0
0
1
0 2
2
3
2 16
(T37–T34) ← (B)
(R37–R34) ← (B)
(T33–T30) ← (A)
(R33–R30) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 3 and timer 3 reload register R3. Transfers the contents of
register A to the low-order 4 bits of timer 3
and timer 3 reload register R3.
T4AB (Transfer data to timer 4 and register R4L from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
0
0
1
1 2
2
3
3 16
(T47–T44) ← (B)
(R4L7–R4L4) ← (B)
(T43–T40) ← (A)
(R4L3–R4L0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 4 and timer 4 reload register R4L. Transfers the contents of
register A to the low-order 4 bits of timer 4
and timer 4 reload register R4L.
T4HAB (Transfer data to register R4H from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
0
1
1
1
2
2
3
7 16
(R4H7–R4H4) ← (B)
(R4H3–R4H0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 4 and timer 4 reload register R4H. Transfers the contents of
register A to the low-order 4 bits of timer 4
and timer 4 reload register R4H.
T4R4L (Transfer data to timer 4 from register R4L)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
1
0
(T47–T44) ← (R4L7–R4L4)
(T43–T40) ← (R4L3–R4L0)
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REJ03B0008-0301
page 108 of 157
1
1
1
2
2
9
7
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of reload register
R4L to timer 4.
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAB (Transfer data to Accumulator from register B)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
1
1
1
0
2
0
1
E
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
(A) ← (B)
Grouping:
Register to register transfer
Description: Transfers the contents of register B to register A.
TAB1 (Transfer data to Accumulator and register B from timer 1)
Instruction
code
Operation:
D0
D9
1
0
0
1
1
1
0
0
0
0
2
2
7
0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
(B) ← (T17–T14)
(A) ← (T13–T10)
Grouping:
Timer operation
Description: Transfers the high-order 4 bits (T17–T14) of
timer 1 to register B.
Transfers the low-order 4 bits (T13–T10) of
timer 1 to register A.
TAB2 (Transfer data to Accumulator and register B from timer 2)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
1
0
0
0
1
2
2
7
1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
(B) ← (T27–T24)
(A) ← (T23–T20)
Grouping:
Timer operation
Description: Transfers the high-order 4 bits (T27–T24) of
timer 2 to register B.
Transfers the low-order 4 bits (T23–T20) of
timer 2 to register A.
TAB3 (Transfer data to Accumulator and register B from timer 3)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
1
0
(B) ← (T37–T34)
(A) ← (T33–T30)
Rev.3.01 2005.06.15
REJ03B0008-0301
page 109 of 157
0
1
0
2
2
7
2
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the high-order 4 bits (T37–T34) of
timer 3 to register B.
Transfers the low-order 4 bits (T33–T30) of
timer 3 to register A.
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAB4 (Transfer data to Accumulator and register B from timer 4)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
1
0
0
1
1
2
2
7
3
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
(B) ← (T47–T44)
(A) ← (T43–T40)
Grouping:
Timer operation
Description: Transfers the high-order 4 bits (T47–T44) of
timer 4 to register B.
Transfers the low-order 4 bits (T43–T40) of
timer 4 to register A.
TABAD (Transfer data to Accumulator and register B from register AD)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
1
1
0
0
1
2
2
7
9
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
Grouping:
A/D conversion operation
Description: In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD 9 –AD 6 ) of
register AD to register B, and the middle-order 4 bits (AD 5 –AD 2 ) of register AD to
register A. In the comparator mode (Q13 = 1),
transfers the middle-order 4 bits (AD7–AD4)
of register AD to register B, and the low-order
4 bits (AD3–AD0) of register AD to register A.
In A/D conversion mode (Q13 = 0),
(B) ← (AD9–AD6)
(A) ← (AD5–AD2)
In comparator mode (Q13 = 1),
(B) ← (AD7–AD4)
(A) ← (AD3–AD0)
(Q13 : bit 3 of A/D control register Q1)
TABE (Transfer data to Accumulator and register B from register E)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
0
1
0
1
0
2
0
2
A
16
(B) ← (E7–E4)
(A) ← (E3–E0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the high-order 4 bits (E 7 –E4) of
register E to register B, and low-order 4 bits
of register E to register A.
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
Instruction
code
Operation:
D9
0
D0
0
1
0
p5 p4 p3 p2 p1 p0
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
(DR2) ← 0
(DR1, DR0) ← (ROM(PC))9, 8
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Rev.3.01 2005.06.15
REJ03B0008-0301
page 110 of 157
2
0
8
+p
p
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
3
–
–
Grouping:
Arithmetic operation
Description: Transfers bits 9 and 8 to register D, bits 7 to 4
to register B and bits 3 to 0 to register A.
These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified
by registers A and D in page p.
Note: p is 0 to 15 for M34518M2, and p is 0 to 31 for
M34518M6, p is 0 to 47 for M34518M6, and p is 0 to
63 for M34518M8E8.
When this instruction is executed, be careful not to over
the stack because 1 stage of stack register is used.
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TABPS (Transfer data to Accumulator and register B from PreScaler)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
1
0
1
0
1
2
2
7
5 16
(B) ← (TPS7–TPS4)
(A) ← (TPS3–TPS0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the high-order 4 bits (TPS 7 –
TPS 4 ) of prescaler to register B, and
transfers the low-order 4 bits (TPS3–TPS0)
of prescaler to register A.
TABSI (Transfer data to Accumulator and register B from register SI)
Instruction
code
Operation:
D0
D9
1
0
0
1
1
1
1
0
0
0
2
2
7
8 16
(B) ← (SI7–SI4)
(A) ← (SI3–SI0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Serial I/O operation
Description: Transfers the high-order 4 bits (SI7–SI4) of
serial I/O register SI to register B, and
transfers the low-order 4 bits (SI 3–SI0) of
serial I/O register SI to register A.
TAD (Transfer data to Accumulator from register D)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
0
0
0
1
2
0
5
1
16
(A2–A0) ← (DR2–DR0)
(A3) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register D to the
low-order 3 bits (A2–A0) of register A.
Note:
When this instruction is executed, “0” is
stored to the bit 3 (A3) of register A.
TADAB (Transfer data to register AD from Accumulator from register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
1
(AD7–AD4) ← (B)
(AD3–AD0) ← (A)
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REJ03B0008-0301
page 111 of 157
0
0
1
2
2
3
9
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: In the A/D conversion mode (Q13 = 0), this instruction is equivalent to the NOP instruction.
In the comparator mode (Q13 = 1), transfers the contents of register B to the
high-order 4 bits (AD7–AD4) of comparator
register, and the contents of register A to
the low-order 4 bits (AD3–AD0) of comparator register.
(Q13 = bit 3 of A/D control register Q1)
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAI1 (Transfer data to Accumulator from register I1)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
0
0
1
1
2
2
5
3
16
(A) ← (I1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of interrupt control
register I1 to register A.
TAI2 (Transfer data to Accumulator from register I2)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
0
1
0
0
2
2
5
4
16
(A) ← (I2)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of interrupt control
register I2 to register A.
TAJ1 (Transfer data to Accumulator from register J1)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
0
0
1
0
2
2
4
2
16
(A) ← (J1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Serial I/O operation
Description: Transfers the contents of serial I/O control
register J1 to register A.
TAK0 (Transfer data to Accumulator from register K0)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
0
(A) ← (K0)
Rev.3.01 2005.06.15
REJ03B0008-0301
1
1
0
2
2
5
6
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of key-on wakeup
control register K0 to register A.
page 112 of 157
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAK1 (Transfer data to Accumulator from register K1)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
1
0
0
1
2
2
5
9
16
(A) ← (K1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of key-on wakeup
control register K1 to register A.
TAK2 (Transfer data to Accumulator from register K2)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
1
0
1
0
2
2
5
A
16
(A) ← (K2)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of key-on wakeup
control register K2 to register A.
TALA (Transfer data to Accumulator from register LA)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
1
0
0
1
2
2
4
9
16
(A3, A2) ← (AD1, AD0)
(A1, A0) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: Transfers the low-order 2 bits (AD1, AD0) of
register AD to the high-order 2 bits (A3, A2)
of register A.
Note:
After this instruction is executed, “0” is
stored to the low-order 2 bits (A 1 , A 0 ) of
register A.
TAM j (Transfer data to Accumulator from Memory)
Instruction
code
Operation:
D9
1
D0
0
1
1
0
0
j
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
Rev.3.01 2005.06.15
REJ03B0008-0301
page 113 of 157
j
j
j
2
2
C
j
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
RAM to register transfer
Description: After transferring the contents of M(DP) to
register A, an exclusive OR operation is
performed between register X and the value
j in the immediate field, and stores the result in register X.
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAMR (Transfer data to Accumulator from register MR)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
0
0
1
0
2
2
5
2
16
(A) ← (MR)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Clock operation
Description: Transfers the contents of clock control register MR to register A.
TAPU0 (Transfer data to Accumulator from register PU0)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
0
1
1
1
2
2
5
7 16
(A) ← (PU0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of pull-up control
register PU0 to register A.
TAPU1 (Transfer data to Accumulator from register PU1)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
1
1
1
0
2
2
5
E 16
(A) ← (PU1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of pull-up control
register PU1 to register A.
TAQ1 (Transfer data to Accumulator from register Q1)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
0
(A) ← (Q1)
Rev.3.01 2005.06.15
REJ03B0008-0301
1
0
0
2
2
4
4 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: Transfers the contents of A/D control register Q1 to register A.
page 114 of 157
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAQ2 (Transfer data to Accumulator from register Q2)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
0
1
0
1
2
2
4
5
16
(A) ← (Q2)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: Transfers the contents of A/D control register Q2 to register A.
TAQ3 (Transfer data to Accumulator from register Q3)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
0
1
1
0
2
2
4
6 16
(A) ← (Q3)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: Transfers the contents of A/D control register Q3 to register A.
TASP (Transfer data to Accumulator from Stack Pointer)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
0
0
0
0
2
0
5
0
16
(A2–A0) ← (SP2–SP0)
(A3) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of stack pointer (SP)
to the low-order 3 bits (A2–A0) of register A.
Note:
After this instruction is executed, “0” is
stored to the bit 3 (A3) of register A.
TAV1 (Transfer data to Accumulator from register V1)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
0
(A) ← (V1)
Rev.3.01 2005.06.15
REJ03B0008-0301
1
0
0
2
0
5
4
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of interrupt control
register V1 to register A.
page 115 of 157
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAV2 (Transfer data to Accumulator from register V2)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
0
1
0
1
2
0
5
5
16
(A) ← (V2)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of interrupt control
register V2 to register A.
TAW1 (Transfer data to Accumulator from register W1)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
1
0
1
1
2
2
4
B
16
(A) ← (W1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer control register W1 to register A.
TAW2 (Transfer data to Accumulator from register W2)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
1
1
0
0
2
2
4
C
16
(A) ← (W2)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer control register W2 to register A.
TAW3 (Transfer data to Accumulator from register W3)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
1
(A) ← (W3)
Rev.3.01 2005.06.15
REJ03B0008-0301
1
0
1
2
2
4
D
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer control register W3 to register A.
page 116 of 157
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAW4 (Transfer data to Accumulator from register W4)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
1
1
1
0
2
2
4
E
16
(A) ← (W4)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer control register W4 to register A.
TAW5 (Transfer data to Accumulator from register W5)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
1
1
1
1
2
2
4
F
16
(A) ← (W5)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer control register W5 to register A.
TAW6 (Transfer data to Accumulator from register W6)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
0
0
0
0
2
2
5
0
16
(A) ← (W6)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer control register W6 to register A.
TAX (Transfer data to Accumulator from register X)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
0
(A) ← (X)
Rev.3.01 2005.06.15
REJ03B0008-0301
0
1
0
2
0
5
2
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register X to register A.
page 117 of 157
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAY (Transfer data to Accumulator from register Y)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
1
1
1
1
2
0
1
F
16
(A) ← (Y)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register Y to register A.
TAZ (Transfer data to Accumulator from register Z)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
0
0
1
1 2
0
5
3 16
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register Z to the
low-order 2 bits (A1, A0) of register A.
Note:
After this instruction is executed, “0” is
stored to the high-order 2 bits (A3 , A 2) of
register A.
TBA (Transfer data to register B from Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
1
1
1
0
2
0
0
E
16
(B) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register A to register B.
TDA (Transfer data to register D from Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
0
1
(DR2–DR0) ← (A2–A0)
Rev.3.01 2005.06.15
REJ03B0008-0301
page 118 of 157
0
0
1
2
0
2
9
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of the low-order 3
bits (A2–A0) of register A to register D.
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TEAB (Transfer data to register E from Accumulator and register B)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
1
0
1
0
2
0
1
A
16
(E7–E4) ← (B)
(E3–E0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register B to the
high-order 4 bits (E7–E4) of register E, and
the contents of register A to the low-order 4
bits (E3–E0) of register E.
TFR0A (Transfer data to register FR0 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
1
0
0
0
2
2
2
8
16
(FR0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to the
port output structure control register FR0.
TFR1A (Transfer data to register FR1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
1
0
0
1
2
2
2
9
16
(FR1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to the
port output structure control register FR1.
TFR2A (Transfer data to register FR2 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
1
(FR2) ← (A)
Rev.3.01 2005.06.15
REJ03B0008-0301
0
1
0
2
2
2
A
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to the
port output structure control register FR2.
page 119 of 157
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TI1A (Transfer data to register I1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
1
1
1
2
2
1
7
16
(I1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of register A to interrupt control register I1.
TI2A (Transfer data to register I2 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
1
0
0
0
2
2
1
8
16
(I2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of register A to interrupt control register I2.
TJ1A (Transfer data to register J1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
0
0
0
1
0
2
2
0
2
16
(J1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Serial I/O operation
Description: Transfers the contents of register A to serial
I/O control register J1.
TK0A (Transfer data to register K0 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
1
(K0) ← (A)
Rev.3.01 2005.06.15
REJ03B0008-0301
0
1
1
2
2
1
B
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to keyon wakeup control register K0.
page 120 of 157
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TK1A (Transfer data to register K1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
1
0
0 2
2
1
4 16
(K1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to keyon wakeup control register K1.
TK2A (Transfer data to register K2 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
1
0
1 2
2
1
5 16
(K2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to keyon wakeup control register K2.
TMA j (Transfer data to Memory from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
1
0
1
1
j
j
j
j
2
2
B
j
16
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
RAM to register transfer
Description: After transferring the contents of register A
to M(DP), an exclusive OR operation is performed between register X and the value j
in the immediate field, and stores the result
in register X.
TMRA (Transfer data to register MR from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
(MR) ← (A)
Rev.3.01 2005.06.15
REJ03B0008-0301
1
1
0
2
2
1
6
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Transfers the contents of register A to clock
control register MR.
page 121 of 157
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TPAA (Transfer data to register PA from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
1
0
1
0
1
0
1
0
2
2
A
A
16
(PA0) ← (A0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of lowermost bit (A0)
register A to timer control register PA.
TPSAB (Transfer data to Pre-Scaler from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
0
1
0
1
2
2
3
5
16
(RPS7–RPS4) ← (B)
(TPS7–TPS4) ← (B)
(RPS3–RPS0) ← (A)
(TPS3–TPS0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of prescaler and prescaler
reload register RPS, and transfers the contents of register A to the low-order 4 bits of
prescaler and prescaler reload register
RPS.
TPU0A (Transfer data to register PU0 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
1
1
0
1
2
2
2
D
16
(PU0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to pullup control register PU0.
TPU1A (Transfer data to register PU1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
1
(PU1) ← (A)
Rev.3.01 2005.06.15
REJ03B0008-0301
page 122 of 157
1
1
0
2
2
2
E
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to pullup control register PU1.
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TQ1A (Transfer data to register Q1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
0
0
1
0
0
2
2
0
4
16
(Q1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: Transfers the contents of register A to A/D
control register Q1.
TQ2A (Transfer data to register Q2 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
0
0
1
0
1
2
2
0
5 16
(Q2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: Transfers the contents of register A to A/D
control register Q2.
TQ3A (Transfer data to register Q3 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
0
0
1
1
0
2
2
0
6
16
(Q3) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: Transfers the contents of register A to A/D
control register Q3.
TR1AB (Transfer data to register R1 from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
1
(R17–R14) ← (B)
(R13–R10) ← (A)
Rev.3.01 2005.06.15
REJ03B0008-0301
page 123 of 157
1
1
1
2
2
3
F
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits (R17–R14) of reload register R1, and the contents of register A to the
low-order 4 bits (R13–R10) of reload register R1.
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TR3AB (Transfer data to register R3 from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
1
0
1
1
2
2
3
B
16
(R37–R34) ← (B)
(R33–R30) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits (R37–R34) of reload register R3, and the contents of register A to the
low-order 4 bits (R33–R3 0) of reload register R3.
TRGA (Transfer data to register RG from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
0
1
0
0
1
2
2
0
9
16
(RG0) ← (A0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Clock control operation
Description: Transfers the contents of register A to register RG.
TSIAB (Transfer data to register SI from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
1
0
0
0
2
2
3
8
16
(SI7–SI4) ← (B)
(SI3–SI0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Serial I/O operation
Description: Transfers the contents of register B to the
high-order 4 bits (SI7–SI4) of serial I/O register SI, and transfers the contents of
register A to the low-order 4 bits (SI3–SI0) of
serial I/O register SI.
TV1A (Transfer data to register V1 from Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
1
1
(V1) ← (A)
Rev.3.01 2005.06.15
REJ03B0008-0301
1
1
1
2
0
3
F
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of register A to interrupt control register V1.
page 124 of 157
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TV2A (Transfer data to register V2 from Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
1
1
1
1
0 2
0
3
E 16
(V2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of register A to interrupt control register V2.
TW1A (Transfer data to register W1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
0
1
1
1
0
2
2
0
E
16
(W1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to timer
control register W1.
TW2A (Transfer data to register W2 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
0
1
1
1
1
2
2
0
F
16
(W2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to timer
control register W2.
TW3A (Transfer data to register W3 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
(W3) ← (A)
Rev.3.01 2005.06.15
REJ03B0008-0301
0
0
0 2
2
1
0 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to timer
control register W3.
page 125 of 157
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TW4A (Transfer data to register W4 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
0
0
1 2
2
1
1 16
(W4) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to timer
control register W4.
TW5A (Transfer data to register W5 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
0
1
0
2
2
1
2 16
(W5) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to timer
control register W5.
TW6A (Transfer data to register W6 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
0
1
1
2
2
1
3 16
(W6) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to timer
control register W6.
TYA (Transfer data to register Y from Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
1
(Y) ← (A)
Rev.3.01 2005.06.15
REJ03B0008-0301
1
0
0
2
0
0
C
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register A to register Y.
page 126 of 157
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
WRST (Watchdog timer ReSeT)
Instruction
code
Operation:
D9
1
D0
0
1
0
1
0
0
0
0
0
2
2
A
0
16
(WDF1) = 1 ?
After skipping, (WDF1) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(WDF1) = 1
Grouping:
Other operation
Description: Skips the next instruction when watchdog
timer flag WDF1 is “1.” After skipping, clears
(0) to the WDF1 flag. When the WDF1 flag
is “0,” executes the next instruction. Also,
stops the watchdog timer function when executing the WRST instruction immediately
after the DWDT instruction.
XAM j (eXchange Accumulator and Memory data)
Instruction
code
Operation:
D9
1
D0
0
1
1
0
1
j
j
j
j
2
2
D
j
16
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
RAM to register transfer
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between register X and the value j in the immediate field,
and stores the result in register X.
XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip)
Instruction
code
Operation:
D9
1
D0
0
1
1
1
1
j
j
j
j
2
2
F
j
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 15
Grouping:
RAM to register transfer
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between register X and the value j in the immediate field,
and stores the result in register X.
Subtracts 1 from the contents of register Y.
As a result of subtraction, when the contents of register Y is 15, the next instruction
is skipped. When the contents of register Y
is not 15, the next instruction is executed.
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1
XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip)
Instruction
code
Operation:
D9
1
D0
0
1
1
1
0
j
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
Rev.3.01 2005.06.15
REJ03B0008-0301
page 127 of 157
j
j
j
2
2
E
j
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 0
Grouping:
RAM to register transfer
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between register X and the value j in the immediate field,
and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition, when the contents of
register Y is 0, the next instruction is
skipped. when the contents of register Y is
not 0, the next instruction is executed.
4518 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES)
Number of
words
Number of
cycles
Instruction code
TAB
0
0
0
0
0
1
1
1
1
0
0 1 E
1
1
(A) ← (B)
TBA
0
0
0
0
0
0
1
1
1
0
0 0 E
1
1
(B) ← (A)
TAY
0
0
0
0
0
1
1
1
1
1
0 1 F
1
1
(A) ← (Y)
TYA
0
0
0
0
0
0
1
1
0
0
0 0 C
1
1
(Y) ← (A)
TEAB
0
0
0
0
0
1
1
0
1
0
0 1 A
1
1
(E7–E4) ← (B)
(E3–E0) ← (A)
TABE
0
0
0
0
1
0
1
0
1
0
0 2 A
1
1
(B) ← (E7–E4)
(A) ← (E3–E0)
TDA
0
0
0
0
1
0
1
0
0
1
0 2 9
1
1
(DR2–DR0) ← (A2–A0)
TAD
0
0
0
1
0
1
0
0
0
1
0 5 1
1
1
(A2–A0) ← (DR2–DR0)
(A3) ← 0
TAZ
0
0
0
1
0
1
0
0
1
1
0 5 3
1
1
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
TAX
0
0
0
1
0
1
0
0
1
0
0 5 2
1
1
(A) ← (X)
TASP
0
0
0
1
0
1
0
0
0
0
0 5 0
1
1
(A2–A0) ← (SP2–SP0)
(A3) ← 0
LXY x, y
1
1
x3 x2 x1 x0 y3 y2 y1 y0
3 x y
1
1
(X) ← x x = 0 to 15
(Y) ← y y = 0 to 15
LZ z
0
0
0
1
0
0
1
0
z1 z0
0 4 8
+z
1
1
(Z) ← z z = 0 to 3
INY
0
0
0
0
0
1
0
0
1
1
0 1 3
1
1
(Y) ← (Y) + 1
DEY
0
0
0
0
0
1
0
1
1
1
0 1 7
1
1
(Y) ← (Y) – 1
TAM j
1
0
1
1
0
0
j
j
j
j
2 C j
1
1
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
XAM j
1
0
1
1
0
1
j
j
j
j
2 D j
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
XAMD j
1
0
1
1
1
1
j
j
j
j
2 F j
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1
XAMI j
1
0
1
1
1
0
j
j
j
j
2 E j
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
TMA j
1
0
1
0
1
1
j
j
j
j
2 B j
1
1
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
Parameter
Mnemonic
RAM to register transfer
RAM addresses
Register to register transfer
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Rev.3.01 2005.06.15
REJ03B0008-0301
page 128 of 157
Hexadecimal
notation
Function
Skip condition
Carry flag CY
4518 Group
–
–
Transfers the contents of register B to register A.
–
–
Transfers the contents of register A to register B.
–
–
Transfers the contents of register Y to register A.
–
–
Transfers the contents of register A to register Y.
–
–
Transfers the contents of register B to the high-order 4 bits (E7–E4) of register E, and the contents of register A to the low-order 4 bits (E3–E0) of register E.
–
–
Transfers the high-order 4 bits (E7–E4) of register E to register B, and low-order 4 bits (E3–E0) of register E
to register A.
–
–
Transfers the contents of the low-order 3 bits (A2–A0) of register A to register D.
–
–
Transfers the contents of register D to the low-order 3 bits (A2–A0) of register A.
–
–
Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A.
–
–
Transfers the contents of register X to register A.
–
–
Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2–A0) of register A.
Continuous
description
–
Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y.
When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed
and other LXY instructions coded continuously are skipped.
–
–
Loads the value z in the immediate field to register Z.
(Y) = 0
–
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed.
(Y) = 15
–
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,
the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.
–
–
After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
–
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
(Y) = 15
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,
the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.
(Y) = 0
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed.
–
–
After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
Rev.3.01 2005.06.15
REJ03B0008-0301
Datailed description
page 129 of 157
4518 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Arithmetic operation
Bit operation
Comparison
operation
Note: p
p
p
p
is
is
is
is
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
notation
Number of
cycles
Mnemonic
Type of
instructions
Number of
words
Instruction code
Parameter
0 7 n
1
1
(A) ← n
n = 0 to 15
Hexadecimal
Function
LA n
0
0
0
1
1
TABP p
0
0
1
0
p5 p4 p3 p2 p1 p0
0 8 p
+p
1
3
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
(DR2) ← 0
(DR1, DR0) ← (ROM(PC))9, 8
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(SK(SP)) ← (PC)
(SP) ← (SP) – 1
AM
0
0
0
0
0
0
1
0
1
0
0 0 A
1
1
(A) ← (A) + (M(DP))
AMC
0
0
0
0
0
0
1
0
1
1
0 0 B
1
1
(A) ← (A) + (M(DP)) +(CY)
(CY) ← Carry
An
0
0
0
1
1
0
n
n
n
n
0 6 n
1
1
(A) ← (A) + n
n = 0 to 15
AND
0
0
0
0
0
1
1
0
0
0
0 1 8
1
1
(A) ← (A) AND (M(DP))
OR
0
0
0
0
0
1
1
0
0
1
0 1 9
1
1
(A) ← (A) OR (M(DP))
SC
0
0
0
0
0
0
0
1
1
1
0 0 7
1
1
(CY) ← 1
RC
0
0
0
0
0
0
0
1
1
0
0 0 6
1
1
(CY) ← 0
SZC
0
0
0
0
1
0
1
1
1
1
0 2 F
1
1
(CY) = 0 ?
CMA
0
0
0
0
0
1
1
1
0
0
0 1 C
1
1
(A) ← (A)
RAR
0
0
0
0
0
1
1
1
0
1
0 1 D
1
1
→ CY → A3A2A1A0
SB j
0
0
0
1
0
1
1
1
j
j
0 5 C
+j
1
1
(Mj(DP)) ← 1
j = 0 to 3
RB j
0
0
0
1
0
0
1
1
j
j
0 4 C
+j
1
1
(Mj(DP)) ← 0
j = 0 to 3
SZB j
0
0
0
0
1
0
0
0
j
j
0 2 j
1
1
(Mj(DP)) = 0 ?
j = 0 to 3
SEAM
0
0
0
0
1
0
0
1
1
0
0 2 6
1
1
(A) = (M(DP)) ?
SEA n
0
0
0
0
1
0
0
1
0
1
0 2 5
2
2
(A) = n ?
n = 0 to 15
0
0
0
1
1
1
n
n
n
n
0 7 n
0
0
0
0
to
to
to
to
15
31
47
63
for
for
for
for
1
M34518M2,
M34518M4,
M34518M6,
M34518M8/E8.
Rev.3.01 2005.06.15
REJ03B0008-0301
page 130 of 157
n
n
n
n
Carry flag CY
4518 Group
Skip condition
Datailed description
Continuous
description
–
Loads the value n in the immediate field to register A.
When the LA instructions are continuously coded and executed, only the first LA instruction is executed and
other LA instructions coded continuously are skipped.
–
–
Transfers bits 9 and 8 to register D, bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0
are the ROM pattern in ad-dress (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p.
When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used.
–
–
Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged.
–
0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY.
Overflow = 0
–
Adds the value n in the immediate field to register A, and stores a result in register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no overflow as the result of operation.
Executes the next instruction when there is overflow as the result of operation.
–
–
Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A.
–
–
Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result
in register A.
–
1
Sets (1) to carry flag CY.
–
0
Clears (0) to carry flag CY.
(CY) = 0
–
Skips the next instruction when the contents of carry flag CY is “0.”
–
–
Stores the one’s complement for register A’s contents in register A.
–
0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right.
–
–
Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
–
–
Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
(Mj(DP)) = 0
j = 0 to 3
–
Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of
M(DP) is “0.”
Executes the next instruction when the contents of bit j of M(DP) is “1.”
(A) = (M(DP))
–
Skips the next instruction when the contents of register A is equal to the contents of M(DP).
Executes the next instruction when the contents of register A is not equal to the contents of M(DP).
(A) = n
–
Skips the next instruction when the contents of register A is equal to the value n in the immediate field.
Executes the next instruction when the contents of register A is not equal to the value n in the immediate
field.
Rev.3.01 2005.06.15
REJ03B0008-0301
page 131 of 157
4518 Group
MACHINE INSTRUCTIONS (continued)
Number of
words
Number of
cycles
Instruction code
Ba
0
1
1
a6 a5 a4 a3 a2 a1 a0
1 8 a
+a
1
1
(PCL) ← a6–a0
BL p, a
0
0
1
1
p4 p3 p2 p1 p0
0 E p
+p
2
2
(PCH) ← p (Note)
(PCL) ← a6–a0
1
0
p5 a6 a5 a4 a3 a2 a1 a0
2 p a
+a
0
0
0
0
1
0
0 1 0
2
2
(PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
1
0
p5 p4 0
0
p3 p2 p1 p0
2 p p
BM a
0
1
0
a6 a5 a4 a3 a2 a1 a0
1 a a
1
1
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
(PCL) ← a6–a0
BML p, a
0
0
1
1
p4 p3 p2 p1 p0
0 C p
+p
2
2
1
0
p5 a6 a5 a4 a3 a2 a1 a0
2 p a
+a
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← a6–a0
0
0
0
1
1
0
0 3 0
2
2
1
0
p5 p4 0
0
p3 p2 p1 p0
2 p p
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← (DR2–DR0,A3–A0)
RTI
0
0
0
1
0
0
0
1
1
0
0 4 6
1
1
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RT
0
0
0
1
0
0
0
1
0
0
0 4 4
1
2
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RTS
0
0
0
1
0
0
0
1
0
1
0 4 5
1
2
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Parameter
Mnemonic
Branch operation
Type of
instructions
Subroutine operation
BLA p
BMLA p
Return operation
Note: p
p
p
p
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
is
is
is
is
0
0
0
0
to
to
to
to
15
31
47
63
for
for
for
for
0
0
1
0
M34518M2,
M34518M4,
M34518M6,
M34518M8/E8.
Rev.3.01 2005.06.15
REJ03B0008-0301
page 132 of 157
0
0
0
0
0
0
Hexadecimal
notation
Function
Skip condition
Carry flag CY
4518 Group
–
–
Branch within a page : Branches to address a in the identical page.
–
–
Branch out of a page : Branches to address a in page p.
–
–
Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in
page p.
–
–
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
–
–
Call the subroutine : Calls the subroutine at address a in page p.
–
–
Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D
and A in page p.
–
–
Returns from interrupt service routine to main routine.
Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt.
–
–
Returns from subroutine to the routine called the subroutine.
Skip at uncondition
–
Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
Rev.3.01 2005.06.15
REJ03B0008-0301
Datailed description
page 133 of 157
4518 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of
words
Number of
cycles
Instruction code
DI
0
0
0
0
0
0
0
1
0
0
0 0 4
1
1
(INTE) ← 0
EI
0
0
0
0
0
0
0
1
0
1
0 0 5
1
1
(INTE) ← 1
SNZ0
0
0
0
0
1
1
1
0
0
0
0 3 8
1
1
V10 = 0: (EXF0) = 1 ?
After skipping, (EXF0) ← 0
V10 = 1: SNZ0 = NOP
SNZ1
0
0
0
0
1
1
1
0
0
1
0 3 9
1
1
V11 = 0: (EXF1) = 1 ?
After skipping, (EXF1) ← 0
V11 = 1: SNZ1 = NOP
SNZI0
0
0
0
0
1
1
1
0
1
0
0 3 A
1
1
I12 = 1 : (INT0) = “H” ?
Parameter
Mnemonic
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecimal
notation
Function
Timer operation
Interrupt operation
I12 = 0 : (INT0) = “L” ?
SNZI1
0
0
0
0
1
1
1
0
1
1
0 3 B
1
1
I22 = 1 : (INT1) = “H” ?
I22 = 0 : (INT1) = “L” ?
TAV1
0
0
0
1
0
1
0
1
0
0
0 5 4
1
1
(A) ← (V1)
TV1A
0
0
0
0
1
1
1
1
1
1
0 3 F
1
1
(V1) ← (A)
TAV2
0
0
0
1
0
1
0
1
0
1
0 5 5
1
1
(A) ← (V2)
TV2A
0
0
0
0
1
1
1
1
1
0
0 3 E
1
1
(V2) ← (A)
TAI1
1
0
0
1
0
1
0
0
1
1
2 5 3
1
1
(A) ← (I1)
TI1A
1
0
0
0
0
1
0
1
1
1
2 1 7
1
1
(I1) ← (A)
TAI2
1
0
0
1
0
1
0
1
0
0
2 5 4
1
1
(A) ← (I2)
TI2A
1
0
0
0
0
1
1
0
0
0
2 1 8
1
1
(I2) ← (A)
TPAA
1
0
1
0
1
0
1
0
1
0
2 A A
1
1
(PA0) ← (A0)
TAW1
1
0
0
1
0
0
1
0
1
1
2 4 B
1
1
(A) ← (W1)
TW1A
1
0
0
0
0
0
1
1
1
0
2 0 E
1
1
(W1) ← (A)
TAW2
1
0
0
1
0
0
1
1
0
0
2 4 C
1
1
(A) ← (W2)
TW2A
1
0
0
0
0
0
1
1
1
1
2 0 F
1
1
(W2) ← (A)
TAW3
1
0
0
1
0
0
1
1
0
1
2 4 D
1
1
(A) ← (W3)
TW3A
1
0
0
0
0
1
0
0
0
0
2 1 0
1
1
(W3) ← (A)
TAW4
1
0
0
1
0
0
1
1
1
0
2 4 E
1
1
(A) ← (W4)
TW4A
1
0
0
0
0
1
0
0
0
1
2 1 1
1
1
(W4) ← (A)
Rev.3.01 2005.06.15
REJ03B0008-0301
page 134 of 157
Skip condition
Carry flag CY
4518 Group
–
–
Clears (0) to interrupt enable flag INTE, and disables the interrupt.
–
–
Sets (1) to interrupt enable flag INTE, and enables the interrupt.
V10 = 0: (EXF0) = 1
–
When V10 = 0 : Skips the next instruction when external 0 interrupt request flag EXF0 is “1.” After skipping,
clears (0) to the EXF0 flag. When the EXF0 flag is “0,” executes the next instruction.
When V10 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register V1)
V11 = 0: (EXF1) = 1
–
When V11 = 0 : Skips the next instruction when external 1 interrupt request flag EXF1 is “1.” After skipping,
clears (0) to the EXF1 flag. When the EXF1 flag is “0,” executes the next instruction.
When V11 = 1 : This instruction is equivalent to the NOP instruction. (V11: bit 1 of interrupt control register V1)
(INT0) = “H”
However, I12 = 1
–
When I12 = 1 : Skips the next instruction when the level of INT0 pin is “H.” (I12: bit 2 of interrupt control register I1)
(INT0) = “L”
However, I12 = 0
–
When I12 = 0 : Skips the next instruction when the level of INT0 pin is “L.”
(INT1) = “H”
However, I22 = 1
–
When I22 = 1 : Skips the next instruction when the level of INT1 pin is “H.” (I22: bit 2 of interrupt control register I2)
(INT1) = “L”
However, I22 = 0
–
When I22 = 0 : Skips the next instruction when the level of INT1 pin is “L.”
–
–
Transfers the contents of interrupt control register V1 to register A.
–
–
Transfers the contents of register A to interrupt control register V1.
–
–
Transfers the contents of interrupt control register V2 to register A.
–
–
Transfers the contents of register A to interrupt control register V2.
–
–
Transfers the contents of interrupt control register I1 to register A.
–
–
Transfers the contents of register A to interrupt control register I1.
–
–
Transfers the contents of interrupt control register I2 to register A.
–
–
Transfers the contents of register A to interrupt control register I2.
–
–
Transfers the contents of register A to timer control register PA.
–
–
Transfers the contents of timer control register W1 to register A.
–
–
Transfers the contents of register A to timer control register W1.
–
–
Transfers the contents of timer control register W2 to register A.
–
–
Transfers the contents of register A to timer control register W2.
–
–
Transfers the contents of timer control register W3 to register A.
–
–
Transfers the contents of register A to timer control register W3.
–
–
Transfers the contents of timer control register W4 to register A.
–
–
Transfers the contents of register A to timer control register W4.
Rev.3.01 2005.06.15
REJ03B0008-0301
Datailed description
page 135 of 157
4518 Group
Number of
words
Number of
cycles
Instruction code
TAW5
1
0
0
1
0
0
1
1
1
1
2 4 F
1
1
(A) ← (W5)
TW5A
1
0
0
0
0
1
0
0
1
0
2 1 2
1
1
(W5) ← (A)
TAW6
1
0
0
1
0
1
0
0
0
0
2 5 0
1
1
(A) ← (W6)
TW6A
1
0
0
0
0
1
0
0
1
1
2 1 3
1
1
(W6) ← (A)
TABPS
1
0
0
1
1
1
0
1
0
1
2 7 5
1
1
(B) ← (TPS7–TPS4)
(A) ← (TPS3–TPS0)
TPSAB
1
0
0
0
1
1
0
1
0
1
2 3 5
1
1
(RPS7–RPS4) ← (B)
(TPS7–TPS4) ← (B)
(RPS3–RPS0) ← (A)
(TPS3–TPS0) ← (A)
TAB1
1
0
0
1
1
1
0
0
0
0
2 7 0
1
1
(B) ← (T17–T14)
(A) ← (T13–T10)
T1AB
1
0
0
0
1
1
0
0
0
0
2 3 0
1
1
(R17–R14) ← (B)
(T17–T14) ← (B)
(R13–R10) ← (A)
(T13–T10) ← (A)
TAB2
1
0
0
1
1
1
0
0
0
1
2 7 1
1
1
(B) ← (T27–T24)
(A) ← (T23–T20)
T2AB
1
0
0
0
1
1
0
0
0
1
2 3 1
1
1
(R27–R24) ← (B)
(T27–T24) ← (B)
(R23–R20) ← (A)
(T23–T20) ← (A)
TAB3
1
0
0
1
1
1
0
0
1
0
2 7 2
1
1
(B) ← (T37–T34)
(A) ← (T33–T30)
T3AB
1
0
0
0
1
1
0
0
1
0
2 3 2
1
1
(R37–R34) ← (B)
(T37–T34) ← (B)
(R33–R30) ← (A)
(T33–T30) ← (A)
TAB4
1
0
0
1
1
1
0
0
1
1
2 7 3
1
1
(B) ← (T47–T44)
(A) ← (T43–T40)
T4AB
1
0
0
0
1
1
0
0
1
1
2 3 3
1
1
(R4L7–R4L4) ← (B)
(T47–T44) ← (B)
(R4L3–R4L0) ← (A)
(T43–T40) ← (A)
T4HAB
1
0
0
0
1
1
0
1
1
1
2 3 7
1
1
(R4H7–R4H4) ← (B)
(R4H3–R4H0) ← (A)
TR1AB
1
0
0
0
1
1
1
1
1
1
2 3 F
1
1
(R17–R14) ← (B)
(R13–R10) ← (A)
TR3AB
1
0
0
0
1
1
1
0
1
1
2 3 B
1
1
(R37–R34) ← (B)
(R33–R30) ← (A)
T4R4L
1
0
1
0
0
1
0
1
1
1
2 9 7
1
1
(T47–T40) ← (R4L7–R4L0)
Parameter
Mnemonic
Timer operation
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Rev.3.01 2005.06.15
REJ03B0008-0301
page 136 of 157
Hexadecimal
notation
Function
Skip condition
Carry flag CY
4518 Group
Datailed description
–
–
Transfers the contents of timer control register W5 to register A.
–
–
Transfers the contents of register A to timer control register W5.
–
–
Transfers the contents of timer control register W6 to register A.
–
–
Transfers the contents of register A to timer control register W6.
–
–
Transfers the high-order 4 bits of prescaler to register B, and transfers the low-order 4 bits of prescaler to
register A.
–
–
Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS,
and transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register
RPS.
–
–
Transfers the high-order 4 bits of timer 1 to register B, and transfers the low-order 4 bits of timer 1 to register A.
–
–
Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1, and
transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1.
–
–
Transfers the high-order 4 bits of timer 2 to register B, and transfers the low-order 4 bits of timer 2 to register A.
–
–
Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2, and
transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2.
–
–
Transfers the high-order 4 bits of timer 3 to register B, and transfers the low-order 4 bits of timer 3 to register A.
–
–
Transfers the contents of register B to the high-order 4 bits of timer 3 and timer 3 reload register R3, and
transfers the contents of register A to the low-order 4 bits of timer 3 and timer 3 reload register R3.
–
–
Transfers the high-order 4 bits of timer 4 to register B, and transfers the low-order 4 bits of timer 4 to register A.
–
–
Transfers the contents of register B to the high-order 4 bits of timer 4 and timer 4 reload register R4L, and
transfers the contents of register A to the low-order 4 bits of timer 4 and timer 4 reload register R4L.
–
–
Transfers the contents of register B to the high-order 4 bits of timer 4 reload register R4H, and transfers the
contents of register A to the low-order 4 bits of timer 4 reload register R4H.
–
–
Transfers the contents of register B to the high-order 4 bits of timer 1 reload register R1, and transfers the
contents of register A to the low-order 4 bits of timer 1 reload register R1.
–
–
Transfers the contents of register B to the high-order 4 bits of timer 3 reload register R3, and transfers the
contents of register A to the low-order 4 bits of timer 3 reload register R3.
–
–
Transfers the contents of timer 4 reload register R4L to timer 4.
–
–
Rev.3.01 2005.06.15
REJ03B0008-0301
page 137 of 157
4518 Group
Number of
words
Number of
cycles
Instruction code
Function
SNZT1
1
0
1
0
0
0
0
0
0
0
2 8 0
1
1
V12 = 0: (T1F) = 1 ? After skipping, (T1F) ← 0
V12 = 0: NOP
SNZT2
1
0
1
0
0
0
0
0
0
1
2 8 1
1
1
V13 = 0: (T2F) = 1 ? After skipping, (T2F) ← 0
V13 = 0: NOP
SNZT3
1
0
1
0
0
0
0
0
1
0
2 8 2
1
1
V20 = 0: (T3F) = 1 ? After skipping, (T3F) ← 0
V20 = 0: NOP
SNZT4
1
0
1
0
0
0
0
0
1
1
2 8 3
1
1
V21 = 0: (T4F) = 1 ? After skipping, (T4F) ← 0
V21 = 0: NOP
IAP0
1
0
0
1
1
0
0
0
0
0
2 6 0
1
1
(A) ← (P0)
OP0A
1
0
0
0
1
0
0
0
0
0
2 2 0
1
1
(P0) ← (A)
IAP1
1
0
0
1
1
0
0
0
0
1
2 6 1
1
1
(A) ← (P1)
OP1A
1
0
0
0
1
0
0
0
0
1
2 2 1
1
1
(P1) ← (A)
IAP2
1
0
0
1
1
0
0
0
1
0
2 6 2
1
1
(A2–A0) ← (P22–P20) (A3) ← 0
OP2A
1
0
0
0
1
0
0
0
1
0
2 2 2
1
1
(P22–P20) ← (A2–A0)
IAP3
1
0
0
1
1
0
0
0
1
1
2 6 3
1
1
(A1, A0) ← (P31, P30)
OP3A
1
0
0
0
1
0
0
0
1
1
2 2 3
1
1
(P31, P30) ← (A1, A0)
IAP6
1
0
0
1
1
0
0
1
1
0
2 6 6
1
1
(A) ← (P6)
OP6A
1
0
0
0
1
0
0
1
1
0
2 2 6
1
1
(P6) ← (A)
CLD
0
0
0
0
0
1
0
0
0
1
0 1 1
1
1
(D) ← 1
RD
0
0
0
0
0
1
0
1
0
0
0 1 4
1
1
(D(Y)) ← 0
(Y) = 0 to 7
SD
0
0
0
0
0
1
0
1
0
1
0 1 5
1
1
(D(Y)) ← 1
(Y) = 0 to 7
SZD
0
0
0
0
1
0
0
1
0
0
0 2 4
1
1
(D(Y)) = 0 ?
(Y) = 0 to 7
0
0
0
0
1
0
1
0
1
1
0 2 B
1
1
TAPU0
1
0
0
1
0
1
0
1
1
1
2 5 7
1
1
(A) ← (PU0)
TPU0A
1
0
0
0
1
0
1
1
0
1
2 2 D
1
1
(PU0) ← (A)
TAPU1
1
0
0
1
0
1
1
1
1
0
2 5 E
1
1
(A) ← (PU1)
TPU1A
1
0
0
0
1
0
1
1
1
0
2 2 E
1
1
(PU1) ← (A)
Parameter
Mnemonic
Input/Output operation
Timer operation
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Rev.3.01 2005.06.15
REJ03B0008-0301
page 138 of 157
Hexadecimal
notation
Skip condition
Carry flag CY
4518 Group
V12 = 0: (T1F) = 1
–
Skips the next instruction when the contents of bit 2 (V12) of interrupt control register V1 is “0” and the contents of T1F flag is “1.” After skipping, clears (0) to T1F flag.
V13 = 0: (T2F) =1
–
Skips the next instruction when the contents of bit 3 (V13) of interrupt control register V1 is “0” and the contents of T2F flag is “1.” After skipping, clears (0) to T2F flag.
V20 = 0: (T3F) = 1
–
Skips the next instruction when the contents of bit 0 (V20) of interrupt control register V2 is “0” and the contents of T3F flag is “1.” After skipping, clears (0) to T3F flag.
V21 = 0: (T4F) =1
–
Skips the next instruction when the contents of bit 1 (V21) of interrupt control register V2 is “0” and the contents of T4F flag is “1.” After skipping, clears (0) to T4F flag.
–
–
Transfers the input of port P0 to register A.
–
–
Outputs the contents of register A to port P0.
–
–
Transfers the input of port P1 to register A.
–
–
Outputs the contents of register A to port P1.
–
–
Transfers the input of port P2 to register A.
–
–
Outputs the contents of register A to port P2.
–
–
Transfers the input of port P3 to register A.
–
–
Outputs the contents of register A to port P3.
–
–
Transfers the input of port P6 to register A.
–
–
Outputs the contents of register A to port P6.
–
–
Sets (1) to all port D.
–
–
Clears (0) to a bit of port D specified by register Y.
–
–
Sets (1) to a bit of port D specified by register Y.
(D(Y)) = 0
However, (Y)=0 to 7
–
Skips the next instruction when a bit of port D specified by register Y is “0.” Executes the next instruction
when a bit of port D specified by register Y is “1.”
–
–
Transfers the contents of pull-up control register PU0 to register A.
–
–
Transfers the contents of register A to pull-up control register PU0.
–
–
Transfers the contents of pull-up control register PU1 to register A.
–
–
Transfers the contents of register A to pull-up control register PU1.
Rev.3.01 2005.06.15
REJ03B0008-0301
Datailed description
page 139 of 157
4518 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of
words
Number of
cycles
Instruction code
TAK0
1
0
0
1
0
1
0
1
1
0
2 5 6
1
1
(A) ← (K0)
TK0A
1
0
0
0
0
1
1
0
1
1
2 1 B
1
1
(K0) ← (A)
TAK1
1
0
0
1
0
1
1
0
0
1
2 5 9
1
1
(A) ← (K1)
TK1A
1
0
0
0
0
1
0
1
0
0
2 1 4
1
1
(K1) ← (A)
TAK2
1
0
0
1
0
1
1
0
1
0
2 5 A
1
1
(A) ← (K2)
TK2A
1
0
0
0
0
1
0
1
0
1
2 1 5
1
1
(K2) ← (A)
TFR0A
1
0
0
0
1
0
1
0
0
0
2 2 8
1
1
(FR0) ← (A)
TFR1A
1
0
0
0
1
0
1
0
0
1
2 2 9
1
1
(FR1) ← (A)
TFR2A
1
0
0
0
1
0
1
0
1
0
2 2 A
1
1
(FR2) ← (A)
TABSI
1
0
0
1
1
1
1
0
0
0
2 7 8
1
1
(B) ← (SI7–SI4) (A) ← (SI3–SI0)
TSIAB
1
0
0
0
1
1
1
0
0
0
2 3 8
1
1
(SI7–SI4) ← (B) (SI3–SI0) ← (A)
SST
1
0
1
0
0
1
1
1
1
0
2 9 E
1
1
(SIOF) ← 0
Serial I/O starting
SNZSI
1
0
1
0
0
0
1
0
0
0
2 8 8
1
1
V23=0: (SIOF)=1?
After skipping, (SIOF) ← 0 V23 = 1: NOP
TAJ1
1
0
0
1
0
0
0
0
1
0
2 4 2
1
1
(A) ← (J1)
TJ1A
1
0
0
0
0
0
0
0
1
0
2 0 2
1
1
(J1) ← (A)
CMCK
1
0
1
0
0
1
1
0
1
0
2 9 A
1
1
Ceramic resonator selected
CRCK
1
0
1
0
0
1
1
0
1
1
2 9 B
1
1
RC oscillator selected
CYCK
1
0
1
0
0
1
1
1
0
1
2 9 D
1
1
Quartz-crystal oscillator selected
TRGA
1
0
0
0
0
0
1
0
0
1
2 0 9
1
1
(RG0) ← (A0)
TAMR
1
0
0
1
0
1
0
0
1
0
2 5 2
1
1
(A) ← (MR)
TMRA
1
0
0
0
0
1
0
1
1
0
2 1 6
1
1
(MR) ← (A)
Parameter
Mnemonic
Clock operation
Serial I/O operation
Input/Output operation
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Rev.3.01 2005.06.15
REJ03B0008-0301
page 140 of 157
Hexadecimal
notation
Function
Skip condition
Carry flag CY
4518 Group
–
–
Transfers the contents of key-on wakeup control register K0 to register A.
–
–
Transfers the contents of register A to key-on wakeup control register K0 .
–
–
Transfers the contents of key-on wakeup control register K1 to register A.
–
–
Transfers the contents of register A to key-on wakeup control register K1.
–
–
Transfers the contents of key-on wakeup control register K2 to register A.
–
–
Transfers the contents of register A to key-on wakeup control register K2.
–
–
Transferts the contents of register A to port output format control register FR0.
–
–
Transferts the contents of register A to port output format control register FR1.
–
–
Transferts the contents of register A to port output format control register FR2.
–
–
Transfers the high-order 4 bits of serial I/O register SI to register B, and transfers the low-order 4 bits of serial I/O register SI to register A.
–
–
Transfers the contents of register B to the high-order 4 bits of serial I/O register SI, and transfers the contents of register A to the low-order 4 bits of serial I/O register SI.
–
–
Clears (0) to SIOF flag and starts serial I/O.
V23 = 0: (SIOF) = 1
–
Skips the next instruction when the contents of bit 3 (V23) of interrupt control register V2 is “0” and contents
of SIOF flag is “1.” After skipping, clears (0) to SIOF flag.
–
–
Transfers the contents of serial I/O control register J1 to register A.
–
–
Transfers the contents of register A to serial I/O control register J1.
–
–
Selects the ceramic resonator for main clock f(XIN).
–
–
Selects the RC oscillation circuit for main clock f(XIN).
–
–
Selects the quartz-crystal oscillation circuit for main clock f(XIN).
–
–
Transfers the contents of clock control regiser RG to register A.
–
–
Transfers the contents of clock control regiser MR to register A.
–
–
Transfers the contents of register A to clock control register MR.
Rev.3.01 2005.06.15
REJ03B0008-0301
Datailed description
page 141 of 157
4518 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of
words
Number of
cycles
Instruction code
TABAD
1
0
0
1
1
1
1
0
0
1
2 7 9
1
1
Q13 = 0:
(B) ← (AD9–AD6)
(A) ← (AD5–AD2)
Q13 = 1:
(B) ← (AD7–AD4)
(A) ← (AD3–AD0)
TALA
1
0
0
1
0
0
1
0
0
1
2 4 9
1
1
(A3, A2) ← (AD1, AD0)
(A1, A0) ← 0
TADAB
1
0
0
0
1
1
1
0
0
1
2 3 9
1
1
(AD7–AD4) ← (B)
(AD3–AD0) ← (A)
ADST
1
0
1
0
0
1
1
1
1
1
2 9 F
1
1
(ADF) ← 0
A/D conversion starting
SNZAD
1
0
1
0
0
0
0
1
1
1
2 8 7
1
1
V21 = 0: (ADF) = 1 ?
After skipping, (ADF) ← 0 V22 = 1: NOP
TAQ1
1
0
0
1
0
0
0
1
0
0
2 4 4
1
1
(A) ← (Q1)
TQ1A
1
0
0
0
0
0
0
1
0
0
2 0 4
1
1
(Q1) ← (A)
TAQ2
1
0
0
1
0
0
0
1
0
1
2 4 5
1
1
(A) ← (Q2)
TQ2A
1
0
0
0
0
0
0
1
0
1
2 0 5
1
1
(Q2) ← (A)
TAQ3
1
0
0
1
0
0
0
1
1
0
2 4 6
1
1
(A) ← (Q3)
TQ3A
1
0
0
0
0
0
0
1
1
0
2 0 6
1
1
(Q3) ← (A)
NOP
0
0
0
0
0
0
0
0
0
0
0 0 0
1
1
(PC) ← (PC) + 1
POF
0
0
0
0
0
0
0
0
1
0
0 0 2
1
1
Transition to RAM back-up mode
EPOF
0
0
0
1
0
1
1
0
1
1
0 5 B
1
1
POF instruction valid
SNZP
0
0
0
0
0
0
0
0
1
1
0 0 3
1
1
(P) = 1 ?
WRST
1
0
1
0
1
0
0
0
0
0
2 A 0
1
1
(WDF1) = 1 ?
After skipping, (WDF1) ← 0
DWDT
1
0
1
0
0
1
1
1
0
0
2 9 C
1
1
Stop of watchdog timer function enabled
SRST
0
0
0
0
0
0
0
0
0
1
0 0 1
1
1
System reset occurrence
Parameter
Mnemonic
Other operation
A/D conversion operation
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Rev.3.01 2005.06.15
REJ03B0008-0301
page 142 of 157
Hexadecimal
notation
Function
Skip condition
Carry flag CY
4518 Group
–
–
In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9–AD6) of register AD to register
B, and the middle-order 4 bits (AD5–AD2) of register AD to register A.
In the comparator mode (Q13 = 1), transfers the middle-order 4 bits (AD7–AD4) of register AD to register B,
and the low-order 4 bits (AD3–AD0) of register AD to register A.
(Q13: bit 3 of A/D control register Q1)
–
–
Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (AD3, AD2) of register A.
–
–
In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD7–AD4) of
comparator register, and the contents of register A to the low-order 4 bits (AD3–AD0) of comparator register.
(Q13 = bit 3 of A/D control register Q1)
–
–
Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q13
= 0) or the comparator operation at the comparator mode (Q13 = 1) is started.
(Q13 = bit 3 of A/D control register Q1)
V22 = 0: (ADF) = 1
–
When V22 = 0 : Skips the next instruction when A/D conversion completion flag ADF is “1.” After skipping,
clears (0) to the ADF flag. When the ADF flag is “0,” executes the next instruction. (V22: bit 2 of interrupt control register V2)
–
–
Transfers the contents of A/D control register Q1 to register A.
–
–
Transfers the contents of register A to A/D control register Q1.
–
–
Transfers the contents of A/D control register Q2 to register A.
–
–
Transfers the contents of register A to A/D control register Q2.
–
–
Transfers the contents of A/D control register Q3 to register A.
–
–
Transfers the contents of register A to A/D control register Q3.
–
–
No operation; Adds 1 to program counter value, and others remain unchanged.
–
–
Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruction.
–
–
Makes the immediate after POF instruction valid by executing the EPOF instruction.
(P) = 1
–
Skips the next instruction when the P flag is “1”.
After skipping, the P flag remains unchanged.
(WDF1) = 1
–
Skips the next instruction when watchdog timer flag WDF1 is “1.” After skipping, clears (0) to the WDF1 flag.
Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT
instruction.
–
–
Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction.
–
–
System reset occurs.
Rev.3.01 2005.06.15
REJ03B0008-0301
Datailed description
page 143 of 157
4518 Group
INSTRUCTION CODE TABLE
D9–D4 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001001010 001011001100 001101 001110 001111
010000 011000
010111 011111
Hex.
D3–D0 notation
00
01
BLA
02
03
04
05
06
07
08
09
SZB
BMLA
0
–
TASP
A
0
LA
0
TABP TABP TABP TABP
BML*** BML BL***
0
16*** 32** 48*
BL
BM
B
SZB
1
–
–
TAD
A
1
LA
1
TABP TABP TABP TABP
BML*** BML BL***
1
17*** 33** 49*
BL
BM
B
SZB
2
–
–
TAX
A
2
LA
2
TABP TABP TABP TABP
BML*** BML BL***
2
18*** 34** 50*
BL
BM
B
SNZP INY
SZB
3
–
–
TAZ
A
3
LA
3
TABP TABP TABP TABP
BML*** BML BL***
3
19*** 35** 51*
BL
BM
B
RT
TAV1
A
4
LA
4
TABP TABP TABP TABP
BML*** BML BL***
4
20*** 36** 52*
BL
BM
B
0A
0B
0C
0D
0E
0F
10–17 18–1F
0000
0
NOP
0001
1
SRST CLD
0010
2
0011
3
0100
4
DI
RD
SZD
–
0101
5
EI
SD
SEAn
–
RTS TAV2
A
5
LA
5
TABP TABP TABP TABP
BML*** BML BL***
5
21*** 37** 53*
BL
BM
B
0110
6
RC
–
SEAM
–
RTI
–
A
6
LA
6
TABP TABP TABP TABP
BML*** BML BL***
6
22*** 38** 54*
BL
BM
B
0111
7
SC
DEY
–
–
–
–
A
7
LA
7
TABP TABP TABP TABP
BML*** BML BL***
7
23*** 39** 55*
BL
BM
B
1000
8
–
AND
–
SNZ0
LZ
0
–
A
8
LA
8
TABP TABP TABP TABP
BML*** BML BL***
8
24*** 40** 56*
BL
BM
B
1001
9
–
OR
TDA SNZ1
LZ
1
–
A
9
LA
9
TABP TABP TABP TABP
BML*** BML BL***
9
25*** 41** 57*
BL
BM
B
1010
A
AM
TEAB TABE SNZI0
LZ
2
–
A
10
LA
10
TABP TABP TABP TABP
BML*** BML BL***
10 26*** 42** 58*
BL
BM
B
1011
B
AMC
–
–
SNZI1
LZ
3
EPOF
A
11
LA
11
TABP TABP TABP TABP
BML*** BML BL***
11 27*** 43** 59*
BL
BM
B
1100
C
TYA
CMA
–
–
RB
0
SB
0
A
12
LA
12
TABP TABP TABP TABP
BML*** BML BL***
12 28*** 44** 60*
BL
BM
B
1101
D
–
RAR
–
–
RB
1
SB
1
A
13
LA
13
TABP TABP TABP TABP
BML*** BML BL***
13 29*** 45** 61*
BL
BM
B
1110
E
TBA
TAB
–
TV2A
RB
2
SB
2
A
14
LA
14
TABP TABP TABP TABP
BML*** BML BL***
14 30*** 46** 62*
BL
BM
B
1111
F
–
TAY
SZC TV1A
RB
3
SB
3
A
15
LA
15
TABP TABP TABP TABP
BML*** BML BL***
15 31*** 47** 63*
BL
BM
B
POF
–
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order
4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is
shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below.
BL
BML
BLA
BMLA
SEA
SZD
The second word
1p paaa aaaa
1p paaa aaaa
1p pp00 pppp
1p pp00 pppp
00 0111 nnnn
00 0010 1011
Rev.3.01 2005.06.15
REJ03B0008-0301
• *, **, *** cannot be used in the M34518M2.
• *, ** cannot be used in the M34518M4.
• * cannot be used in the M34518M6.
page 144 of 157
4518 Group
INSTRUCTION CODE TABLE (continued)
D9–D4 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001101010 101011 101100 101101 101110 101111
110000
111111
Hex.
D3–D0 notation
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
–
WRST
TMA
0
TAM
0
XAM XAMI XAMD LXY
0
0
0
IAP1 TAB2 SNZT2
–
–
TMA
1
TAM
1
XAM XAMI XAMD LXY
1
1
1
TJ1A TW5A OP2A T3AB TAJ1 TAMR IAP2 TAB3 SNZT3
–
–
TMA
2
TAM
2
XAM XAMI XAMD LXY
2
2
2
–
–
TMA
3
TAM
3
XAM XAMI XAMD LXY
3
3
3
0000
0
–
TW3A OP0A T1AB
–
0001
1
–
TW4A OP1A T2AB
–
0010
2
0011
3
0100
4
TQ1A TK1A
–
0101
5
TQ2A TK2A
–
0110
6
TQ3A TMRA OP6A
0111
7
–
TI1A
T4HAB
–
TAPU0
–
1000
8
–
TI2A TFR0A TSIAB
–
–
–
TABSI SNZSI
1001
9
TRGA
–
TFR1ATADAB TALA TAK1
–
TABAD
–
1010
A
–
–
TFR2A
TAK2
–
–
–
1011
B
–
TK0A
–
–
–
–
1100
C
–
–
–
–
TAW2
–
–
1101
D
–
–
TPU0A
–
TAW3
–
1110
E
TW1A
–
TPU1A
–
TAW4 TAPU1
1111
F
TW2A
–
–
–
TW6A OP3A T4AB
–
–
–
–
–
TAI1
TAQ1 TAI2
TPSAB TAQ2
–
TAW6 IAP0 TAB1 SNZT1
–
IAP3 TAB4 SNZT4
TR3AB TAW1
TR1AB TAW5
–
2E
2F
30–3F
–
–
–
–
–
TMA
4
TAM
4
XAM XAMI XAMD LXY
4
4
4
–
TABPS
–
–
–
TMA
5
TAM
5
XAM XAMI XAMD LXY
5
5
5
–
–
–
–
TMA
6
TAM
6
XAM XAMI XAMD LXY
6
6
6
–
TMA
7
TAM
7
XAM XAMI XAMD LXY
7
7
7
–
–
TMA
8
TAM
8
XAM XAMI XAMD LXY
8
8
8
–
–
TMA
9
TAM
9
XAM XAMI XAMD LXY
9
9
9
CMCK TPAA
TMA
10
TAM
10
XAM XAMI XAMD LXY
10
10
10
–
CRCK
–
TMA
11
TAM
11
XAM XAMI XAMD LXY
11
11
11
–
–
DWDT
–
TMA
12
TAM
12
XAM XAMI XAMD LXY
12
12
12
–
–
–
CYCK
–
TMA
13
TAM
13
XAM XAMI XAMD LXY
13
13
13
–
–
–
SST
–
TMA
14
TAM
14
XAM XAMI XAMD LXY
14
14
14
–
–
–
ADST
–
TMA
15
TAM
15
XAM XAMI XAMD
LXY
15
15
15
TAQ3 TAK0 IAP6
–
2D
–
SNZAD T4R4L
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the loworder 4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal
representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of
each instruction is shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below.
BL
BML
BLA
BMLA
SEA
SZD
The second word
1p paaa aaaa
1p paaa aaaa
1p pp00 pppp
1p pp00 pppp
00 0111 nnnn
00 0010 1011
Rev.3.01 2005.06.15
REJ03B0008-0301
page 145 of 157
4518 Group
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDD
Supply voltage
VI
Input voltage
P0, P1, P2, P3, P6, D0–D7, RESET, XIN, VDCE
VI
Input voltage SCK, SIN, CNTR0, CNTR1, INT0, INT1
VI
Input voltage AIN0–AIN3
VO
Output voltage
P0, P1, P2, P3, P6, D0–D7, RESET
VO
Output voltage SCK, SOUT, CNTR0, CNTR1
VO
Output voltage XOUT
Pd
Power dissipation
Topr
Tstg
Operating temperature range
Storage temperature range
Rev.3.01 2005.06.15
REJ03B0008-0301
page 146 of 157
Conditions
Output transistors in cut-off state
Output transistors in cut-off state
Ta = 25 °C
PLQP0032GB-A
PRDP0032BA-A
Ratings
–0.3 to 6.5
–0.3 to VDD+0.3
Unit
V
V
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to VDD+0.3
V
V
V
–0.3 to VDD+0.3
–0.3 to VDD+0.3
300
1100
–20 to 85
–40 to 125
V
V
mW
°C
°C
4518 Group
RECOMMENDED OPERATING CONDITIONS 1
(Mask ROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
(One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted)
Symbol
VDD
Parameter
Supply voltage
(when ceramic resonator/
Conditions
Max.
5.5
4.0
2.7
f(STCK) ≤ 2.2 MHz
2.0
5.5
f(STCK) ≤ 1.1 MHz
1.8
5.5
One Time PROM version f(STCK) ≤ 6 MHz
f(STCK) ≤ 4.4 MHz
f(STCK) ≤ 2.2 MHz
4.0
5.5
2.7
5.5
5.5
f(STCK) ≤ 4.4 MHz
Supply voltage
Typ.
f(STCK) ≤ 4.4 MHz
Mask ROM version
on-chip oscillator is used)
VDD
f(STCK) ≤ 6 MHz
Limits
Min.
Unit
V
5.5
2.5
2.7
5.5
V
2.0
5.5
V
2.5
5.5
(when RC oscillation is used)
VDD
VRAM
f(XIN) ≤ 50 kHz
Supply voltage
Mask ROM version
(when quartz-crystal oscillator is used)
One Time PROM version f(XIN) ≤ 50 kHz
at RAM back-up mode
Mask ROM version
One Time PROM version at RAM back-up mode
RAM back-up voltage
Supply voltage
VIH
“H” level input voltage
P0, P1, P2, P3, P6, D0–D7, VDCE, XIN
VIH
“H” level input voltage
VIH
“H” level input voltage
VIL
VIL
IOH(peak)
2.0
V
0
VSS
VIL
V
1.6
“L” level input voltage
“L” level input voltage
“L” level input voltage
“H” level peak output current
0.8VDD
VDD
V
RESET
0.85VDD
VDD
V
SCK, SIN, CNTR0, CNTR1, INT0, INT1
0.85VDD
VDD
V
P0, P1, P2, P3, P6, D0–D7, VDCE, XIN
0
RESET
0
0
0.2VDD
0.3VDD
V
V
SCK, SIN, CNTR0, CNTR1, INT0, INT1
VDD = 5 V
P0, P1, D0–D7
0.15VDD
V
–20
mA
CNTR0, CNTR1
VDD = 3 V
–10
VDD = 5 V
VDD = 3 V
–10
–5
mA
VDD = 5 V
24
mA
SCK, SOUT
VDD = 3 V
12
P3, RESET
VDD = 5 V
10
VDD = 3 V
4
IOH(avg)
“H” level average output current
P0, P1, D0–D7
IOL(peak)
(Note)
“L” level peak output current
CNTR0, CNTR1
P0, P1, P2, P6
IOL(peak)
“L” level peak output current
mA
IOL(peak)
“L” level peak output current
D0–D5
VDD = 5 V
VDD = 3 V
24
12
mA
IOL(peak)
“L” level peak output current
D 6 , D7
VDD = 5 V
40
mA
CNTR0, CNTR1
VDD = 3 V
30
“L” level average output current
P0, P1, P2, P6
VDD = 5 V
12
(Note)
SCK, SOUT
VDD = 3 V
6
IOL(avg)
“L” level average output current
P3, RESET
VDD = 5 V
VDD = 3 V
5
2
mA
IOL(avg)
(Note)
“L” level average output current
D0–D5
VDD = 5 V
15
mA
VDD = 3 V
7
IOL(avg)
(Note)
IOL(avg)
ΣIOH(avg)
ΣIOL(avg)
“L” level average output current
D 6 , D7
VDD = 5 V
30
(Note)
CNTR0, CNTR1
VDD = 3 V
15
“H” level total average current
D0–D7, CNTR0, CNTR1
“L” level total average current
P0, P1
P2, D0–D7, RESET, CNTR0, CNTR1
P0, P1, P3, P6
Note: The average output current is the average value during 100 ms.
Rev.3.01 2005.06.15
REJ03B0008-0301
page 147 of 157
mA
mA
–60
–60
mA
80
mA
80
4518 Group
RECOMMENDED OPERATING CONDITIONS 2
(Mask ROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
(One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted)
Symbol
f(XIN)
Parameter
Conditions
Oscillation frequency
Mask ROM
(with a ceramic resonator)
version
Through mode
Limits
Typ.
Min.
VDD = 4.0 to 5.5 V
6.0
VDD = 2.7 to 5.5 V
VDD = 2.0 to 5.5 V
4.4
2.2
VDD = 1.8 to 5.5 V
1.1
Frequency/2 mode VDD = 2.7 to 5.5 V
6.0
VDD = 2.0 to 5.5 V
VDD = 1.8 to 5.5 V
4.4
Frequency/4, 8 mode VDD = 2.0 to 5.5 V
VDD = 1.8 to 5.5 V
6.0
4.4
VDD = 4.0 to 5.5 V
6.0
VDD = 2.7 to 5.5 V
4.4
VDD = 2.5 to 5.5 V
Frequency/2 mode VDD = 2.7 to 5.5 V
2.2
VDD = 2.5 to 5.5 V
4.4
6.0
One Time PROM Through mode
version
Oscillation frequency
Unit
MHz
2.2
6.0
Frequency/4, 8 mode VDD = 2.5 to 5.5 V
f(XIN)
Max.
4.4
MHz
VDD = 4.0 to 5.5 V
VDD = 2.7 to 5.5 V
4.8
MHz
VDD = 2.0 to 5.5 V
VDD = 1.8 to 5.5 V
1.6
0.8
Frequency/2 mode VDD = 2.7 to 5.5 V
4.8
VDD = 2.0 to 5.5 V
3.2
VDD = 1.8 to 5.5 V
Frequency/4, 8 mode VDD = 2.0 to 5.5 V
1.6
VDD = 2.7 to 5.5 V
(at RC oscillation) (Note)
f(XIN)
Oscillation frequency
(with a ceramic resonator selected,
Through mode
Mask ROM
version
external clock input)
3.2
VDD = 1.8 to 5.5 V
4.8
3.2
VDD = 4.0 to 5.5 V
4.8
VDD = 2.7 to 5.5 V
3.2
VDD = 2.5 to 5.5 V
1.6
Frequency/2 mode VDD = 2.7 to 5.5 V
VDD = 2.5 to 5.5 V
4.8
One Time PROM Through mode
version
3.2
4.8
Frequency/4, 8 mode VDD = 2.5 to 5.5 V
Note: The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits.
<System clock (STCK) operating condition map>
When ceramic resonance is used
When RC oscillation is used
When external clock is used
f(STCK)
[MHz]
f(STCK)
[MHz]
f(STCK)
[MHz]
6
4.8
4.4
4.4
3.2
Recommended
operating operation
2.2
Recommended
operating operation
Recommended
operating operation
1.6
1.1
0.8
1.8 2 2.7
(2.5)
4
5.5
VDD[V]
( ): One Time PROM version
Rev.3.01 2005.06.15
REJ03B0008-0301
page 148 of 157
2.7
5.5
VDD[V]
1.8 2 2.7
(2.5)
4
5.5
VDD
4518 Group
RECOMMENDED OPERATING CONDITIONS 3
(Mask ROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
(One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted)
Symbol
f(XIN)
Parameter
Conditions
Min.
Limits
Typ.
Oscillation frequency
Mask ROM version
VDD = 2.0 to 5.5 V
Max.
50
(with a quartz-crystal oscillator)
One Time PROM version
VDD = 2.5 to 5.5 V
50
f(CNTR) Timer external input frequency
CNTR0, CNTR1
tw(CNTR) Timer external input period
CNTR0, CNTR1
3/f(STCK)
SCK
SCK
3/f(STCK)
f(SCK)
(“H” and “L” pulse width)
Serial I/O external input frequency
tw(SCK)
Serial I/O external input frequency
Unit
kHz
f(STCK)/6 Hz
s
f(STCK)/6 Hz
s
(“H” and “L“ pulse width)
TPON
Power-on reset circuit
Mask ROM version
VDD = 0 → 1.8 V
100
valid supply voltage rising time
One Time PROM version
VDD = 0 → 2.5 V
100
Rev.3.01 2005.06.15
REJ03B0008-0301
page 149 of 157
µs
4518 Group
ELECTRICAL CHARACTERISTICS 1
(Mask ROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
(One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted)
Symbol
VOH
Parameter
“H” level output voltage
Test conditions
“L” level output voltage
VOL
4.1
VDD = 3 V
IOH = –5 mA
IOH = –1 mA
2.1
VDD = 5 V
IOL = 12 mA
2
IOL = 4 mA
0.9
IOL = 6 mA
0.9
IOL = 2 mA
0.6
VDD = 5 V
IOL = 5 mA
IOL = 1 mA
2
0.9
VDD = 3 V
VDD = 5 V
IOL = 2 mA
0.9
VDD = 3 V
“L” level output voltage
P3, RESET
VOL
“L” level output voltage
“L” level output voltage
D6, D7, CNTR0, CNTR1
IIH
2.4
2
IOL = 5 mA
0.9
VDD = 3 V
IOL = 9 mA
1.4
VDD = 5 V
IOL = 3 mA
IOL = 30 mA
0.9
2
IOL = 10 mA
0.9
VDD = 3 V
“H” level input current
VI = VDD
P0, P1, P2, P3, P6,
D0–D7, VDCE, RESET,
Port P6 selected
Unit
V
IOL = 15 mA
D0–D5
VOL
Max.
IOH = –10 mA
P0, P1, P2, P6
SCK, SOUT
Typ.
IOH = –3 mA
VDD = 5 V
P0, P1, D0–D7, CNTR0, CNTR1
VOL
Limits
Min.
3
IOL = 15 mA
2
IOL = 5 mA
0.9
V
V
V
V
2
µA
–2
µA
125
kΩ
SCK, SIN, CNTR0, CNTR1,
INT0, INT1
IIL
“L” level input current
VI = 0 V
P0, P1, P2, P3, P6,
P0, P1 No pull-up
D0–D7, VDCE,
SCK, SIN, CNTR0, CNTR1,
Port P6 selected
INT0, INT1
RPU
Pull-up resistor value
P0, P1, RESET
VT+ – VT– Hysteresis
SCK, SIN, CNTR0, CNTR1, INT0, INT1
VT+ – VT– Hysteresis RESET
f(RING)
On-chip oscillator clock frequency
VI = 0 V
30
VDD = 3 V
50
60
120
VDD = 5 V
0.2
VDD = 3 V
0.2
250
V
VDD = 5 V
1
VDD = 3 V
VDD = 5 V
0.4
200
100
500
250
700
VDD = 3 V
30
120
200
Mask ROM version
∆f(XIN)
VDD = 5 V
VDD = 1.8 V
V
kHz
400
Frequency error
(with RC oscillation,
VDD = 5 V ± 10 %, Ta = 25 °C
±17
%
error of external R, C not included )
VDD = 3 V ± 10 %, Ta = 25 °C
±17
%
(Note)
Note: When RC oscillation is used, use the external 30 or 33 pF capacitor (C).
Rev.3.01 2005.06.15
REJ03B0008-0301
page 150 of 157
4518 Group
ELECTRICAL CHARACTERISTICS 2
(Mask ROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
(One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted)
Symbol
IDD
Parameter
Test conditions
Max.
f(STCK) = f(XIN)/8
Typ.
1.4
(with a ceramic resonator, f(XIN) = 6 MHz
f(STCK) = f(XIN)/4
1.6
3.2
on-chip oscillator stop)
f(STCK) = f(XIN)/2
2.0
f(STCK) = f(XIN)
2.8
1.1
4.0
5.6
Supply current at active mode
VDD = 5 V
VDD = 5 V
f(XIN) = 4 MHz
f(STCK) = f(XIN)/8
2.8
2.2
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
1.2
2.4
1.5
3.0
f(STCK) = f(XIN)
2.0
4.0
VDD = 3 V
f(STCK) = f(XIN)/8
0.4
f(XIN) = 4 MHz
f(STCK) = f(XIN)/4
0.5
0.6
0.8
1.0
f(STCK) = f(XIN)/2
1.6
55
110
at active mode
VDD = 5 V
(with a quartz-crystal
f(XIN) = 32 kHz
f(STCK) = f(XIN)/4
60
120
f(STCK) = f(XIN)/2
65
f(STCK) = f(XIN)
70
12
130
140
VDD = 3 V
f(XIN) = 32 kHz
f(STCK) = f(XIN)/8
24
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
13
26
14
28
f(STCK) = f(XIN)
15
30
VDD = 5 V
at active mode
(with an on-chip oscillator,
f(STCK) = f(RING)/8
50
f(STCK) = f(RING)/4
f(XIN) stop)
f(STCK) = f(RING)/2
f(STCK) = f(RING)
70
100
100
140
VDD = 3 V
at RAM back-up mode
(POF instruction execution)
Ta = 25 °C
VDD = 5 V
VDD = 3 V
page 151 of 157
Unit
mA
mA
mA
1.2
0.8
f(STCK) = f(XIN)
f(STCK) = f(XIN)/8
oscillator,
on-chip oscillator stop)
Rev.3.01 2005.06.15
REJ03B0008-0301
Limits
Min.
µA
µA
µA
200
150
300
f(STCK) = f(RING)/8
10
20
f(STCK) = f(RING)/4
15
30
f(STCK) = f(RING)/2
20
f(STCK) = f(RING)
35
0.1
40
70
3
10
6
µA
µA
4518 Group
A/D CONVERTER RECOMMENDED OPERATING CONDITIONS
(Comparator mode included, Ta = –20 °C to 85 °C, unless otherwise noted)
Symbol
VDD
Parameter
Conditions
Supply voltage
Min.
Mask ROM version
One Time PROM version
VIA
f(ADCK)
Limits
Typ.
Max.
2.0
3.0
5.5
5.5
Unit
V
0
VDD
V
VDD = 4.0 to 5.5 V
0.8
334
kHz
frequency
VDD = 2.7 to 5.5 V
0.8
245
(Note)
VDD = 2.2 to 5.5 V
0.8
3.9
VDD = 2.0 to 5.5 V
VDD = 4.0 to 5.5 V
0.8
0.8
1.8
334
VDD = 3.0 to 5.5 V
0.8
123
Analog input voltage
A/D conversion clock
Mask ROM version
One Time PROM version
Note: Definition of A/D conversion clock (ADCK)
On-chip oscillator clock (RING)
MR3, MR2
11
Division circuit
Divided by 8
On-chip oscillator
Divided by 2
1
Ceramic resonance
RC oscillation
Multiplexer
Quartz-crystal
oscillation
(CMCK,
CRCK,
CYCK)
Instruction clock (INSTCK)
On-chip oscillator clock(RING)
Division circuit
Q31, Q30
Divided by 48
11
Q32
Divided by 24
10
0
Divided by 12
Divided by 6
1
f(ADCK)
[kHz]
334
245
(123)
Recommended
operating operation
3.9
1.8
0.8
4
5.5
page 152 of 157
00
Internal clock
generating circuit
(divided by 3)
Instruction clock
(INSTCK)
0
<Operating condition map of A/D conversion clock (ADCK) >
Rev.3.01 2005.06.15
REJ03B0008-0301
01
MR0
XIN
2 2.2 2.7
(3.0)
( ): One Time PROM version
10
Divided by 4
System clock (STCK)
VDD[V]
01
00
A/D conversion clock (ADCK)
4518 Group
A/D CONVERTER CHARACTERISTICS
(Ta = –20 °C to 85 °C, unless otherwise noted)
Symbol
Test conditions
Parameter
–
Resolution
–
Linearity error
–
V0T
Differential non-linearity error 2.2 (3.0) V ≤ VDD ≤ 5.5 V ((): One Time PROM version)
VDD = 5.12 V
Mask ROM version
Zero transition voltage
VDD = 3.072 V
VDD = 2.56 V
One Time PROM version
Full-scale transition voltage
Mask ROM version
One Time PROM version
–
Limits
Typ.
2.7(3.0) V ≤ VDD ≤ 5.5 V ((): One Time PROM version)
Mask ROM version
VFST
Min.
Absolute accuracy
(Quantization error excluded)
IADD
A/D operating current
TCONV
(Note 1)
A/D conversion time
2.2 V ≤ VDD < 2.7 V
0
10
0
7.5
0
Max.
10
±2
±4
±0.9
20
15
15
30
VDD = 5.12 V
0
7.5
15
VDD = 3.072 V
3
5105
13
23
VDD = 5.12 V
5115
VDD = 3.072 V
3064.5
3072
VDD = 2.56 V
VDD = 5.12 V
2552.5
2560
5100
VDD = 3.072 V
3065
5115
3075
5125
3079.5
2567.5
5130
Mask ROM version
2.0 V ≤ VDD < 2.2 V
VDD = 5 V
150
VDD = 3 V
75
f(XIN) = 6 MHz
Unit
bits
LSB
LSB
mV
mV
3085
±8
LSB
450
225
31
µA
8
±20
±15
±15
±30
±23
4
bits
mV
µs
f(STCK) = f(XIN) (XIN through mode)
ADCK=INSTCK/6
–
–
Comparator resolution
Comparator error (Note 2)
Mask ROM version
VDD = 5.12 V
VDD = 3.072 V
VDD = 2.56 V
One Time PROM version
VDD = 5.12 V
VDD = 3.072 V
–
Comparator comparison time f(XIN) = 6 MHz
f(STCK) = f(XIN) (XIN through mode)
µs
ADCK=INSTCK/6
Notes 1: When the A/D converter is used, IADD is added to IDD (supply current).
2: As for the error from the ideal value in the comparator mode, when the contents of the comparator register is n, the logic value of the comparison
voltage Vref which is generated by the built-in DA converter can be obtained by the following formula.
Logic value of comparison voltage Vref
Vref =
VDD
256
✕n
n = Value of register AD (n = 0 to 255)
Rev.3.01 2005.06.15
REJ03B0008-0301
page 153 of 157
4518 Group
VOLTAGE DROP DETECTION CIRCUIT CHARACTERISTICS
(Ta = –20 °C to 85 °C, unless otherwise noted)
Symbol
VRST–
Test conditions
Parameter
VRST+–
Limits
Typ.
Max.
3.5
3.7
Detection voltage
Ta = 25 °C
3.3
(reset occurs) (Note 1)
Mask ROM version
2.7
2.6
One Time PROM version
VRST+
Min.
Detection voltage
(reset release) (Note 2)
Ta = 25 °C
Mask ROM version
3.5
One Time PROM version
2.8
V
4.2
4.2
3.7
2.9
Detection voltage hysteresis
Unit
3.9
V
4.4
4.4
0.2
V
VRST–
IRST
TRST
Operation current (Note 3)
VDD = 5 V
50
100
30
60
Detection time
VDD = 3 V
VDD → (VRST– – 0.1 V) (Note 4)
0.2
1.2
Notes 1: The detected voltage (V RST–) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling.
2: The detected voltage (V RST+) is defined as the voltage when reset is released when the supply voltage (VDD) is rising from reset occurs.
3: When the voltage drop detection circuit is used (VDCE pin = “H”), IRST is added to IDD (power current).
4: The detection time (TRST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST– – 0.1 V].
BASIC TIMING DIAGRAM
Machine cycle
Parameter
Pin (signal) name
System clock
STCK
Port D output
D0–D7
Port D input
D0–D7
Ports P0, P1, P2, P3, P00–P03
P10–P13
P6 output
P20–P23
P30, P31
P60–P63
Ports P0, P1, P2, P3, P00–P03
P10–P13
P6 input
P20–P23
P30, P31
P60–P63
Interrupt input
Rev.3.01 2005.06.15
REJ03B0008-0301
INT0, INT1
page 154 of 157
Mi
Mi+1
µA
ms
4518 Group
BUILT-IN PROM VERSION
Table 23 shows the product of built-in PROM version. Figure 75
shows the pin configurations of built-in PROM versions.
The One Time PROM version has pin-compatibility with the mask
ROM version.
In addition to the mask ROM versions, the 4518 Group has the
One Time PROM versions whose PROMs can only be written to
and not be erased.
The built-in PROM version has functions similar to those of the
mask ROM versions, but it has PROM mode that enables writing to
built-in PROM.
Table 23 Product of built-in PROM version
PROM size
Part number
(✕ 10 bits)
M34518E8FP
8192 words
M34518E8SP
8192 words
RAM size
(✕ 4 bits)
384 words
384 words
Package
ROM type
PLQP0032GB-A
PRDP0032BA-A
One Time PROM [shipped in blank]
One Time PROM [shipped in blank]
PIN CONFIGURATION (TOP VIEW)
1
32
P13
D1
2
31
P12
D2
3
30
P11
D3
4
29
P10
D4
5
28
P03
D5
6
27
P02
D6/CNTR0
7
26
P01
D7/CNTR1
8
25
P00
24
P63/AIN3
23
P62/AIN2
P60/AIN0
CNVSS
13
20
P31/INT1
XOUT
14
19
P30/INT0
XIN
15
18
VDCE
VSS
16
17
VDD
P31/INT1
21
P60/AIN0
12
P61/AIN1
P61/AIN1
RESET
P62/AIN2
22
P63/AIN3
P22/SIN
11
P00
10
P01
P21/SOUT
P02
P20/SCK
9
24
23
22
21
20
19
18
17
P03
25
16
P30/INT0
P10
26
15
VDCE
P11
27
14
VDD
P12
28
13
VSS
P13
29
12
XIN
D0
30
11
XOUT
D1
31
10
CNVSS
D2
32
9
RESET
Fig. 75 Pin configuration of built-in PROM version
Rev.3.01 2005.06.15
REJ03B0008-0301
M34518E8SP
D0
page 155 of 157
1
2
3
4
5
6
7
8
D3
D4
D5
D6/CNTR0
D7/CNTR1
P20/SCK
P21/SOUT
P22/SIN
M34518E8FP
4518 Group
(1) PROM mode
The built-in PROM version has a PROM mode in addition to a normal operation mode. The PROM mode is used to write to and read
from the built-in PROM.
In the PROM mode, the programming adapter can be used with a
general-purpose PROM programmer to write to or read from the
built-in PROM as if it were M5M27C256K.
Programming adapter is listed in Table 24. Contact addresses at
the end of this data sheet for the appropriate PROM programmer.
• Writing and reading of built-in PROM
Programming voltage is 12.5 V. Write the program in the PROM of
the built-in PROM version as shown in Figure 76.
(2) Notes on handling
➀A high-voltage is used for writing. Take care that overvoltage is
not applied. Take care especially at turning on the power.
➁For the One Time PROM version shipped in blank, Renesas
Technology Corp. does not perform PROM writing test and
screening in the assembly process and following processes. In
order to improve reliability after writing, performing writing and
test according to the flow shown in Figure 77 before using is recommended (Products shipped in blank: PROM contents is not
written in factory when shipped).
(3) E l e c t r i c C h a r a c t e r i s t i c D i f f e r e n c e s
Between Mask ROM and One TIme PROM
Version MCU
There are differences in electric characteristics, operation margin,
noise immunity, and noise radiation between Mask ROM and One
Time PROM version MCUs due to the difference in the manufacturing processes.
When manufacturing an application system with the One Time
PROM version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial
samples of the Mask ROM version.
Table 24 Programming adapter
Microcomputer
Name of Programming Adapter
M34518E8FP
PCA7442FP
M34518E8SP
PCA7442SP
Address
000016
1
1
1
D4 D3
D2
D1
D0
Low-order 5 bits
1FFF16
3FFF16
400016
1
1
1
D4 D3
D2
D1
D0
High-order 5 bits
5FFF16
7FFF16
Fig. 76 PROM memory map
Writing with PROM programmer
Screening (Leave at 150 °C for 40 hours) (Note)
Verify test with PROM programmer
Function test in target device
Note: Since the screening temperature is higher
than storage temperature, never expose the
microcomputer to 150 °C exceeding 100
hours.
Fig. 77 Flow of writing and test of the product shipped in blank
Rev.3.01 2005.06.15
REJ03B0008-0301
page 156 of 157
4518 Group
JEITA Package Code
RENESAS Code
Previous Code
MASS[Typ.]
P-SDIP32-8.9x28-1.78
PRDP0032BA-A
32P4B
2.2g
17
1
16
*1
E
32
e1
PACKAGE OUTLINE
*2
c
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
Reference
Symbol
L
A1
A
A2
D
Dimension in Millimeters
Min
Nom
Max
e1
9.86
10.16
10.46
D
27.8
28.0
28.2
E
8.75
8.9
*3 b
3
e
SEATING PLANE
*3
bp
A1
b2
0.51
3.8
A2
bp
0.35
0.45
0.55
b2
0.63
0.73
1.03
b3
0.9
1.0
1.3
c
0.22
0.27
0.34
e
1.528
1.778
2.028
L
3.0
0°
JEITA Package Code
RENESAS Code
Previous Code
MASS[Typ.]
P-LQFP32-7x7-0.80
PLQP0032GB-A
32P6U-A
0.2g
9.05
5.08
A
15°
HD
*1
D
24
17
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
16
25
bp
c
c1
HE
*2
E
b1
Reference
Symbol
32
9
1
ZE
Terminal cross section
Nom
D
6.9
7.0
7.1
E
6.9
7.0
7.1
A2
8
ZD
Dimension in Millimeters
Min
1.4
HD
8.8
9.0
9.2
HE
8.8
9.0
9.2
A1
0
0.1
0.2
bp
0.32
0.37
0.42
0.09
0.145
A
c
A
F
A2
Index mark
A1
1.7
0.35
b1
c
L
0°
e
e
*3
Detail F
bp
x
page 157 of 157
0.20
x
y
0.10
0.7
ZE
0.7
L
Rev.3.01 2005.06.15
REJ03B0008-0301
8°
0.8
ZD
L1
0.20
0.125
c1
L1
y
Max
0.3
0.5
1.0
0.7
4518 Group Data Sheet
REVISION HISTORY
Rev.
Date
1.00 Jan. 14, 2003
2.00 Apr. 15, 2003
Description
Summary
Page
–
First edition issued
Some values of the following table are revised.
145
RECOMMENDED OPERATING CONDITIONS 1;
• Supply voltage (when quartz-crystal oscillator is used)
• RAM back voltage
147
RECOMMENDED OPERATING CONDITIONS 3;
• Oscillation frequency (with a quartz-crystal oscillator)
150
A/D CONVERTER RECOMMENDED OPERATING CONDITIONS;
• Supply voltage
• A/D conversion clock frequency
151
A/D CONVERTER CHARACTERISTCS;
• Linearity error
• Differential non-linearity error
• Zero transition voltage
• Full-scale transition voltage
• Comparator error
152
VOLTAGE DROP DETECTION CIRCUIT;
• Detection voltage (reset occurs)
•Detection voltage (reset release)
3.00 Jul. 27, 2004 All pages Words standardized: On-chip oscillator, A/D converter
4
PERFORMANCE OVERVIEW: Power dissipation revised.
5
PIN DESCRIPTION: Description of RESET pin revised.
15
Port block diagram (7): Period measurement circuit added.
25
Fig.17: Period measurement circuit added.
28
Fig.20 revised.
29
Fig.23 revised.
33
Fig.26: Note added.
34
Table 10 W13: (Note 2) added, W33: (Note 2) → (Note 3).
39
(12): Some description added.
40
(14): Some description added.
44
Some description added.
45
Fig.33: “DI” instruction added.
46
Table 11: Relative accuracy revised.
Fig.46: SRST instruction added.
57
11 Timer 4: Some description added.
70
Fig.64 revised.
72
Fig.67 revised.
73
Note on Power Source Voltage added.
75
I13, I12: (Note 2) added.
76
W13: (Note 2) added, and Note 2 added.
77
SNZ0, SNZ1 revised.
85
Fig.73 revised.
154
3.01 Jun.15, 2005 All pages
1
2
4
41
Delete the following: “PRELIMINARY”.
Package name revised.
Pin configuration: Package name revised.
PERFORMANCE OVERVIEW: Package name revised.
•Prescaler, Timer 1, Timer 2 and Timer 3 count start timing and count time when
operation starts, •Timer 4 count start timing and count time when operation starts
added.
(1/2)
4518 Group Data Sheet
REVISION HISTORY
Rev.
Date
Description
Summary
Page
3.01 Jun.15, 2005
72
146
155
157
Prescaler, Timer 1, Timer 2 and Timer 3 count start timing and count time
when operation starts, 14 Timer 4 count start timing and count time when operation starts added.
ABSOLUTE MAXIMUM RATINGS: Package name revised.
BUILT-IN PROM VERSION: Package name revised.
PACKAGE OUTLINE revised.
13
(2/2)
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
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4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
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5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
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7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
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Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> 2-796-3115, Fax: <82> 2-796-2145
Renesas Technology Malaysia Sdn. Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
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