RENESAS M3455AGC

455A Group
REJ03B0224-0101
Rev.1.01
Feb 15, 2008
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 455A Group is a 4-bit single-chip microcomputer designed
with CMOS technology. Its CPU is that of the 4500 Series using
a simple, high-speed instruction set. The computer is equipped
with two 8-bit timers (each timer has one or two reload registers),
a 16-bit timer for clock count, interrupts, and oscillation circuit
switch function.
The various microcomputers in the 455A Group include
variations of type as shown in the table below.
FEATURES
• Minimum instruction execution time..............................0.5 µs
(at 6 MHz oscillation frequency, in high-speed through-mode)
• Supply voltage .......................................................1.8 to 5.5 V
(It depends on operation source clock, oscillation frequency
and operation mode)
• Timers
Timer 1..............................................................8-bit timer with
a reload register and carrier wave output auto-control function
Timer 2............................. 8-bit timer with two reload registers
and carrier wave generation circuit
Timer 3........................ 16-bit timer (fixed dividing frequency)
Table 1
•
•
•
•
•
Interrupt ..................................................................... 4 sources
Key-on wakeup function pins .............................................. 24
I/O ports ............................................................................... 24
Output ports ........................................................................... 1
LCD control circuit
Segment output ..................................................................... 32
Common output ...................................................................... 4
• Voltage drop detection circuit
Reset occurrence..................................Typ. 1.7 V (Ta = 25 °C)
Reset release ........................................Typ. 1.8 V (Ta = 25 °C)
Skip occurrence ...................................Typ. 2.0 V (Ta = 25 °C)
• Power-on reset circuit
• Watchdog timer
• Clock generating circuit
Built-in clock (high-speed/low-speed on-chip oscillator)
Main clock (ceramic resonator)
Sub-clock (quartz-crystal oscillation)
• LED drive directly enabled (port D)
APPLICATION
Remote control transmitter
Support Product
Part number
M3455AG8FP (Note 1)
M3455AG8-XXXFP
M3455AGCFP (Note 1)
M3455AGC-XXXFP
Note1.Shipped in blank
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
ROM size (× 10 bits)
RAM size (× 4 bits)
Package
ROM type
512 words
PLQP0052JA-A
QzROM
8192 words
12288 words
Page 1 of 146
455A Group
PIN CONFIGURATION
P0 1/SEG 17
P0 0/SEG 16
SEG 15
SEG 14
SEG 13
SEG 12
SEG 11
SEG 10
SEG 9
SEG 8
36
34
33
32
31
30
29
28
27
P0 2/SEG 18
37
35
P1 0/SEG 20
P0 3/SEG 19
38
40
26
41
25
42
24
23
43
M3455AG8FP
44
45
46
47
48
22
M3455AG8-XXXFP
21
M3455AGCFP
19
20
18
M3455AGC-XXXFP
49
17
7
8
9
10
11
12
RESET
X OUT
Vss
X IN
V DD
C/CNTR
13
6
X CIN /D 6
5
D 5 /INT
CNVss
X COUT /D 7
4
3
14
D4
15
52
2
51
D3
16
1
50
D2
P11/SEG21
P12/SEG22
P13/SEG23
P20/SEG24
P21/SEG25
P22/SEG26
P23/SEG27
P30/SEG28
P31/SEG29
P32/SEG30
P33/SEG31
D0
D1
39
Pin configuration (top view)
OUTLINE PLQP0052JA-A (52P6A-A)
Fig 1.
Pin configuration (PLQP0052JA-A type)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 2 of 146
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2/VLC1
SEG1/VLC2
SEG0/VLC3
COM3
COM2
COM1
COM0
VDCE
Fig 2.
Port P0
Port P1
4
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Functional block diagram
Page 3 of 146
32
Segment output
4
Port P2
Register A (4 bits) Register B (4 bits)
Register D (3 bits) Register E (8 bits)
Stack register SK (8 levels)
Interrupt stack register SDP (1 level)
ALU (4 bits)
4500 Series
CPU core
Power-on reset circuit
4
Common output
LCD drive control circuit
(Max.32 segments × 4 common)
Watchdog timer (16 bits)
Timer LC (4 bits for LCD)
Timer 3 (16 bits)
Timer 2 (8 bits)
Timer 1 (8 bits)
Timer
Internal peripheral functions
I/O port
4
Port D
8
1
Port C
(including LCD display
RAM 32 words × 4 bits)
512 words × 4 bits
RAM
8192/12288 words × 10
bits
ROM
Memory
Voltage drop detection circuit
X CIN -X COUT (Quartz-crystal)
High-speed/low-speed on-chip oscillator
X IN -X OUT (Ceramic)
System clock generating circuit
Port P3
4
455A Group
FUNCTIONAL BLOCK DIAGRAM
455A Group
PERFORMANCE OVERVIEW
Table 2
Performance overview
Parameter
Function
Number of basic instructions
138
Minimum instruction execution time
Memory sizes
ROM
8192 words × 10 bits
M3455AGC
12288 words × 10 bits
512 words × 4 bits (including LCD display RAM 32 words × 4 bits)
RAM
I/O port
Timer
D0−D5
I/O
(Input is
examined by
skip decision.)
Six independent I/O ports. A pull-up function, a key-on wakeup function and output
structure can be switched by software.
Port D5 is also used as INT pin.
D6, D7
I/O
(Input is
examined by
skip decision.)
Two independent I/O ports; each pin is equipped with a pull-up function and a key-on
wakeup function. Both functions can be switched by software.
Ports D6 and D7 are also used as XCIN and XCOUT, respectively.
P00−P03
I/O
4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can
be switched by software.
Ports P00−P03 are also used as SEG16−SEG19, respectively.
P10−P13
I/O
4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can
be switched by software.
Ports P10−P13 are also used as SEG20−SEG23, respectively.
P20−P23
I/O
4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can
be switched by software.
Ports P20−P23 are also used as SEG24−SEG27, respectively.
P30−P33
I/O
4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can
be switched by software.
Ports P30−P33 are also used as SEG28−SEG31, respectively.
C
Output
1-bit output; Port C is also used as CNTR pin.
Timer 1
8-bit timer with a reload register and carrier wave output auto-control function, and
has an event counter.
Timer 2
8-bit timer with two reload registers and carrier wave generation function.
Timer 3
16-bit timer, fixed dividing frequency (timer for clock count)
Timer LC
4-bit programmable timer with a reload register (for LCD clock generating)
Watchdog timer
LCD control circuit
Voltage drop
detection circuit
0.5 µs (Oscillation frequency 6 MHz: high-speed through mode)
M3455AG8
16-bit timer, fixed dividing frequency (timer for monitor)
Selective bias value
1/2, 1/3 bias
Selective duty value
2, 3, 4 duty
Common output
4
Segment output
32
Internal resistor for power
supply
2r × 3, 2r × 2, r × 3, r × 2 (r = 100 kΩ, (Ta = 25 °C, Typical value))
Reset occurrence
Typ. 1.7 V (Ta=25 °C)
Reset release
Typ. 1.8 V (Ta=25 °C)
Skip occurrence
Typ. 2.0 V (Ta=25 °C)
Power-on reset circuit
Built-in
Interrupt
4 sources (one for external, three for timers)
Source
Nesting
1 level
Subroutine nesting
8 levels
Device structure
CMOS silicon gate
Package
52-pin plastic molded LQFP (PLQP0052JA-A)
Operating temperature range
-20 to 85 °C
Power source voltage
1.8 to 5.5 V (It depends on operation source clock, oscillation frequency and
operation mode)
At active mode
Power
dissipation
(Typ. value) At clock operating mode
0.3 mA (Ta = 25 °C, VDD = 3.0 V, f(XIN) = 4 MHz, f(XCIN) = stop, f(HSOCO) = stop,
f(LSOCO)=stop, f(STCK) = f(XIN/8)
At RAM back-up
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
5 µA (Ta = 25 °C, VDD = 3.0 V, f(XCIN) = 32 kHz)
0.1 µA (Ta = 25 °C, output transistor is cut-off state)
Page 4 of 146
455A Group
PIN DESCRIPTION
Table 3
Pin description
Pin
Name
Input/Output
−
Function
VDD
Power source
Connected to a plus power supply.
VSS
Power source
−
Connected to a 0 V power supply.
CNVSS
CNVSS
−
Connect this pin to VSS and always apply “L”(0 V) to it.
VDCE
Voltage drop detection
circuit enable
Input
This pin is used to operate/stop the voltage drop detection circuit.
When “H“ level is input to this pin, the circuit starts operating.
When “L“ level is input to this pin, the circuit stops operating.
Input
I/O pins of the main clock generating circuit. When using a ceramic resonator,
connect it between pins XIN and XOUT. A feedback resistor is built-in between them.
XIN
Main clock input
XOUT
Main clock output
XCIN
Sub clock input
XCOUT
Sub clock output
RESET
Reset I/O
I/O
An N-channel open-drain I/O pin for a system reset. When the SRST instruction,
watchdog timer, the built-in power-on reset or the voltage drop detection circuit
causes the system to be reset, the RESET pin outputs “L” level.
D0−D5
I/O port D
(Input is examined by
skip decision.)
I/O
Each pin of port D has an independent 1-bit wide I/O function. The output structure
can be switched to N-channel open-drain or CMOS by software. For input use, set
the latch of the specified bit to “1” and select the N-channel open-drain. Port D0 to
D5 has a key-on wakeup function and a pull-up function. Both functions can be
switched by software.
Port D5 is also used as INT pin.
D6, D7
I/O port D
(Input is examined by
skip decision.)
I/O
Each pin of port D has an independent 1-bit wide I/O function. The output structure
is N-channel open-drain. Port D6, D7 has a key-on wakeup function and a pull-up
function. Both functions can be switched by software.
Ports D6 and D7 are also used as XCIN pin and XCOUT pin, respectively.
P00−P03 I/O port P0
I/O
Port P0 serves as a 4-bit I/O port. The output structure can be switched to Nchannel open-drain or CMOS by software. For input use, set the latch of the
specified bit to “1” and select the N-channel open-drain. Port P0 has a key-on
wakeup function and a pull-up function. Both functions can be switched by software.
Ports P00-P03 are also used as SEG16-SEG19, respectively.
P10−P13 I/O port P1
I/O
Port P1 serves as a 4-bit I/O port. The output structure can be switched to Nchannel open-drain or CMOS by software. For input use, set the latch of the
specified bit to “1” and select the N-channel open-drain. Port P1 has a key-on
wakeup function and a pull-up function. Both functions can be switched by software.
Ports P10-P13 are also used as SEG20-SEG23, respectively.
P20−P23 I/O port P2
I/O
Port P2 serves as a 4-bit I/O port. The output structure can be switched to Nchannel open-drain or CMOS by software. For input use, set the latch of the
specified bit to “1” and select the N-channel open-drain. Port P2 has a key-on
wakeup function and a pull-up function. Both functions can be switched by software.
Ports P20–P23 are also used as SEG24–SEG27, respectively.
P30−P33 I/O port P3
I/O
Port P3 serves as a 4-bit I/O port. The output structure can be switched to Nchannel open-drain or CMOS by software. For input use, set the latch of the
specified bit to “1” and select the N-channel open-drain. Port P3 has a key-on
wakeup function and a pull-up function. Both functions can be switched by software.
Ports P30–P33 are also used as SEG28–SEG31, respectively.
Output
Input
Output
I/O pins of the sub-clock generating circuit. Connect a 32.768 kHz quartz-crystal
oscillator between pins XCIN and XCOUT. A feedback resistor is built-in between
them. XCIN and XCOUT pins are also used as ports D6 and D7, respectively.
C
Output port C
Output
1-bit output port. The output structure is CMOS. Port C is also used as CNTR pin.
COM0−
COM3
Common output
Output
LCD common output pins. Pins COM0 and COM1 are used at 1/2 duty, pins COM0–
COM2 are used at 1/3 duty and pins COM0–COM3 are used at 1/4 duty.
SEG0−
SEG31
Segment output
Output
LCD segment output pins. SEG 0– SEG 2 pins are used as V LC3– V LC1 pins,
respectively. SEG16-SEG31 pins are used as Ports P00-P03, Ports P10-P13, Ports
P20-P23, and Ports P30-P33, respectively.
CNTR
Timer I/O
I/O
CNTR pin has the function to input the clock for the timer 1 event counter and to
output the PWM signal generated by timer 2. CNTR pin is also used as Port C.
INT
Interrupt input
Input
INT pin accepts external interrupts. They have the key-on wakeup function which
can be switched by software. INT pin is also used as Port D5.
VLC3−
VLC1
LCD power source
−
These are the LCD power supply pins. If an internal resistor is used, connect the
VLC3 pin to the VDD pin. (If brightness adjustment is required, connect via a resistor.)
When using an external power supply, apply voltage such that VSS ≤ VLC1 ≤ VLC2 ≤
VLC3 ≤ VDD. Pins VLC3 to VLC1 also function as pins SEG0 to SEG2.
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 5 of 146
455A Group
Table 4
Pin
P00
P01
P02
P03
P10
P11
P12
P13
P20
P21
P22
P23
Pin description
Multifunction
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
Pin
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
Multifunction
P00
P01
P02
P03
P10
P11
P12
P13
P20
P21
P22
P23
Pin
P30
P31
P32
P33
D5
D6
D7
C
SEG0
SEG1
SEG2
Multifunction
SEG28
SEG29
SEG30
SEG31
INT
XCIN
XCOUT
CNTR
VLC3
VLC2
VLC1
Pin
SEG28
SEG29
SEG30
SEG31
INT
XCIN
XCOUT
CNTR
VLC3
VLC2
VLC1
Multifunction
P30
P31
P32
P33
D5
D6
D7
C
SEG0
SEG1
SEG2
Note 1. Pins except above have just single function.
Note 2. The input/output of D5 can be used even when INT is selected.
Be careful when using inputs of both INT and D5 since the input threshold value of INT pin is different from that of port D5.
Note 3. “H“ output function of port C can be used even when the CNTR (output) is used.
PORT FUNCTION
Table 5
Port
Port function
Pin
Input
Output
Output
structure
I/O unit
D0−D4,
D5/INT
I/O
(6)
N-channel
open-drain/
CMOS
D6/XCIN,
D7/XCOUT
I/O
(2)
N-channel
open-drain
Port P0
P00/SEG16,
P01/SEG17,
P02/SEG18,
P03/SEG19
I/O
(4)
N-channel
open-drain/
CMOS
4 bits
Port P1
P10/SEG20,
P11/SEG21,
P12/SEG22,
P13/SEG23
I/O
(4)
N-channel
open-drain/
CMOS
Port P2
P20/SEG24,
P21/SEG25,
P22/SEG26,
P23/SEG27,
I/O
(4)
Port P3
P30/SEG28,
P31/SEG29,
P32/SEG30,
P33/SEG31
I/O
(4)
Port C
C/CNTR
Port D
Output
(1)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
SD, RD
SZD, CLD
Control
registers
Remark
FR1, FR2,
I1, K3, PU3
Programmable pull-up, keyon wakeup and output
structure selection function
RG, K3, PU3
Programmable pull-up and
key-on wakeup function
OP0A
IAP0
PU0, K0,
FR0, C1
Programmable pull-up, keyon wakeup and output
structure selection function
4 bits
OP1A
IAP1
PU0, K0,
FR0, C2
Programmable pull-up, keyon wakeup and output
structure selection function
N-channel
open-drain/
CMOS
4 bits
OP2A
IAP2
PU1, K1,
FR3, L3
Programmable pull-up, keyon wakeup and output
structure selection function
N-channel
open-drain/
CMOS
4 bits
OP3A
IAP3
PU2, K2, K3,
FR2, C3
Programmable pull-up, keyon wakeup and output
structure selection function
CMOS
1 bit
RCP
SCP
W1, W2, W4
−
Page 6 of 146
1 bit
Control
instructions
455A Group
CONNECTIONS OF UNUSED PINS
Table 6
Port function
Pin
Connection
Usage condition
XIN
Connect to VSS.
−
XOUT
Open.
−
XCIN/D6
Connect to VSS.
Pull-up transistor is OFF.
The key-on wakeup function is invalid.
XCOUT/D7
Open.
The key-on wakeup function is invalid.
D0−D4
Open.
The key-on wakeup function is invalid.
Connect to VSS.
N-channel open-drain is selected for the output structure.
Pull-up transistor is OFF.
The key-on wakeup function is invalid.
Open.
INT pin input is disabled.
The key-on wakeup function is invalid.
Connect to VSS.
N-channel open-drain is selected for the output structure.
Pull-up transistor is OFF.
The key-on wakeup function is invalid.
D5/INT
C/CNTR
Open.
CNTR input is not selected for timer 1 count source.
P00/SEG16−
P03/SEG19
Open.
The key-on wakeup function is invalid.
Connect to VSS.
Segment output is not selected.
N-channel open-drain is selected for the output structure.
Pull-up transistor is OFF.
The key-on wakeup function is invalid.
P10/SEG20−
P13/SEG23
Open.
The key-on wakeup function is invalid.
Connect to VSS.
Segment output is not selected.
N-channel open-drain is selected for the output structure.
Pull-up transistor is OFF.
The key-on wakeup function is invalid.
P20/SEG24−
P23/SEG27
Open.
The key-on wakeup function is invalid.
Connect to VSS.
Segment output is not selected.
N-channel open-drain is selected for the output structure.
Pull-up transistor is OFF.
The key-on wakeup function is invalid.
P30/SEG28−
P33/SEG31
Open.
The key-on wakeup function is invalid.
Connect to VSS.
Segment output is not selected.
N-channel open-drain is selected for the output structure.
Pull-up transistor is OFF.
The key-on wakeup function is invalid.
COM0–COM3
Open.
−
SEG0/VLC3
Open.
SEG0 pin is selected.
SEG1/VLC2
Open.
SEG1 pin is selected.
SEG2/VLC1
Open.
SEG2 pin is selected.
SEG3–SEG15
Open.
−
(Note when connecting to VSS or VDD)
Connect the unused pins to VSS using the thickest wire at the shortest distance against noise.
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 7 of 146
455A Group
DEFINITION OF CLOCK AND CYCLE
• Operation source clock
The operation source clock is the source clock to operate this
product. In this product, the following clocks are used.
• Clock (f(XIN)) by the external ceramic resonator
• Clock (f(XIN)) by the external input
• Clock (f(HSOCO)) of the high-speed on-chip oscillator which is
the internal oscillator
• Clock (f(XCIN)) by the external quartz-crystal oscillation
• Clock (f(LSOCO)) by the low-speed on-chip oscillator
Table 7
• System clock (STCK)
The system clock is the basic clock for controlling this product.
The system clock is selected by the clock control register MR
shown as the table below.
• Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
• Instruction clock (INSTCK)
The instruction clock is the basic clock for controlling CPU. The
instruction clock (INSTCK) is a signal derived by dividing the
system clock (STCK) by 3. The one instruction clock cycle
generates the one machine cycle.
Table Selection of system clock
Register MR
System clock
Operation mode
MR3
MR2
MR1
MR0
1
1
0
0
f(STCK) = f(HSOCO)/8
Internal frequency divided by 8 mode
1
0
0
0
f(STCK) = f(HSOCO)/4
Internal frequency divided by 4 mode
0
1
0
0
f(STCK) = f(HSOCO)/2
Internal frequency divided by 2 mode
0
0
0
0
f(STCK) = f(HSOCO)
Internal frequency through mode
1
1
0
1
f(STCK) = f(XIN)/8
High-speed frequency divided by 8 mode
1
0
0
1
f(STCK) = f(XIN)/4
High-speed frequency divided by 4 mode
0
1
0
1
f(STCK) = f(XIN)/2
High-speed frequency divided by 2 mode
0
0
0
1
f(STCK) = f(XIN)
High-speed through mode
1
1
1
0
f(STCK) = f(XCIN)/8
Low-speed frequency divided by 8 mode
1
0
1
0
f(STCK) = f(XCIN)/4
Low-speed frequency divided by 4 mode
0
1
1
0
f(STCK) = f(XCIN)/2
Low-speed frequency divided by 2 mode
0
0
1
0
f(STCK) = f(XCIN)
Low-speed through mode
1
1
1
1
f(STCK) = f(LSOCO)/8
Internal Low-speed frequency divided by 8 mode
1
0
1
1
f(STCK) = f(LSOCO)/4
Internal Low-speed frequency divided by 4 mode
0
1
1
1
f(STCK) = f(LSOCO)/2
Internal Low-speed frequency divided by 2 mode
0
0
1
1
f(STCK) = f(LSOCO)
Internal Low-speed through mode
Note 1. The f(HSOCO)/8 is selected after system is released from reset
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 8 of 146
455A Group
PORT BLOCK DIAGRAM
Skip decision
Register Y
Decoder
SZD instruction
CLD （Note3） FR1i
instruction
（Note1）
D0∼D3（Note2）
S
SD instruction
（Note1）
R Q
RD instruction
（Note4）
（Note4）
K3j
Key-on wakeup
input
Edge detection
circuit
PU3j
Pull-up
transistor
Skip decision
Register Y
Decoder
SZD instruction
CLD
instruction
FR20
（Note1）
D4（Note2)
S
SD instruction
（Note1）
R Q
RD instruction
K32
Key-on wakeup
input
Edge detection
circuit
K32
Key-on wakeup
input
Edge detection
circuit
PU32
Pull-up
transistor
PU32
Pull-up
transistor
Skip decision
Register Y
Decoder
SZD instruction
CLD
instruction
FR21
（Note1）
D5/INT（Note2）
S
SD instruction
RD instruction
External 0 interrupt
Key-on wakeup input
（Note1）
R Q
External 0 interrupt circuit
（Note5）
Timer 1 count start
synchronous circuit input
Notes 1.
This symbol represents a parasitic diode on the port.
2. Applied potential to these ports must be VDD or less.
3. i represents bits 0 to 3.
4. j represents bits 0 to 1.
5. As for details, refer to the external interrupt structure.
Fig 3.
Port block diagram (1)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 9 of 146
455A Group
K33
Key-on wakeup
input
Register Y
Edge detection
circuit
PU33
Pull-up
transistor
Skip decision
Decoder
SZD instruction
CLD
instruction
(Note 1)
S
SD instruction
R Q
RD instruction
XCIN/D6 (Note 2)
RG2
1
(Note 1)
0
Sub-clock input
Quartz-crystal
oscillation circuit
PU33 Pull-up
transistor
RG2
Register Y
Decoder
Skip decision
SZD instruction
CLD
instruction
(Note 1)
S
SD instruction
R Q
RD instruction
XCOUT/D7 (Note 2)
RG2
1
(Note 1)
0
K33
Key-on wakeup
input
Edge detection
circuit
Clock input for timer 1 event count
Timer 1 underflow signal
D
W41
T
Q
R
(Note 1)
W12
C/CNTR (Note 2)
PWMOD
(Note 1)
SCP instruction
S
RCP instruction
R
Q
W10
W11
Notes 1.
This symbol represents a parasitic diode on the port.
2. Applied potential to these ports must be VDD or less.
Fig 4.
Port block diagram (2)
Rev.1.01 Feb 15, 2008
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Page 10 of 146
455A Group
LCD power supply
0
1
C1j (Note 3)
LCD control signal
(Note 1)
P00/SEG16,
P01/SEG17
(Note 2)
(Note 1)
(Note 3)
C1j
LCD power
supply
K00
Edge detection
circuit
Key-on wakeup
input
IAP0
instruction
(Note 3)
Register A
Aj
Pull-up
transistor
PU00
FR00
Aj
D
OP0A
instruction
T
Q
LCD power supply
0
1
C1k (Note 4)
LCD control signal
（Note1）
P02/SEG18,
P03/SEG19
（Note1）
（Note2）
(Note 4)
C1k
LCD power
supply
K01
Edge detection
circuit
Key-on wakeup
input
IAP0
(Note 4)
instruction
Register A
Ak
Pull-up
transistor
FR01
Ak
D
OP0A
instruction
T
Q
Notes 1.
This symbol represents a parasitic diode on the port.
2. Applied potential to these ports must be VDD or less.
3. j represents bits 0, 1.
4. k represents bits 2, 3.
Fig 5.
Port block diagram (3)
Rev.1.01 Feb 15, 2008
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Page 11 of 146
PU01
455A Group
LCD power supply
0
1
C2j (Note 3)
LCD control signal
(Note 1)
P10/SEG20,
P11/SEG21
(Note 2)
(Note 1)
(Note 3)
C2j
LCD power
supply
K02
Edge detection
circuit
Key-on wakeup
input
IAP1
（ 注3）
instruction
Register A
Aj
Pull-up
transistor
PU02
FR02
Aj
D
OP1A
T
instruction
Q
LCD power supply
0
1
C2k （Note 4）
LCD control signal
（Note 1）
P12/SEG22,
P13/SEG23
（Note 2）
（Note 1）
（Note 4）
C2k
LCD power
supply
K03
Edge detection
circuit
Key-on wakeup
input
IAP1
（Note4）
instruction
Register A
Ak
Pull-up
transistor
FR03
Ak
D
OP1A
instruction
T
Q
Notes 1.
This symbol represents a parasitic diode on the port.
2. Applied potential to these ports must be VDD or less.
3. j represents bits 0, 1.
4. k represents bits 2, 3.
Fig 6.
Port block diagram (4)
Rev.1.01 Feb 15, 2008
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PU03
455A Group
LCD power supply
0
1
L3j (Note 3)
LCD control signal
(Note 3)
L3j
(Note 3)
K1j
(Note 1)
P20/SEG24,
P21/SEG25
(Note 2)
(Note 1)
LCD power
supply
Edge detection
circuit
Key-on wakeup
input
IAP2
(Note 3)
instruction
Register A
Aj
Pull-up
transistor
(Note 3)
FR3j
PU1j
(Note 3)
Aj
D
OP2A
T
instruction
Q
LCD power supply
0
1
L3k (Note 4)
LCD control signal
(Note 1)
P22/SEG26,
P23/SEG27
(Note 1) (Note 2)
(Note 4)
L3k
(Note 4)
K1k
LCD power
supply
Edge detection
circuit
Key-on wakeup
input
IAP2
(Note 4)
instruction
Register A
Ak
(Note 4)
FR3k
Ak
Pull-up
transistor
D
OP2A T
instruction
Q
Notes 1.
This symbol represents a parasitic diode on the port.
2. Applied potential to these ports must be VDD or less.
3. j represents bits 0, 1.
4. k represents bits 2, 3.
Fig 7.
Port block diagram (5)
Rev.1.01 Feb 15, 2008
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Page 13 of 146
PU1k
(Note 4)
455A Group
LCD power supply
0
1
C3j（Note3）
LCD control signal
（Note1）
P30/SEG28,
P31/SEG29
（Note2）
（Note1）
（Note3）
C3j
LCD power
supply
K22
Edge detection
circuit
Key-on wakeup
input
（Note3）
IAP3
instruction
Register A
Aj
（Note3）
PU2j
FR22
Pull-up transistor
Aj
D
OP3A
instruction
T
Q
LCD power supply
0
1
C3k （Note4）
LCD control signal
（Note1）
P32/SEG30,
P33/SEG31
（Note1）
（Note2）
（Note4）
C3k
LCD power
supply
K23
Edge detection
circuit
Key-on wakeup
input
（Note4）
Register A
Ak
IAP3
instruction
（Note4）
FR23
PU2k
Pull-up transistor
Ak
D
OP3A
instruction
T
Q
Notes 1.
This symbol represents a parasitic diode on the port.
2. Applied potential to these ports must be VDD or less.
3. j represents bits 0, 1.
4. k represents bits 2, 3.
Fig 8.
Port block diagram (6)
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Page 14 of 146
455A Group
LCD power supply
LCD control signal
(Note 1)
SEG3 - SEG 15
LCD control signal
(Note 1)
(Note 2)
LCD power supply
LCD power supply
LCD control signal
(Note 1)
COM 0 - COM 3
LCD control signal
(Note 1)
(Note 2)
LCD power supply
LCD power supply
LCD control signal
LCD control signal
Notes 1.
This symbol represents a parasitic diode on the port.
2. Applied potential to these ports must be VDD or less.
Fig 9.
Port block diagram (7)
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REJ03B0224-0101
Page 15 of 146
455A Group
LCD power supply
0
L2 3
1
LCD control signal
(Note 1)
SEG0 /V LC3
(Note 2)
(Note 1)
L2 3
L2 3
0
LCD power supply
(VLC3)
LCD power
supply
1
LCD power supply
L1 3
1
0
0
LCD control
signal
L2 2
1
(Note 1)
SEG1 /V LC2
(Note 1)
(Note 2)
L2 2
0
1
L2 2
L2 0
0
LCD power supply
(VLC2)
LCD power
supply
1
LCD power supply
L1 3
1
0
0
1
LCD control
signal
0
1
L2 1
(Note 1)
L1 1
SEG2 /V LC1
(Note 2)
(Note 1)
L2 1
0
1
L2 1
L2 0
0
LCD power supply
(VLC1)
LCD power
supply
1
L1 3
1
0
L2 0
Reset signal
L1 2
EPOF instruction
+
POF2 instruction
Notes 1.
This symbol represents a parasitic diode on the port.
2. Applied potential to these ports must be VDD or less.
注
Fig 10. Port block diagram (8)
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Page 16 of 146
455A Group
I12
Falling
(Note 1)
D9 /INT
One-sided edge
detection circuit
I1 1
Both edges
detection circuit
1
0
0
(Note 1)
1
Rising
I1 3
Timer 1 count start
synchronization
circuit input
External 0
interrupt
EXF0
or
SNZI0 instruction
Skip decision
(Note 2)
K2 0
K21
Level detection circuit
0
Edge detection circuit
1
Key-on wakeup input
(Note 3)
Notes 1:
This symbol represents a parasitic diode on the port.
2: When I12 is 0, “L” level is detected.
When I12 is 1, “H” level is detected.
3: When I12 is 0, falling edge is detected.
When I12 is 1, rising edge is detected.
Fig 11. External interrupt circuit structure
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Page 17 of 146
455A Group
FUNCTION BLOCK OPERATIONS
CPU
<Carry>
(1) Arithmetic logic unit (ALU)
The arithmetic logic unit ALU performs 4-bit arithmetic such as
4-bit data addition, comparison, AND operation, OR operation,
and bit manipulation.
(CY)
(M(DP))
Addition
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer,
exchange, and I/O operation.
Carry flag CY is a 1-bit flag that is set to “1” when there is a
carry with the AMC instruction (Figure 12).
It is unchanged with both A n instruction and AM instruction.
The value of A 0 is stored in carry flag CY with the RAR
instruction (Figure 13).
Carry flag CY can be set to “1” with the SC instruction and
cleared to “0” with the RC instruction.
(A)
<Result>
Fig 12. AMC instruction execution example
<Set>
SC instruction
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4-bit
data, and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data
transfer with register B used as the high-order 4 bits and register
A as the low-order 4 bits (Figure 14).
Register E is undefined after system is released from reset and
returned from the power down mode. Accordingly, set the initial
value.
<Clear>
RC instruction
CY
A3 A2 A 1 A0
<Rotation>
RAR instruction
A0
CY A3 A2 A1
Fig 13. RAR instruction execution example
(4) Register D
Register D is a 3-bit register.
It is used to store a 7-bit ROM address together with register A
and is used as a pointer within the specified page when the TABP
p, BLA p, or BMLA p instruction is executed (Figure 15).
Also, when the TABP p instruction is executed at UPTF flag =
“1”, the high-order 2 bits of ROM reference data is stored to the
low-order 2 bits of register D, the high-order 1 bit of register D is
“0”.
When the TABP p instruction is executed at UPTF flag = “0”, the
contents of register D remains unchanged. The UPTF flag is set
to “1” with the SUPT instruction and cleared to “0” with the
RUPT instruction.
The initial value of UPTF flag is “0”.
Register D is undefined after system is released from reset and
returned from the power down mode. Accordingly, set the initial
value.
Register B TAB instruction Register A
B 3 B2 B1 B0
A3 A2 A 1 A 0
TEAB instruction
E7 E 6 E5 E4 E3 E 2 E 1 E0
Register E
TABE instruction
B 3 B2 B1 B0
Register B
A3 A2 A 1 A 0
TBA instruction
Fig 14. Registers A, B and register E
ROM
TABP p
instruction
Specifying address
p 6 p5
ALU
PCH
p4 p3 p2 p 1 p0
PCL
DR2 DR1 DR0 A3 A2 A1 A0
8
4
0
Low-order 2 bits
Register A (4)
Middle-order 2 bits
High-order 2 bits
Field value p
The contents
of register D
The contents
of register A
Register B (4)
Register D (3)
Flag UPTF = 1;
High-order 2 bits of reference data is transferred to the low-order 2
bits of register D.
“0” is stored to the high-order 1 bit of register D.
Flag UPTF = 0;
Data is not transferred to register D.
Fig 15. TABP p instruction execution example
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Page 18 of 146
Register A
455A Group
(5) Stack registers (SKs) and stack pointer (SP)
Stack registers are 14-bit registers.
Stack registers (SKs) are used to temporarily store the contents of
program counter (PC) just before branching until returning to the
original routine when;
• branching to an interrupt service routine (referred to as an
interrupt service routine),
• performing a subroutine call, or
• executing the table reference instruction (TABP p).
Stack registers (SKs) are eight identical registers, so that
subroutines can be nested up to 8 levels. However, one of stack
registers is used respectively when using an interrupt service
routine and when executing a table reference instruction.
Accordingly, be careful not to over the stack when performing
these operations together. The contents of registers SKs are
destroyed when 8 levels are exceeded.
The register SK nesting level is pointed automatically by 3-bit
stack pointer (SP). The contents of the stack pointer (SP) can be
transferred to register A with the TASP instruction.
Figure 16 shows the stack registers (SKs) structure.
Figure 17 shows the example of operation at subroutine call.
(6) Interrupt stack register (SDP)
Interrupt stack register (SDP) is a 1-stage register. When an
interrupt occurs, this register (SDP) is used to temporarily store
the contents of data pointer, carry flag, skip flag, register A, and
register B just before an interrupt until returning to the original
routine.
Unlike the stack registers (SKs), this register (SDP) is not used
when executing the subroutine call instruction and the table
reference instruction.
Executing BM instruction
Executing RT instruction
SK0
(SP) = 0
SK1
(SP) = 1
SK2
(SP) = 2
SK3
(SP) = 3
SK4
(SP) = 4
SK5
(SP) = 5
SK6
(SP) = 6
SK7
(SP) = 7
Stack pointer (SP) points “7” at reset or
returning from power down mode.
It points “0” b y executing the first B M
instruction, and the contents of program
counter is stored in SK0.
When the BM instruction is executed after
eight stack registers are used ((SP) = 7), (SP)
= 0 and the contents of SK0 is destroyed.
Fig 16. Stack registers (SKs) structure
(SP) ← 0
(SK0) ← 000116
(PC) ← SUB1
Main program
Subroutine
SUB1:
Address
NOP
000016 NOP
000116 BM SUB1
...
(7) Skip flag
Skip flag controls skip decision for the conditional skip
instructions and continuous described skip instructions. When an
interrupt occurs, the contents of skip flag is stored automatically
in the interrupt stack register (SDP) and the skip condition is
retained.
Program counter (PC)
RT
000216 NOP
(PC) ← (SK0)
(SP) ← 7
Note :Returning to the BM instruction execution
address with the RT instruction, and the BM
instruction becomes the NOP instruction.
Fig 17. Example of operation at subroutine call
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Page 19 of 146
455A Group
(8) Program counter (PC)
Program counter (PC) is used to specify a ROM address (page
and address). It determines a sequence in which instructions
stored in ROM are read. It is a binary counter that increments the
number of instruction bytes each time an instruction is executed.
However, the value changes to a specified address when branch
instructions, subroutine call instructions, return instructions, or
the table reference instruction (TABP p) is executed.
Program counter consists of PCH (most significant bit to bit 7)
which specifies to a ROM page and PCL (bits 6 to 0) which
specifies an address within a page. After it reaches the last
address (address 127) of a page, it specifies address 0 of the next
page (Figure 18).
Make sure that the PCH does not specify after the last page of the
built-in ROM.
(9) Data pointer (DP)
Data pointer (DP) is used to specify a RAM address and consists
of registers Z, X, and Y. Register Z specifies a RAM file group,
register X specifies a file, and register Y specifies a RAM digit
(Figure 19).
Register Y is also used to specify the port D bit position.
When using port D, set the port D bit position to register Y
certainly and execute the SD, RD, or SZD instruction (Figure
20).
• Note
Register Z of data pointer is undefined after system is released
from reset.
Also, registers Z, X and Y are undefined in the power down
mode. After system is returned from the power down mode, set
these registers.
Program counter (PC)
p 6 p5 p4 p3 p2 p1 p0
a6 a5 a4 a3 a2 a 1 a 0
PCH
Specifying page
PCL
Specifying address
Fig 18. Program counter (PC) structure
Data pointer (DP)
Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0
Register Y (4)
Register X (4)
Register Z (2)
Specifying RAM digit
Specifying RAM file
Specifying RAM file group
Fig 19. Data pointer (DP) structure
Specifying bit position
Set
D3
0
0
0
1
Register Y (4)
D2 D1
1
Port D output latch
Fig 20. SD instruction execution example
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Page 20 of 146
D0
455A Group
PROGRAM MEMORY (ROM)
The program memory is a mask ROM. 1 word of ROM is
composed of 10 bits. ROM is separated every 128 words by the
unit of page (addresses 0 to 127). Table 8 shows the ROM size
and pages. Figure 21 shows the ROM map of M3455AGD.
A part of page 1 (addresses 008016 to 00FF16) is reserved for
interrupt addresses (Figure 22). When an interrupt occurs, the
address (interrupt address) corresponding to each interrupt is set
in the program counter, and the instruction at the interrupt
address is executed. When using an interrupt service routine,
write the instruction generating the branch to that routine at an
interrupt address.
Page 2 (addresses 0100 16 to 017F 16 ) is the special page for
subroutine calls. Subroutines written in this page can be called
from any page with the 1-word instruction (BM). Subroutines
extending from page 2 to another page can also be called with the
BM instruction when it starts on page 2.
ROM pattern (bits 9 to 0) of all addresses can be used as data
areas with the TABP p instruction.
Table 8
ROM (PROM) size
(× 10 bits)
M3455AG8
8192 words
M3455AGC (Note 1) 12288 words
7
6
5
4
3
2
1
0
Page 0
Interrupt address page
Page 1
Subroutine special page
Page 2
Page 3
2FFF16
Page 95
Fig 21. ROM map of M3455AGC
ROM size and pages
Part number
9 8
000016
007F16
008016
00FF16
010016
017F16
018016
Pages
64 (0 to 63)
96 (0 to 95)
Note1.In the initial state, data in pages 0 to 63 can be
refered with the TABP instruction. Data in pages
64 to 95 can be refferd with the TABP p instruction
after the SBK instruction is executed.Data in
pages 0 to 63 can be referred with the TABP p
instruction after the RBK instruction is executed.
ROM Code Protect Address
When selecting the protect bit write by using a serial
programmer or selecting protect enabled for writing shipment by
Renesas Technology corp., reading or writing from/to QzROM is
disabled by a serial programmer.
As for the QzROM product in blank, the ROM code is protected
by selecting the protect bit write at ROM writing with a serial
programmer.
As for the QzROM product shipped after writing, whether the
ROM code protect is used or not can be selected as ROM option
setup (“MASK option” written in the mask file converter) when
ordering.
9
008016
8
7
6
5
4
3
2
1
0
External 0 interrupt address
008216
008416
Timer 1 interrupt address
008616
Timer 2 interrupt address
008816
Timer 3 interrupt address
008A16
008C16
008E16
00FF16
Fig 22. Page 1 (addresses 008016 to 00FF16) structure
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455A Group
DATA MEMORY (RAM)
1 word of RAM is composed of 4 bits, but 1-bit manipulation
(with the SB j, RB j, and SZB j instructions) is enabled for the
entire memory area. A RAM address is specified by a data
pointer. The data pointer consists of registers Z, X, and Y. Set a
value to the data pointer certainly when executing an instruction
to access RAM (also, set a value after system returns from power
down mode).
RAM includes the area for LCD.
When writing “1” to a bit corresponding to displayed segment,
the segment is turned on.
Table 9 shows the RAM size. Figure 23 shows the RAM map.
• Note
Register Z of data pointer is undefined after system is released
from reset.
Also, registers Z, X and Y are undefined in power down mode.
After system is returned from the power down mode, set these
registers.
Table 9
RAM size and pages
Part number
M3455AG8
M3455AGC
RAM size
512 words × 4 bits (2048 bits)
RAM 512 words×4 bits (2048 bits)
Register Z
Register X 0
1
0
1
2
3
… 12 13 14 15
0
1
2
3 … 12 13 14 15
0
1
2
3
4
Register Y
5
6
7
8
0
8 16 24
9
1
9 17 25
10
2 10 18 26
11
3 11 19 27
12
4 12 20 28
13
5 13 21 29
14
6 14 22 30
15
7 15 23 31
Note: The numbers in the shaded area indicate the corresponding segment output pin numbers.
Fig 23. RAM map
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Page 22 of 146
455A Group
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an
individual address (interrupt address) according to each interrupt
source. An interrupt occurs when the following 3 conditions are
satisfied.
• An interrupt activated condition is satisfied (request flag =
“1”)
• Interrupt enable bit is enabled (“1”)
• Interrupt enable flag is enabled (INTE = “1”)
Table 10 shows interrupt sources. (Refer to each interrupt request
flag for details of activated conditions.)
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every
interrupt enable/disable. Interrupts are enabled when INTE flag
is set to “1” with the EI instruction and disabled when INTE flag
is cleared to “0” with the DI instruction. When any interrupt
occurs, the INTE flag is automatically cleared to “0,” so that
other interrupts are disabled until the EI instruction is executed.
(2) Interrupt enable bit
Use an interrupt enable bit of interrupt control registers V1 and
V2 to select the corresponding interrupt or skip instruction.
Table 11 shows the interrupt request flag, interrupt enable bit and
skip instruction.
Table 12 shows the interrupt enable bit function.
(3) Interrupt request flag
When the activated condition for each interrupt is satisfied, the
corresponding interrupt request flag is set to “1.” Each interrupt
request flag except the voltage drop detection circuit interrupt
request flag is cleared to “0” when either;
• an interrupt occurs, or
• a skip instruction is executed.
The voltage drop detection circuit interrupt request flag cannot
be cleared to “0” at the state that the activated condition is
satisfied.
Each interrupt request flag is set when the activated condition is
satisfied even if the interrupt is disabled by the INTE flag or its
interrupt enable bit. Once set, the interrupt request flag retains set
until a clear condition is satisfied.
Accordingly, an interrupt occurs when the interrupt disable state
is released while the interrupt request flag is set.
If more than one interrupt request flag is set when the interrupt
disable state is released, the interrupt priority level is as follows
shown in Table 10.
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Page 23 of 146
Table 10 Interrupt sources
Priority
level
1
2
3
4
Interrupt source
Activated
Interrupt name
condition
External 0
Level change of
interrupt
INT0 pin
Timer 1 interrupt Timer 1
underflow
Timer 2 interrupt Timer 2
underflow
Timer 3 interrupt Timer 3
underflow
Interrupt
address
Address 0
in page 1
Address 4
in page 1
Address 6
in page 1
Address 8
in page 1
Table 11 Interrupt request flag, interrupt enable bit
and skip instruction
Interrupt
request
flag
External 0 interrupt EXF0
Timer 1 interrupt
T1F
Timer 2 interrupt
T2F
Timer 3 interrupt
T3F
Interrupt name
Skip
instruction
SNZ0
SNZT1
SNZT2
SNZT3
Interrupt
enable bit
V10
V12
V13
V20
Table 12 Interrupt enable bit function
Interrupt enable
bit
1
0
Occurrence of
interrupt
Enabled
Disabled
Skip instruction
Invalid
Valid
455A Group
(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is as
follows (Figure 25).
• Program counter (PC)
An interrupt address is set in program counter. The address to
b e e x e c u t e d w h e n r e t u r n i ng t o t h e m a i n r o u t i n e i s
automatically stored in the stack register (SK).
• Interrupt enable flag (INTE)
INTE flag is cleared to “0” so that interrupts are disabled.
• Interrupt request flag
Only the request flag for the current interrupt source is cleared
to “0”.
• Data pointer, carry flag, skip flag, registers A and B
The contents of these registers and flags are stored
automatically in the interrupt stack register (SDP).
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address is
executed after branching a data store sequence to stack register.
Write the branch instruction to an interrupt service routine at an
interrupt address. Use the RTI instruction to return from an
interrupt service routine.
Interrupt enabled by executing the EI instruction is performed
after executing 1 instruction (just after the next instruction is
executed). Accordingly, when the EI instruction is executed just
before the RTI instruction, interrupts are enabled after returning
the main routine. (Refer to Figure 24)
• Program counter (PC)
Each interrupt address
• Stack register (SK)
The address of main routine to be
executed when returning
• Interrupt enable flag (INTE)
0 (Interrupt disabled)
• Interrupt request flag (only the flag for the current interrupt
source)
0
• Data pointer, carry flag, registers A and B, skip flag
Stored in the interrupt stack register (SDP)
automatically
Fig 25. Internal state when interrupt occurs
Activated
condition
INT pin interrupt
waveform input
Request flag
(state retained)
Enable bit
EXF0
V10
T1F
V12
T2F
V13
T3F
V20
Enable flag
Address 0
in page 1
Timer 1
underflow
Main
routine
Address 6
in page 1
Timer 2
underflow
Interrupt
service routine
Interrupt
occurs
Timer 3
underflow
Address 8
in page 1
Fig 26. Interrupt system diagram
EI
RTI
Interrupt is
enabled
: Interrupt enabled state
: Interrupt disabled state
Fig 24. Program example of interrupt processing
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REJ03B0224-0101
Address 4
in page 1
Page 24 of 146
INTE
455A Group
(6) Interrupt control registers
• Interrupt control register V1
Interrupt enable bits of external 0, timer 1 and timer 2 are
assigned to register V1. Set the contents of this register through
register A with the TV1A instruction. The TAV1 instruction can
be used to transfer the contents of register V1 to register A.
• Interrupt control register V2
The timer 3 interrupt enable bit are assigned to register V2. Set
the contents of this register through register A with the TV2A
instruction. The TAV2 instruction can be used to transfer the
contents of register V2 to register A.
Table 13 Interrupt control registers
Interrupt control register V1
V13 Timer 2 interrupt enable bit
V12 Timer 1 interrupt enable bit
V11 Not used
V10 External 0 interrupt enable bit
Interrupt control register V2
at reset : 00002
0
1
0
1
0
1
0
1
at power down : 00002
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
at reset : 00002
at power down : 00002
0
This bit has no function, but read/write is enabled.
1
0
V22 Not used
This bit has no function, but read/write is enabled.
1
0
V21 Not used
This bit has no function, but read/write is enabled.
1
0 Interrupt disabled (SNZT3 instruction is valid)
V20 Timer 3 interrupt enable bit
1 Interrupt enabled (SNZT3 instruction is invalid)
Note 1.“R” represents read enabled, and “W” represents write enabled.
V23
Not used
(7) Interrupt sequence
Interrupts occur only when the respective INTE flag, interrupt
enable bits (V10, V12, V13, V30), and interrupt request flag are
set to “1.” The interrupt occurs two or three cycles after the cycle
where all the above three conditions are satisfied.
The interrupt occurs after three machine cycles if instructions
other than one-cycle instruction are executed when the
conditions are satisfied (Refer to Figure 27).
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 25 of 146
R/W
TAV1/TV1A
R/W
TAV2/TV2A
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Fig 27. Interrupt sequence
Page 26 of 146
Timer 1
Timer 2
Timer 3
interrupt
External 0
interrupt
T2
T3
EI instruction execution
cycle
T1
T1
T2
T3
T2
T3
Interrupt enabled state
T1
Notes 1: The address is stacked to the last cycle.
2: This interval of cycles depends on the executed instruction at the time
when each interrupt activated condition is satisfied.
T1F
T2F
T3F
EXF0
INT
Interrupt enable
flag (INTE)
System clock
(STCK)
1 machine cycle
When an interrupt request flag is set after its interrupt is enabled
T2
T1
T2
The program starts
from the interrupt
address.
Retaining level of system
clock for 4 periods or more
is necessary.
Interrupt disabled state
Flag cleared
T3
2 to 3 machine cycles
(Notes 1, 2)
Interrupt activated
condition is satisfied.
T1
455A Group
455A Group
EXTERNAL INTERRUPTS
The 455A Group has the external 0 interrupt. An external
interrupt request occurs when a valid waveform is input to an
interrupt input pin (edge detection).
The external interrupt can be controlled with the interrupt control
register I1.
Table 14 External interrupt activated conditions
Name
External 0 interrupt
Input pin
Activated condition
D5/INT
When the next waveform is input to D5/INT pin
• Falling waveform (“H” → “L”)
Valid waveform
selection bit
I11
I12
• Rising waveform (“L” → “H”)
• Both rising and falling waveforms
I12
Falling
0
(Note 1)
D5/INT
One-sided edge
detection circuit
I11
0
EXF0
or
1
Rising
(Note 1)
Both edges
detection circuit
1
Timer 1 count start
synchronization
circuit input
SNZI0 instruction
I13
Skip
K20
(Note 2)
Level detection circuit
K21
0
Edge detection circuit
1
(Note 3)
Note 1:
This symbol represents a parasitic diode on the port.
2: When I12= 0(X=0 or 1) is 0, “L” level is detected.
When I12 is 1, “H” level is detected.
3: When I12 is 0, falling edge is detected.
When I12 is 1, rising edge is detected.
Fig 28. External interrupt circuit structure
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 27 of 146
External 0
interrupt
Key-on wakeup input
455A Group
(1) External 0 interrupt request flag (EXF0)
External 0 interrupt request flag (EXF0) is set to “1” when a
valid waveform is input to D5/INT pin.
The valid waveforms causing the interrupt must be retained at
their level for 4 clock cycles or more of the system clock (Refer
to Figure 27).
The state of EXF0 flag can be examined with the skip instruction
(SNZ0). Use the interrupt control register V1 to select the
interrupt or the skip instruction. The EXF0 flag is cleared to “0”
when an interrupt occurs or when the next instruction is skipped
with the skip instruction.
(2) External interrupt control registers
(1) Interrupt control register I1
Register I1 controls the valid waveform for the external 0
interrupt. Set the contents of this register through register A
with the TI1A instruction. The TAI1 instruction can be used
to transfer the contents of register I1 to register A.
• External 0 interrupt activated condition
External 0 interrupt activated condition is satisfied when a
valid waveform is input to D5/INT pin.
The valid waveform can be selected from rising waveform,
falling waveform or both rising and falling waveforms. An
example of how to use the external 0 interrupt is as follows.
(1) Set the bit 3 of register I1 to “1” for the INT pin to be in the
input enabled state.
(2) Select the valid waveform with the bits 1 and 2 of register
I1.
(3) Clear the EXF0 flag to “0” with the SNZ0 instruction.
(4) Set the NOP instruction for the case when a skip is
performed with the SNZ0 instruction.
(5) Set both the external 0 interrupt enable bit (V10) and the
INTE flag to “1.”
The external 0 interrupt is now enabled. Now when a valid
waveform is input to the D5/INT pin, the EXF0 flag is set to “1”
and the external 0 interrupt occurs.
Table 15 External interrupt control register
Interrupt control register I1
I13
INT pin input control bit (Note 2)
I12
Interrupt valid waveform for INT pin/
return level selection bit (Note 2)
I11
INT pin edge detection circuit control bit
at reset : 00002
0
1
0
1
0
1
at power down : state retained
INT pin input disabled
INT pin input enabled
Falling waveform (“L” level of INT pin is recognized with the SNZI0
instruction)/“L” level
Rising waveform (“H” level of INT pin is recognized with the SNZI0
instruction)/“H” level
One-sided edge detected
Both edges detected
0
Timer 1 count start synchronous circuit not selected
1
Timer 1 count start synchronous circuit selected
cuit selection bit
Note 1.“R” represents read enabled, and “W” represents write enabled.
Note 2.When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set.
I10
INT pin timer 1 count start synchronous cir-
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 28 of 146
R/W
TAI1/TI1A
455A Group
(3) Notes on interrupts
(1) Bit 3 of register I1
When the input of the INT pin is controlled with the bit 3 of
register I1 in software, be careful about the following notes.
(3) Bit 2 of register I1
When the interrupt valid waveform of the INT pin is
changed with the bit 2 of register I1 in software, be careful
about the following notes.
• Depending on the input state of the D5/INT pin, the external 0
interrupt request flag (EXF0) may be set when the bit 3 of
register I1 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 0 of register V1 to “0” (refer
to (1) in Figure 29.) and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0
flag to “0” after executing at least one instruction (refer to (2)
in Figure 29.).
Also, set the NOP instruction for the case when a skip is
performed with the SNZ0 instruction (refer to (3) in Figure
29.).
• Depending on the input state of the D5/INT pin, the external 0
interrupt request flag (EXF0) may be set when the bit 2 of
register I1 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 0 of register V1 to “0” (refer
to (1) in Figure 31.) and then, change the bit 2 of register I1 is
changed.
In addition, execute the SNZ0 instruction to clear the EXF0
flag to “0” after executing at least one instruction (refer to (2)
in Figure 31.).
Also, set the NOP instruction for the case when a skip is
performed with the SNZ0 instruction (refer to (3) in Figure
31.).
•
•
•
LA 4
TV1A
LA 8
TI1A
NOP
SNZ0
NOP
•
•
•
; (×××02)
; The SNZ0 instruction is valid ...... (1)
; (1×××2)
; Control of INT pin input is changed
...................................................... (2)
; The SNZ0 instruction is executed
(EXF0 flag cleared)
...................................................... (3)
×: these bits are not used here.
•
•
•
LA 4
TV1A
LA 12
TI1A
NOP
SNZ0
NOP
•
•
•
; (×××02)
; The SNZ0 instruction is valid ......(1)
; (×1××2)
; Interrupt valid waveform is changed
.......................................................(2)
; The SNZ0 instruction is executed
(EXF0 flag cleared)
.......................................................(3)
×: these bits are not used here.
Fig 29. External 0 interrupt program example-1
Fig 31. External 0 interrupt program example-3
(2) Bit 3 of register I1
When the bit 3 of register I1 is cleared to “0”, the power
down mode is selected and the input of INT pin is disabled,
be careful about the following notes.
• When the INT pin input is disabled (register I13 = “0”), set the
key-on wakeup of INT pin to be invalid (register K20 = “0”)
before system enters to power down mode. (refer to (1) in
Figure 30.).
•
•
•
LA 0
TK2A
DI
EPOF
POF2
•
•
•
; (×××02)
; INT0 key-on wakeup disabled .....(1)
; RAM back-up
×: these bits are not used here.
Fig 30. External 0 interrupt program example-2
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 29 of 146
455A Group
TIMERS
The 455A Group has the following timers.
• Programmable timer
The programmable timer has a reload register and enables the
frequency dividing ratio to be set. It is decremented from a
setting value n. When it underflows (count to n + 1), a timer
interrupt request flag is set to “1,” new data is loaded from the
reload register, and count continues (auto-reload function).
• Fixed dividing frequency timer
The fixed dividing frequency timer has the fixed frequency
dividing ratio (n). An interrupt request flag is set to “1” after
every n count of a count pulse.
FF16
n : Counter initial value
Count starts
Reload
Reload
The contents of counter
n
1st underflow
2nd underflow
0016
n+1 count
n+1 count
Time
Timer interrupt “1”
“0”
request flag
An interrupt occurs or
a skip instruction is executed.
Fig 32. Auto-reload function
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 30 of 146
455A Group
The 455A Group timer consists of the following circuits.
• Prescaler : 8-bit programmable timer
• Timer 1 : 8-bit programmable timer
• Timer 2 : 8-bit programmable timer
• Timer 3 : 16-bit fixed frequency timer
• Timer LC : 4-bit programmable timer
• Watchdog timer: 16-bit fixed frequency timer
(Timers 1, 2 and 3 have the interrupt function, respectively)
Prescaler, timer 1, timer 2, timer 3 and timer LC can be
controlled with the timer control registers PA and W1 to W5. The
watchdog timer is a free counter which is not controlled with the
control register.
Each function is described below.
Table 16 Function related timers
Circuit
Structure
Count source
Prescaler
8-bit programmable
binary down counter
• Instruction clock (INSTCK)
Timer 1
8-bit programmable
binary down counter
(link to INT input)
(carrier wave output autocontrol function)
8-bit programmable
binary down counter
(with carrier wave
generation function)
16-bit fixed dividing
frequency
•
•
•
•
Timer 2
Timer 3
Timer LC
4-bit programmable binary
down counter
Watchdog 16-bit fixed dividing
timer
frequency
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
PWM signal (PWMOUT)
Prescaler output (ORCLK)
Timer 3 underflow (T3UDF)
CNTR input
Frequency
dividing ratio
1 to 256
•
•
•
1 to 256
•
•
Use of output signal
Timer 1 count source
Timer 2 count source
Timer 3 count source
CNTR output control
Timer 1 interrupt
Control
register
PA
W1
W4
• XIN input
• Prescaler output divided by 2
(ORCLK/2)
1 to 256
• Timer 1 count source
• CNTR output
• Timer 2 interrupt
W2
W4
• XCIN input
• Prescaler output (ORCLK)
• High-speed on-chip oscillator
(f(HSOCO))
• Low-speed on-chip oscillator
(f(LSOCO))
512
1024
2048
4096
8192
16384
32768
65536
1 to 16
• Timer 1 count source
• Timer LC count source
• Timer 3 interrupt
W3
W5
• LCD clock
W4
• Bit 4 of timer 3 (T34)
• System clock (STCK)
• Instruction clock (INSTCK)
Page 31 of 146
65536
• System reset (counting twice)
• Decision of flag WDF1
-
455A Group
Division circuit
MR1, MR0
High-speed on-chip oscillator
00
Ceramic resonance
01
10
XIN
Quartz-crystal
oscillation
XＣＩN
Divided by 8
MR3, MR2
11
Divided by 4
Divided by 2
System clock (STCK)
10
Internal clock
generating circuit
(divided by 3)
01
00
Instruction clock
(INSTCK)
11
Low-speed on-chip oscillator
Prescaler (8)
PA0
ORCLK
Reload register RPS (8)
(TPSAB)
Register B
I12
0
One-sided edge
detection circuit
1
Both edges
detection circuit
D5/INT
I13
(TPSAB)
(TPSAB)
(TABPS)
(TABPS)
Register A
I11
0
S
I10
1
Q
1
R
0
I10
W13
T1UDF
PWMOUT
10
T3UDF
(TAB1)
11
W40
0
Register B
Timer 1
interrupt
T1F
Reload register R1 (8)
(T1AB)
(T1AB)
(TR1AB)
(T1AB)
01
ORCLK
C/CNTR
Timer 1 (8)
W11, W10
00
Timer 1 underflow signal
(T1UDF)
(TAB1)
Register A
W12
1
PWMOUT
Port C output
T1UDF
D
W41
W11
W10
QR T
W12
Register B
Register A
Q
(T2HAB)
Reload register R2H (8)
W20
0
XIN
1/2
R
“H” interval
expansion
1
W21
(TAB2)
(T2AB)
(T2AB)
(T2AB)
(TAB2)
Register A
Data is set automatically from each reload register
when timer underflows (auto-reload function).
Fig 33. Timers structure (1)
Page 32 of 146
W22
1
W23
T2F
0
(T2R2L)
Reload register R2L (8)
Register B
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
PWMOD
Reload control circuit
Timer 2 (8)
ORCLK
T
Timer 2
interrupt
455A Group
W51, W50
XCIN
ORCLK
Low-speed OCO
High-speed OCO
00
01
Timer3 (16)
1 - - 4 - - - - - 9 10 11 12 13 14 15 16
10
11
W32、W31、W30
111
W33
110
101
100
011
T3F
Timer 3
interrupt
Timer 3 underflow signal
(T3UDF)
010
001
000
W42
0
Timer LC (4)
1/2
1
STCK
W43
LCD clock
Reload register RLC (4)
(TLCA)
(TLCA)
Register A
INSTCK
Watchdog timer (16)
1 - - - - - - - - - - - - - 16
(Note 1)
S
Q
WDF1
WRST
instruction
Reset signal
(Note 3)
DWDT instruction
+
WRST instruction
R
S
Q
WEF
R
D
Q
Watchdog reset
signal
T
R
reset signal
(Note 2)
Data is set automatically from each reload register
when timer underflows (auto-reload function).
Note 1: Flag WDF1 is cleared to “0” and the next instruction is skipped when the WRST instruction is executed
while flag WDF1 = “1”.
The WRST instruction is equivalent to the NOP instruction while flag WDF1 = “0”.
2: Flag WEF is cleared to “0” and watchdog timer reset does not occur when the DWDT instruction and
WRST instruction are executed continuously.
3: The WEF flag is set to “1” at system reset or RAM back-up mode.
Fig 34. Timers structure (2)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 33 of 146
455A Group
Table 17 Timer control registers
Timer control register PA
at reset : 02
0
1
PA0 Prescaler control bit
Timer control register W1
W13
Timer 1 count auto-stop circuit selection bit
(Note 2)
W12 Timer 1 control bit
W11
at reset : 00002
at power down : state retained
0
1
0
1
W11
Timer 1 count auto-stop circuit not selected
Timer 1 count auto-stop circuit selected
Stop (state retained)
Operating
W10
Count source
0
0
PWM signal (PWMOUT)
1
Prescaler output (ORCLK)
1
0
Timer 3 underflow signal (T3UDF)
1
1
CNTR input
Timer control register W2
at reset : 00002
0
1
0
1
0
1
0
1
W23 CNTR pin function control bit
PWM signal
“H” interval expansion function control bit
W21 Timer 2 control bit
W20 Timer 2 count source selection bit
Timer control register W3
W33 Timer 3 control bit
W32
W31 Timer 3 count value selection bits
W30
at power down : 00002
R/W
TAW1/TW1A
R/W
TAW2/TW2A
CNTR pin output invalid
CNTR pin output valid
PWM signal “H” interval expansion function invalid
PWM signal “H” interval expansion function valid
Stop (state retained)
Operating
XIN input
Prescaler output (ORCLK)/2
at reset : 00002
at power down : state retained
R/W
TAW3/TW3A
0
Stop (initial state)
1
Operating
W32 W31 W30
Count value
000
Underflow every 512 count
001
Underflow every 1024 count
010
Underflow every 2048 count
011
Underflow every 4096 count
100
Underflow every 8192 count
101
Underflow every 16384 count
110
Underflow every 32768 count
111
Underflow every 65536 count
Timer control register W4
at reset : 00002
at power down : state retained
0 Stop (state retained)
1 Operating
0 Bit 4 (T34) of timer 3
W42 Timer LC count source selection bit
1 System clock (STCK)
0 CNTR output auto-control circuit not selected
CNTR pin output auto-control circuit
W41
selection bit
1 CNTR output auto-control circuit selected
0 Falling edge
W40 CNTR pin input count edge selection bit
1 Rising edge
Note 1. “R” represents read enabled, and “W” represents write enabled.
Note 2. This function is valid only when the timer 1 control start synchronous circuit is selected (I10 =“1”).
Note 3. Port C output is invalid when CNTR input is selected for the timer 1 count source.
W43 Timer LC control bit
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
W
TPAA
Stop (state retained)
Operating
Timer 1 count source selection bits (Note 3) 0
W10
W22
at power down : 02
Page 34 of 146
R/W
TAW4/TW4A
455A Group
Timer control register W5
W53 Not used
W52 Not used
W51
Timer 3 count source selection bits
W50
at reset : 00002
R/W
TAW5/TW5A
0 This bit has no function, but read/write is enabled.
1 This bit has no function, but read/write is enabled.
0 This bit has no function, but read/write is enabled.
1 This bit has no function, but read/write is enabled.
W51W52 Count source
00
XCIN input
01
ORCLK input
10
Low-speed on-chip oscillator
11
High-speed on-chip oscillator
(1) Timer control registers
• Timer control register PA
Register PA controls the count operation of prescaler. Set the
contents of this register through register A with the TPAA
instruction.
• Timer control register W1
Register W1 controls the count operation and count source of
timer 1, and timer 1 count auto-stop circuit. Set the contents of
this register through register A with the TW1A instruction.
The TAW1 instruction can be used to transfer the contents of
register W1 to register A.
• Timer control register W2
Register W2 controls the count operation and count source of
timer 2, CNTR pin output, and extension function of PWM
signal “H” interval. Set the contents of this register through
register A with the TW2A instruction. The TAW2 instruction
can be used to transfer the contents of register W2 to register
A.
• Timer control register W3
Register W3 controls the count operation and count value of
timer 3. Set the contents of this register through register A with
the TW3A instruction. The TAW3 instruction can be used to
transfer the contents of register W3 to register A.
• Timer control register W4
Register W4 controls the input count edge of CNTR pin,
CNTR1 pin output auto-control circuit. Set the contents of this
register through register A with the TW4A instruction. The
TAW4 instruction can be used to transfer the contents of
register W4 to register A.
• Timer control register W5
Register W5 controls the count source of timer 3. Set the
contents of this register through register A with the TW5A
instruction. The TAW5A instruction can be used to transfer the
contents of register W5 to register A.
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
at power down : state retained
Page 35 of 146
(2) Prescaler
Prescaler is an 8-bit binary down counter with the prescaler
reload register PRS. Data can be set simultaneously in prescaler
and the reload register RPS with the TPSAB instruction. Data
can be read from reload register RPS with the TABPS
instruction.
Stop counting and then execute the TPSAB or TABPS
instruction to read or set prescaler data.
Prescaler starts counting after the following process;
(1) set data in prescaler, and
(2) set the bit 0 of register PA to “1.”
When a value set in reload register RPS is n, prescaler divides the
count source signal by n + 1 (n = 0 to 255).
Count source for prescaler can be selected the instruction clock
(INSTCK).
Once count is started, when prescaler underflows (the next count
pulse is input after the contents of prescaler becomes “0”), new
data is loaded from reload register RPS, and count continues
(auto-reload function).
The output signal (ORCLK) of prescaler can be used for timer 1,
2 and 3 count sources.
455A Group
(3) Timer 1 (interrupt function)
Timer 1 is an 8-bit binary down counter with a timer 1 reload
register (R1). Data can be set simultaneously in timer 1 and the
reload register R1 with the T1AB instruction. Data can be read
from timer 1 with the TAB1 instruction.
Stop counting and then execute the T1AB or TAB1 instruction to
read or set timer 1 data.
When executing the TR1AB instruction to set data to reload
register R1 while timer 1 is operating, avoid a timing when timer
1 underflows.
Timer 1 starts counting after the following process;
(1) set data in timer 1
(2) set count source by bit 0 and 1 of register W1, and
(3) set the bit 2 of register W1 to “1.”
When a value set in reload register R1 is n, timer 1 divides the
count source signal by n + 1 (n = 0 to 255).
Once count is started, when timer 1 underflows (the next count
pulse is input after the contents of timer 1 becomes “0”), the
timer 1 interrupt request flag (T1F) is set to “1,” new data is
loaded from reload register R1, and count continues (auto-reload
function).
The INT pin input can be used as the start trigger for timer 1
count operation by setting “1” in bit 0 of interrupt control register
l1.
Also, in this time, the auto-stop function by timer 1 underflow
can be performed by setting the bit 3 of register W1 to “1.”
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 36 of 146
(4) Timer 2 (interrupt function)
Timer 2 is an 8-bit binary down counter with two timer 2 reload
register (R2L, R2H). Data can be set simultaneously in timer 2
and the reload register R2L with the T2AB instruction. Data can
be set in the reload register R2H with the T2HAB instruction.
The contents of reload register R2L set with the T2AB
instruction can be set to timer 2 again with the T2R2L
instruction. Data can be read from timer 2 with the TAB2
instruction.
Stop counting and then execute the T2AB or TAB2 instruction to
read or set timer 2 data.
When executing the T2HAB instruction to set data to reload
register R2H while timer 2 is operating, avoid a timing when
timer 2 underflows.
Timer 2 starts counting after the following process;
(1) set data in timer 2
(2) set count source by bit 0 of register W2, and
(3) set the bit 1 of register W2 to “1.”
When a value set in reload register R2L is n and R2H is m, timer
2 divides the count source signal by n + 1 or m + 1 (n = 0 to 255,
m = 0 to 255).
Once count is started, when timer 2 underflows (the next count
pulse is input after the contents of timer 2 becomes “0”), the
timer 2 interrupt request flag (T2F) is set to “1,” new data is
loaded from reload register R2L, and count continues (autoreload function).
When bit 3 of register W2 is set to “1”, timer 2 reloads data from
reload register R2L and R2H alternately each underflow.
Timer 2 generates the PWM signal (PWMOUT) of the “L”
interval set as reload register R2L, and the “H” interval set as
reload registerR2H. The PWM signal (PWMOUT) is output
from CNTR pin. When bit 2 of register W2 is set to “1” at this
time, the interval (PWM signal “H” interval) set to reload
register R2H for the counter of timer 2 is extended for a half
period of count source.
In this case, when a value set in reload register R2H is m, timer 2
divides the count source signal by n + 1.5 (m = 1 to 255).
When this function is used, set “1” or more to reload register
R2H.
When bit 1 of register W4 is set to “1”, the PWM signal output to
CNTR pin is switched to valid/invalid each timer 1 underflow.
However, when timer 1 is stopped (bit 2 of register W1 is cleared
to “0”), this function is canceled.
Even when bit 1 of a register W2 is cleared to “0” in the “H”
interval of PWM signal, timer 2 does not stop until it next timer 2
underflow.
When clearing bit 1 of register W2 to “0” to stop timer 2, avoid a
timing when timer 2 underflows.
455A Group
(5) Timer 3 (interrupt function)
Timer 3 is a 16-bit binary down counter.
Timer 3 starts counting after the following process;
(1) set count value by bits 0, 1 and 2 of register W3,
(2) set count source by bit 0 and 1 of register W5, and
(3) set the bit 3 of register W3 to “1.”
Once count is started, when timer 3 underflows (the set count
value is counted), the timer 3 interrupt request flag (T3F) is set to
“1,” and count continues.
Bit 4 of timer 3 can be used as the timer LC count source for the
LCD clock generating.
When bit 3 of register W3 is cleared to “0”, timer 3 is initialized
to “FFFF16” and count is stopped.
Timer 3 can be used as the counter for clock because it can be
operated at clock operating mode (POF instruction execution).
When timer 3 underflow occurs at clock operating mode, system
returns from the power down state.
When operating timer 3 during clock operating mode, set 1 cycle
or more of count source to the following period; from setting bit
3 of register W3 to “1” till executing the POF instruction.
(6) Timer LC
Timer LC is a 4-bit binary down counter with the timer LC
reload register (RLC). Data can be set simultaneously in timer
LC and the reload register (RLC) with the TLCA instruction.
Data cannot be read from timer LC. Stop counting and then
execute the TLCA instruction to set timer LC data.
Timer LC starts counting after the following process;
(1) set data in timer LC,
(2) select the count source with the bit 2 of register W4, and
(3) set the bit 3 of register W4 to “1.”
When a value set in reload register RLC is n, timer LC divides
the count source signal by n + 1 (n = 0 to 15).
Once count is started, when timer LC underflows (the next count
pulse is input after the contents of timer LC becomes “0”), new
data is loaded from reload register RLC, and count continues
(auto-reload function).
Timer LC underflow signal divided by 2 can be used for the LCD
clock.
(7) Timer input/output pin (C/CNTR pin)
CNTR pin is used to input the timer 1 count source and output
the PWM signal generated by timer 2. The selection of CNTR
output signal can be controlled by bit 3 of register W2.
When the PWM signal is output from C/CNTR pin, set “0” to the
output latch of port C.
When the CNTR input is selected for timer 1 count source, timer
1 counts the waveform of CNTR input selected by bit 0 of
register W4. Also, when the CNTR input is selected, the output
of port C is invalid (high-impedance state).
Rev.1.01 Feb 15, 2008
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(8) Timer interrupt request flags (T1F, T2F, T3F)
Each timer interrupt request flag is set to “1” when each timer
underflows. The state of these flags can be examined with the
skip instructions (SNZT1, SNZT2, SNZT3).
Use the interrupt control register V1, V2 to select an interrupt or
a skip instruction.
An interrupt request flag is cleared to “0” when an interrupt
occurs or when the next instruction is skipped with a skip
instruction.
(9) Count start synchronization circuit (timer 1)
Timer 1 has the count start synchronous circuit which
synchronizes the input of INT pin, and can start the timer count
operation.
Timer 1 count start synchronous circuit function is selected by
setting the bit 0 of register I1 to “1” and the control by INT pin
input can be performed.
When timer 1 count start synchronous circuit is used, the count
start synchronous circuit is set, the count source is input to timer
by inputting valid waveform to INT pin.
The valid waveform of INT pin to set the count start synchronous
circuit is the same as the external interrupt activated condition.
Once set, the count start synchronous circuit is cleared by
clearing the bit I10 to “0” or system reset.
However, when the count auto-stop circuit is selected, the count
start synchronous circuit is cleared (auto-stop) at the timer 1
underflow.
(10)Count auto-stop circuit (timer 1)
Timer 1 has the count auto-stop circuit which is used to stop
timer 1 automatically by the timer 1 underflow when the count
start synchronous circuit is used.
The count auto-stop circuit is valid by setting the bit 3 of register
W1 to “1”. It is cleared by the timer 1 underflow and the count
source to timer 1 is stopped.
This function is valid only when the timer 1 count start
synchronous circuit is selected.
455A Group
(11) Precautions
• Prescaler
Stop prescaler counting and then execute the TABPS
instruction to read its data.
Stop prescaler counting and then execute the TPSAB
instruction to write data to prescaler.
• Timer count source
Stop timer 1, 2, 3 or LC counting to change its count source.
• Reading the count value
Stop timer 1 or 2 counting and then execute the TAB1 or
TAB2 instruction to read its data.
• Writing to the timer
Stop timer 1, 2 or LC counting and then execute the T1AB,
T2AB, T2R2L or TLCA instruction to write data to timer.
• Writing to reload register
In order to write a data to the reload register R1 while the timer
1 is operating, execute the TR1AB instruction except a timing
of the timer 1 underflow.
In order to write a data to the reload register R2H while the
timer 2 is operating, execute the T2HAB instruction except a
timing of the timer 3 underflow.
• PWM signal
If the timer 2 count stop timing and the timer 2 underflow
timing overlap during output of the PWM signal, a hazard may
occur in the PWM output waveform.
When “H” interval expansion function of the PWM signal is
used, set “1” or more to reload register R2H.
Set the port C output latch to “0” to output the PWM signal
from C/CNTR pin.
• Timer 3
Stop timer 3 counting to change its count source.
When operating timer 3 during clock operating mode, set 1
cycle or more of count source to the following period; from
setting bit 3 of register W3 to “1” till executing the POF
instruction.
• Prescaler and timer 1 count start timing and count time when
operation starts
Count starts from the first rising edge of the count source (2) in
Figure 35 after prescaler and timer operations start (1) in
Figure 35.
Time to first underflow (3) in Figure 35 is shorter (for up to 1
period of the count source) than time among next underflow
(4) in Figure 35 by the timing to start the timer and count
source operations after count starts.
When selecting CNTR input as the count source of timer 1,
timer 1 operates synchronizing with the falling edge of CNTR
input.
(2)
Count source
Count source
(When falling edge of
CNTR input is selected)
Timer 1 value
3
1
2
0
3
2
1
0
3
2
Timer 1 underflow signal
(3)
(4)
(1) Timer start
Fig 35. Timer count start timing and count time when
operation starts
• Timer 2 and Timer LC count start timing and count time when
operation starts
Count starts from the rising edge (2) after the first falling edge
of the count source, after Timer 2 and Timer LC operations
start (1).
Time to first underflow (3) is different from time among next
underflow (4) by the timing to start the timer and count source
operations after count starts.
(2)
Count source
Timer value
3
2
1
0
3
2
1
0
3
Timer underflow signal
(3)
(4)
(1) Timer start
Fig 36. Timer count start timing and count time when
operation starts (Timer 2 and Timer LC)
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455A Group
- CNTR pin output invalid (W23=0)
Timer 2 count source
Timer 2 count value
(Reload register)
0316
0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016
(R2L)
(R2L)
(R2L)
(R2L)
(R2L)
Timer 2 underflow signal
PWM signal
PWM1 signal “L” fixed
Timer 2 start
- CNTR pin output valid (W23=1), PWM signal “H” interval expansion function invalid (W22=0)
Timer 2 count source
Timer 2 count value
(Reload register)
0316
0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116
(R2L)
(R2L)
(R2H)
(R2H)
(R2L)
(R2H)
Timer 2 underflow signal
4 clock
PWM signal
3 clock
4 clock
3 clock
PWM period 7 clock
Timer 2 start
4 clock
PWM period 7 clock
- CNTR pin output valid (W23=1), PWM signal “H” interval expansion function valid (W22=1) (Note)
Timer 2 count source
Timer 2 count value
(Reload register)
0316
0216 0116 0016
0216
0116 0016 0316 0216 0116 0016
0216
0116 0016 0316 0216 0116 0016 0216
(R2L)
(R2L)
(R2H)
(R2H)
(R2L)
(R2H)
Timer 2 underflow signal
4 clock
PWM signal
3.5 clock
4 clock
PWM period 7.5 clock
Timer 2 start
3.5 clock
4 clock
PWM period 7.5 clock
* : “0316” is set to reload register R3L and “0216” is set to reload register R3H.
Note: When the PWM signal “H” interval expansion function is valid,
set “1” or more to reload register R2H.
Fig 37. Timer 2 operation example
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Page 39 of 146
455A Group
• CNTR output auto-control circuit operation example 1 (W23 = “1”, W41 = “1”)
PWM signal
Timer 1 underflow signal
Timer 1 start
CNTR output
CNTR output start
* When the CNTR1 output auto-control circuit is selected, valid/invalid of CNTR output is repeated every timer 1 underflows.
• CNTR output auto-control circuit operation example 2 (W23 = “1”, W41 = “1”)
PWM signal
Timer 1 underflow signal
Register W41
Timer 1 start
(1)
(2)
Timer 1 stop
(3)
CNTR output
CNTR output start
(1) When the CNTR output auto-control function is not selected while the CNTR output is invalid,
CNTR output invalid state is retained.
(2) When the CNTR output auto-control function is not selected while the CNTR output is valid,
CNTR output valid state is retained.
(3) When the timer 1 is stopped, the CNTR output auto-control function becomes invalid.
Fig 38. CNTR output auto-control function by timer 1
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Page 40 of 146
CNTR output stop
455A Group
Timer 2 count start timing (R2L = “0216”, R2H = “0216”, W23 = “1”)
Machine cycle
Mi
Timer 2 count source
(XIN input)
Mi + 1
TW2A instruction execution (W21←1)
Mi + 2
Mi + 3
Register W21
Timer 2 count value
(reload register)
0216
(R2L)
0116
0016
0216
(R2H)
0116
0016
0216
(R2L)
Timer 2 underflow signal
PWM signal
Timer 2 count start timing
Timer 2 count stop timing (R2L = “0216”, R2H = “0216”, W23 = “1”)
Machine cycle
Mi
Mi + 1
Timer 2 count source
(XIN input)
Mi + 2
TW2A instruction execution (W21←0)
Mi + 3
Register W21
Timer 2 count value
(reload register)
0216
(R2H)
0116
0016
0216
(R2L)
0116
0016
0216
(R2H)
Timer 2 underflow signal
PWM signal
(Note 1)
Timer 2 count stop timing
Notes 1: If the timer count stop timing and the timer underflow timing overlap while the CNTR pin output
is valid (W23=“1”), a hazard may occur in the PWM signal waveform.
2: When timer count is stopped during “H” interval of the PWM signal, timer is stopped after
the end of the “H” output interval.
Fig 39. Timer count start/stop timing
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Page 41 of 146
455A Group
WATCHDOG TIMER
Watchdog timer provides a method to reset the system when a
program run-away occurs. Watchdog timer consists of timer
WDT(16-bit binary counter), watchdog timer enable flag (WEF),
and watchdog timer flags (WDF1, WDF2).
The timer WDT downcounts the instruction clocks (INSTCK) as
the count source from “FFFF16” after system is released from
reset.
After the count is started, when the timer WDT underflow occurs
(after the count value of timer WDT reaches “000016,” the next
count pulse is input), the WDF1 flag is set to “1.” If the WRST
instruction is never executed until the timer WDT underflow
occurs (until timer WDT counts 65534), WDF2 flag is set to “1,”
and the RESET pin outputs “L” level to reset the microcomputer.
Execute the WRST instruction at each period of 65534 machine
cycle or less by software when using watchdog timer to keep the
microcomputer operating normally.
When the WEF flag is set to “1” after system is released from
reset, the watchdog timer function is valid.
When the DWDT instruction and the WRST instruction are
executed continuously, the WEF flag is cleared to “0” and the
watchdog timer function is invalid.
The WEF flag is set to “1” at system reset or RAM back-up
mode.
The WRST instruction has the skip function. When the WRST
instruction is executed while the WDF1 flag is “1”, the WDF1
flag is cleared to “0” and the next instruction is skipped.
When the WRST instruction is executed while the WDF1 flag is
“0”, the next instruction is not skipped.
The skip function of the WRST instruction can be used even
when the watchdog timer function is invalid.
FFFF16
Value of 16-bit timer (WDT)
000016
(2)
(2)
WDF1 flag
65534 count
(Note)
(4)
WDF2 flag
RESET pin output
(1) Reset released
(3) WRST instruction
(5) System reset
executed (skip occurrence)
(1) After system is released from reset (= after program is started), timer WDT starts count down.
(2) When timer WDT underflow occurs, WDF1 flag is set to “1.”
(3) When the WRST instruction is executed while the WDF1 flag is “1”, WDF1 flag is cleared to “0,” the next
instruction is skipped.
(4) When timer WDT underflow occurs while WDF1 flag is “1,” WDF2 flag is set to “1” and the watchdog reset
signal is output.
(5) The output transistor of RESET pin is turned “ON” by the watchdog reset signal and system reset is
executed.
Note: The number of count is equal to the number of machine cycle because the count source of watchdog timer
is the instruction clock.
Fig 40. Watchdog timer function
Rev.1.01 Feb 15, 2008
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Page 42 of 146
455A Group
When the watchdog timer is used, clear the WDF1 flag at the
period of 65534 machine cycles or less with the WRST
instruction.
When the watchdog timer is not used, execute the DWDT
instruction and the WRST instruction continuously (refer to
Figure 41).
The watchdog timer is not stopped with only the DWDT
instruction.
The contents of WDF1 flag and timer WDT are initialized at the
power down mode.
When using the watchdog timer and the power down mode,
initialize the WDF1 flag with the WRST instruction just before
the microcomputer enters the power down mode. Also, set the
NOP instruction after the WRST instruction, for the case when a
skip is performed with the WRST instruction (refer to Figure 42).
•
•
•
WRST
; WDF1 flag cleared
•
•
•
DI
DWDT
WRST
•
•
•
; Watchdog timer function enabled/disabled
; WEF and WDF1 flags cleared
Fig 41. Program example to start/stop watchdog timer
•
•
•
WRST
; WDF1 flag cleared
NOP
DI
; Interrupt disabled
EPOF
; POF instruction enabled
POF2
; RAM back-up mode
↓
Oscillation stop
•
•
•
Fig 42. Program example when using the watchdog
timer
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Page 43 of 146
455A Group
(1) Duty and bias
There are 3 combinations of duty and bias for displaying data on
the LCD. Use bits 0 and 1 of LCD control register (L1) to select
the proper display method for the LCD panel being used.
LCD FUNCTION
The 455A Group has an LCD (Liquid Crystal Display)
controller/ driver. When data are set in LCD RAM and timer LC,
LCD control registers (L1, L2, L3, C1, C2, C3), and timer
control registers (W3, W4), the LCD controller/driver
automatically reads the display data and controls the LCD
display by setting duty and bias.
4 common signal output pins and 32 segment signal output pins
can be used to drive the LCD. By using these pins, up to 128
pixels (when internal power, 1/4 duty and 1/3 bias are selected)
can be controlled to display. When using the external input, set
necessary pins with the LCD control register 2 and apply the
proper voltage to the pins .
The LCD power input pins (VLC3–VLC1) are also used as pins
SEG0–SEG2. When SEG0 is selected, the internal power (VDD)
is used for the LCD power.
• 1/2 duty, 1/2 bias
• 1/3 duty, 1/3 bias
• 1/4 duty, 1/3 bias
Table 18
Duty and maximum number of displayed
pixels
Maximum number of displayed
pixels
64 pixels
96 pixels
128 pixels
Duty
1/2
1/3
1/4
Used COM pins
COM0, COM1 (Note)
COM0–COM2 (Note)
COM0–COM3
to
P3 3/SEG 31
P3 0/SEG 28
to
P2 3/SEG 27
P1 3 /SEG 23
to
P2 0/SEG 24
to
P1 0/SEG 20
P0 3/SEG 19
P0 0/SEG 16
to
SEG 15
SEG 3
SEG 2/V LC1
SEG 1/V LC2
SEG 0/V LC3
COM 0
COM 1
COM 2
COM 3
Note. Leave unused COM pins open.
VDD
L23
L13
L22
r
C2 0 to C2 3
L3 0 to L3 3
C3 0 to C3 3
LCD ON/OFF
control
Decoder
....
....
Segment
driver
Segment
driver
Segment
driver
Segment
driver
Segment
driver
....
....
....
....
....
Selector
Selector
Selector
Selector
Selector
LCD RAM
L11
L10
Register A
LCD clock
(from timer LC)
Fig 43. LCD controller/driver
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
....
C10 to C1 3
L2 3
Segment
driver
Bias control
Selector
1/2, 1/3, 1/4
counter
....
....
L20
L12
....
....
L13
r
Common
driver
....
L21
r
r
....
L13
L2 1
r
L2 2
r
L23
Page 44 of 146
455A Group
(2) LCD clock control
The LCD clock is determined by the timer LC setting value and
timer LC count source.
After setting data to timer LC, timer LC starts counting by setting
count source with bit 2 of register W4 and setting bit 3 of register
W4 to “1.”
Accordingly, the frequency (F) of the LCD clock is obtained by
the following formula. Numbers ((1) to (3)) shown below the
formula correspond to numbers in Figure 44, respectively.
• When using the bit 4 of timer 3 as timer LC count source
(W42=“0”)
1
1
F = T34 ×
×
LC + 1
2
(1)
(2)
(3)
[LC: 0 to 15]
• When using the system clock (STCK) as timer LC count
source (W42=“1”)
F = STCK ×
(1)
(2)
The frame frequency and frame period for each display method
can be obtained by the following formula:
F
Frame frequency =
(Hz)
n
1
2
1
×
LC + 1
(3)
[LC: 0 to 15]
Frame frequency =
n
F
(Hz)
F: LCD clock frequency
1/n: Duty
(1)
W42
0
T34
(2)
1
STCK
(3)
1/2
Timer LC (4)
LCD clock
W43
Reload register RLC (4)
(TLCA)
(TLCA)
Register A
Fig 44. LCD clock control circuit structure
(3) LCD RAM
RAM contains areas corresponding to the liquid crystal display.
When “1” is written to this LCD RAM, the display pixel
corresponding to the bit is automatically displayed.
Z
1
12
X
bit
Y
8
13
14
15
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
SEG0 SEG0 SEG0 SEG0 SEG8 SEG8 SEG8 SEG8 SEG16 SEG16 SEG16 SEG16 SEG24 SEG24 SEG24 SEG24
9
SEG1 SEG1 SEG1 SEG1 SEG9 SEG9 SEG9 SEG9 SEG17 SEG17 SEG17 SEG17 SEG25 SEG25 SEG25 SEG25
10
SEG2 SEG2 SEG2 SEG2 SEG10 SEG10 SEG10 SEG10 SEG18 SEG18 SEG18 SEG18 SEG26 SEG26 SEG26 SEG26
11
12
SEG3 SEG3 SEG3 SEG3 SEG11 SEG11 SEG11 SEG11 SEG19 SEG19 SEG19 SEG19 SEG27 SEG27 SEG27 SEG27
SEG4 SEG4 SEG4 SEG4 SEG12 SEG12 SEG12 SEG12 SEG20 SEG20 SEG20 SEG20 SEG28 SEG28 SEG28 SEG28
13
SEG5 SEG5 SEG5 SEG5 SEG13 SEG13 SEG13 SEG13 SEG21 SEG21 SEG21 SEG21 SEG29 SEG29 SEG29 SEG29
14
SEG6 SEG6 SEG6 SEG6 SEG14 SEG14 SEG14 SEG14 SEG22 SEG22 SEG22 SEG22 SEG30 SEG30 SEG30 SEG30
15
SEG7 SEG7 SEG7 SEG7 SEG15 SEG15 SEG15 SEG15 SEG23 SEG23 SEG23 SEG23 SEG31 SEG31 SEG31 SEG31
COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
COM
Fig 45. LCD RAM map
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Page 45 of 146
455A Group
(4) LCD drive waveform
When “1” is written to a bit in the LCD RAM data, the voltage
difference between common pin and segment pin which
correspond to the bit automatically becomes lV LC3 l and the
display pixel at the cross section turns on.
When returning from reset, and in the RAM back-up mode, a
display pixel turns off because every segment output pin and
common output pin becomes VLC3 level.
1/2 Duty, 1/2 Bias: When writing (XX10)2 to address M (1, 14, 8) in RAM.
1 flame
M (1, 14, 8)
COM0
(2/F)
1/F
Voltage level
0 (bit 0)
VLC3
VLC1=VLC2
VSS
COM1
COM1
1
X
COM0
X (bit 3)
VLC3
VLC1=VLC2
VSS
SEG16
SEG16
COM1
SEG16
COM 0
SEG16
ON
OFF
1/3 Duty, 1/3 Bias: When writing (X101)2 to address M (1, 14, 8) in RAM.
1 flame (3/F)
M (1, 14, 8)
COM0
1/F
Voltage level
1 (bit 0)
COM1
COM2
0
COM2
VLC3
VLC2
VLC1
VSS
1
X (bit 3)
SEG16
COM1
COM0
SEG16
COM2
SEG16
COM1
SEG16
COM0
SEG16
ON
OFF
ON
VLC3
VLC2
VLC1
VSS
1/4 Duty, 1/3 Bias: When writing (1010)2 to address M (1, 14, 8) in RAM.
1 flame
M (1, 14, 8)
COM0
COM1
COM2
COM3
SEG16
(4/F)
1/F
Voltage level
0 (bit 0)
VLC3
VLC2
VLC1
VSS
COM3
1
0
1 (bit 3)
COM2
COM1
COM0
F : LCD clock frequency
SEG16
X: Set an arbitrary value.
(These bits are not related to
set the drive waveform at each duty.)
Fig 46. LCD controller/driver structure
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 46 of 146
COM3
SEG16
COM2
SEG16
COM 1
SEG16
COM0
SEG16
ON
OFF
ON
OFF
VLC3
VLC2
VLC1
VSS
455A Group
(5) LCD power supply circuit
Select the LCD power supply circuit suitable for the using LCD
panel.
The LCD power supply circuit is fixed by the followings;
• The internal dividing resistor is controlled by bit 0 of register
L2.
• The internal dividing resistor is selected by bit 3 of register L1.
• The bias condition is selected by bits 0 and 1 of register L1.
• Internal dividing resistor
The 4553 Group has the internal dividing resistor for LCD power
supply.
When bit 0 of register L2 is set to ì0î, the internal dividing
resistor is valid. However, when the LCD is turned off by setting
bit 2 of register L1 to ì0î, the internal dividing resistor is turned
off.
The same six resistor (r) is prepared for the internal dividing
resistor.
According to the setting value of bit 3 of register L1 and using
bias condition, the resistor is prepared as follows;
• L13 = “0”, 1/3 bias used: 2r × 3 = 6r
• L13 = “0”, 1/2 bias used: 2r × 2 = 4r
• L13 = “1”, 1/3 bias used: r × 3 = 3r
• L13 = “1”, 1/2 bias used: r × 2 = 2r
• SEG0/VLC3 pin
The selection of SEG0/VLC3 pin function is controlled with the
bit 3 of register L2.
When the VLC3 pin function is selected, apply voltage of VLC3 <
VDD to the pin externally.
When the SEG0 pin function is selected, VLC3 is connected to
VDD internally.
• SEG1/VLC2, SEG2/VLC1 pin
The selection of SEG1/VLC2 pin function is controlled with the
bit 2 of register L2.
The selection of SEG2/VLC1 pin function is controlled with the
bit 1 of register L2.
When the VLC2 pin and VLC1 pin functions are selected and the
internal dividing resistor is not used, apply voltage of 0 < VLC1 <
VLC2 < VLC3 to these pins. Short the VLC2 pin and VLC1 pin at
1/2 bias.
When the VLC2 pin and VLC1 pin functions are selected and the
internal dividing resistor is used, the dividing voltage value
generated internally is output from the VLC1 pin and VLC2 pin.
The VLC2 pin and VLC1 pin have the same electric potential at
1/2 bias.
When SEG1 and SEG2 pin functions are selected, use the
internal dividing resistor (L20 = ”0”). In this time, VLC2 and
VLC1 are connected to the generated dividing voltage.
External power supply
VLC3
VLC3
SEG0
VLC3
VLC2
SEG1
VLC2
SEG1
VLC1
SEG2
VLC1
SEG2
VSS
VSS
(a) Register L2 = (0000)2
(b) Register L2 = (1000)2
External power supply
VLC3
VLC3
External power supply
VLC3
VLC2
VLC2
VLC2
VLC1
VLC1
VLC1
VSS
VLC2
VLC1
VSS
(c) Register L2 = (1110)2
(d) Register L2 = (1111)2
Fig 47. LCD power supply circuit example (1/3 bias condition selected)
Rev.1.01 Feb 15, 2008
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VLC3
Page 47 of 146
455A Group
(6) LCD control register
• LCD control register L1
Register L1 controls duty/bias selection, LCD operation, internal
dividing resistor selection. Set the contents of this register
through register A with the TL1A instruction. The TAL1
instruction can be used to transfer the contents of register L1.
• LCD control register L2
Register L2 controls internal dividing resistor operation,
selection of pin functions; SEG0/VLC3, SEG1/VLC2, SEG2/VLC1.
Set the contents of this register through register A with the TL2A
instruction.
• LCD control register L3
Register L3 controls selection of pin functions; P20/SEG24 to
P23/SEG27. Set the contents of this register through register A
with the TL3A instruction.
• LCD control register C1
Register C1 controls selection of pin functions; P00/SEG16 to
P03/SEG19. Set the contents of this register through register A
with the TC1A instruction.
• LCD control register C2
Register C2 controls selection of pin functions; P10/SEG20 to
P13/SEG23. Set the contents of this register through register A
with the TC2A instruction.
• LCD control register C3
Register C3 controls selection of pin functions; P30/SEG28 to
P33/SEG31. The contents of this register through register A with
the TC3A instruction.
Table 19 LCD control registers (1)
LCD control register L1
L13
Internal dividing resistor for LCD power
supply selection bit (Note 2)
L12
LCD control bit
L11
LCD duty and bias selection bits
L10
at reset : 00002
0
1
0
1
L11
Not available
Not available
0
1
1/2
1/2
1
0
1/3
1/3
1
1
1/4
1/3
supply control bit
1
SEG1/VLC2 pin function switch bit (Note 4)
L21
SEG2/VLC1 pin function switch bit (Note 4)
L20
at reset : 00002
Internal dividing resistor for LCD power
L22
LCD control register L3
at power down : state retained
P23/SEG27 pin function switch bit
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W
TL2A
SEG0
VLC3
SEG1
VLC2
SEG2
VLC1
Internal dividing resistor valid
Internal dividing resistor invalid
at reset : 11112
at power down : state retained
0 SEG27
1 P23
0 SEG26
L32 P22/SEG26 pin function switch bit
1 P22
0 SEG25
L31 P21/SEG25 pin function switch bit
1 P21
0 SEG24
L30 P20/SEG24 pin function switch bit
1 P20
Note 1.“R” represents read enabled, and “W” represents write enabled.
Note 2.“r (resistor) multiplied by 3” is used at 1/3 bias, and “r multiplied by 2” is used at 1/2 bias.
Note 3.VLC3 is connected to VDD internally when SEG0 pin is selected.
Note 4.Use internal dividing resistor when SEG1 and SEG2 pins are selected.
L33
Bias
0
0
1
0
1
0
1
0
SEG0/VLC3 pin function switch bit (Note 3)
Duty
0
LCD control register L2
L23
2r × 3, 2r × 2
r × 3, r × 2
Stop (OFF)
Operating
L1
R/W
TAL1/TL1A
at power down : state retained
W
TL3A
455A Group
Table 20 LCD control registers (2)
LCD control register C1
C13 P03/SEG19 pin function switch bit
C12 P02/SEG18 pin function switch bit
C11 P01/SEG17 pin function switch bit
C10 P00/SEG16 pin function switch bit
at reset : 11112
0
1
0
1
0
1
0
1
LCD control register C2
C23 P13/SEG23 pin function switch bit
C22 P12/SEG22 pin function switch bit
C21 P11/SEG21 pin function switch bit
C20 P10/SEG20 pin function switch bit
LCD control register C3
C33 P33/SEG31 pin function switch bit
C32 P32/SEG30 pin function switch bit
C31 P31/SEG29 pin function switch bit
C30 P30/SEG28 pin function switch bit
SEG31
P33
SEG30
P32
SEG29
P31
SEG28
P30
Note 1.“R” represents read enabled, and “W” represents write enabled.
Rev.1.01 Feb 15, 2008
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Page 49 of 146
at power down : state retained
W
TC2A
at power down : state retained
W
TC3A
SEG23
P13
SEG22
P12
SEG21
P11
SEG20
P00
at reset : 11112
0
1
0
1
0
1
0
1
W
TC1A
SEG19
P03
SEG18
P02
SEG17
P01
SEG16
P00
at reset : 11112
0
1
0
1
0
1
0
1
at power down : state retained
455A Group
RESET FUNCTION
System reset is performed by the followings:
• “L” level is applied to the RESET pin externally,
• System reset instruction (SRST) is executed,
• Reset occurs by watchdog timer,
• Reset occurs by built-in power-on reset
• Reset occurs by voltage drop detection circuit
Then when “H” level is applied to RESET pin, software starts
from address 0 in page 0.
(Note 1)
Pull-up transistor
Voltage drop
detection circuit
Internal reset signal
RESET pin
(Note 2)
(Note 1)
Power-on reset circuit
SRST instruction
Watchdog reset signal
WEF
Notes 1:
This symbol represents a parasitic diode.
2: Applied potential to RESET pin must be VDD or less.
Fig 48. Structure of RESET pin and its peripherals
Table 21 Port state at reset
Name
Function
D0−D4
D0−D4
D5/INT
D5
XCIN/D6, XCOUT/D7
XCIN, XCOUT
P00/SEG16−P03/SEG19
P00−P03
P10/SEG20−P13/SEG23
P10−P13
P20/SEG24−P23/SEG27
P20−P23
P30/SEG28−P33/SEG31
P30−P33
SEG0/VLC3−SEG2/VLC1
SEG0−SEG2
SEG3−SEG15
SEG3−SEG15
COM0−COM3
COM0−COM3
C/CNTR
C/CNTR
Note 1. Output latch is set to “1.”
Note 2. The output structure is N-channel open-drain.
Note 3. Pull-up transistor is turned OFF.
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 50 of 146
State
High-impedance (Notes 1, 2)
High-impedance (Notes 1, 2)
Sub-clock input
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
VLC3 (VDD) level
VLC3 (VDD) level
VLC3 (VDD) level
“L” (VSS) level
455A Group
(1) RESET pin input
System reset is performed certainly by applying “L” level to
RESET pin for 1 machine cycle or more when the following
condition is satisfied;
the value of supply voltage is the minimum value or more of the
recommended operating conditions.
=
Reset input
1 machine cycle or more
0.85VDD
RESET
Program starts
(address 0 in page 0)
0.3VDD
(Note 1)
f(HSOCO)
High-speed on-chip oscillator (internal oscillator) is
counted 1376 times (Note 2).
Notes 1: Keep the value of supply voltage to the minimum value or more of the
recommended operating conditions.
2: It depends on the internal state at reset.
Fig 49. RESET pin input waveform and reset release timing
(2) Power-on reset
Reset can be automatically performed at power on (power-on
reset) by the built-in power-on reset circuit. When the built-in
power-on reset circuit is used, set the time for the supply voltage
to rise from 0 V to the minimum voltage of recommended
operating conditions to 100 µs or less.
If the rising time exceeds 100 µs, connect a capacitor between
the RESET pin and Vss at the shortest distance, and input “L”
level to RESET pin until the value of supply voltage reaches the
minimum operating voltage.
(3) System reset instruction (SRST)
By executing the SRST instruction, “L” level is output to RESET
pin and system reset is performed.
100µs or less
VDD (Note)
Power-on reset
circuit output
Internal reset signal
Power-on Reset Reset
state released
Note: Keep the value of supply voltage to
the minimum value or more of the
recommended operating conditions.
Fig 50. Power-on reset operation
Rev.1.01 Feb 15, 2008
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Page 51 of 146
455A Group
(4) Internal state at reset
Figure 51 and 52 shows internal state at reset (they are the same
after system is released from reset). The contents of timers,
registers, flags and RAM except shown in Figure 51 and 52 are
undefined, so set the initial value to them.
• Program counter (PC)
Address 0 in page 0 is set to program counter.
0
0
0
0
0
0
0
0
0
0
0
• Interrupt enable flag (INTE)
0
(Interrupt disabled)
• Power down flag (P)
0
• External 0 interrupt request flag (EXF0)
0
• Interrupt control register V1
0
0
0
0
(Interrupt disabled)
• Interrupt control register V2
0
0
0
0
(Interrupt disabled)
• Interrupt control register I1
0
0
0
0
• Timer 1 interrupt request flag (T1F)
0
• Timer 2 interrupt request flag (T2F)
0
• Timer 3 interrupt request flag (T3F)
0
• Watchdog timer flags (WDF1, WDF2)
0
• Watchdog timer enable flag (WEF)
1
• Timer control register PA
0
(Prescaler stopped)
• Timer control register W1
0
0
0
0
(Timer 1 stopped)
• Timer control register W2
0
0
0
0
(Timer 2 stopped)
•Timer control register W3
0
0
0
0
(Timer 3 stopped)
• Timer control register W4
0
0
0
0
(Timer LC stopped)
• Timer control register W5
0
0
0
0
• Clock control register MR
1
1
0
0
• Clock control register RG
1
0
0
0
• LCD control register L1
0
0
0
0
• LCD control register L2
0
0
0
0
• LCD control register L3
1
1
1
1
• LCD control register C1
1
1
1
1
• LCD control register C2
1
1
1
1
• LCD control register C3
1
1
1
1
Fig 51. Internal state at reset (1)
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0
0
0
455A Group
• Key-on wakeup control register K0
0
0
0
0
• Key-on wakeup control register K1
0
0
0
0
• Key-on wakeup control register K2
0
0
0
0
• Key-on wakeup control register K3
0
0
0
0
• Pull-up control register PU0
0
0
0
0
• Pull-up control register PU1
0
0
0
0
• Pull-up control register PU2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
• Pull-up control register PU3
• Port output structure control register FR0
• Port output structure control register FR1
• Port output structure control register FR2
• Port output structure control register FR3
• High-order bit reference enable flag (UPTF)
0
• Carry flag (CY)
0
• Register A
0
0
0
0
• Register B
0
0
0
0
×
×
×
×
×
×
×
• Register X
0
0
0
0
• Register Y
0
0
0
0
×
×
1
1
• Register D
×
• Register E
×
×
×
• Register Z
• Stack pointer (SP)
1
• Operation source clock
High-speed on-chip oscillator (operating)
• Ceramic resonator circuit
Operating
• Low-speed on-chip oscillator
Stop
• Quartz-crystal oscillator
Operating
“X” represents undefined.
Fig 52. Internal state at reset (2)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 53 of 146
455A Group
VOLTAGE DROP DETECTION CIRCUIT (WITH SKIP
JUDGMENT)
The built-in voltage drop detection circuit is used to set the
voltage drop detection circuit flag (VDF) or to perform system
reset.
EPOF instruction + POF instruction
EPOF instruction + POF2 instruction
Internal reset signal
T3UDF
Key-on wakeup signal
SVDE instruction
S
Q
R
Q
S
Q
Oscillation stop signal
VDD
−
Internal reset signal
VRST−/VRST+
R
Voltage drop detection
circuit reset signal
＋
Reset occurrence
(Note 1)
VDCE
(Note 2)
VDD
−
(Note 1)
VSKIP
＋
Voltage drop detection
circuit flag
VDF
Skip judgement
Flag occurrence
Voltage drop
detection circuit
Notes 1:
This symbol represents a parasitic diode.
2: Applied potential to RESET pin must be VDD or less.
Fig 53. Voltage drop detection reset circuit
(1) Operating state of voltage drop detection circuit
The voltage drop detection circuit becomes valid by inputting
“H” to the VDCE pin and it becomes invalid by inputting “L.”
When not executing the SVDE instruction under “H” level of the
VDCE pin, the voltage drop detection circuit become invalid in
power down state (RAM back-up, clock operating mode). As for
this, the voltage drop detection circuit becomes valid at returning
from power down, again.
When executing the SVDE instruction under “H” level of the
VDCE pin, the voltage drop detection circuit becomes valid in
power down state (RAM back-up, clock operating mode).
The state of executing SVDE instruction can be cleared by
system reset.
Table 22 Operating state of voltage drop detection circuit
VDCE pin
SVDE instruction
at CPU operating
No execute
×
“L”
Execute
×
No execute
O
“H”
Execute
O
Note. “O” indicates valid, “×” indicates invalid.
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REJ03B0224-0101
Page 54 of 146
at power down
×
×
×
O
455A Group
(2) Voltage drop detection circuit flag (VDF)
Voltage drop detection circuit flag (VDF) is set to “1” when the
supply voltage goes the skip occurrence voltage (VSKIP) or less.
Moreover, voltage drop detection circuit flag (VDF) is cleared to
“0” when the supply voltage goes the skip occurrence voltage
(VSKIP) or more. The state of the voltage drop detection circuit
flag (VDF) can be examined with the skip instruction (SNZVD).
Even when the skip instruction is executed, the voltage drop
detection circuit flag is not cleared to “0”.
Refer to the electrical characteristics for skip occurrence voltage
value.
(3) Voltage drop detection circuit reset
System reset is performed when the supply voltage goes the reset
occurrence voltage (VRST-) or less.
When the supply voltage goes reset release voltage (VRST+) or
more, the oscillation circuit goes to be in the operating enabled
state and system reset is released .
Refer to the electrical characteristics for reset occurrence value
and reset release voltage value.
VDD
VSKIP (skip occurrence voltage)
VRST+(reset release voltage)
VRST-(reset occurrence voltage)
Voltage drop detection circuit
flag (VDF)
Voltage drop
detection circuit
reset signal
(Note 1)
Note 1: Microcomputer starts operation after high-speed on-chip oscillator clock is counted 1376 times.
Fig 54. Voltage drop detection circuit operation waveform
VDD
Recommended operating condition
min.value
VRST+
VRSTNo reset
Program failure may occur.
Normal operation
VDD
Recommended operating condition
min.value
VRST+
VRSTReset
Fig 55. VDD and VRST-
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REJ03B0224-0101
Page 55 of 146
(4) Note on voltage drop detection circuit
The voltage drop detection circuit detection voltage of this
product is set up lower than the minimum value of the supply
voltage of the recommended operating conditions.
When the supply voltage of a microcomputer falls below to the
minimum value of recommended operating conditions and
regoes up, depending on the capacity value of the bypass
capacitor added to the power supply pin, the following case may
cause program failure (Figure 55);
supply voltage does not fall below to VRST-, and its voltage regoes up with no reset.
In such a case, please design a system which supply voltage is
once reduced below to VRST- and re-goes up after that.
455A Group
POWER DOWN FUNCTION
The 455A Group has 2-type power down functions.
System enters into each power down state by executing the
following instructions.
• Clock operating mode ................. EPOF and POF instructions
• RAM back-up mode ................... EPOF and POF2 instructions
When the EPOF instruction is not executed before the POF or
POF2 instruction is executed, these instructions are equivalent to
the NOP instruction.
(1) Clock operating mode
The following functions and states are retained.
• RAM
• Reset circuit
• XCIN–XCOUT oscillation
• LCD display
• Timer 3
• Low-speed on-chip oscillator
(2) RAM back-up mode
The following functions and states are retained.
• RAM
• Reset circuit
(3) Warm start condition
The system returns from the power down state when;
• External wakeup signal is input
• Timer 3 underflow occurs
in the power down mode.
In either case, the CPU starts executing the software from
address 0 in page 0. In this case, the P flag is “1.”
(4) Cold start condition
The CPU starts executing the software from address 0 in page 0
when;
• external “L” level is input to RESET pin,
• execute system reset instruction (SRST instruction)
• reset by watchdog timer is performed
• reset by internal power-on reset, or
• reset by the voltage drop detection circuit is performed.
In this case, the P flag is “0.”
(5) Identification of the start condition
Warm start or cold start can be identified by examining the state
of the power down flag (P) with the SNZP instruction.
(6) Identification of the return condition using the timer
3 interrupt request flag
When the system returns from the power down mode, the
following conditions can be identified by examining the state of
the timer 3 interrupt request flag (T3F):
• When T3F = “1”, return by timer 3 underflow (time elapse)
• When T3F = “0”, return by key-on wakeup (key input)
Rev.1.01 Feb 15, 2008
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Page 56 of 146
Table 23 Functions and states retained at power down
mode
Function
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note
2)
Contents of RAM
Interrupt control registers V1, V2
Interrupt control registers I1, V2
Selected oscillation circuit
Clock control register MR, RG
Timer 1, Timer 2 functions
Timer 3 function
Timer LC function
Watchdog timer function
Timer control registers PA, W2
Timer control registers W1, W3, W4, W5
LCD display function
LCD control registers L1 to L3, C1 to C3
Voltage drop detection circuit
Port level
Key-on wakeup control registers K0 to K3
Pull-up control registers PU0 to PU3
Port output structure control registers
FR0 to FR3
External interrupt request flags (EXF0)
Timer interrupt request flags (T1F, T2F)
Timer interrupt request flag (T3F)
Interrupt enable flag (INTE)
Voltage drop detection circuit flag (VDF)
Watchdog timer flags (WDF1, WDF2)
Watchdog timer enable flag (WEF)
Power down mode
Clock
RAM
operating back-up
×
×
O
×
O
O
O
(Note 3)
O
O
× (Note
4)
×
O
O
O
(Note 6)
(Note 7)
O
O
O
×
O
O
O
(Note 3)
O
(Note 3)
× (Note
4)
×
O
(Note 5)
O
(Note 6)
(Note 7)
O
O
O
O
×
(Note 3)
O
×
×
× (Note
4)
× (Note
4)
×
(Note 3)
O
×
×
× (Note
4)
× (Note
4)
Note 1. “O” represents that the function can be retained, and “×”
represents that the function is initialized.
Registers and flags other than the above are undefined at
power down mode, and set an initial value after returning.
Note 2. The stack pointer (SP) points the level of the stack
register and is initialized to “7” at power down mode.
Note 3. The state of the timer is undefined.
Note 4. Initialize the WDF1 flag with the WRST instruction, and
then go into the power down state.
Note 5. LCD is turned off.
Note 6. When the SVDE instruction is executed, this function is
valid at power down.
Note 7. In the power down mode, C/CNTR pin outputs “L” level.
However, when the CNTR input is selected (W11 ,
W1 0 =“11”), C/CNTR pin is in an input enabled state
(output = high-impedance).
Other ports retain their respective output levels.
455A Group
(7) Return signal
An external wakeup signal or timer 3 interrupt request flag (T3F)
is used to return from the clock operating mode.
An external wakeup signal is used to return from the RAM backup mode because the oscillation is stopped.
Table 24 shows the return condition for each return source.
(8) Control registers
• Key-on wakeup control register K0
Register K0 controls the ports P0 and P1 key-on wakeup
function. Set the contents of this register through register A
with the TK0A instruction. In addition, the TAK0 instruction
can be used to transfer the contents of register K0 to register A.
• Key-on wakeup control register K1
Register K1 controls the port P2 key-on wakeup function. Set
the contents of this register through register A with the TK1A
instruction. In addition,the TAK1 instruction can be used to
transfer the contents of register K1 to register A.
• Key-on wakeup control register K2
Register K2 controls the port P3 and INT pin key-on wakeup
function and the selection of return condition of INT pin. Set
the contents of this register through register A with the TK2A
instruction. In addition, the TAK2 instruction can be used to
transfer the contents of register K2 to register A.
• Key-on wakeup control register K3
Register K3 controls the port D 0 to D7 pin key-on wakeup
function. Set the contents of this register through register A
with the TK3A instruction. In addition, the TAK3 instruction
can be used to transfer the contents of register K3 to register A.
• Pull-up control register PU0
Register PU0 controls the ON/OFF of the port P0 and P1 pullup transistor. Set the contents of this register through register
A with the TPU0A instruction. In addition, the TAPU0
instruction can be used to transfer the contents of register PU0
to register A.
• Pull-up control register PU1
Register PU1 controls the ON/OFF of the port P2 pull-up
transistor. Set the contents of this register through register A
with the TPU1A instruction. In addition, the TAPU1
instruction can be used to transfer the contents of register PU1
to register A.
• Pull-up control register PU2
Register PU2 controls the ON/OFF of the ports P3 pull-up
transistor. Set the contents of this register through register A
with the TPU2A instruction. In addition, the TAPU2
instruction can be used to transfer the contents of register PU2
to register A.
• Pull-up control register PU3
Register PU3 controls the ON/OFF of the ports D0 to D7 pullup transistor. Set the contents of this register through register
A with the TPU3A instruction. In addition, the TAPU3
instruction can be used to transfer the contents of register PU3
to register A.
• External interrupt control register I1
Register I1 controls the input control and the selection of valid
waveform/level of INT pin. Set the contents of this register
through register A with the TI1A instruction. In addition, the
TAI1 instruction can be used to transfer the contents of register
I1 to register A.
External wakeup signal
Table 24 Return source and return condition
Return source
Ports P00−P03
Ports P10−P13
Ports P20−P23
Ports P30−P33
Ports D0−D7
Return condition
Return by an external falling edge (“H” → “L”).
Remarks
For ports P0, P1, P3 and D0 to D7 the key-on
wakeup function can be selected by two port unit,
for port P2, it can be selected by a unit.
INT pin
Return by an external “H” level or “L” level
input, or rising edge (“L” → “H”) or falling edge
(“H” → “L”).
When the return level is input, the interrupt
request flag (EXF0) is not set.
Return by timer 3 underflow or by setting T3F
to “1”.
It can be used in the clock operating mode.
Select the return level (“L” level or “H” level) with
register I1 and return condition (return by level or
edge) with register K2 according to the external
state before going into the power down state.
Timer 3 interrupt request flag
(T3F)
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REJ03B0224-0101
Page 57 of 146
Clear T3F with the SNZT3 instruction before
system enters into the power down state.
When system enters into the power down state
while T3F is “1”, system returns from the state
immediately because it is recognized as return
condition.
455A Group
Key-on wakeup
Timer 3 underflow
(Stabilizing time [c] )
MR1, MR0 ← 01
Key-on wakeup
Timer 3 underflow
(Stabilizing time [b] )
Internal mode
EPOF + POF2 instruction
execution
A
Operation state
Operation source clock:
f(HSOCO)
High-speed on-chip oscillator
MR1, MR0 ← 00
Key-on wakeup
(Stabilizing time [b] )
MR1, MR0 ← 10
Low-speed mode
EPOF + POF instruction
execution
EPOF + POF2 instruction
execution
C
Operation state
Operation source clock: f(XCIN)
Quartz-crystal oscillation
EPOF + POF instruction
execution
MR1, MR0 ← 11
MR1, MR0 ← 01
Key-on wakeup
Timer 3 underflow
(Stabilizing time [d] )
Stabilizing time
Stabilizing time
Stabilizing time
Stabilizing time
Stabilizing time
MR1, MR0 ← 00
MR1, MR0 ← 01
MR1, MR0 ← 11
MR1, MR0 ← 10
Key-on wakeup
(Stabilizing time [d] )
EPOF + POF2
instruction execution
Internal low-speed mode
D
Operation state
Operation source clock: f(LSOCO)
Low-spped on-chip oscillator
Key-on wakeup
Timer 3 underflow
(Stabilizing time [e] )
MR1, MR0 ← 11
Reset
(Stabilizing time [a] )
F
RAM back-up mode
Key-on wakeup
(Stabilizing time [c] )
Operation source clock: f(XIN)
Ceramic resonator
EPOF + POF instruction
execution
f(HSOCO): stop
f(XIN): stop
f(XCIN),
f(LSOCO)：
by RG register
EPOF + POF2 instruction
execution
B
Operation state
MR1, MR0 ← 00
Clock operating mode
High-speed mode
EPOF + POF instruction
execution
MR1, MR0 ← 10
E
f(HSOCO): stop
f(XIN): stop
f(XCIN): stop
f(LSOCO): stop
Key-on wakeup
(Stabilizing time [e] )
[a] : Microcomputer starts its operation after counting the f(HSOCO) to 1376 times.
[b] : Microcomputer starts its operation after counting the f(HSOCO) to (system clock division ratio X 15) times.
[c] : Microcomputer starts its operation after counting the f(XIN) to (system clock division ratio X 171) times.
[d] : Microcomputer starts its operation after counting the f(XCIN) to (system clock division ratio X 171) times.
[e] : Microcomputer starts its operation after counting the f(LSOCO) to (system clock division ratio X 15) times.
Notes 1. The system clock selected by the clock control registers MR and RG is retained at power down.
The oscillation stability time at return can be adjusted by setting the clock control registers MR and RG before transiting to
the power down state.
2. To transmit to the clock operating mode, the EPOF and POF instructions must be executed continuously.
3. To transmit to the RAM back-up mode, the EPOF and POF2 instructions must be executed continuously.
4. After reset release, the main clock (f(XIN)), the sub-clock, and the internal clock (f(HSOCO)) are enabled.
5. To select a stopped clock as the system clock, first start the clock selected by the clock control register RG and generate
the oscillation stability time by software. Then switch the system clock.
Fig 56. State transition
Power down flag P
POF or
EPOF instruction + POF2
instruction
S
Q
Program start
P
SNZP
instruction
R
Reset input
P = “1”
?
No
Cold start
POF or
EPOF instruction + POF2
instruction
Clear source • • • • • • System reset
Set source
Warm start
Yes
Yes
•••••••
Fig 57. Set source and clear source of the P flag
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 58 of 146
Return from
timer 3 underflow
T3F = “1”
?
No
SNZT3
instruction
Return from
external wakeup signal
Fig 58. Start condition identified example using the
SNZP instruction
455A Group
Table 25 Key-on wakeup control register
Key-on wakeup control register K0
K03
Ports P12 and P13 key-on wakeup
control bit
K02
Ports P10 and P11 key-on wakeup
control bit
K01
Ports P02 and P03 key-on wakeup
control bit
K00
Ports P00 and P01 key-on wakeup
control bit
at reset : 00002
0
1
0
1
0
1
0
1
Key-on wakeup control register K1
K13 Port P23 key-on wakeup control bit
K12 Port P22 key-on wakeup control bit
K11 Port P21 key-on wakeup control bit
K10 Port P20 key-on wakeup control bit
Key-on wakeup control register K2
K23
Ports P32 and P33 key-on wakeup
control bit
K22
Ports P30 and P31 key-on wakeup
control bit
K21 INT pin return condition selection bit
K20 INT pin key-on wakeup control bit
Key-on wakeup control register K3
at power down : state retained
at power down : state retained
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Page 59 of 146
R/W
TAK2/TK2A
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Return by level
Return by edge
Key-on wakeup invalid
Key-on wakeup valid
at reset : 00002
at power down : state retained
0 Key-on wakeup not used
1 Key-on wakeup used
0 Key-on wakeup not used
K32 Ports D4 and D5 key-on wakeup control bit
1 Key-on wakeup used
0 Key-on wakeup not used
K31 Ports D2 and D3 key-on wakeup control bit
1 Key-on wakeup used
0 Key-on wakeup not used
K30 Ports D0 and D1 key-on wakeup control bit
1 Key-on wakeup used
Note 1. “R” represents read enabled, and “W” represents write enabled.
K33 Ports D6 and D7 key-on wakeup control bit
R/W
TAK1/TK1A
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
at reset : 00002
0
1
0
1
0
1
0
1
R/W
TAK0/TK0A
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
at reset : 00002
0
1
0
1
0
1
0
1
at power down : state retained
R/W
TAK3/TK3A
455A Group
Table 26 Pull-up control register
Pull-up control register PU0
PU03
Port P12 and P13 pull-up transistor control
bit
PU02
Port P10 and P11 pull-up transistor control
bit
PU01
Port P02 and P03 pull-up transistor control
bit
PU00
Port P00 and P01 pull-up transistor control
bit
at reset : 00002
0
1
0
1
0
1
0
1
Pull-up control register PU1
PU13 Port P23 pull-up transistor control bit
PU12 Port P22 pull-up transistor control bit
PU11 Port P21 pull-up transistor control bit
PU10 Port P20 pull-up transistor control bit
Pull-up control register PU2
PU23 Port P33 pull-up transistor control bit
PU22 Port P32 pull-up transistor control bit
PU21 Port P31 pull-up transistor control bit
PU20 Port P30 pull-up transistor control bit
Pull-up control register PU3
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R/W
TAPU1/TPU1A
at power down : state retained
R/W
TAPU2/TPU2A
at power down : state retained
R/W
TAPU3/TPU3A
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
at reset : 00002
0 Pull-up transistor OFF
1 Pull-up transistor ON
0 Pull-up transistor OFF
PU32 Port D4 and D5 pull-up transistor control bit
1 Pull-up transistor ON
0 Pull-up transistor OFF
PU31 Port D2 and D3 pull-up transistor control bit
1 Pull-up transistor ON
0 Pull-up transistor OFF
PU30 Port D0 and D1 pull-up transistor control bit
1 Pull-up transistor ON
Note 1.“R” represents read enabled, and “W” represents write enabled.
PU33 Port D6 and D7 pull-up transistor control bit
at power down : state retained
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
at reset : 00002
0
1
0
1
0
1
0
1
R/W
TAPU0/TPU0A
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
at reset : 00002
0
1
0
1
0
1
0
1
at power down : state retained
455A Group
Table 27 Interrupt control register
Interrupt control register I1
at reset : 00002
R/W
TAI1/TI1A
INT pin input disabled
INT pin input enabled
Falling waveform (“L” level of INT pin is recognized with the SNZI0
0
instruction)/“L” level
Interrupt valid waveform for INT pin/
I12
return level selection bit (Note 2)
Rising waveform (“H” level of INT pin is recognized with the SNZI0
1
instruction)/“H” level
0 One-sided edge detected
I11 INT pin edge detection circuit control bit
1 Both edges detected
0 Timer 1 count start synchronous circuit not selected
INT pin timer 1 count start synchronous
I10
circuit selection bit
1 Timer 1 count start synchronous circuit selected
Note 1. “R” represents read enabled, and “W” represents write enabled.
Note 2. When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set.
I13
INT pin input control bit (Note 2)
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Page 61 of 146
0
1
at power down : state retained
455A Group
CLOCK CONTROL
The clock control circuit consists of the following circuits.
• High-speed on-chip oscillator
• Ceramic resonator
• Low-speed on-chip oscillator
• Quartz-crystal oscillation circuit
• Frequency divider
• Internal clock generating circuit
The system clock and the instruction clock are generated as the
source clock for operation by these circuits.
Figure 59 shows the structure of the clock control circuit.
The 455A Group operates by the high-speed on-chip oscillator
clock (f(HSOCO)) which is the internal oscillator after system is
released from reset.
The quartz-crystal oscillator can be used for sub-clock (f(XCIN)).
Division circuit
MR1, MR0
00
High-speed on-chip oscillator
(internal oscillator)
01
Divided by 8
Divided by 4
Divided by 2
10
MR3, MR2
11
System clock (STCK)
10
01
00
Internal clock
generating circuit
(divided by 3)
Instruction clock
(INSTCK)
11
RG0
XIN
XOUT
Ceramic
resonance
RG1
Internal reset signal
T3F signal
Q S
R
XCIN
XCOUT
Quartz-crystal
oscillation
Q S
R
RG2
Low-speed on-chip oscillator
(Low-speed internal oscillator)
RG3
Fig 59. Clock control circuit structure
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Key-on wakeup signal
EPOF instruction + POF instruction
Page 62 of 146
EPOF instruction + POF2 instruction
455A Group
(1) High-speed on-chip oscillator operation
After system is released from reset, the MCU starts operation by
the clock output from the high-speed on-chip oscillator which is
the internal oscillator.
The clock frequency of the high-speed on-chip oscillator depends
on the supply voltage and the operation temperature range.
Be careful that variable frequencies when designing application
products.
(2) Main clock generating circuit (f(XIN))
After reset release, the ceramic oscillation is valid for the main
clock. Connect the ceramic oscillator and the external circuit to
pins X IN and X OUT at the shortest distance (Figure 61). A
feedback resistor is built in between pins XIN and XOUT.
If the main clock is not used, connect the XIN pin to VSS and
leave the XOUT pin open.
455A
XIN
XOUT
Fig 60. Handling of XIN and XOUT when operating onchip oscillator
455A
(3) Low-speed on-chip oscillator operation
After system is released from reset, the low-speed on-chip
oscillator turns invalid which is the internal oscillator.
Oscillator operation/stopping and the control of system clock
selection are operated by the register RG and MR.
The clock frequency of the low-speed on-chip oscillator depends
on the supply voltage and the operation temperature range.
Be careful that variable frequencies when designing application
products.
XIN
XOUT
Rd
CIN
COUT
Note: Externally connect a damping resistor Rd
depending on the oscillation frequency.
(A feedback resistor is built-in.)
Use the resonator manufacturer’s recommended
value because constants such as capacitance
depend on the resonator.
Fig 61. Ceramic resonator external circuit
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Page 63 of 146
455A Group
(4) External clock
When the external clock signal is used as the main clock
(f(XIN)), connect the XIN pin to the clock source and leave XOUT
pin open (Figure 62).
Be careful that the maximum value of the oscillation frequency
when using the external clock differs from the value when using
the ceramic resonator (refer to the recommended operating
condition). Also, note that the power down mode (POF and
POF2 instructions) cannot be used when using the external clock.
(5) Sub-clock generating circuit f(XCIN)
Sub-clock signal f(XCIN) is obtained by externally connecting a
quartz-crystal oscillator. Connect this external circuit and a
quartz-crystal oscillator to pins XCIN and XCOUT at the shortest
distance. A feedback resistor is built in between pins XCIN and
XCOUT (Figure 63). XCIN pin and XCOUT pin are also used as
ports D6 and D7, respectively. The sub-clock oscillation circuit is
invalid and the function of ports D6 and D7 are valid by setting
bit 2 of register RG to “1”.
When sub-clock, ports D6 and D7 are not used, connect XCIN/D6
to VSS and leave XCOUT/D7 open.
455A
X IN
XOUT
VDD
VSS
External oscillation circuit
Fig 62. External clock input circuit
455A
XCIN
XCOUT
Rd
CIN
COUT
Note: Externally connect a damping resistor Rd
depending on the oscillation frequency.
(A feedback resistor is built-in.)
Use the quartz-crystal manufacturer’s
recommended value because constants such as
capacitance depend on the resonator.
Fig 63. External quarts-crystal circuit
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 64 of 146
455A Group
(6) Clock control register MR
Register MR controls system clock and operation mode
(frequency division of system clock). Set the contents of this
register through register A with the TMRA instruction. In
addition, the TAMR instruction can be used to transfer the
contents of register MR to register A.
(7) Clock control register RG
Register RG controls the start/stop of each oscillation circuit. Set
the contents of this register through register A with the TRGA
instruction.
Table 28 Clock control registers
Clock control register MR
MR3
Operation mode selection bits
MR2
MR1
System clock selection bits (Note 2)
MR0
at reset : 11002
MR3 MR2
0
0
0
1
1
0
1
1
MR1 MR0
0
0
R/W
TAMR/TMRA
Operation mode
Through mode
Frequency divided by 2 mode
Frequency divided by 4 mode
Frequency divided by 8 mode
System clock
f(HSOCO)
1
f(XIN)
1
0
f(XCIN)
1
1
f(LSOCO)
0
at power down : state retained
W
TRGA
0
Low-speed on-chip oscillator (f(LSOCO)) oscillation available
Low-speed on-chip oscillator (f(LSOCO))
RG3
control bit (Note 3)
1
Low-speed on-chip oscillator (f(LSOCO)) oscillation stop
0
Sub-clock (f(XCIN)) oscillation available, ports D6 and D7 not selected
RG2 Sub-clock (f(XCIN)) control bit (Note 3)
1
Sub-clock (f(XCIN)) oscillation stop, ports D6 and D7 selected
0
Main clock (f(XIN)) oscillation available
RG1 Main-clock (f(XIN)) control bit (Note 3)
1
Main clock (f(XIN)) oscillation stop
0
High-speed
on-chip oscillator (f(HSOCO)) oscillation available
High-speed on-chip oscillator (f(HSOCO))
RG0
control bit (Note 3)
1
High-speed on-chip oscillator (f(HSOCO)) oscillation stop
Note 1. R” represents read enabled, and “W” represents write enabled.
Note 2. The stopped clock cannot be selected for system clock.
Note 3. The oscillation circuit selected for system clock cannot be stopped.
Clock control register RG
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 65 of 146
at reset : 10002
at power down : state retained
455A Group
QzROM Writing Mode
In the QzROM writing mode, the user ROM area can be
rewritten while the microcomputer is mounted on-board by using
a serial pro-grammer which is applicable for this microcomputer.
Table 29 lists the pin description (QzROM writing mode) and
Figure 64 shows the pin connections.
Refer to Figure 65 for examples of a connection with a serial programmer.
Contact the manufacturer of your serial programmer for serial
pro-grammer. Refer to the user ’s manual of your serial
programmer for details on how to use it.
Table 29 Pin description (QzROM writing mode)
VDD, VSS
Pin
Name
Power source, GND
RESET
Reset input
input
XIN, XCIN
XOUT, XCOUT
D0 − D5
P00/SEG16 − P03/SEG19
P10/SEG20 − P13/SEG23
P20/SEG24 (Note 1) − P23/SEG27
P30/SEG28 − P33/SEG31
CNVSS
D4
D3
Clock input
Clock output
input
output
Either connect an oscillator circuit or connect XIN and XCIN to VSS
and leave XOUT and XCOUT open.
I/O port
I/O
Input “H” or “L” level signal or leave the pin open.
VPP input
SDA input/output
SCLK input
input
I/O
input
QzROM programmable power source pin.
Serial data I/O pin.
Serial clock input pin.
D2
I/O
Function
Apply 2.7 to 4.7V to VCC, and 0V to VSS.
Reset input pin for active “L”. Reset occurs when RESET pin is hold
at an “L” level for 16 cycles or more of XIN.
input
Read/program pulse input pin.
PGM input
Voltage drop
VDCE
detection circuit
input
Input “H” or “L” level signal
enable
SEG0/VLC3 − SEG2/VLC1
Segment output/
SEG3 − SEG15
LCD power source/ output Either connect to an LCD panel or leave open.
COM0 − COM3
Common output
Output port C/
C/CNTR
output C/CNTR pin outputs “L” level.
Timer I/O
Note 1. Note that the P20/SEG24 pin is pulled down internally by the MCU during the transition period (the period when VPP is
approximately 0.5 VDD to 1.3 VDD) when the programming power supply (VPP) is applied to the CNVSS pin. In addition, the
P20/SEG24 pin is high inpedance when VPP is approximately 1.3 VDD or grater.
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 66 of 146
455A Group
P0 2 /SEG 18
P0 1 /SEG 17
P0 0 /SEG 16
SEG 15
SEG 14
SEG 13
SEG 12
SEG 11
SEG 10
SEG 9
SEG 8
37
36
35
34
33
31
30
29
28
27
32
P1 0 /SEG 20
P0 3 /SEG 19
38
40
26
41
25
42
24
43
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2/VLC1
SEG1/VLC2
SEG0/VLC3
COM3
COM2
COM1
COM0
VDCE
23
M3455AG8FP
44
45
46
47
48
22
M3455AG8-XXXFP
21
M3455AGCFP
19
20
18
M3455AGC-XXXFP
49
17
11
12
13
V DD
C/CNTR
8
X IN
7
X COUT /D 7
RESET
9
6
X CIN /D 6
10
5
CNVss
Vss
4
X OUT
3
D4
D 5/INT
14
2
15
52
1
16
51
D3
50
D2
P11/SEG21
P12/SEG22
P13/SEG23
(Note) P20/SEG24
P21/SEG25
P22/SEG26
P23/SEG27
P30/SEG28
P31/SEG29
P32/SEG30
P33/SEG31
D0
D1
39
Pin configuration (top view)
VSS
PGM
＊
＊
SCLK
1KΩ
VDD
SDA
*: Connect an oscillation circuit
VPP
: QzROM pin
OUTLINE
PLQP0052JA-A (52P6A-A)
Note: Note that the P2 0/SEG24 pin is pulled down internally by the MCU during the transition
period (that period when VPP is approximately 0.5 VDD to 1.3 VDD) when the programming
power supply (VPP) is applied to the CNV SS pin. In addition, the P2 0/SEG24 pin is high
impedance when VPP is approximately 1.3 V DD or greater.
Fig 64. Pin connection diagram
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 67 of 146
455A Group
455A Group
T_VDD
Vcc
T_VPP
CNVSS
4.7 kΩ
1 kΩ
T_TXD
T_RXD
D4 (SDA)
T_SCLK
T_ BUSY
D3 (SCLK)
N.C.
T_PGM/OE / MD
D2 (PGM)
RESET circuit
T_RESET
GND
RESET
Vss
XIN
XOUT
Set the same termination
as the single-chip mode.
Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF.
Fig 65. When using programmer of Suisei Electronics System Co., LTD, connection example
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 68 of 146
455A Group
LIST OF PRECAUTIONS
(1) Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
• connect a bypass capacitor (approx. 0.1 µF) between pins VDD
and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use relatively thick wire.
CNVSS is also used as VPP pin. Accordingly, when using this pin,
connect this pin to VSS through a resistor about 5kΩ (connect
this resistor to CNVSS/VPP pin as close as possible).
(2) Note on Power Source Voltage
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and
may perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the supply voltage is less than the
recommended operating conditions and design a system not to
cause errors to the system by this unstable operation.
(3) Register initial values 1
The initial value of the following registers are undefined after
system is released from reset. After system is released from reset,
set initial values.
• Register Z (2 bits)
• Register D (3 bits)
• Register E (8 bits)
(4) Register initial values 2
The initial value of the following registers are undefined at RAM
back-up. After system is returned from RAM back-up, set initial
values.
• Register Z (2 bits)
• Register X (4 bits)
• Register Y (4 bits)
• Register D (3 bits)
• Register E (8 bits)
(5) Program counter
Make sure that the PCH does not specify after the last page of the
built-in ROM.
(6) Stack registers (SKS)
Stack registers (SKs) are eight identical registers, so that
subroutines can be nested up to 8 levels. However, one of stack
registers is used respectively when using an interrupt service
routine and when executing a table reference instruction.
Accordingly, be careful not to over the stack when performing
these operations together.
(7) Multifunction
• The input/output of D5 can be used even when INT is used. Be
careful when using inputs of both INT and D5 since the input
threshold value of INT pin is different from that of port D5.
• “H“ output function of port C can be used even when the
CNTR (output) is used.
Rev.1.01 Feb 15, 2008
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Page 69 of 146
(8) Power-on reset
When the built-in power-on reset circuit is used, set the time for
the supply voltage to rise from 0 V to the minimum voltage of
recommended operating conditions to 100 µs or less.
If the rising time exceeds 100 µs, connect a capacitor between
the RESET pin and Vss at the shortest distance, and input “L”
level to RESET pin until the value of supply voltage reaches the
minimum operating voltage.
(9) POF, POF2 instruction
When the POF or POF2 instruction is executed continuously
after the EPOF instruction, system enters the RAM back-up
state.
Note that system cannot enter the RAM back-up state when
executing only the POF or POF2 instruction.
Be sure to disable interrupts by executing the DI instruction
before executing the EPOF instruction and the POF/POF2
instruction continuously.
455A Group
(10)D5/INT pin
(1) Bit 3 of register I1
When the input of the D5/INT pin is controlled with the bit 3
of register I1 in software, be careful about the following
notes.
• Depending on the input state of the D5/INT pin, the external 0
interrupt request flag (EXF0) may be set when the bit 3 of
register I1 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 0 of register V1 to “0” (refer
to (1) in Figure 66.) and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0
flag to “0” after executing at least one instruction (refer to (2)
in Figure 66.).
Also, set the NOP instruction for the case when a skip is
performed with the SNZ0 instruction (refer to (3) in Figure
66.).
•
•
•
LA 4
TV1A
LA 8
TI1A
NOP
SNZ0
NOP
•
•
•
; (×××02)
; The SNZ0 instruction is valid ...... (1)
; (1×××2)
; Control of INT pin input is changed
...................................................... (2)
; The SNZ0 instruction is executed
(EXF0 flag cleared)
...................................................... (3)
×: these bits are not used here.
Fig 66. External 0 interrupt program example-1
(2) Bit 3 of register I1
When the bit 3 of register I1 is cleared to “0”, the power
down mode is selected and the input of INT pin is disabled,
be careful about the following notes.
• When the INT pin input is disabled (register I13 = “0”), set the
key-on wakeup of INT pin to be invalid (register K20 = “0”)
before system enters to the power down mode. (refer to (1) in
Figure 67.).
•
•
•
LA 0
TK2A
DI
EPOF
POF2
•
•
•
; (×××02)
; INT0 key-on wakeup disabled .....(1)
; RAM back-up
×: these bits are not used here.
Fig 67. External 0 interrupt program example-2
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(3) Bit 2 of register I1
When the interrupt valid waveform of the D5/INT pin is
changed with the bit 2 of register I1 in software, be careful
about the following notes.
• Depending on the input state of the D5/INT pin, the external 0
interrupt request flag (EXF0) may be set when the bit 2 of
register I1 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 0 of register V1 to “0” (refer
to (1) in Figure 68.) and then, change the bit 2 of register I1 is
changed.
In addition, execute the SNZ0 instruction to clear the EXF0
flag to “0” after executing at least one instruction (refer to (2)
in Figure 68.).
Also, set the NOP instruction for the case when a skip is
performed with the SNZ0 instruction (refer to (3) in Figure
68.).
•
•
•
LA 4
TV1A
LA 12
TI1A
NOP
SNZ0
NOP
•
•
•
; (×××02)
; The SNZ0 instruction is valid ......(1)
; (×1××2)
; Interrupt valid waveform is changed
.......................................................(2)
; The SNZ0 instruction is executed
(EXF0 flag cleared)
.......................................................(3)
×: these bits are not used here.
Fig 68. External 0 interrupt program example-3
455A Group
(11)Prescaler
Stop prescaler counting and then execute the TABPS instruction
to read its data.
Stop prescaler counting and then execute the TPSAB instruction
to write data to prescaler.
(12)Timer count source
Stop timer 1, 2 or LC counting to change its count source.
(13)Reading the count value
Stop timer 1 or 2 counting and then execute the TAB1 or TAB2
instruction to read its data.
(14)Writing to the timer
Stop timer 1, 2 or LC counting and then execute the T1AB,
T2AB, T2R2L or TLCA instruction to write data to timer.
(15)Writing to reload register
In order to write a data to the reload register R1 while the timer 1
is operating, execute the TR1AB instruction except a timing of
the timer 1 underflow.
In order to write a data to the reload register R2H while the timer
2 is operating, execute the T3HAB instruction except a timing of
the timer 2 underflow.
(16)PWM signal
If the timer 2 count stop timing and the timer 2 underflow timing
overlap during output of the PWM signal, a hazard may occur in
the PWM output waveform.
When “H” interval expansion function of the PWM signal is
used, set “1” or more to reload register R2H.
Set the port C output latch to “0” to output the PWM signal from
C/CNTR pin.
(17)Timer 3
Stop timer 3 counting to change its count source.
When operating timer 3 during clock operating mode, set 1 cycle
or more of count source to the following period; from setting bit
3 of register W3 to “1” till executing the POF instruction.
(18)Prescaler, timer 1 count start timing and count time
when operation starts
Count starts from the first rising edge of the count source (2) in
Figure 69 after prescaler and timer operations start (1) in Figure
69.
Time to first underflow (3) in Figure 69 is shorter (for up to 1
period of the count source) than time among next underflow (4)
in Figure 69 by the timing to start the timer and count source
operations after count starts.
When selecting CNTR input as the count source of timer 1, timer
1 operates synchronizing with the count edge (falling edge or
rising edge) of CNTR input selected by software.
(2)
Count source
Count source
(When falling edge of
CNTR input is selected)
Timer 1 value
3
2
1
0
3
2
1
0
3
2
Timer 1 underflow signal
(3)
(4)
(1) Timer start
Fig 69. Timer count start timing and count time when
operation starts (1)
(19)Timer 2, LC count start timing and count time when
operation starts
Count starts from the first edge of the count source (2) in Figure
70 after timer 2 and LC operation start (1) in Figure 70.
Time to first underflow (3) in Figure 70 is different (for up to 1
period of the count source) from time among next underflow (4)
in Figure 70 by the timing to start the timer and count source
operations after count starts.
(2)
Count source
Timer value
3
2
1
0
3
2
1
0
3
2
Timer underflow signal
(3)
(4)
(1) Timer start
Fig 70. Timer count start timing and count time when
operation starts (2)
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455A Group
(20)Watchdog timer
• The watchdog timer function is valid after system is released
from reset. When not using the watchdog timer function,
execute the DWDT instruction and the WRST instruction
continuously, and clear the WEF flag to “0” to stop the
watchdog timer function.
• The contents of WDF1 flag and timer WDT are initialized at
the power down.
• When using the watchdog timer and the power down, initialize
the WDF1 flag with the WRST instruction just before the
microcomputer enters the power down mode.
Also, set the NOP instruction after the WRST instruction, for
the case when a skip is performed with the WRST instruction.
(21)Voltage drop detection circuit
The voltage drop detection circuit detection voltage of this
product is set up lower than the minimum value of the supply
voltage of the recommended operating conditions.
When the supply voltage of a microcomputer falls below to the
minimum value of recommended operating conditions and
regoes up (ex. battery exchange of an application product),
depending on the capacity value of the bypass capacitor added to
the power supply pin, the following case may cause program
failure (Figure 71);
supply voltage does not fall below to VRST-, and its voltage regoes up with no reset.
In such a case, please design a system which supply voltage is
once reduced below to VRST- and re-goes up after that.
VDD
Recommended operating
condition min. value
VRST+
VRSTNo reset
Program failure may occur.
Normal operation
VDD
Recommended operating
condition min. value
VRST+
VRSTReset
Fig 71. VDD and VRST(22)On-chip oscillator
The clock frequency of the on-chip oscillator depends on the
supply voltage and the operation temperature range.
Be careful that variable frequencies when designing application
products.
Also, the oscillation stabilize wait time after system is released
from reset is generated by the on-chip oscillator clock. When
considering the oscillation stabilize wait time after system is
released from reset, be careful that the variable frequency of the
on-chip oscillator clock.
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(23)External clock
Be careful that the maximum value of the oscillation frequency
when using the external clock differs from the value when using
the ceramic resonator (refer to the recommended operating
condition).
Also, note that the power-down mode (POF or POF2 instruction)
cannot be used when using the external clock.
(24)QzROM
(1) Be careful not to apply overvoltage to MCU. The contents
of QzROM may be overwritten because of overvoltage.
Take care especially at turning on the power.
(2) As for the product shipped in blank, Renesas does not
perform the writing test to user ROM area after the
assembly process though the QzROM writing test is
performed enough before the assembly process. Therefore, a
writing error of approx. 0.1 % may occur. Moreover, please
note the contact of cables and foreign bodies on a socket,
etc. because a writing environment may cause some writing
errors.
(25)Notes On ROM Code Protect (QzROM product
shipped after writing)
As for the QzROM product shipped after writing, the ROM code
protect is specified according to the ROM option setup data in
the mask file which is submitted at ordering.
The ROM option setup data in the mask file is “0016” for protect
enabled or “FF16” for protect disabled.
Note that the mask file which has nothing at the ROM option
data or has the data other than “0016” and “FF 16” can not be
accepted.
(26)Data Required for QzROM Writing Orders
The following are necessary when ordering a QzROM product
shipped after writing:
1. QzROM Writing Confirmation Form*
2. Mark Specification Form*
3. ROM data...........Mask file
* For the QzROM writing confirmation form and the mark
specification form, refer to the “Renesas Technology Corp.”
Homepage (http://www.renesas.com/homepage.jsp).
Note that we cannot deal with special font marking (customer’s
trademark etc.) in QzROM microcomputer.
455A Group
NOTES ON NOISE
Countermeasures against noise are described below.
The following countermeasures are effective against noise in
theory, however, it is necessary not only to take measures as
follows but to evaluate before actual use.
Noise
(1) Shortest wiring length
The wiring on a printed circuit board can function as an antenna
which feeds noise into the microcomputer.
The shorter the total wiring length (by mm unit), the less the
possibility of noise insertion into a microcomputer.
(1) Wiring for RESET input pin
Make the length of wiring which is connected to the RESET
input pin as short as possible.
Especially, connect a capacitor across the RESET input pin
and the VSS pin with the shortest possible wiring.
XIN
XOUT
VSS
XIN
XOUT
VSS
N.G.
O.K.
Fig 73. Wiring for clock I/O pins
• Reason
In order to reset a microcomputer correctly, 1 machine cycle or
more of the width of a pulse input into the RESET pin is
required.
If noise having a shorter pulse width than this is input to the
RESET input pin, the reset is released before the internal state
of the microcomputer is completely initialized.
This may cause a program runaway.
Noise
Reset
circuit
RESET
VSS
VSS
N.G.
Reset
circuit
VSS
• Reason
If noise enters clock I/O pins, clock waveforms may be
deformed. This may cause a program failure or program
runaway.
Also, if a potential difference is caused by the noise between
the V SS level of a microcomputer and the V SS level of an
oscillator, the correct clock will not be input in the
microcomputer.
(3) Wiring to CNVSS pin
Connect an approximately 5 kΩ resistor to the VPP pin and
also to the GND pattern supplied to the V SS pin with
shortest possible wiring.
• Reason
The CNVSS pin is the power source input pin for the built-in
QzROM. When programming in the built-in QzROM, the
impedance of the CNV SS pin is low to allow the electric
current for writing flow into the QzROM. Because of this,
noise can enter easily. If noise enters the CNVSS pin, abnormal
instruction codes or data are read from the built-in QzROM,
which may cause a program runaway.
RESET
VSS
(Note)
O.K.
Fig 72. Wiring for the RESET input pin
(2) Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O
pins as short as possible.
• Make the length of wiring across the grounding lead of a
capacitor which is connected to an oscillator and the VSS
pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other
VSS patterns.
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T he shortest
C N V ss
about 5kΩ
VSS
(Note)
N ote: T his indicates pin.
Fig 74. Wiring for CNVSS pin
T he shortest
455A Group
(2) Connection of bypass capacitor across VSS line
and VDD line
Connect an approximately 0.1 µF bypass capacitor across the
VSS line and the VDD line as follows:
• Connect a bypass capacitor across the VSS pin and the VDD pin
at equal length.
• Connect a bypass capacitor across the VSS pin and the VDD pin
with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS
line and VDD line.
• Connect the power source wiring via a bypass capacitor to the
VSS pin and the VDD pin.
VDD
(3) Oscillator concerns
Take care to prevent an oscillator that generates clocks for a
microcomputer operation from being affected by other signals.
(1) Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far
as possible from signal lines where a current larger than the
tolerance of current value flows.
• Reason
In the system using a microcomputer, there are signal lines for
controlling motors, LEDs, and thermal heads or others. When
a large current flows through those signal lines, strong noise
occurs because of mutual inductance.
VDD
Microcomputer
Mutual inductance
M
VSS
VSS
XIN
XOUT
VSS
Large
current
GND
N.G.
O.K.
Fig 76. Wiring for a large current signal line
Fig 75. Bypass capacitor across the VSS line and the
VDD line
(2) Installing oscillator away from signal lines where potential
levels change frequently
Install an oscillator and a connecting pattern of an oscillator
away from signal lines where potential levels change
frequently. Also, do not cross such signal lines over the
clock lines or the signal lines which are sensitive to noise.
• Reason
Signal lines where potential levels change frequently (such as
the CNTR pin signal line) may affect other lines at signal
rising edge or falling edge. If such lines cross over a clock line,
clock waveforms may be deformed, which causes a
microcomputer failure or a program runaway.
Do not cross
CNTR
XIN
XOUT
VSS
N.G.
Fig 77. Wiring to a signal line where potential levels
change frequently
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455A Group
(3) Oscillator protection using VSS pattern
As for a two-sided printed circuit board, print a VSS pattern
on the underside (soldering side) of the position (on the
component side) where an oscillator is mounted.
Connect the VSS pattern to the microcomputer VSS pin with
the shortest possible wiring.
Besides, separate this VSS pattern from other VSS patterns.
An example of VSS patterns on the
underside of a printed circuit board
Oscillator wiring
pattern example
XIN
XOUT
VSS
• Watches the operation of the interrupt processing routine by
comparing the SWDT contents with counts of interrupt
processing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and
determines to branch to the program initialization routine for
recovery processing in the following case:
If the SWDT contents do not change after interrupt processing.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt
processing.
• Determines that the main routine operates normally when the
SWDT contents are reset to the initial value N at almost fixed
cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to
branch to the program initialization routine for recovery
processing in the following case:
If the SWDT contents are not initialized to the initial value N
but continued to decrement and if they reach 0 or less.
Separate the VSS line for oscillation from other VSS lines
Fig 78. VSS pattern on the underside of an oscillator
(4) Setup for I/O ports
Setup I/O ports using hardware and software as follows:
<Hardware>
• Connect a resistor of 100 Ω or more to an I/O port in series.
<Software>
• As for an input port, read data several times by a program for
checking whether input levels are equal or not.
• As for an output port or an I/O port, since the output data may
reverse because of noise, rewrite data to its output latch at
fixed periods.
• Rewrite data to pull-up control registers at fixed periods.
(5) Providing of watchdog timer function by software
If a microcomputer runs away because of noise or others, it
can be detected by a software watchdog timer and the
microcomputer can be reset to normal operation. This is
equal to or more effective than program runaway detection
by a hardware watchdog timer. The following shows an
example of a watchdog timer provided by software.
In the following example, to reset a microcomputer to
normal operation, the main routine detects errors of the
interrupt processing routine and the interrupt processing
routine detects errors of the main routine.
This example assumes that interrupt processing is repeated
multiple times in a single main routine processing.
<The main routine>
• Assigns a single word of RAM to a software watchdog timer
(SWDT) and writes the initial value N in the SWDT once at
each execution of the main routine. The initial value N should
satisfy the following condition:
N+1≥
As the main routine execution cycle may change because of
an interrupt processing or others, the initial value N should
have a margin.
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Main routine
Interrupt processing routine
(SWDT) ← N
(SWDT) ← (SWDT)−1
EI
Interrupt processing
Main processing
(SWDT)
≤ 0?
≠N
≤0
(SWDT)
= N?
RTI
Return
N
Interrupt processing
routine errors
>0
Main routine
errors
Fig 79. Watchdog timer by software
455A Group
CONTROL REGISTERS
Interrupt control register V1
V13 Timer 2 interrupt enable bit
V12 Timer 1 interrupt enable bit
V11 Not used
V10 External 0 interrupt enable bit
at reset : 00002
0
1
0
1
0
1
0
1
Interrupt control register V2
V23
Not used
V22
Not used
V21
Not used
V20
Timer 3 interrupt enable bit
Interrupt control register I1
I13
INT pin input control bit (Note 2)
I12
Interrupt valid waveform for INT pin/
return level selection bit (Note 2)
I11
INT pin edge detection circuit control bit
I10
INT pin timer 1 count start synchronous
circuit selection bit
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
0
1
0
1
0
1
at power down : 00002
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid)
at power down : state retained
Page 76 of 146
R/W
TAI1/TI1A
INT pin input disabled
INT pin input enabled
Falling waveform (“L” level of INT pin is recognized with the SNZI0
instruction)/“L” level
Rising waveform (“H” level of INT pin is recognized with the SNZI0
instruction)/“H” level
One-sided edge detected
Both edges detected
Timer 1 count start synchronous circuit not selected
Timer 1 count start synchronous circuit selected
Note 1. “R” represents read enabled, and “W” represents write enabled.
Note 2. When the contents of I12 and I13 are changed, the external interrupt request flag (EXF0) may be set.
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
R/W
TAV2/TV2A
This bit has no function, but read/write is enabled.
at reset : 00002
0
1
R/W (Note 1)
TAV1/TV1A
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
at reset : 00002
0
1
0
1
0
1
0
1
at power down : 00002
455A Group
Clock control register MR
MR3
Operation mode selection bits
MR2
MR1
at reset : 11002
MR3 MR2
0
0
0
1
1
0
1
1
MR1 MR0
0
0
System clock selection bits (Note 2)
MR0
Clock control register RG
at power down : state retained
R/W
TAMR/TMRA
Operation mode
Through mode
Frequency divided by 2 mode
Frequency divided by 4 mode
Frequency divided by 8 mode
System clock
f(HSOCO)
0
1
f(XIN)
1
0
f(XCIN)
1
1
f(LSOCO)
at reset : 10002
at power down : state retained
W
TRGA
0 Low-speed on-chip oscillator (f(LSOCO)) oscillation available
1 Low-speed on-chip oscillator (f(LSOCO)) oscillation stop
0 Sub-clock (f(XCIN)) oscillation available, ports D6 and D7 not selected
RG2 Sub-clock (f(XCIN)) control bit (Note 3)
1 Sub-clock (f(XCIN)) oscillation stop, ports D6 and D7 selected
0 Main clock (f(XIN)) oscillation available
RG1 Main-clock (f(XIN)) control bit (Note 3)
1 Main clock (f(XIN)) oscillation stop
0 High-speed on-chip oscillator (f(HSOCO)) oscillation available
High-speed on-chip oscillator (f(HSOCO))
RG0
control bit (Note 3)
1 High-speed on-chip oscillator (f(HSOCO)) oscillation stop
Note 1. R” represents read enabled, and “W” represents write enabled.
Note 2. The stopped clock cannot be selected for system clock.
Note 3. The oscillation circuit selected for system clock cannot be stopped.
RG3
Low-speed on-chip oscillator (f(LSOCO))
control bit (Note 3)
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455A Group
Timer control register PA
PA0
0
1
Prescaler control bit
Timer control register W1
W13
at power down : 02
W
TAPP
at power down : state retained
R/W (Note 1)
TAW1/TW1A
at reset : 02
Stop (state retained)
Operating
at reset : 00002
0
1
0
1
Timer 1 count auto-stop circuit selection bit
(Note 2)
W12 Timer 1 control bit
Timer 1 count auto-stop circuit not selected
Timer 1 count auto-stop circuit selected
Stop (state retained)
Operating
Count source
W11 W10
W11
Timer 1 count source selection bits (Note 3)
W10
0
0
PWM signal (PWMOUT)
0
1
Prescaler output (ORCLK)
1
0
Timer 3 underflow signal (T3UDF)
1
1
CNTR input
Timer control register W2
at reset : 00002
0
1
0
1
0
1
0
1
W23 CNTR pin function control bit
W22
PWM signal
“H” interval expansion function control bit
W21 Timer 2 control bit
W20 Timer 2 count source selection bit
at reset : 00002
0
1
W31
Timer 3 count value selection bits
W30
Timer control register W4
W43 Timer LC control bit
W42 Timer LC count source selection bit
W41
at power down : state retained
Count value
CNTR pin output auto-control circuit
selection bit
W40 CNTR pin input count edge selection bit
000
Underflow every 512 count
001
Underflow every 1024 count
010
Underflow every 2048 count
011
Underflow every 4096 count
100
Underflow every 8192 count
101
Underflow every 16384 count
110
Underflow every 32768 count
111
Underflow every 65536 count
at reset : 00002
0
1
0
1
0
1
0
1
at power down : state retained
Stop (state retained)
Operating
Bit 4 (T34) of timer 3
System clock (STCK)
CNTR output auto-control circuit not selected
CNTR output auto-control circuit selected
Falling edge
Rising edge
Note 1. “R” represents read enabled, and “W” represents write enabled.
Note 2. This function is valid only when the timer 1 count start synchronous circuit is selected (I10 =“1”).
Note 3. Port C output is invalid when CNTR input is selected for the timer 1 count source.
Rev.1.01 Feb 15, 2008
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Page 78 of 146
R/W
TAW3/TW3A
Stop (initial state)
Operating
W32 W31 W30
W32
R/W
TAW2/TW2A
CNTR pin output invalid
CNTR pin output valid
PWM signal “H” interval expansion function invalid
PWM signal “H” interval expansion function valid
Stop (state retained)
Operating
XIN input
Prescaler output (ORCLK)/2
Timer control register W3
W33 Timer 3 control bit
at power down : 00002
R/W
TAW4/TW4A
455A Group
Timer control register W5
0
1
0
1
W53 Not used
W52 Not used
Timer 3 count source selection bits
W50
LCD control register L1
L13
Internal dividing resistor for LCD power
supply selection bit (Note 2)
L12
LCD control bit
0
1
0
1
L11
LCD duty and bias selection bits
L10
SEG2/VLC1 pin function switch bit (Note 4)
P23/SEG27 pin function switch bit
L32
P22/SEG26 pin function switch bit
L31
P21/SEG25 pin function switch bit
L30
P20/SEG24 pin function switch bit
Note 1.
Note 2.
Note 3.
Note 4.
2r × 3, 2r × 2
r × 3, r × 2
Stop (OFF)
Operating
L1
Duty
1/2
1
0
1/3
1/3
1
1
1/4
1/3
Page 79 of 146
W
TL2A
SEG0
VLC3
SEG1
VLC2
SEG2
VLC1
Internal dividing resistor valid
Internal dividing resistor invalid
at reset : 11112
0
1
0
1
0
1
0
1
at power down : state retained
at power down : state retained
SEG27
P23
SEG26
P22
SEG25
P21
SEG24
P20
”R” represents read enabled, and “W” represents write enabled.
“r (resistor) multiplied by 3” is used at 1/3 bias, and “r multiplied by 2” is used at 1/2 bias.
VLC3 is connected to VDD internally when SEG0 pin is selected.
Use internal dividing resistor when SEG1 and SEG2 pins are selected.
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Bias
Not available
at reset : 00002
R/W
TAL1/TL1A
at power down : state retained
1/2
LCD control register L3
L33
High-speed on-chip oscillator
Not available
1
L21
Low-speed on-chip oscillator
11
1
supply control bit
SEG1/VLC2 pin function switch bit (Note 4)
10
0
Internal dividing resistor for LCD power
L22
XCIN input
ORCLK input
0
0
1
0
1
0
1
0
SEG0/VLC3 pin function switch bit (Note 3)
00
01
0
LCD control register L2
L23
Count source
at reset : 00002
L11
R/W
TAW5/TW5A
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
W51 W52
W51
L20
at power down : state retained
at reset : 00002
W
TL3A
455A Group
LCD control register C1
C13
P03/SEG19 pin function switch bit
C12
P02/SEG18 pin function switch bit
C11
P01/SEG17 pin function switch bit
C10
P00/SEG16 pin function switch bit
at reset : 11112
0
1
0
1
0
1
0
1
LCD control register C2
C23
P13/SEG23 pin function switch bit
C22
P12/SEG22 pin function switch bit
C21
P11/SEG21 pin function switch bit
C20
P10/SEG20 pin function switch bit
LCD control register C3
P33/SEG31 pin function switch bit
Rev.1.01 Feb 15, 2008
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Page 80 of 146
at power down : state retained
W
TC2A
at power down : state retained
W
TC3A
SEG23
P13
SEG22
P12
SEG21
P11
SEG20
P10
at reset : 11112
0 SEG31
1 P33
0 SEG30
C32 P32/SEG30 pin function switch bit
1 P32
0 SEG29
C31 P31/SEG29 pin function switch bit
1 P31
0 SEG28
C30 P30/SEG28 pin function switch bit
1 P30
Note 1.“R” represents read enabled, and “W” represents write enabled. .
C33
W
TC1A
SEG19
P03
SEG18
P02
SEG17
P01
SEG16
P00
at reset : 11112
0
1
0
1
0
1
0
1
at power down : state retained
455A Group
Key-on wakeup control register K0
K03
Ports P12 and P13 key-on wakeup
control bit
K02
Ports P10 and P11 key-on wakeup
control bit
K01
Ports P02 and P03 key-on wakeup
control bit
K00
Ports P00 and P01 key-on wakeup
control bit
at reset : 00002
0
1
0
1
0
1
0
1
Key-on wakeup control register K1
K13
Port P23 key-on wakeup control bit
K12
Port P22 key-on wakeup control bit
K11
Port P21 key-on wakeup control bit
K10
Port P20 key-on wakeup control bit
Key-on wakeup control register K2
K23
Ports P32 and P33 key-on wakeup
control bit (Note 3)
K22
Ports P30 and P31 key-on wakeup
control bit (Note 2)
K21 INT pin return condition selection bit
K20 INT pin key-on wakeup control bit
Key-on wakeup control register K3
at power down : state retained
at power down : state retained
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 81 of 146
R/W
TAK2/TK2A
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Return by level
Return by edge
Key-on wakeup invalid
Key-on wakeup valid
at reset : 00002
at power down : state retained
0 Key-on wakeup not used
1 Key-on wakeup used
0 Key-on wakeup not used
K32 Ports D4 and D5 key-on wakeup control bit
1 Key-on wakeup used
0 Key-on wakeup not used
K31 Ports D2 and D3 key-on wakeup control bit
1 Key-on wakeup used
0 Key-on wakeup not used
K30 Ports D0 and D1 key-on wakeup control bit
1 Key-on wakeup used
Note 1. “R” represents read enabled, and “W” represents write enabled.
Note 2. To be invalid (K22 = “0”) key-on wakeup of ports P30 and P31, set the registers K30 and K31 to “0.”
Note 3. To be invalid (K23 = “0”) key-on wakeup of ports P32 and P33, set the registers K32 and K33 to “0.”
K33 Ports D6 and D7 key-on wakeup control bit
R/W
TAK1/TK1A
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
at reset : 00002
0
1
0
1
0
1
0
1
R/W
TAK0/TK0A
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
at reset : 00002
0
1
0
1
0
1
0
1
at power down : state retained
R/W
TAK3/TK3A
455A Group
Pull-up control register PU0
PU03
Port P12 and P13 pull-up transistor control
bit
PU02
Port P10 and P11 pull-up transistor control
bit
PU01
Port P02 and P03 pull-up transistor control
bit
PU00
Port P00 and P01 pull-up transistor control
bit
at reset : 00002
0
1
0
1
0
1
0
1
Pull-up control register PU1
PU13 Port P23 pull-up transistor control bit
PU12 Port P22 pull-up transistor control bit
PU11 Port P21 pull-up transistor control bit
PU10 Port P20 pull-up transistor control bit
Pull-up control register PU2
PU23 Port P33 pull-up transistor control bit
PU22 Port P32 pull-up transistor control bit
PU21 Port P31 pull-up transistor control bit
PU20 Port P30 pull-up transistor control bit
Pull-up control register PU3
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 82 of 146
R/W
TAPU1/TPU1A
at power down : state retained
R/W
TAPU2/TPU2A
at power down : state retained
R/W
TAPU3/TPU3A
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
at reset : 00002
0 Pull-up transistor OFF
1 Pull-up transistor ON
0 Pull-up transistor OFF
PU32 Port D4 and D5 pull-up transistor control bit
1 Pull-up transistor ON
0 Pull-up transistor OFF
PU31 Port D2 and D3 pull-up transistor control bit
1 Pull-up transistor ON
0 Pull-up transistor OFF
PU30 Port D0 and D1 pull-up transistor control bit
1 Pull-up transistor ON
Note 1. “R” represents read enabled, and “W” represents write enabled.
PU33 Port D6 and D7 pull-up transistor control bit
at power down : state retained
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
at reset : 00002
0
1
0
1
0
1
0
1
R/W
TAPU0/TPU0A
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
at reset : 00002
0
1
0
1
0
1
0
1
at power down : state retained
455A Group
Port output structure control register FR0
FR03
Ports P12 and P13 output structure selection
bit
FR02
Ports P10 and P11 output structure selection
bit
FR01
Ports P02 and P03 output structure selection
bit
FR00
Ports P00 and P01 output structure selection
bit
at reset : 00002
0
1
0
1
0
1
0
1
Port output structure control register FR1
FR13 Ports D3 output structure selection bit
FR12 Ports D2 output structure selection bit
FR11 Ports D1 output structure selection bit
FR10 Ports D0 output structure selection bit
Port output structure control register FR2
FR23
Ports P32 and P33 output structure selection
bit
FR22
Ports P30 and P31 output structure selection
bit
FR21 Ports D5 output structure selection bit
FR20 Ports D4 output structure selection bit
Port output structure control register FR3
FR33 Ports P23 output structure selection bit
FR32 Ports P22 output structure selection bit
FR31 Ports P21 output structure selection bit
FR30 Ports P20 output structure selection bit
Note 1. “W” represents write enabled.
Rev.1.01 Feb 15, 2008
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Page 83 of 146
W (Note 1)
TFR1A
at power down : state retained
W
TFR2A
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
at reset : 00002
0
1
0
1
0
1
0
1
at power down : state retained
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
at reset : 00002
0
1
0
1
0
1
0
1
W
TFR0A
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
at reset : 00002
0
1
0
1
0
1
0
1
at power down : state retained
at power down : state retained
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
W
TFR3A
455A Group
INSTRUCTIONS
Each instruction is described as follows;
1. Index list of instruction function
2. Machine instructions (index by alphabet)
3. Machine instructions (index by function)
4. Instruction code table
SYMBOL
Symbol
A
B
DR
E
V1
V2
I1
PA
W1
W2
W3
W4
W5
MR
RG
L1
L2
L3
C1
C2
C3
K0
K1
K2
K3
PU0
PU1
PU2
PU3
FR0
FR1
FR2
FR3
X
Y
Z
DP
PC
PCH
PCL
SK
SP
CY
UPTF
RPS
R1
R2L
Contents
Register A (4 bits)
Register B (4 bits)
Register DR (3 bits)
Register E (8 bits)
Interrupt control register V1 (4 bits)
Interrupt control register V2 (4 bits)
Interrupt control register I1 (4 bits)
Timer control register PA (1 bit)
Timer control register W1 (4 bits)
Timer control register W2 (4 bits)
Timer control register W3 (4 bits)
Timer control register W4 (4 bits)
Timer control register W5 (5 bits)
Clock control register MR (4 bits)
Clock control register RG (3 bits)
LCD control register L1 (4 bits)
LCD control register L2 (4 bits)
LCD control register L3 (4 bits)
LCD control register C1 (4 bits)
LCD control register C2 (4 bits)
LCD control register C3 (4 bits)
Key-on wakeup control register K0 (4 bits)
Key-on wakeup control register K1 (4 bits)
Key-on wakeup control register K2 (4 bits)
Key-on wakeup control register K3 (4 bits)
Pull-up control register PU0 (4 bits)
Pull-up control register PU1 (4 bits)
Pull-up control register PU2 (4 bits)
Pull-up control register PU3 (4 bits)
Port output structure control register FR0 (4 bits)
Port output structure control register FR1 (4 bits)
Port output structure control register FR2 (4 bits)
Port output structure control register FR3 (4 bits)
Register X (4 bits)
Register Y (4 bits)
Register Z (2 bits)
Data pointer (10 bits)
(It consists of registers X, Y, and Z)
Program counter (14 bits)
High-order 7 bits of program counter
Low-order 7 bits of program counter
Stack register (14 bits × 8)
Stack pointer (3 bits)
Carry flag
High-order bit reference enable flag
Prescaler reload register (8 bits)
Timer 1 reload register (8 bits)
Timer 2 reload register (8 bits)
The symbols shown below are used in the following list of
instruction function and the machine instructions.
Symbol
R2H
RLC
PS
T1
Contents
Timer 2 reload register (8 bits)
Timer LC reload register (4 bits)
Prescaler
Timer 1
T2
TLC
T1F
T2F
T3F
WDF1
WEF
INTE
EXF0
VDF
P
D
P0
P1
P2
P3
C
INT
Timer 2
Timer LC
Timer 1 interrupt request flag
Timer 2 interrupt request flag
Timer 3 interrupt request flag
Watchdog timer flag
Watchdog timer enable flag
Interrupt enable flag
External 0 interrupt request flag
Voltage drop detection circuit flag
Power down flag
Port D (8 bits)
Port P0 (4 bits)
Port P1 (4 bits)
Port P2 (4 bits)
Port P3 (4 bits)
Port C (1 bit)
INT pin (1 bit)
x
y
z
p
n
i
j
A3 A2 A1 A0
Hexadecimal variable
Hexadecimal variable
Hexadecimal variable
Hexadecimal variable
Hexadecimal constant
Hexadecimal constant
Hexadecimal constant
Binary notation of hexadecimal variable A
(same for others)
←
( )
−
M (DP)
a
p, a
Direction of data movement
Contents of registers and memories
Negate, Flag unchanged after executing instruction
RAM address pointed by the data pointer
Label indicating address a6 a5 a4 a3 a2 a1 a0
Label indicating address a6 a5 a4 a3 a2 a1 a0 in page
p6 p5 p4 p3 p2 p1 p0
C+x
?
←→
Hex. C + Hex. number x (also same for others)
Decision of state shown before “?”
Data exchange between a register and memory
Note 1. The 455A Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased
by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if
the TABP p, RT, or RTS instruction is skipped.
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 84 of 146
455A Group
INDEX LIST OF INSTRUCTION FUNCTION
TBA
(B) ← (A)
110 122
TAY
(A) ← (Y)
110 122
TYA
(Y) ← (A)
119 122
TEAB
(E7−E4) ← (B)
(E3−E0) ← (A)
112 122
TABE
(B) ← (E7−E4)
(A) ← (E3−E0)
104 122
TDA
(DR2−DR0) ← (A2−A0)
111 122
TAD
(A2−A0) ← (DR2−DR0)
(A3) ← 0
105 122
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
110 122
TAX
(A) ← (X)
110 122
TASP
(A2−A0) ← (SP2−SP0)
(A3) ← 0
108 122
LXY x, y
(X) ← x, x = 0 to 15
(Y) ← y, y = 0 to 15
LZ z
Function
Mnemonic
Page
LA n
(A) ← n
n = 0 to 15
92 124
TABP p
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2−DR0, A3−A0)
(UPTF) = 1,
(DR2) ← 0
(DR1, DR0) ← (ROM(PC))9, 8
(B) ← (ROM(PC))7−4
(A) ← (ROM(PC))3−0
(PC) ← (SK(SP))
(SP) ← (SP) − 1
104 124
AM
(A) ← (A) + (M(DP))
87 124
AMC
(A) ← (A) + (M(DP)) + (CY)
(CY) ← Carry
87 124
An
(A) ← (A) + n
n = 0 to 15
87 124
AND
(A) ← (A)AND(M(DP))
87 124
OR
(A) ← (A)OR(M(DP))
94 124
93 122
SC
(CY) ← 1
98 124
(Z) ← z, z = 0 to 3
93 122
RC
(CY) ← 0
96 124
INY
(Y) ← (Y) + 1
92 122
SZC
(CY) = 0 ?
102 124
DEY
(Y) ← (Y) − 1
90 122
CMA
(A) ← (A)
89 124
TAM j
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
106 122
RAR
XAM j
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
120 122
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) − 1
120 122
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
120 122
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
115 122
XAMD j
XAMI j
TMA j
M3455AG8: p=0 to 63 and M3455AGC: p=0 to 95.
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 85 of 146
Arithmetic operation
103 122
Bit operation
(A) ← (B)
Grouping
Comparison
operation
RAM addresses
RAM to register transfer
Page
TAB
TAZ
Note 1.
Function
Mnemonic
Branch operation
Register to register transfer
Grouping
CY
A3A2A1A0
95 124
SB j
(Mj(DP)) ← 1
j = 0 to 3
97 124
RB j
(Mj(DP)) ← 0
j = 0 to 3
95 124
SZB j
(Mj(DP)) = 0 ?
j = 0 to 3
101 124
SEAM
(A) = (M(DP)) ?
99 126
SEA n
(A) = n ?
n = 0 to 15
98 126
Ba
(PCL) ← a6−a0
88 126
BL p, a
(PCH) ← p
(PCL) ← a6−a0
88 126
BLA p
(PCH) ← p
(PCL) ← (DR2−DR0, A3−A0)
88 126
455A Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Subroutine operation
Return operation
Page
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
(PCL) ← a6−a0
88 126
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← a6−a0
89 126
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2−DR0, A3−A0)
89 126
RTI
(PC) ← (SK(SP))
(SP) ← (SP) − 1
97 126
RT
(PC) ← (SK(SP))
(SP) ← (SP) − 1
96 126
RTS
(PC) ← (SK(SP))
(SP) ← (SP) − 1
97 126
DI
(INTE) ← 0
90 128
EI
(INTE) ← 1
91 128
SNZ0
V10 = 0 : (EXF0) = 1 ?
(EXF0) ← 0
V10 = 1 : SNZ0 = NOP
99 128
SNZI0
I12 = 0 : (INT) = “L” ?
I12 = 1 : (INT) = “H” ?
TAV1
Grouping
Mnemonic
Function
Page
TPAA
(PA) ← (A)
116 128
TAW1
(A) ← (W1)
109 128
TW1A
(W1) ← (A)
118 128
TAW2
(A) ← (W2)
109 128
TW2A
(W2) ← (A)
118 128
TAW3
(A) ← (W3)
109 128
TW3A
(W3) ← (A)
119 128
TAW4
(A) ← (W4)
109 128
TW4A
(W4) ← (A)
119 128
TAW5
(A) ← (W5)
119 128
TW5A
(W5) ← (A)
119 128
TABPS
(B) ← (TPS7−TPS4)
(A) ← (TPS3−TPS0)
104 130
TPSAB
(RPS7−RPS4) ← (B)
(TPS7−TPS4) ← (B)
(RPS3−RPS0) ← (A)
(TPS3−TPS0) ← (A)
116 130
99 128
TAB1
(B) ← (T17−T14)
(A) ← (T13−T10)
103 130
(A) ← (V1)
108 128
T1AB
102 130
TV1A
(V1) ← (A)
118 128
(R17−R14) ← (B)
(T17−T14) ← (B)
(R13−R10) ← (A)
(T13−T10) ← (A)
TAV2
(A) ← (V2)
108 128
TR1AB
117 130
TV2A
(V2) ← (A)
118 128
(R17−R14) ← (B)
(R13−R10) ← (A)
TAB2
(A) ← (I1)
105 128
(B) ← (T27−T24)
(A) ← (T23−T20)
104 130
TAI1
TI1A
(I1) ← (A)
113 128
T2AB
(R2L7−R2L4) ← (B)
(T27−T24) ← (B)
(R2L3−R2L0) ← (A)
(T23−T20) ← (A)
102 130
T2R2L
(T27−T20) ← (R2L7−R2L0)
103 130
T2HAB
(R2H7−R2H4) ← (B)
(R2H3−R2H0) ← (A)
103 130
BM a
Interrupt operation
Function
Mnemonic
BML p, a
BMLA p
Timer operation
Grouping
Note 1.
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 86 of 146
M3455AG8: p=0 to 63 and M3455AGC: p=0 to 95.
455A Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Page
Grouping
Function
Mnemonic
Page
(PU3) ← (A)
117 132
TAK0
(A) ← (K0)
105 134
TK0A
(K0) ← (A)
113 134
TAK1
(A) ← (K1)
105 134
TK1A
(K1) ← (A)
113 134
TAK2
(A) ← (K2)
106 134
TK2A
(K2) ← (A)
114 134
TAK3
(A) ← (K3)
106 134
TK3A
(K3) ← (A)
114 134
TAL1
(A) ← (L1)
106 134
TL1A
(L1) ← (A)
114 134
TL2A
(L2) ← (A)
114 134
TL3A
(L3) ← (A)
115 134
TC1A
(C1) ← (A)
111 134
94 132
TC2A
(C2) ← (A)
111 134
(A) ← (P3)
92 132
TC3A
(C3) ← (A)
111 134
OP3A
(P3) ← (A)
94 132
TAMR
(A) ← (MR)
107 134
CLD
(D) ← 1
89 132
TMRA
(MR) ← (A)
115 134
TRGA
(RG2−RG0) ← (A2−A0
117 134
RD
(D(Y)) ← 0, (Y) = 0 to 4
96 132
SD
(D(Y)) ← 1, (Y) = 0 to 4
98 132
NOP
(PC) ← (PC)+1
93 136
SZD
(D(Y)) = 0 ?, (Y) = 0 to 4
102 132
POF
Transition to clock operating
95 136
(C) ← 0
POF2
Transition to RAM back-up
95 136
RCP
96 132
EPOF
POF instruction valid
91 136
SCP
(C) ← 1
98 132
SNZP
(P) = 1 ?
99 136
TFR0A
(FR0) ← (A)
112 132
SNZVD
(VDF) = 1?
100 136
TFR1A
(FR1) ← (A)
112 132
WRST
(WDF1) = 1 ?
(WDF1) ← 0
119 136
TFR2A
(FR2) ← (A)
112 132
DWDT
90 136
TFR3A
(FR3) ← (A)
113 132
Stop of watchdog timer function enabled
SRST
System reset
101 136
TAPU0
(A) ← (PU0)
107 132
RUPT
(UPTF) ←0
97 136
TPU0A
(PU0) ← (A)
116 132
SUPT
(UPTF) ←1
101 136
TAPU1
(A) ← (PU1)
107 132
SVDE
101 136
TPU1A
(PU1) ← (A)
116 132
At power down mode, voltage drop detection circuit
valid
TAPU2
(A) ← (PU2)
107 132
RBK
(Note 1)
When TABPp instruction is
executed, p6 ←0
81
117
TPU2A
(PU2) ← (A)
117 132
117
TAPU3
108 132
When TABPp instruction is
executed, p6 ←1
84
(A) ← (PU3)
SBK
(Note 1)
SNZT1
V12 = 0 : (T1F) = 1 ?
(T1F) ← 0
V12 = 1 : SNZT1=NOP
100 130
SNZT2
V13 = 0 : (T2F) = 1 ?
(T2F) ← 0
V13 = 1 : SNZT2=NOP
100 130
V20 = 0 : (T3F) = 1 ?
(T3F) ← 0
V20 = 1 : SNZT3=NOP
100 130
IAP0
(A) ← (P0)
91 132
OP0A
(P0) ← (A)
93 132
IAP1
(A) ←(P1)
91 132
OP1A
(P1) ← (A)
94 132
IAP2
(A) ← (P2)
92 132
OP2A
(P2) ← (A)
IAP3
LCD operation
115 130
Clock operation
(RLC) ← (A)
(TLC) ← (A)
Input/Output operation
TPU3A
TLCA
SNZT3
Input/Output operation
Function
Mnemonic
Other operation
Timer operation
Grouping
Note 1. (SBK, RBK) cannot be used in the M3455AG8.
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 87 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET)
A n (Add n and accumulator)
Instruction
D9
code
0 0
Operation:
D0
0
1
1
0
n
n
n
n 2 0
6
n 16
(A) ← (A) + n
n = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
Overflow = 0
Grouping:
Arithmetic operation
Description: Adds the value n in the immediate field to register A, and
stores a result in register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no overflow as the
result of operation.
Executes the next instruction when there is overflow as the
result of operation.
AM (Add accumulator and Memory)
Instruction
D9
code
0 0
Operation:
D0
0
0
0
0
1
0
1
0 2 0
0 A 16
(A) ← (A)Å{(M(DP))
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Arithmetic operation
Description: Adds the contents of M(DP) to register A.
Stores the result in register A. The contents of carry flag
CY remains unchanged.
AMC (Add accumulator, Memory and Carry)
Instruction
D9
code
0 0
Operation:
D0
0
0
0
0
1
0
1
1 2 0
0 B 16
(A) ← (A) + (M(DP)) + (CY)
(CY) ← Carry
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
0/1
-
Grouping:
Arithmetic operation
Description: Adds the contents of M(DP) and carry flag CY to register
A. Stores the result in register A and carry flag CY.
AND (logical AND between accumulator and memory)
Instruction
D9
code
0 0
Operation:
D0
0
0
0
1
1
0
0
0 2 0
1
(A) ← (A) AND (M(DP))
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
8 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Arithmetic operation
Description: Takes the AND operation between the contents of register
A and the contents of M(DP), and stores the result in register A.
Page 88 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
B a (Branch to address a)
Instruction
D9
code
0 1
Operation:
D0
1 a6 a5 a4 a3 a2 a1 a0 2 1 8 a 16
+a
(PCL) ← a6 to a0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Branch operation
Description: Branch within a page : Branches to address a in the identical page.
Note:
Specify the branch address within the page including this
instruction.
BL p,a (Branch Long to address a in page p)
Instruction
D9
code
0 0
1
1
D0
Number of
words
Number of
cycles
Flag CY
Skip condition
1 p4 p3 p2 p1 p0 2 0 E p 16
+p
2
2
-
-
1 p6 p5 a6 a5 a4 a3 a2 a1 a0 2 2
Operation:
a
(PCH) ← p
(PCL) ← a6 to a0
a 16 Grouping: Branch operation
Description: Branch out of a page : Branches to address a in page p.
Note:
M3455AG8: p=0 to 63 p6=0
M3455AGC: p=0 to 95
BLA p (Branch Long to address (D)+(A) in page p)
Instruction
D9
code
0 0
D0
0
0
0
1 p6 p5 p4 0
Operation:
1
0
0
0
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
-
-
0 2 0
1
0 16
0 p3 p2 p1 p0 2 2
p
p 16 Grouping: Branch operation
Description: Branch out of a page : Branches to address (DR2 DR1 DR0
A3 A2 A1 A0)2 specified by registers D and A in page p.
Note:
M3455AG8: p=0 to 63 p6=0
M3455AGC: p=0 to 95
(PCH) ← p
(PCL) ← (DR2−R0, A3−A0)
BM a (Branch and Mark to address a in page 2)
Instruction
D9
code
0 1
Operation:
D0
0 a6 a5 a4 a3 a2 a1 a0 2 1
a
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
(PCL) ← a6−a0
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
a 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Subroutine call operation
Description: Call the subroutine in page 2 : Calls the subroutine at
address a in page 2.
Note:
Subroutine extending from page 2 to another page can
also be called with the BM instruction when it starts on
page 2.
Be careful not to over the stack because the maximum
level of subroutine nesting is 8.
Page 89 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
BML p,a (Branch and Mark Long to address a in page p)
Instruction
D9
code
0 0
1
1
D0
Number of
words
Number of
cycles
Flag CY
Skip condition
0 p4 p3 p2 p1 p0 2 0 c p 16
+p
2
2
-
-
1 p6 p5 a6 a5 a4 a3 a2 a1 a0 2 2
Operation:
a
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← a6−a0
a 16 Grouping: Subroutine call operation
Description: Call the subroutine : Calls the subroutine at address a in
page p.
Note:
M3455AG8: p=0 to 63 p6=0
M3455AGC: p=0 to 95
Be careful not to over the stack because the maximum
level of subroutine nesting is 8.
BMLA p (Branch and Mark Long to address (D)+(A) in page p)
Instruction
D9
code
0 0
D0
0
0
1
1 p6 p5 p4 0
Operation:
1
0
0
0
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
-
-
0 2 0
3
0 16
0 p3 p2 p1 p0 2 2
p
p 16 Grouping: Subroutine call operation
Description: Call the subroutine : Calls the subroutine at address (DR2
DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in
page p.
Note:
M3455AG8: p=0 to 63 p6=0
M3455AGC: p=0 to 95
Be careful not to over the stack because the maximum
level of subroutine nesting is 8.
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2−DR0, A3−A0)
CLD (CLear port D)
Instruction
D9
code
0 0
Operation:
D0
0
0
0
1
0
0
0
1 2 0
1
1 16
(D) ← 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Sets (1) to port D.
CMA (CoMplement of Accumulator)
Instruction
D9
code
0 0
Operation:
D0
0
0
0
1
1
1
0
0 2 0
1 C 16
(A) ←(A)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Arithmetic operation
Description: Stores the one’s complement for register A’s contents in
register A.
Page 90 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
DEY (DEcrement register Y)
Instruction
D9
code
0 0
Operation:
D0
0
0
0
1
0
1
1
1 2 0
1
7 16
(Y) ← (Y) −1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
(Y) = 15
Grouping:
RAM addresses
Description: Subtracts 1 from the contents of register Y.
As a result of subtraction, when the contents of register Y
is 15, the next instruction is skipped. When the contents of
register Y is not 15, the next instruction is executed.
DI (Disable Interrupt)
Instruction
D9
code
0 0
Operation:
D0
0
0
0
0
0
1
0
0 2 0
0
4 16
(INTE) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Interrupt control operation
Description: Clears (0) to interrupt enable flag INTE, and disables the
interrupt.
Note:
Interrupt is disabled by executing the DI instruction after
executing 1 machine cycle.
DWDT (Disable WatchDog Timer)
Instruction
D9
code
1 0
Operation:
D0
1
0
0
1
1
1
0
0 2 2
9 C 16
Stop of watchdog timer function enabled
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Other operation
Description: Stops the watchdog timer function by the WRST instruction
after executing the DWDT instruction.
Page 91 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
EI (Enable Interrupt)
Instruction
D9
code
0 0
Operation:
D0
0
0
0
0
0
1
0
1 2 0
0
5 16
(INTE) ← 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Interrupt control operation
Description: Sets (1) to interrupt enable flag INTE, and enables the
interrupt.
Note:
Interrupt is enabled by executing the EI instruction after
executing 1 machine cycle.
EPOF (Enable POF instruction)
Instruction
D9
code
0 0
Operation:
D0
0
1
0
1
1
0
1
1 2 0
5 B 16
POF instruction or POF2 instruction valid
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Other operation
Description: Makes the immediate after POF instruction or POF2
instruction valid by executing the EPOF instruction.
IAP0 (Input Accumulator from port P0)
Instruction
D9
code
1 0
Operation:
D0
0
1
1
0
0
0
0
0 2 2
6
0 16
(A) ← (P0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Transfers the input of port P0 to register A.
IAP1 (Input Accumulator from port P1)
Instruction
D9
code
1 0
Operation:
D0
0
1
1
0
0
0
0
1 2 2
6
(A) ← (P1)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
1 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Transfers the input of port P1 to register A.
Page 92 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
IAP2 (Input Accumulator from port P2)
Instruction
D9
code
1 0
Operation:
D0
0
1
1
0
0
0
1
0 2 2
6
2 16
(A) ← (P2)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Transfers the input of port P2 to the register A.
IAP3 (Input Accumulator from port P3)
Instruction
D9
code
1 0
Operation:
D0
0
1
1
0
0
0
1
1 2 2
6
3 16
(A) ← (P3)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Transfers the input of port P3 to the register A.
INY (INcrement register Y)
Instruction
D9
code
0 0
Operation:
D0
0
0
0
1
0
0
1
1 2 0
1
3 16
(Y) ← (Y) + 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
(Y) = 0
Grouping:
RAM addresses
Description: Adds 1 to the contents of register Y. As a result of addition,
when the contents of register Y is 0, the next instruction is
skipped. When the contents of register Y is not 0, the next
instruction is executed.
LA n (Load n in Accumulator)
Instruction
D9
code
0 0
Operation:
D0
0
1
1
1
n
n
n
n 2 0
7
(A) ← n
n = 0 to 15
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
n 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
Continuous
description
Grouping:
Arithmetic operation
Description: Loads the value n in the immediate field to register A.
When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA
instructions coded continuously are skipped.
Page 93 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
LXY x,y (Load register X and Y with x and y)
Instruction
D9
D0
code
1 1 x3 x2 x1 x0 y3 y2 y1 y0 2 3
Operation:
x
y 16
(X) ← x x = 0 to 15
(Y) ← y y = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
Continuous
description
Grouping:
RAM addresses
Description: Loads the value x in the immediate field to register X, and
the value y in the immediate field to register Y. When the
LXY instructions are continuously coded and executed,
only the first LXY instruction is executed and other LXY
instructions coded continuously are skipped.
LZ z (Load register Z with z)
Instruction
D9
code
0 0
Operation:
D0
0
1
0
0
1
0 Z1 Z0 2 0
4
8
+z 16
(Z) ← z z = 0 to 3
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
RAM addresses
Description: Loads the value z in the immediate field to register Z.
NOP (No OPeration)
Instruction
D9
code
0 0
Operation:
D0
0
0
0
0
0
0
0
0 2 0
0
0 16
(PC) ← (PC) + 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Other operation
Description: No operation; Adds 1 to program counter value, and others
remain unchanged.
OP0A (Output port P0 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
1
0
0
0
0
0 2 2
2
(P0) ← (A)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
0 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Outputs the contents of register A to port P0.
Page 94 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
OP1A (Output port P1 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
1
0
0
0
0
1 2 2
2
1 16
(P1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Outputs the contents of register A to port P1.
OP2A (Output port P2 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
1
0
0
0
1
0 2 2
2
2 16
(P2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Outputs the contents of the register A to port P2.
OP3A (Output port P3 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
1
0
0
0
1
1 2 2
2
3 16
(P3) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Outputs the contents of the register A to port P3.
OR (logical OR between accumulator and memory)
Instruction
D9
code
0 0
Operation:
D0
0
0
0
1
1
0
0
1 2 0
1
(A) ← (A) OR (M(DP))
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
9 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Arithmetic operation
Description: Takes the OR operation between the contents of register A
and the contents of M(DP), and stores the result in register
A.
Page 95 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
POF (Power OFf)
Instruction
D9
code
0 0
Operation:
D0
0
0
0
0
0
0
1
0 2 0
0
2 16
Transition to clock operating mode
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Other operation
Description: Puts the system in clock operating mode by executing the
POF2 instruction after executing the EPOF instruction.
Note:
If the EPOF instruction is not executed just before this
instruction, this instruction is equivalent to the NOP instruction.
POF2 (Power OFf2)
Instruction
D9
code
0 0
Operation:
D0
0
0
0
0
1
0
0
0 2 0
0
8 16
Transition to RAM back-up mode
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Other operation
Description: Puts the system in RAM back-up state by executing the
POF2 instruction after executing the EPOF instruction.
Note:
If the EPOF instruction is not executed before executing
this instruction, this instruction is equivalent to the NOP
instruction.
RAR (Rotate Accumulator Right)
Instruction
D9
code
0 0
Operation:
D0
0
CY
0
0
1
1
1
0
1 2 0
1 D 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
0/1
-
Grouping:
A3A2A1A0
Arithmetic operation
Description: Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right.
RB j (Reset Bit)
Instruction
D9
code
0 0
Operation:
D0
0
1
0
0
1
1
j
j 2 0
4 C 16
+j
(Mj(DP)) ← 0
j = 0 to 3
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Bit operation
Description: Clears (0) the contents of bit j (bit specified by the value j in
the immediate field) of M(DP).
Page 96 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
RBK (Reset Bank flag)
Instruction
D9
code
0 0
Operation:
D0
0
1
0
0
0
0
0
0 2 0
4
0 16
When TABPp instruction is executed, p6 ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Other operation
Description: Sets referring data area to pages 0 to 63 when the TABPp
instruction is executed. This instruction is valid only for the
TABPp instruction.
Note:
This instruction cannot be used in M3455AG8.
RC (Reset Carry flag)
Instruction
D9
code
0 0
Operation:
D0
0
0
0
0
0
1
1
0 2 0
0
6 16
(CY) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
0
-
Grouping:
Arithmetic operation
Description: Clears (0) to carry flag CY.
RCP (Reset Port C)
Instruction
D9
code
1 0
Operation:
D0
1
0
0
0
1
1
0
0 2 2
8 C 16
(C) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Clears (0) to port C.
RD (Reset port D specified by register Y)
Instruction
D9
code
0 0
Operation:
D0
0
0
0
1
0
1
0
0 2 0
1
(D(Y)) ← 0
(Y) = 0 to 7
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
4 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Clears (0) to a bit of port D specified by register Y.
Note:
(Y) = 0 to 7.
Do not execute this instruction if values except above are
set to register Y.
Page 97 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
RT (ReTurn from subroutine)
Instruction
D9
code
0 0
Operation:
D0
0
1
0
0
0
1
0
0 2 0
4
4 16
(PC) ← (SK(SP))
(SP) ← (SP) −1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
2
-
-
Grouping:
Return operation
Description: Returns from subroutine to the routine called the subroutine.
RTI (ReTurn from Interrupt)
Instruction
D9
code
0 0
Operation:
D0
0
1
0
0
0
1
1
0 2 0
4
6 16
(PC) ← (SK(SP))
(SP) ← (SP) − 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Return operation
Description: Returns from interrupt service routine to main routine.
Returns each value of data pointer (X, Y, Z), carry flag, skip
status, NOP mode status by the continuous description of
the LA/LXY instruction, register A and register B to the
states just before interrupt.
RTS (ReTurn from subroutine and Skip)
Instruction
D9
code
0 0
D0
0
1
0
0
0
1
0
1 2 0
4
5 16
Operation:
(PC) ← (SK(SP))
(SP) ← (SP) − 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
2
-
Skip at uncondition
Grouping:
Return operation
Description: Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
RUPT (Reset UPT flag)
Instruction
D9
code
0 0
Operation:
D0
0
1
0
1
1
0
0
0 2 0
5
8 16
(UPTF) ←0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Other operation
Description: Clears (0) to the high-order bit reference enable flag
UPTF.
Note:
Even when the table reference instruction (TABP p) is executed, the high-order 2 bits of ROM reference data is not
transferred to register D.
SB j (Set Bit)
Instruction
D9
code
0 0
Operation:
D0
0
1
0
1
1
1
j
j 2 0
5 C 16
+j
(Mj(DP)) ← 1
j = 0 to 3
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Bit operation
Description: Sets (1) the contents of bit j (bit specified by the value j in
the immediate field) of M(DP).
Page 98 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SBK (Set BanK flag)
Instruction
D9
code
0 0
Operation:
D0
0
1
0
0
0
0
0
1 2 0
4
1 16
When TABPp instruction is executed, p6 ← 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Arithmetic operation
Description: Sets referring data area to pages 64 to 127 when the
TABPp instruction is executed. This instruction is valid only
for the TABPp instruction.
Note:
This instruction cannot be used in M3455AG8.
SC (Set Carry flag)
Instruction
D9
code
0 0
Operation:
D0
0
0
0
0
0
1
1
1 2 0
0
7 16
(CY) ← 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
1
-
Grouping:
Arithmetic operation
Description: Sets (1) to carry flag CY.
SCP (Set Port C)
Instruction
D9
code
1 0
Operation:
D0
1
0
0
0
1
1
0
1 2 2
8 D 16
(C) ← 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Sets (1) to port C.
SD (Set port D specified by register Y)
Instruction
D9
code
0 0
Operation:
D0
0
0
0
1
0
1
0
1 2 0
1
5 16
(D(Y)) ← 1
(Y) = 0 to 7
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Sets (1) to a bit of port D specified by register Y.
Note:
(Y) = 0 to 7.
Do not execute this instruction if values except above are
set to register Y.
SEA n (Skip Equal, Accumulator with immediate data n)
Instruction
D9
code
0 0
0
Operation:
0
D0
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
-
(A) = n
n = 0 to 15
0
0
1
0
0
1
0
1 2 0
2
5 16
0
1
1
1
n
n
n
n 2 0
7
n 16 Grouping: Comparison operation
Description: Skips the next instruction when the contents of register A is
equal to the value n in the immediate field.
Executes the next instruction when the contents of register
A is not equal to the value n in the immediate field.
(A) = n ?
n = 0 to 15
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 99 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SEAM (Skip Equal, Accumulator with Memory)
Instruction
D9
code
0 0
Operation:
D0
0
0
1
0
0
1
1
0 2 0
2
6 16
(A) = (M(DP)) ?
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
(A) = (M(DP))
Grouping:
Comparison operation
Description: Skips the next instruction when the contents of register A is
equal to the contents of M(DP).
Executes the next instruction when the contents of register
A is not equal to the contents of M(DP).
SNZ0 (Skip if Non Zero condition of external interrupt 0 request flag)
Instruction
D9
code
0 0
Operation:
D0
0
0
1
1
1
0
0
0 2 0
3
8 16
V10 = 0 : (EXF0) = 1 ?
(EXF0) ← 0
V10 = 1 : SNZ0 = NOP
(V10 : bit 0 of the interrupt control register V1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
V10 = 0 : (EXF0) = 1
Grouping:
Interrupt operation
Description: When V10 = 0 : Clears (0) to the EXF0 flag and skips the
next instruction when external 0 interrupt request flag
EXF0 is “1”. When the EXF0 flag is “0”, executes the next
instruction.
When V10 = 1 : This instruction is equivalent to the NOP
instruction.
SNZI0 (Skip if Non Zero condition of external Interrupt 0 input pin)
Instruction
D9
code
0 0
Operation:
D0
0
0
1
1
1
0
1
0 2 0
3 A 16
I12 = 0 : (INT) = “L” ?
I12 = 1 : (INT) = “H” ?
(I12 : bit 2 of the interrupt control register I1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
I12 = 0 : (INT0) = “L”
I12 = 1 : (INT0) = “H”
Grouping:
Interrupt operation
Description: When I12 = 0 : Skips the next instruction when the level of
INT pin is “L”. Executes the next instruction when the level
of INT pin is “H”.
When I12 = 1 : Skips the next instruction when the level of
INT pin is “H.” Executes the next instruction when the level
of INT pin is “L”.
SNZP (Skip if Non Zero condition of Power down flag)
Instruction
D9
code
0 0
Operation:
D0
0
0
0
0
0
0
1
1 2 0
0
(P) = 1 ?
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
3 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
(P) = 1
Grouping:
Other operation
Description: Skips the next instruction when the P flag is “1”.
After skipping, the P flag remains unchanged.
Executes the next instruction when the P flag is “0”.
Page 100 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SNZT1 (Skip if Non Zero condition of Timer 1 interrupt request flag)
Instruction
D9
code
1 0
Operation:
D0
1
0
0
0
0
0
0
0 2 2
8
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
V12 = 0 : (T1F) = 1
0 16
V12 = 0 : (T1F) = 1 ?
(T1F) ← 0
V12 = 1 : SNZT1 = NOP
(V12 = bit 2 of interrupt control register V1)
Grouping:
Timer operation
Description: When V12 = 0 : Clears (0) to the T1F flag and skips the
next instruction when timer 1 interrupt request flag T1F is
“1”. When the T1F flag is “0,” executes the next instruction.
When V12 = 1 : This instruction is equivalent to the NOP
instruction.
SNZT2 (Skip if Non Zero condition of Timer 2 interrupt request flag)
Instruction
D9
code
1 0
Operation:
D0
1
0
0
0
0
0
0
1 2 2
8
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
V13 = 0 : (T2F) = 1
1 16
V13 = 0 : (T2F) = 1 ?
(T2F) ← 0
V13 = 1 : SNZT2 = NOP
(V13 = bit 3 of interrupt control register V1)
Grouping:
Timer operation
Description: When V13 = 0 : Clears (0) to the T2F flag and skips the
next instruction when timer 2 interrupt request flag T2F is
“1”. When the T2F flag is “0”, executes the next instruction.
When V13 = 1 : This instruction is equivalent to the NOP
instruction.
SNZT3 (Skip if Non Zero condition of Timer 3 interrupt request flag)
Instruction
D9
code
1 0
Operation:
D0
1
0
0
0
0
0
1
0 2 2
8
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
V20 = 0 : (T3F) = 1
2 16
V20 = 0 : (T3F) = 1 ?
(T3F) ← 0
V20 = 1 : SNZT3 = NOP
Grouping:
Timer operation
Description: When V20 = 0 : Clears (0) to the T3F flag and skips the
next instruction when timer 3 interrupt request flag T3F is
“1”. When the T3F flag is “0”, executes the next instruction.
When V20 = 1 : This instruction is equivalent to the NOP
instruction.
SNZVD (Skip if Non Zero condition of Voltage Detector flag)
Instruction
D9
code
1 0
Operation:
D0
1
0
0
0
1
0
1
0 2 2
8 A 16
(VDF) = 1?
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
V23 = 0 : (VDF) = 1
Grouping:
Other operation
Description: Skips the next instruction when voltage drop detection circuit flag VDF is “1”. Execute instruction when VDF is “0”.
After skipping, the contents of VDF remains unchanged.
Page 101 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SRST (System ReSet)
Instruction
D9
code
0 0
Operation:
D0
0
0
0
0
0
0
0
1 2 0
0
1 16
System reset
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Other operation
Description: System reset occurs.
SUPT (Set UPT flag)
Instruction
D9
code
0 0
Operation:
D0
0
1
0
1
1
0
0
1 2 0
5
9 16
(UPTF) ←1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Other operation
Description: Sets (1) to the high-order bit reference enable flag UPTF.
When the table reference instruction (TABP p) is executed,
the high-order 2 bits of ROM reference data is transferred
to the low-order 2 bits of register D.
SVDE (Set Voltage Detector Enable flag)
Instruction
D9
code
1 0
Operation:
D0
1
0
0
1
0
0
1
1 2 2
9
3 16
Voltage drop detection circuit valid at powerdown
mode.
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Other operation
Description: Voltage drop detection circuit is valid at powerdown mode
(clock operating mode, RAM back-up mode)
Note:
This instruction can be used only for H version.
SZB j (Skip if Zero, Bit)
Instruction
D9
code
0 0
Operation:
D0
0
0
1
0
0
0
j
j 2 0
2
(Mj(DP)) = 0 ?
j = 0 to 3
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
j 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
(Mj(DP)) = 0
j = 0 to 3
Grouping:
Bit operation
Description: Skips the next instruction when the contents of bit j (bit
specified by the value j in the immediate field) of M(DP) is
“0”.
Executes the next instruction when the contents of bit j of
M(DP) is “1”.
Page 102 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SZC (Skip if Zero, Carry flag )
Instruction
D9
code
0 0
Operation:
D0
0
0
1
0
1
1
1
1 2 0
2
F 16
(CY) = 0 ?
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
(CY) = 0
Grouping:
Arithmetic operation
Description: Skips the next instruction when the contents of carry flag
CY is “0”.
After skipping, the CY flag remains unchanged.
Executes the next instruction when the contents of the CY
flag is “1”.
SZD (Skip if Zero, port D specified by register Y)
Instruction
D9
code
0 0
0
Operation:
0
D0
Number of
cycles
Flag CY
Skip condition
2
2
-
(D(Y)) = 0
0
0
1
0
0
1
0
0 2 0
2
0
0
1
0
1
0
1
1 2 0
2 B 16 Grouping: Input/Output operation
Description: Skips the next instruction when a bit of port D specified by
register Y is “0”. Executes the next instruction when the bit
is “1”.
Note:
(Y) = 0 to 5.
Do not execute this instruction if values except above are
set to register Y.
(D(Y)) = 0 ?
(Y) = 0 to 5
4 16
Number of
words
T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B)
Instruction
D9
code
1 0
Operation:
D0
0
0
1
1
0
0
0
0 2 2
3
0 16
(T17−T14) ← (B)
(R17−R14) ← (B)
(T13−T10) ← (A)
(R13−R10) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Timer operation
Description: Transfers the contents of register B to the high-order 4 bits
of timer 1 and timer 1 reload register R1. Transfers the
contents of register A to the low-order 4 bits of timer 1 and
timer 1 reload register R1.
T2AB (Transfer data to timer 2 and register R2L from Accumulator and register B)
Instruction
D9
code
1 0
Operation:
D0
0
0
1
1
0
0
0
1 2 2
3
(T27−T24) ← (B)
(R2L7−R2L4) ← (B)
(T23−T20) ← (A)
(R2L3−R2L0) ← (A)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
1 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Timer operation
Description: Transfers the contents of register B to the high-order 4 bits
(T27−T24) of timer 2 and the high-order 4 bits (R2L7−R2L4)
of timer 2 reload register R2L. Transfers the contents of
register A to the low-order 4 bits (T23−T20) of timer 2 and
the low-order 4 bits (R2L3−R2L0) of timer 2 reload register
R2.
Page 103 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
T2HAB (Transfer data to register R2H from Accumulator and register B)
Instruction
D9
code
1 0
Operation:
D0
1
0
0
1
0
1
0
0 2 2
9
4 16
(R2H7−R2H4) ← (B)
(R2H3−R2H0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Timer operation
Description: Transfers the contents of register B to the high-order 4 bits
of timer 2 and timer 2 reload register R2H. Transfers the
contents of register A to the low-order 4 bits of timer 2 and
timer 2 reload register R2H.
T2R2L (Transfer data to timer 2 from register R2L)
Instruction
D9
code
1 0
Operation:
D0
1
0
0
1
0
1
0
1 2 2
9
5 16
(T27−T20) ← (R2L7−R2L0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Timer operation
Description: Transfers the contents of reload register R2L to timer 2.
TAB (Transfer data to Accumulator from register B)
Instruction
D9
code
0 0
Operation:
D0
0
0
0
1
1
1
1
0 2 0
1 E 16
(A) ← (B)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Register to register transfer
Description: Transfers the contents of register B to register A.
TAB1 (Transfer data to Accumulator and register B from timer 1)
Instruction
D9
code
1 0
Operation:
D0
0
1
1
1
0
0
0
0 2 2
7
(B) ← (T17−T14)
(A) ← (T13−T10)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
0 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Timer operation
Description: Transfers the high-order 4 bits (T17−T14) of timer 1 to register B.
Transfers the low-order 4 bits (T13−T10) of timer 1 to register A.
Page 104 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAB2 (Transfer data to Accumulator and register B from timer 2)
Instruction
D9
code
1 0
Operation:
D0
0
1
1
1
0
0
0
1 2 2
7
1 16
(B) ← (T27−T24)
(A) ← (T23−T20)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Timer operation
Description: Transfers the high-order 4 bits (T27−T24) of timer 2 to register B.
Transfers the low-order 4 bits (T23−T20) of timer 2 to register A.
TABE (Transfer data to Accumulator and register B from register E)
Instruction
D9
code
0 0
Operation:
D0
0
0
1
0
1
0
1
0 2 0
2 A 16
(B) ← (E7−E4)
(A) ← (E3−E0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Register to register transfer
Description: Transfers the high-order 4 bits (E7−E4) of register E to register B, and low-order 4 bits of register E to register A.
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
Instruction
D9
code
0 0
Operation:
D0
1
0 p5 p4 p3 p2 p1 p0 2 0 8 p 16
+p
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2−DR0, A3−A0)
(B) ← (ROM(PC))7−4
(A) ← (ROM(PC))3−0
(UPTF) ← 1
(DR1, DR0) ← (ROM(PC))9, 8
(DR2) ← 0
(PC) ← (SK(SP))
(SP) ← (SP) − 1
Grouping:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
3
-
-
Arithmetic operation
Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to
0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by
registers A and D in page p. When UPTF is 1, Transfers bits 9, 8 to the loworder 2 bits (DR1, DR0) of register D, and “0” is stored to the least significant
bit (DR2) of register D.
When this instruction is executed, 1 stage of stack register (SK) is used.
Note:
p is 0 to 63 for M3455AG8, and p is 0 to 95 for M3455AGC.
When this instruction is executed, be careful not to over the stack because 1
stage of stack register is used.
TABPS (Transfer data to Accumulator and register B from Pre-Scaler)
Instruction
D9
code
1 0
Operation:
D0
0
1
1
1
0
1
0
1 2 2
7
(B) ← (TPS7−TPS4)
(A) ← (TPS3−TPS0)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
5 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Timer operation
Description: Transfers the high-order 4 bits of prescaler to register B.
Transfers the low-order 4 bits of prescaler to register A.
Page 105 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAD (Transfer data to Accumulator from register D)
Instruction
D9
code
0 0
Operation:
D0
0
1
0
1
0
0
0
1 2 0
5
1 16
(A2−A0) ← (DR2−DR0)
(A3) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Register to register transfer
Description: Transfers the contents of register D to the low-order 3 bits
(A2−A0) of register A.
“0” is stored to the bit 3 (A3) of register A.
TAI1 (Transfer data to Accumulator from register I1)
Instruction
D9
code
1 0
Operation:
D0
0
1
0
1
0
0
1
1 2 2
5
3 16
(A) ← (I1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Interrupt operation
Description: Transfers the contents of interrupt control register I1 to register A.
TAK0 (Transfer data to Accumulator from register K0)
Instruction
D9
code
1 0
Operation:
D0
0
1
0
1
0
1
1
0 2 2
5
6 16
(A) ← (K0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Transfers the contents of key-on wakeup control register
K0 to register A.
TAK1 (Transfer data to Accumulator from register K1)
Instruction
D9
code
1 0
Operation:
D0
0
1
0
1
1
0
0
1 2 2
5
(A) ← (K1)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
9 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Transfers the contents of key-on wakeup control register
K1 to register A.
Page 106 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAK2 (Transfer data to Accumulator from register K2)
Instruction
D9
code
1 0
Operation:
D0
0
1
0
1
1
0
1
0 2 2
5 A 16
(A) ← (K2)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Transfers the contents of key-on wakeup control register
K2 to register A.
TAK3 (Transfer data to Accumulator from register K3)
Instruction
D9
code
1 0
Operation:
D0
0
1
0
1
1
0
1
1 2 2
5 B 16
(A) ← (K3)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Transfers the contents of key-on wakeup control register
K3 to register A.
TAL1 (Transfer data to Accumulator from register L1)
Instruction
D9
code
1 0
Operation:
D0
0
1
0
0
1
0
1
0 2 2
4 A 16
(A) ← (L1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
LCD operation
Description: Transfers the contents of LCD control register L1 to register A.
TAM j (Transfer data to Accumulator from Memory)
Instruction
D9
code
1 0
Operation:
D0
1
1
0
0
j
j
j
j 2 2 C
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
j 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
RAM to register transfer
Description: After transferring the contents of M(DP) to register A, an
exclusive OR operation is performed between register X
and the value j in the immediate field, and stores the result
in register X.
Page 107 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAMR (Transfer data to Accumulator from register MR)
Instruction
D9
code
1 0
Operation:
D0
0
1
0
1
0
0
1
0 2 2
5
2 16
(A) ← (MR)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Clock operation
Description: Transfers the contents of clock control register MR to register A.
TAPU0 (Transfer data to Accumulator from register PU0)
Instruction
D9
code
1 0
Operation:
D0
0
1
0
1
0
1
1
1 2 2
5
7 16
(A) ← (PU0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Transfers the contents of pull-up control register PU0 to
register A.
TAPU1 (Transfer data to Accumulator from register PU1)
Instruction
D9
code
1 0
Operation:
D0
0
1
0
1
1
1
1
0 2 2
5 E 16
(A) ← (PU1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Transfers the contents of pull-up control register PU1 to
register A.
TAPU2 (Transfer data to Accumulator from register PU2)
Instruction
D9
code
1 0
Operation:
D0
0
1
0
1
1
1
1
1 2 2
5
(A) ← (PU2)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
F 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Transfers the contents of pull-up control register PU2 to
register A.
Page 108 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAPU3 (Transfer data to Accumulator from register PU3)
Instruction
D9
code
1 0
Operation:
D0
0
1
0
1
1
1
0
1 2 2
5 D 16
(A) ← (PU3)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Transfers the contents of pull-up control register PU3 to
register A.
TASP (Transfer data to Accumulator from Stack Pointer)
Instruction
D9
code
0 0
Operation:
D0
0
1
0
1
0
0
0
0 2 0
5
0 16
(A2−A0) ← (SP2−SP0)
(A3) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Register to register transfer
Description: Transfers the contents of stack pointer (SP) to the loworder 3 bits (A2−A0) of register A.
“0” is stored to the bit 3 (A3) of register A.
TAV1 (Transfer data to Accumulator from register V1)
Instruction
D9
code
0 0
Operation:
D0
0
1
0
1
0
1
0
0 2 0
5
4 16
(A) ← (V1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Interrupt operation
Description: Transfers the contents of interrupt control register V1 to
register A.
TAV2 (Transfer data to Accumulator from register V2)
Instruction
D9
code
0 0
Operation:
D0
0
1
0
1
0
1
0
1 2 0
5
(A) ← (V2)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
5 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Interrupt operation
Description: Transfers the contents of interrupt control register V2 to
register A.
Page 109 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAW1 (Transfer data to Accumulator from register W1)
Instruction
D9
code
1 0
Operation:
D0
0
1
0
0
1
0
1
1 2 2
4 B 16
(A) ← (W1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Timer operation
Description: Transfers the contents of timer control register W1 to register A.
TAW2 (Transfer data to Accumulator from register W2)
Instruction
D9
code
1 0
Operation:
D0
0
1
0
0
1
1
0
0 2 2
4 C 16
(A) ← (W2)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Timer operation
Description: Transfers the contents of timer control register W2 to register A.
TAW3 (Transfer data to Accumulator from register W3)
Instruction
D9
code
1 0
Operation:
D0
0
1
0
0
1
1
0
1 2 2
4 D 16
(A) ← (W3)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Timer operation
Description: Transfers the contents of timer control register W3 to register A.
TAW4 (Transfer data to Accumulator from register W4)
Instruction
D9
code
1 0
Operation:
D0
0
1
0
0
1
1
1
0 2 2
4 E 16
(A) ← (W4)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Timer operation
Description: Transfers the contents of timer control register W4 to register A.
TAW5 (Transfer data to Accumulator from register W5)
Instruction
D9
code
1 0
Operation:
D0
0
1
0
0
1
1
1
1 2 2
4
(A) ← (W5)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
F 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Timer operation
Description: Transfers the contents of timer control register W5 to register A.
Page 110 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAX (Transfer data to Accumulator from register X)
Instruction
D9
code
0 0
Operation:
D0
0
1
0
1
0
0
1
0 2 0
5
2 16
(A) ← (X)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Register to register transfer
Description: Transfers the contents of register X to register A.
TAY (Transfer data to Accumulator from register Y)
Instruction
D9
code
0 0
Operation:
D0
0
0
0
1
1
1
1
1 2 0
1
F 16
(A) ← (Y)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Register to register transfer
Description: Transfers the contents of register Y to register A.
TAZ (Transfer data to Accumulator from register Z)
Instruction
D9
code
0 0
Operation:
D0
0
1
0
1
0
0
1
1 2 0
5
3 16
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Register to register transfer
Description: Transfers the contents of register Z to the low-order 2 bits
(A1, A0) of register A. “0” is stored to the high-order 2 bits
(A3, A2) of register A.
TBA (Transfer data to register B from Accumulator)
Instruction
D9
code
0 0
Operation:
D0
0
0
0
0
1
1
1
0 2 0
0 E 16
(B) ← (A)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Register to register transfer
Description: Transfers the contents of register A to register B.
Page 111 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TC1A (Transfer data to register C1 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
1
0
1
0
1
0
0
0 2 2 A 8 16
(C1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
LCD control operation
Description: Transfers the contents of register A to the LCD control register C1.
TC2A (Transfer data to register C2 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
1
0
1
0
1
0
0
1 2 2 A 9 16
(C2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
LCD control operation
Description: Transfers the contents of register A to the LCD control register C2.
TC3A (Transfer data to register C3 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
1
0
0
1
1
0 2 2
2
6 16
(C3) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
LCD control operation
Description: Transfers the contents of register A to the LCD control register C3.
TDA (Transfer data to register D from Accumulator)
Instruction
D9
code
0 0
Operation:
D0
0
0
1
0
1
0
0
1 2 0
2
(DR2−DR0) ← (A2−A0)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
9 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Register to register transfer
Description: Transfers the contents of the low-order 3 bits (A2−A0) of
register A to register D.
Page 112 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TEAB (Transfer data to register E from Accumulator and register B)
Instruction
D9
code
0 0
Operation:
D0
0
0
0
1
1
0
1
0 2 0
1 A 16
(E7−E4) ← (B)
(E3−E0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Register to register transfer
Description: Transfers the contents of register B to the high-order 4 bits
(E3−E0) of register E, and the contents of register A to the
low-order 4 bits (E3−E0) of register E.
TFR0A (Transfer data to register FR0 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
1
0
1
0
0
0 2 2
2
8 16
(FR0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Transfers the contents of register A to port output structure
control register FR0.
TFR1A (Transfer data to register FR1 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
1
0
1
0
0
1 2 2
2
9 16
(FR1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Transfers the contents of register A to port output structure
control register FR1.
TFR2A (Transfer data to register FR2 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
1
0
1
0
1
0 2 2
2 A 16
(FR2) ← (A)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Transfers the contents of register A to port output structure
control register FR2.
Page 113 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TFR3A (Transfer data to register FR3 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
1
0
1
0
1
1 2 2
2 B 16
(FR3) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Transfers the contents of register A to port output structure
control register FR3.
TI1A (Transfer data to register I1 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
0
1
0
1
1
1 2 2
1
7 16
(I1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Interrupt operation
Description: Transfers the contents of register A to interrupt control register I1.
TK0A (Transfer data to register K0 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
0
1
1
0
1
1 2 2
1 B 16
(K0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Transfers the contents of register A to key-on wakeup control register K0.
TK1A (Transfer data to register K1 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
0
1
0
1
0
0 2 2
1
(K1) ← (A)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
4 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Transfers the contents of register A to key-on wakeup control register K1.
Page 114 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TK2A (Transfer data to register K2 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
0
1
0
1
0
1 2 2
1
5 16
(K2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Transfers the contents of register A to key-on wakeup control register K2.
TK3A (Transfer data to register K3 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
1
0
1
1
0
0 2 2
2 C 16
(K3) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Transfers the contents of register A to key-on wakeup control register K3.
TL1A (Transfer data to register L1 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
0
0
1
0
1
0 2 2
0 A 16
(L1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
LCD control operation
Description: Transfers the contents of register A to the LCD control register L1.
TL2A (Transfer data to register L2 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
0
0
1
0
1
1 2 2
0 B 16
(L2) ← (A)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
LCD control operation
Description: Transfers the contents of register A to the LCD control register L2.
Page 115 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TL3A (Transfer data to register L3 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
0
0
1
1
0
0 2 2
0 C 16
(L3) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
LCD control operation
Description: Transfers the contents of register A to the LCD control register L3.
TLCA (Transfer data to timer LC and register RLC from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
0
0
1
1
0
1 2 2
0 D 16
(LC) ← (A)
(RLC) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Timer control operation
Description: Transfers the contents of register A to timer LC and reload
register RLC.
TMA j (Transfer data to Memory from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
1
0
1
1
j
j
j
j 2 2 B
j 16
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
RAM to register transfer
Description: After transferring the contents of register A to M(DP), an
exclusive OR operation is performed between register X
and the value j in the immediate field, and stores the result
in register X.
TMRA (Transfer data to register MR from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
0
1
0
1
1
0 2 2
1
(MR) ← (A)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
6 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Clock operation
Description: Transfers the contents of register A to clock control register
MR.
Page 116 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TPAA (Transfer data to register PA from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
1
0
1
0
1
0
1
0 2 2 A A 16
(PA0) ← (A0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Timer operation
Description: Transfers the least significant bit of register A (A0) to timer
control register PA.
TPSAB (Transfer data to Pre-Scaler and register RPS from Accumulator and register B)
Instruction
D9
code
1 0
Operation:
D0
0
0
1
1
0
1
0
1 2 2
3
5 16
(RPS7−RPS4) ← (B)
(TPS7−TPS4) ← (B)
(RPS3−RPS0) ← (A)
(TPS3−TPS0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Timer operation
Description: Transfers the contents of register B to the high-order 4 bits
of prescaler and prescaler reload register RPS. Transfers
the contents of register A to the low-order 4 bits of
prescaler and prescaler reload register RPS.
TPU0A (Transfer data to register PU0 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
1
0
1
1
0
1 2 2
2 D 16
(PU0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Transfers the contents of register A to pull-up control register PU0.
TPU1A (Transfer data to register PU1 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
1
0
1
1
1
0 2 2
2 E 16
(PU1) ← (A)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Transfers the contents of register A to pull-up control register PU1.
Page 117 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TPU2A (Transfer data to register PU2 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
1
0
1
1
1
1 2 2
2
F 16
(PU2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Transfers the contents of register A to pull-up control register PU2.
TPU3A (Transfer data to register PU3 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
0
0
1
0
0
0 2 2
0
8 16
(PU3) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Input/Output operation
Description: Transfers the contents of register A to pull-up control register PU3.
TR1AB (Transfer data to register R1 from Accumulator and register B)
Instruction
D9
code
1 0
Operation:
D0
0
0
1
1
1
1
1
1 2 2
3
F 16
(R17−R14) ← (B)
(R13−R10) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Timer control operation
Description: Transfers the contents of register B to the high-order 4 bits
(R17−R14) of timer 1 reload register R1, and the contents
of register A to the low-order 4 bits (R13−R10) of timer 1
reload register R1.
TRGA (Transfer data to register RG from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
0
0
1
0
0
1 2 2
0
(RG2−RG0) ← (A2−A0)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
9 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Clock control operation
Description: Transfers the contents of register A to register RG.
Page 118 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TV1A (Transfer data to register V1 from Accumulator)
Instruction
D9
code
0 0
Operation:
D0
0
0
1
1
1
1
1
1 2 0
3
F 16
(V1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Interrupt operation
Description: Transfers the contents of register A to interrupt control register V1.
TV2A (Transfer data to register V2 from Accumulator)
Instruction
D9
code
0 0
Operation:
D0
0
0
1
1
1
1
1
0 2 0
3 E 16
(V2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Interrupt operation
Description: Transfers the contents of register A to interrupt control register V2.
TW1A (Transfer data to register W1 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
0
0
1
1
1
0 2 2
0 E 16
(W1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Timer operation
Description: Transfers the contents of register A to timer control register
W1.
TW2A (Transfer data to register W2 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
0
0
1
1
1
1 2 2
0
(W2) ← (A)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
F 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Timer operation
Description: Transfers the contents of register A to timer control register
W2.
Page 119 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TW3A (Transfer data to register W3 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
0
1
0
0
0
0 2 2
1
0 16
(W3) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Timer operation
Description: Transfers the contents of register A to timer control register
W3.
TW4A (Transfer data to register W4 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
0
1
0
0
0
1 2 2
1
1 16
(W4) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Timer operation
Description: Transfers the contents of register A to timer control register
W4.
TW5A (Transfer data to register W5 from Accumulator)
Instruction
D9
code
1 0
Operation:
D0
0
0
0
1
0
0
1
0 2 2
1
2 16
(W5) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Timer operation
Description: Transfers the contents of register A to timer control register
W5.
TYA (Transfer data to register Y from Accumulator)
Instruction
D9
code
0 0
Operation:
D0
0
0
0
0
1
1
0
0 2 0
0 C 16
(Y) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
Register to register transfer
Description: Transfers the contents of register A to register Y.
WRST (Watchdog timer ReSeT)
Instruction
D9
code
1 0
Operation:
D0
1
0
1
0
0
0
0
0 2 2 A 0 16
(WDF1) = 1 ?
(WDF1) ← 0
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
(WDF1) = 1
Grouping:
Other operation
Description: Clears (0) to the WDF1 flag and skips the next instruction
when watchdog timer flag WDF1 is “1”. When the WDF1
flag is “0”, executes the next instruction. Also, stops the
watchdog timer function when executing the WRST
instruction immediately after the DWDT instruction.
Page 120 of 146
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
XAM j (eXchange Accumulator and Memory data)
Instruction
D9
code
1 0
Operation:
D0
1
1
0
1
j
j
j
j 2 2 D
j 16
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
-
Grouping:
RAM to register transfer
Description: After exchanging the contents of M(DP) with the contents
of register A, an exclusive OR operation is performed
between register X and the value j in the immediate field,
and stores the result in register X.
XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip)
Instruction
D9
code
1 0
Operation:
D0
1
1
1
1
j
j
j
j 2 2
F
j 16
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) −1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
(Y) = 15
Grouping:
RAM to register transfer
Description: After exchanging the contents of M(DP) with the contents
of register A, an exclusive OR operation is performed
between register X and the value j in the immediate field,
and stores the result in register X.
Subtracts 1 from the contents of register Y.
As a result of subtraction, when the contents of register Y
is 15, the next instruction is skipped. When the contents of
register Y is not 15, the next instruction is executed.
XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip)
Instruction
D9
code
1 0
Operation:
D0
1
1
1
0
j
j
j
j 2 2 E
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
j 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
-
(Y) = 0
Grouping:
RAM to register transfer
Description: After exchanging the contents of M(DP) with the contents
of register A, an exclusive OR operation is performed
between register X and the value j in the immediate field,
and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition,
when the contents of register Y is 0, the next instruction is
skipped. When the contents of register Y is not 0, the next
instruction is executed.
Page 121 of 146
455A Group
Para
meter
Instruction code
Mnemonic
Register to register transfer
RAM addresses
Function
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecim
al notation
TAB
0
0
0
0
0
1
1
1
1
0
0
1
E
1
1
(A) ← (B)
TBA
0
0
0
0
0
0
1
1
1
0
0
0
E
1
1
(B) ← (A)
TAY
0
0
0
0
0
1
1
1
1
1
0
1
F
1
1
(A) ← (Y)
TYA
0
0
0
0
0
0
1
1
0
0
0
0
C
1
1
(Y) ← (A)
TEAB
0
0
0
0
0
1
1
0
1
0
0
1
A
1
1
(E7−E4) ← (B)
(E3−E0) ← (A)
TABE
0
0
0
0
1
0
1
0
1
0
0
2
A
1
1
(B) ← (E7−E4)
(A) ← (E3−E0)
TDA
0
0
0
0
1
0
1
0
0
1
0
2
9
1
1
(DR2−DR0) ← (A2−A0)
TAD
0
0
0
1
0
1
0
0
0
1
0
5
1
1
1
(A2−A0) ← (DR2−DR0)
(A3) ← 0
TAZ
0
0
0
1
0
1
0
0
1
1
0
5
3
1
1
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
TAX
0
0
0
1
0
1
0
0
1
0
0
5
2
1
1
(A) ← (X)
TASP
0
0
0
1
0
1
0
0
0
0
0
5
0
1
1
(A2−A0) ← (SP2−SP0)
(A3) ← 0
LXY x, y
1
1
x3
x2
x1
x0
y3
y2
y1
y0
3
x
y
1
1
(X) ← x x = 0 to 15
(Y) ← y y = 0 to 15
LZ z
0
0
0
1
0
0
1
0
z1
z0
0
4
8
+z
1
1
(Z) ← z z = 0 to 3
INY
0
0
0
0
0
1
0
0
1
1
0
1
3
1
1
(Y) ← (Y) + 1
DEY
0
0
0
0
0
1
0
1
1
1
0
1
7
1
1
(Y) ← (Y) − 1
TAM j
1
0
1
1
0
0
j
j
j
j
2
C
j
1
1
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
XAM j
1
0
1
1
0
1
j
j
j
j
2
D
j
1
1
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
XAMD j
1
0
1
1
1
1
j
j
j
j
2
F
j
1
1
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) − 1
XAMI j
1
0
1
1
1
0
j
j
j
j
2
E
j
1
1
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
TMA j
1
0
1
0
1
1
j
j
j
j
2
B
j
1
1
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
Type of
instructi
ons
RAM to register transfer
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (INDEX BY TYPES)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 122 of 146
Skip condition
Carry flag CY
455A Group
−
−
Transfers the contents of register B to register A.
−
−
Transfers the contents of register A to register B.
−
−
Transfers the contents of register Y to register A.
−
−
Transfers the contents of register A to register Y.
−
−
Transfers the contents of register B to the high-order 4 bits (E3−E0) of register E, and the contents of register
A to the low-order 4 bits (E3−E0) of register E.
−
−
Transfers the high-order 4 bits (E7−E4) of register E to register B, and low-order 4 bits of register E to register
A.
−
−
Transfers the contents of the low-order 3 bits (A2−A0) of register A to register D.
−
−
Transfers the contents of register D to the low-order 3 bits (A2−A0) of register A.
“0” is stored to the bit 3 (A3) of register A.
−
−
Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A.
“0” is stored to the high-order 2 bits (A3, A2) of register A.
−
−
Transfers the contents of register X to register A.
−
−
Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2−A0) of register A.
“0” is stored to the bit 3 (A3) of register A.
Continuous
description
−
Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y.
When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed
and other LXY instructions coded continuously are skipped.
−
−
Loads the value z in the immediate field to register Z.
(Y) = 0
−
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next
instruction is skipped. When the contents of register Y is not 0, the next instruction is executed.
(Y) = 15
−
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,
the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.
−
−
After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between
register X and the value j in the immediate field, and stores the result in register X.
−
−
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
(Y) = 15
−
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,
the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.
(Y) = 0
−
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next
instruction is skipped. when the contents of register Y is not 0, the next instruction is executed.
−
−
After transferring the contents of register A to M(DP), an exclusive OR operation is performed between
register X and the value j in the immediate field, and stores the result in register X.
Detailed description
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 123 of 146
455A Group
Para
meter
Instruction code
Mnemonic
Arithmetic operation
Function
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecim
al notation
LA n
0
0
0
1
1
n
0
7
n
1
1
(A) ← n
n = 0 to 15
TABP p
0
0
1
0
p5 p4 p3 p2 p1 p0
0
8
+p
p
1
3
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note 1)
(PCL) ← (DR2−DR0, A3−A0)
(B) ← (ROM(PC))7-4
(A) ← (ROM(PC))3-0
(UPTF) = 1
(DR1, DR0) ← (ROM(PC))9, 8
(DR2) ← 0
(PC) ← (SK(SP))
(SP) ← (SP) − 1
AM
0
0
0
0
0
0
1
0
1
0
0
0
A
1
1
(A) ← (A) + (M(DP))
AMC
0
0
0
0
0
0
1
0
1
1
0
0
B
1
1
(A) ← (A) + (M(DP)) + (CY)
(CY) ← Carry
An
0
0
0
1
1
0
n
n
n
n
0
6
n
1
1
(A) ← (A) + n
n = 0 to 15
AND
0
0
0
0
0
1
1
0
0
0
0
1
8
1
1
(A) ← (A) AND (M(DP))
OR
0
0
0
0
0
1
1
0
0
1
0
1
9
1
1
(A) ← (A) OR (M(DP))
SC
0
0
0
0
0
0
0
1
1
1
0
0
7
1
1
(CY) ← 1
RC
0
0
0
0
0
0
0
1
1
0
0
0
6
1
1
(CY) ← 0
SZC
0
0
0
0
1
0
1
1
1
1
0
2
F
1
1
(CY) = 0 ?
CMA
0
0
0
0
0
1
1
1
0
0
0
1
C
1
1
(A) ← (A)
RAR
0
0
0
0
0
1
1
1
0
1
0
1
D
1
1
SB j
0
0
0
1
0
1
1
1
j
j
0
5
C
+j
1
1
(Mj(DP)) ← 1
j = 0 to 3
RB j
0
0
0
1
0
0
1
1
j
j
0
4
C
+j
1
1
(Mj(DP)) ← 0
j = 0 to 3
SZB j
0
0
0
0
1
0
0
0
j
j
0
2
j
1
1
(Mj(DP)) = 0 ?
j = 0 to 3
Type of
instructi
ons
Bit operation
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Note 1.
1
n
n
n
M3455AG8: p=0 to 63 and M3455AGC: p=0 to 95.
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 124 of 146
CY
A3A2A1A0
Skip condition
Carry flag CY
455A Group
Detailed description
Continuous
description
−
Loads the value n in the immediate field to register A.
When the LA instructions are continuously coded and executed, only the first LA instruction is executed and
other LA instructions coded continuously are skipped.
−
−
Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in
address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When UPTF is 1, Transfers
bits 9, 8 to the low-order 2 bits (DR1, DR0) of register D, and “0” is stored to the least significant bit (DR2) of
register D.
When this instruction is executed, 1 stage of stack register (SK) is used.
−
−
Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY
remains unchanged.
−
0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY.
Overflow = 0
−
Adds the value n in the immediate field to register A, and stores a result in register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no overflow as the result of operation.
Executes the next instruction when there is overflow as the result of operation.
−
−
Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result
in register A.
−
−
Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result
in register A.
−
1
Sets (1) to carry flag CY.
−
0
Clears (0) to carry flag CY.
(CY) = 0
−
Skips the next instruction when the contents of carry flag CY is “0”. Executes the next instruction when the
contents of carry flag CY is “1”.
The contents of carry flag CY remains unchanged.
−
−
Stores the one’s complement for register A’s contents in register A.
−
0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right.
−
−
Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
−
−
Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
(Mj(DP)) = 0
j = 0 to 3
−
Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of
M(DP) is “0”.
Executes the next instruction when the contents of bit j of M(DP) is “1”.
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 125 of 146
455A Group
Para
meter
Instruction code
Mnemonic
Comparison
operation
Branch operation
Subroutine operation
Function
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecim
al notation
SEAM
0
0
0
0
1
0
0
1
1
0
0
2
6
1
1
(A) = (M(DP)) ?
SEA n
0
0
0
0
1
0
0
1
0
1
0
2
5
2
2
(A) = n ?
n = 0 to 15
0
0
0
1
1
1
n
n
n
n
0
7
n
Ba
0
1
1
a6 a5 a4 a3 a2 a1 a0
1
8
+a
a
1
1
(PCL) ← a6−a0
BL p, a
0
0
1
1
p4 p3 p2 p1 p0
0
E
+p
p
2
2
(PCH) ←p (Note 1)
(PCL) ← a6−a0
1
p6 p5 a6 a5 a4 a3 a2 a1 a0
2
a
a
0
0
0
0
1
0
0
0
1
0
2
2
(PCH) ← p (Note 1)
(PCL) ← (DR2−DR0, A3−A0)
1
p6 p5 p4
0
0
p3 p2 p1 p0
2
p
p
BM a
0
1
0
a6 a5 a4 a3 a2 a1 a0
1
a
a
1
1
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
(PCL) ← a6−a0
BML p, a
0
0
1
1
p4 p3 p2 p1 p0
0
C
+p
p
2
2
1
p6 p5 a6 a5 a4 a3 a2 a1 a0
2
a
a
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note 1)
(PCL) ← a6−a0
0
0
0
1
1
0
0
0
3
0
2
2
1
p6 p5 p4
0
0
p3 p2 p1 p0
2
p
p
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note 1)
(PCL) ← (DR2−DR0, A3−A0)
RTI
0
0
0
1
0
0
0
1
1
0
0
4
6
1
1
(PC) ← (SK(SP))
(SP) ← (SP) − 1
RT
0
0
0
1
0
0
0
1
0
0
0
4
4
1
2
(PC) ← (SK(SP))
(SP) ← (SP) − 1
RTS
0
0
0
1
0
0
0
1
0
1
0
4
5
1
2
(PC) ← (SK(SP))
(SP) ← (SP) − 1
Type of
instructi
ons
Return operation
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
BLA p
BMLA p
Note 1.
0
0
1
0
0
0
0
0
M3455AG8: p=0 to 63 and p6=0, and M3455AGC: p=0 to 95.
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 126 of 146
Skip condition
Carry flag CY
455A Group
(A) = (M(DP))
−
Skips the next instruction when the contents of register A is equal to the contents of M(DP).
Executes the next instruction when the contents of register A is not equal to the contents of M(DP).
(A) = n
n = 0 to 15
−
Skips the next instruction when the contents of register A is equal to the value n in the immediate field.
Executes the next instruction when the contents of register A is not equal to the value n in the immediate
field.
−
−
Branch within a page : Branches to address a in the identical page.
−
−
Branch out of a page : Branches to address a in page p.
−
−
Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in
page p.
−
−
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
−
−
Call the subroutine : Calls the subroutine at address a in page p.
−
−
Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D
and A in page p.
−
−
Returns from interrupt service routine to main routine.
Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous
description of the LA/LXY instruction, register A and register B to the states just before interrupt.
−
−
Returns from subroutine to the routine called the subroutine.
Skip at uncondition
−
Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
Detailed description
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 127 of 146
455A Group
Para
meter
Instruction code
Mnemonic
Interrupt operation
Function
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecim
al notation
DI
0
0
0
0
0
0
0
1
0
0
0
0
4
1
1
(INTE) ← 0
EI
0
0
0
0
0
0
0
1
0
1
0
0
5
1
1
(INTE) ← 1
SNZ0
0
0
0
0
1
1
1
0
0
0
0
3
8
1
1
V10 = 0 : (EXF0) = 1 ?
(EXF0) ← 0
V10 = 1 : SNZ0 = NOP
SNZI0
0
0
0
0
1
1
1
0
1
0
0
3
A
1
1
I12 = 0 : (INT) = “L”?
Type of
instructi
ons
Timer operation
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
I12 = 1 : (INT) = “H”?
TAV1
0
0
0
1
0
1
0
1
0
0
0
5
4
1
1
(A) ← (V1)
TV1A
0
0
0
0
1
1
1
1
1
1
0
3
F
1
1
(V1) ← (A)
TAV2
0
0
0
1
0
1
0
1
0
1
0
5
5
1
1
(A) ← (V2)
TV2A
0
0
0
0
1
1
1
1
1
0
0
3
E
1
1
(V2) ← (A)
TAI1
1
0
0
1
0
1
0
0
1
1
2
5
3
1
1
(A) ← (I1)
TI1A
1
0
0
0
0
1
0
1
1
1
2
1
7
1
1
(I1) ← (A)
TPAA
1
0
1
0
1
0
1
0
1
0
2
A
A
1
1
(PA) ← (A)
TAW1
1
0
0
1
0
0
1
0
1
1
2
4
B
1
1
(A) ← (W1)
TW1A
1
0
0
0
0
0
1
1
1
0
2
0
E
1
1
(W1) ← (A)
TAW2
1
0
0
1
0
0
1
1
0
0
2
4
C
1
1
(A) ← (W2)
TW2A
1
0
0
0
0
0
1
1
1
1
2
0
F
1
1
(W2) ← (A)
TAW3
1
0
0
1
0
0
1
1
0
1
2
4
D
1
1
(A) ← (W3)
TW3A
1
0
0
0
0
1
0
0
0
0
2
1
0
1
1
(W3) ← (A)
TAW4
1
0
0
1
0
0
1
1
1
0
2
4
E
1
1
(A) ← (W4)
TW4A
1
0
0
0
0
1
0
0
0
1
2
1
1
1
1
(W4) ← (A)
TAW5
1
0
0
1
0
0
1
1
1
1
2
4
F
1
1
(A) ← (W5)
TW5A
1
0
0
0
0
1
0
0
1
0
2
1
2
1
1
(W5) ← (A)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 128 of 146
Skip condition
Carry flag CY
455A Group
−
−
Clears (0) to interrupt enable flag INTE, and disables the interrupt.
−
−
Sets (1) to interrupt enable flag INTE, and enables the interrupt.
V10 = 0 : (EXF0) = 1
−
When V10 = 0 : Clears (0) to the EXF0 flag and skips the next instruction when external 0 interrupt request
flag EXF0 is “1”. When the EXF0 flag is “0”, executes the next instruction.
When V10 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register
V1)
(INT) = “L”
However, I12 = 0
−
When I12 = 0 : Skips the next instruction when the level of INT pin is “L”. Executes the next instruction when
the level of INT0 pin is “H”.
(INT) = “H”
However, I12 = 1
Detailed description
When I12 = 1 : Skips the next instruction when the level of INT pin is “H”. Executes the next instruction when
the level of INT0 pin is “L”. (I12: bit 2 of interrupt control register I1)
−
−
Transfers the contents of interrupt control register V1 to register A.
−
−
Transfers the contents of register A to interrupt control register V1.
−
−
Transfers the contents of interrupt control register V2 to register A.
−
−
Transfers the contents of register A to interrupt control register V2.
−
−
Transfers the contents of interrupt control register I1 to register A.
−
−
Transfers the contents of register A to interrupt control register I1.
−
−
Transfers the contents of register A (A0) to timer control register PA.
−
−
Transfers the contents of timer control register W1 to register A.
−
−
Transfers the contents of register A to timer control register W1.
−
−
Transfers the contents of timer control register W2 to register A.
−
−
Transfers the contents of register A to timer control register W2.
−
−
Transfers the contents of timer control register W3 to register A.
−
−
Transfers the contents of register A to timer control register W3.
−
−
Transfers the contents of timer control register W4 to register A.
−
−
Transfers the contents of register A to timer control register W4.
−
−
Transfers the contents of timer control register W5 to register A.
−
−
Transfers the contents of register A to timer control register W5.
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 129 of 146
455A Group
Para
meter
Instruction code
Mnemonic
Function
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecim
al notation
TABPS
1
0
0
1
1
1
0
1
0
1
2
7
5
1
1
(B) ← (TPS7−TPS4)
(A) ← (TPS3−TPS0)
TPSAB
1
0
0
0
1
1
0
1
0
1
2
3
5
1
1
(RPS7−RPS4) ← (B)
(TPS7−TPS4) ← (B)
(RPS3−RPS0) ← (A)
(TPS3−TPS0) ← (A)
TAB1
1
0
0
1
1
1
0
0
0
0
2
7
0
1
1
(B) ← (T17−T14)
(A) ← (T13−T10)
T1AB
1
0
0
0
1
1
0
0
0
0
2
3
0
1
1
(R17−R14) ← (B)
(T17−T14) ← (B)
(R13−R10) ← (A)
(T13−T10) ← (A)
TR1AB
1
0
0
0
1
1
1
1
1
1
2
3
F
1
1
(R17−R14) ← (B)
(R13−R10) ← (A)
TAB2
1
0
0
1
1
1
0
0
0
1
2
7
1
1
1
(B) ← (T27−T24)
(A) ← (T23−T20)
T2AB
1
0
0
0
1
1
0
0
0
1
2
3
1
1
1
(R2L7−R2L4) ← (B)
(T27−T24) ← (B)
(R2L3−R2L0) ← (A)
(T23−T20) ← (A)
T2HAB
1
0
1
0
0
1
0
1
0
0
2
9
4
1
1
(R2H7−R2H4) ← (B)
(R2H3−R2H0) ← (A)
T2R2L
1
0
1
0
0
1
0
1
0
1
2
9
5
1
1
(T27) ← (R2L)
TLCA
1
0
0
0
0
0
1
1
0
1
2
0
D
1
1
(RLC) ← (A)
(TLC) ← (A)
SNZT1
1
0
1
0
0
0
0
0
0
0
2
8
0
1
1
V12 = 0 : (T1F) = 1 ?
After skipping, (T1F) ← 0
V12 = 1 : SNZT1=NOP
SNZT2
1
0
1
0
0
0
0
0
0
1
2
8
1
1
1
V13 = 0 : (T2F) = 1 ?
After skipping, (T2F) ← 0
V13 = 1 : SNZT2=NOP
SNZT3
1
0
1
0
0
0
0
0
1
0
2
8
2
1
1
V20 = 0 : (T3F) = 1 ?
After skipping, (T3F) ← 0
V20 = 1 : SNZT3=NOP
Type of
instructi
ons
Timer operation
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 130 of 146
Skip condition
Carry flag CY
455A Group
−
−
Transfers the high-order 4 bits of prescaler to register B.
Transfers the low-order 4 bits of prescaler to register A.
−
−
Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS.
Transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS.
−
−
Transfers the high-order 4 bits (T17−T14) of timer 1 to register B.
Transfers the low-order 4 bits (T13−T10) of timer 1 to register A.
−
−
Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1L.
Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1L.
−
−
Transfers the contents of register B to the high-order 4 bits (R17−R14) of reload register R1, and the contents
of register A to the low-order 4 bits (R13−R10) of reload register R1.
−
−
Transfers the high-order 4 bits (T27−T24) of timer 2 to register B.
Transfers the low-order 4 bits (T23−T20) of timer 2 to register A.
−
−
Transfers the contents of register B to the high-order 4 bits (R2L7−R2L4) of timer 2 and timer 2 reload register
R2L. Transfers the contents of register A to the low-order 4 bits (R2L3−R2L0) of timer 2 and timer 2 reload
register R2L.
−
−
Transfers the contents of register B to the high-order 4 bits (R2H7−R2H4) of timer 2 and timer 2 reload
register R2H. Transfers the contents of register A to the low-order 4 bits (R2H3−R2H0) of timer 2 and timer 2
reload register R2H.
−
−
Transfers the contents of timer 2 reload register R2L to timer 2.
−
−
Transfers the contents of register A to timer LC and reload register RLC.
V12 = 0 : (T1F) = 1
−
When V12 = 0 : Clears (0) to the T1F flag and skips the next instruction when timer 1 interrupt request flag
T1F is “1”. When the T1F flag is “0”, executes the next instruction.
When V12 = 1 : This instruction is equivalent to the NOP instruction.
(V12: bit 2 of interrupt control register V1)
V13 = 0 : (T2F) = 1
−
When V13 = 0 : Clears (0) to the T2F flag and skips the next instruction when timer 2 interrupt request flag
T2F is “1”. When the T2F flag is “0”, executes the next instruction.
When V13 = 1 : This instruction is equivalent to the NOP instruction.
(V13: bit 3 of interrupt control register V1)
V20 = 0 : (T3F) = 1
−
When V20 = 0 : Clears (0) to the T3F flag and skips the next instruction when timer 3 interrupt request flag
T3F is “1”. When the T3F flag is “0”, executes the next instruction.
When V20 = 1 : This instruction is equivalent to the NOP instruction.
(V20: bit 0 of interrupt control register V2)
Detailed description
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 131 of 146
455A Group
Para
meter
Instruction code
Mnemonic
Function
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecim
al notation
IAP0
1
0
0
1
1
0
0
0
0
0
2
6
0
1
1
(A) ← (P0)
OP0A
1
0
0
0
1
0
0
0
0
0
2
2
0
1
1
(P0) ← (A)
IAP1
1
0
0
1
1
0
0
0
0
1
2
6
1
1
1
(A) ← (P1)
OP1A
1
0
0
0
1
0
0
0
0
1
2
2
1
1
1
(P1) ← (A)
IAP2
1
0
0
1
1
0
0
0
1
0
2
6
2
1
1
(A) ← (P2)
OP2A
1
0
0
0
1
0
0
0
1
0
2
2
2
1
1
(P2) ← (A)
IAP3
1
0
0
1
1
0
0
0
1
1
2
6
3
1
1
(A) ← (P3)
OP3A
1
0
0
0
1
0
0
0
1
1
2
2
3
1
1
(P3) ← (A)
CLD
0
0
0
0
0
1
0
0
0
1
0
1
1
1
1
(D) ← 1
RD
0
0
0
0
0
1
0
1
0
0
0
1
4
1
1
(D(Y)) ← 0
(Y) = 0 to 7
SD
0
0
0
0
0
1
0
1
0
1
0
1
5
1
1
(D(Y)) ← 1
(Y) = 0 to 7
SZD
0
0
0
0
1
0
0
1
0
0
0
2
4
2
2
(D(Y)) = 0 ?
(Y) = 0 to 5
0
0
0
0
1
0
1
0
1
1
0
2
B
RCP
1
0
1
0
0
0
1
1
0
0
2
8
C
1
1
(C) ← 0
SCP
1
0
1
0
0
0
1
1
0
1
2
8
D
1
1
(C) ← 1
TFR0A
1
0
0
0
1
0
1
0
0
0
2
2
8
1
1
(FR0) ← (A)
TFR1A
1
0
0
0
1
0
1
0
0
1
2
2
9
1
1
(FR1) ← (A)
TFR2A
1
0
0
0
1
0
1
0
1
0
2
2
A
1
1
(FR2) ← (A)
TFR3A
1
0
0
0
1
0
1
0
1
1
2
2
B
1
1
(FR3) ← (A)
TAPU0
1
0
0
1
0
1
0
1
1
1
2
5
7
1
1
(A) ← (PU0)
TPU0A
1
0
0
0
1
0
1
1
0
1
2
2
D
1
1
(PU0) ← (A)
TAPU1
1
0
0
1
0
1
1
1
1
0
2
5
E
1
1
(A) ← (PU1)
TPU1A
1
0
0
0
1
0
1
1
1
0
2
2
E
1
1
(PU1) ← (A)
TAPU2
1
0
0
1
0
1
1
1
1
1
2
5
F
1
1
(A) ← (PU2)
TPU2A
1
0
0
0
1
0
1
1
1
1
2
2
F
1
1
(PU2) ← (A)
TAPU3
1
0
0
1
0
1
1
1
0
1
2
5
D
1
1
(A) ← (PU3)
TPU3A
1
0
0
0
0
0
1
0
0
0
2
0
8
1
1
(PU3) ← (A)
Type of
instructi
ons
Input/Output operation
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 132 of 146
Skip condition
Carry flag CY
455A Group
−
−
Transfers the input of port P0 to register A.
−
−
Outputs the contents of register A to port P0.
−
−
Transfers the input of port P1 to register A.
−
−
Outputs the contents of register A to port P1.
−
−
Transfers the input of port P2 to the register A.
−
−
Outputs the contents of the register A to port P2.
−
−
Transfers the input of port P3 to the register A.
−
−
Outputs the contents of the register A to port P3.
−
−
Sets (1) to port D.
−
−
Clears (0) to a bit of port D specified by register Y.
−
−
Sets (1) to a bit of port D specified by register Y.
(D(Y)) = 0
Y = 0 to 4
−
Skips the next instruction when a bit of port D specified by register Y is “0”. Executes the next instruction
when a bit of port D specified by register Y is “1”.
−
−
Clears (0) to port C.
−
−
Sets (1) to port C.
−
−
Transfers the contents of register A to port output structure control register FR0.
−
−
Transfers the contents of register A to port output structure control register FR1.
−
−
Transfers the contents of register A to port output structure control register FR2.
−
−
Transfers the contents of register A to port output structure control register FR3.
−
−
Transfers the contents of pull-up control register PU0 to register A.
−
−
Transfers the contents of register A to pull-up control register PU0.
−
−
Transfers the contents of pull-up control register PU1 to register A.
−
−
Transfers the contents of register A to pull-up control register PU1.
−
−
Transfers the contents of pull-up control register PU2 to register A.
−
−
Transfers the contents of register A to pull-up control register PU2.
−
−
Transfers the contents of pull-up control register PU3 to register A.
−
−
Transfers the contents of register A to pull-up control register PU3.
Detailed description
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 133 of 146
455A Group
Para
meter
Instruction code
Mnemonic
Input/Output operation
LCD operation
Function
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecim
al notation
TAK0
1
0
0
1
0
1
0
1
1
0
2
5
6
1
1
(A) ← (K0)
TK0A
1
0
0
0
0
1
1
0
1
1
2
1
B
1
1
(K0) ← (A)
TAK1
1
0
0
1
0
1
1
0
0
1
2
5
9
1
1
(A) ← (K1)
TK1A
1
0
0
0
0
1
0
1
0
0
2
1
4
1
1
(K1) ← (A)
TAK2
1
0
0
1
0
1
1
0
1
0
2
5
A
1
1
(A) ← (K2)
TK2A
1
0
0
0
0
1
0
1
0
1
2
1
5
1
1
(K2) ← (A)
TAK3
1
0
0
1
0
1
1
0
1
1
2
5
B
1
1
(A) ← (K3)
TK3A
1
0
0
0
1
0
1
1
0
0
2
2
C
1
1
(K3) ← (A)
TAL1
1
0
0
1
0
0
1
0
1
0
2
4
A
1
1
(A) ← (L1)
TL1A
1
0
0
0
0
0
1
0
1
0
2
0
A
1
1
(L1) ← (A)
TL2A
1
0
0
0
0
0
1
0
1
1
2
0
B
1
1
(L2) ← (A)
TL3A
1
0
0
0
0
0
1
1
0
0
2
0
C
1
1
(L3) ← (A)
TC1A
1
0
1
0
1
0
1
0
0
0
2
A
8
1
1
(C1) ← (A)
TC2A
1
0
1
0
1
0
1
0
0
1
2
A
9
1
1
(C2) ← (A)
TC3A
1
0
0
0
1
0
0
1
1
0
2
2
6
1
1
(C3) ← (A)
TAMR
1
0
0
1
0
1
0
0
1
0
2
5
2
1
1
(A) ← (MR)
TMRA
1
0
0
0
0
1
0
1
1
0
2
1
6
1
1
(MR) ← (A)
TRGA
1
0
0
0
0
0
1
0
0
1
2
0
9
1
1
(RG2−RG0) ← (A2−A0)
Type of
instructi
ons
Clock operation
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 134 of 146
Skip condition
Carry flag CY
455A Group
−
−
Transfers the contents of key-on wakeup control register K0 to register A.
−
−
Transfers the contents of register A to key-on wakeup control register K0.
−
−
Transfers the contents of key-on wakeup control register K1 to register A.
−
−
Transfers the contents of register A to key-on wakeup control register K1.
−
−
Transfers the contents of key-on wakeup control register K2 to register A.
−
−
Transfers the contents of register A to key-on wakeup control register K2.
−
−
Transfers the contents of key-on wakeup control register K3 to register A.
−
−
Transfers the contents of register A to key-on wakeup control register K3.
−
−
Transfers the contents of the LCD control register L1 to register A.
−
−
Transfers the contents of register A to the LCD control register L1.
−
−
Transfers the contents of register A to the LCD control register L2.
−
−
Transfers the contents of register A to the LCD control register L3.
−
−
Transfers the contents of register A to the LCD control register C1.
−
−
Transfers the contents of register A to the LCD control register C2.
−
−
Transfers the contents of register A to the LCD control register C3.
−
−
Transfers the contents of clock control regiser MR to register A.
−
−
Transfers the contents of register A to clock control register MR.
−
−
Transfers the contents of register A to clock control register RG.
Detailed description
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 135 of 146
455A Group
Para
meter
Instruction code
Mnemonic
Function
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecim
al notation
NOP
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
(PC) ← (PC) + 1
POF
0
0
0
0
0
0
0
0
1
0
0
0
2
1
1
Transition to clock operating mode
POF2
0
0
0
0
0
0
1
0
0
0
0
0
8
1
1
Transition to RAM back-up mode
EPOF
0
0
0
1
0
1
1
0
1
1
0
5
B
1
1
POF or POF2 instruction valid
SNZP
0
0
0
0
0
0
0
0
1
1
0
0
3
1
1
(P) = 1 ?
WRST
1
0
1
0
1
0
0
0
0
0
2
A
0
1
1
(WDF1) = 1 ?
(WDF1) ← 0
DWDT
1
0
1
0
0
1
1
1
0
0
2
9
C
1
1
Stop of watchdog timer function enabled
SRST
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
System reset
RUPT
0
0
0
1
0
1
1
0
0
0
0
5
8
1
1
(UPTF) ← 0
SUPT
0
0
0
1
0
1
1
0
0
1
0
5
9
1
1
(UPTF) ← 1
SVDE
1
0
1
0
0
1
0
0
1
1
2
9
3
1
1
At power down mode, voltage drop detection
circuit valid
SNZVD
1
0
1
0
0
0
1
0
1
0
2
8
A
1
1
(VDF) = 1?
RBK
(Note 1)
0
0
0
1
0
0
0
0
0
0
0
4
0
1
1
When TABPp instruction is executed, p6 ← 0
SBK
(Note 1)
0
0
0
1
0
0
0
0
0
1
0
4
1
1
1
When TABPp instruction is executed, p6 ← 1
Type of
instructi
ons
Other operation
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Note 1. (SBK, RBK) cannot be used int the M3455AG8. The pages which can be referred by the TABP instruction after the SBK
instruction is executed are 64 to 95 in the M3455AGC.
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 136 of 146
Skip condition
Carry flag CY
455A Group
−
−
No operation; Adds 1 to program counter value, and others remain unchanged.
−
−
Puts the system in clock operating mode by executing the POF instruction after executing the EPOF
instruction.
−
−
Puts the system in RAM back-up state by executing the POF2 instruction after executing the EPOF
instruction.
−
−
Makes the immediate after POF or POF2 instruction valid by executing the EPOF instruction.
(P) = 1
−
Skips the next instruction when the P flag is “1”.
After skipping, the P flag remains unchanged.
Executes the next instruction when the P flag is “0”.
(WDF1) = 1
Detailed description
Clears (0) to the WDF1 flag and skips the next instruction when watchdog timer flag WDF1 is “1”. When the
WDF1 flag is “0”, executes the next instruction. Also, stops the watchdog timer function when executing the
WRST instruction immediately after the DWDT instruction.
−
−
Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction.
−
−
System reset occurs.
−
−
Clears (0) to the high-order bit reference enable flag UPTF.
−
−
Sets (1) to the high-order bit reference enable flag UPTF.
(VDF) = 1
−
Skips the next instruction when voltage drop detection circuit flag VDF is “1”. Execute instruction when VPF
is “0”.
After skipping, the contents of VDF remains unchanged.
−
−
Validates the voltage drop detection circuit at power down (clock operating mode and RAM back-up mode).
−
−
Sets referring data area to pages 0 to 63 when the TABP p instruction is executed.
This instruction is valid only for the TABP p instruction.
−
−
Sets referring data area to pages 64 to 127 when the TABP p instruction is executed.
This instruction is valid only for the TABP p instruction.
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 137 of 146
455A Group
INSTRUCTION CODE TABLE
010000 011000
D9−
to
000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111
to
D4
010111 011111
D3− H e x ,
notation
D0
00
01
BLA
02
03
04
05
06
07
SZB
BMLA RBK** TASP
0
A
0
LA
0
SZB
1
−
A
1
SZB
2
−
−
TAX
SZB
3
−
−
RT
08
09
0A
0B
0C
0D
10−17 18−F
0E
0F
TABP TABP TABP TABP
BML BML
0
16
32*
48*
BL
BL
BM
B
LA
1
TABP TABP TABP TABP
BML BML
1
17
33*
49*
BL
BL
BM
B
A
2
LA
2
TABP TABP TABP TABP
BML BML
2
18
34*
50*
BL
BL
BM
B
TAZ
A
3
LA
3
TABP TABP TABP TABP
BML BML
3
19
35*
51*
BL
BL
BM
B
TAV1
A
4
LA
4
TABP TABP TABP TABP
BML BML
4
20
36*
52*
BL
BL
BM
B
A
5
LA
5
TABP TABP TABP TABP
BML BML
5
21
37*
53*
BL
BL
BM
B
0000
0
NOP
0001
1
SRST CLD
0010
2
0011
3
0100
4
DI
RD
SZD
−
0101
5
EI
SD
SEAn
−
RTS TAV2
0110
6
RC
−
SEAM
−
RTI
−
A
6
LA
6
TABP TABP TABP TABP
BML BML
6
22
38*
54*
BL
BL
BM
B
0111
7
SC
DEY
−
−
−
−
A
7
LA
7
TABP TABP TABP TABP
BML BML
7
23
39*
55*
BL
BL
BM
B
1000
8
POF2 AND
−
SNZ0
LZ
0
RUPT
A
8
LA
8
TABP TABP TABP TABP
BML BML
8
24
40*
56*
BL
BL
BM
B
1001
9
TDA
−
LZ
1
SUPT
A
9
LA
9
TABP TABP TABP TABP
BML BML
9
25
41*
57*
BL
BL
BM
B
1010
A
AM TEAB TABE
SNZI
0
LZ
2
−
A
10
LA
10
TABP TABP TABP TABP
BML BML
10
26
42*
58*
BL
BL
BM
B
1011
B
AMC
−
−
−
LZ
3
EPOF
A
11
LA
11
TABP TABP TABP TABP
BML BML
11
27
43*
59*
BL
BL
BM
B
1100
C
TYA
CMA
−
−
RB
0
SB
0
A
12
LA
12
TABP TABP TABP TABP
BML BML
12
28
44*
60*
BL
BL
BM
B
1101
D
−
RAR
−
−
RB
1
SB
1
A
13
LA
13
TABP TABP TABP TABP
BML BML
13
29
45*
61*
BL
BL
BM
B
1110
E
TBA
TAB
−
TV2A
RB
2
SB
2
A
14
LA
14
TABP TABP TABP TABP
BML BML
14
30
46*
62*
BL
BL
BM
B
1111
F
−
TAY
SZC TV1A
RB
3
SB
3
A
15
LA
15
TABP TABP TABP TABP
BML BML
15
31
47*
63*
BL
BL
BM
B
POF
−
SNZP INY
−
OR
SBK** TAD
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order
4 bits of the machine language code, and D 9– D 4 show the high-order 6 bits of the machine language code. The hexadecimal
representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each
instruction is shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are
described below.
BL
BML
BLA
BMLA
SEA
SZD
The second word
10 paaa aaaa
10 paaa aaaa
10 pp00 pppp
10 pp00 pppp
00 0111 nnnn
00 0010 1011
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
• **(SBK and RBK instructions) cannot be used in the M3455AG8.
• * cannot be used after the SBK instruction executed in the M3455AGC.
• A page referred by the TABP instruction can be switched by the SBK and RBK instructions in
the M3455AGC.
• The pages which can be referred by the TABP instruction after the SBK instruction is executed
are 64 to 95 in the M3455AGC.
• The pages which can be referred by the TABP instruction after the RBK instruction is executed
are 0 to 63.
• When the SBK instruction is not used, the pages which can be referred by the TABP instruction
are 0 to 63.
Page 138 of 146
455A Group
INSTRUCTION CODE TABLE
110000
D9−
to
100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111
D4
111111
D3−
D0
Hex,
notation
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30−3F
0000
0
−
TW3A OP0A T1AB
−
−
IAP0 TAB1
SNZT
1
−
WRST
TMA
0
TAM
0
XAM XAMI XAMD
LXY
0
0
0
0001
1
−
TW4A OP1A T2AB
−
−
IAP1 TAB2
SNZT
2
−
−
TMA
1
TAM
1
XAM XAMI XAMD
LXY
1
1
1
0010
2
−
TW5A OP2A
−
SNZT
3
−
−
TMA
2
TAM
2
XAM XAMI XAMD
LXY
2
2
2
0011
3
−
−
0100
4
−
0101
5
0110
−
−
OP3A
−
−
TAI1
IAP3
−
−
SVDE
−
TMA
3
TAM
3
XAM XAMI XAMD
LXY
3
3
3
TK1A
−
−
−
−
−
−
−
T2HA
B
−
TMA
4
TAM
4
XAM XAMI XAMD
LXY
4
4
4
−
TK2A
−
TPSAB
−
−
−
TABPS
−
T2R2
L
−
TMA
5
TAM
5
XAM XAMI XAMD
LXY
5
5
5
6
−
TMRA TC3A
−
−
TAK0
−
−
−
−
−
TMA
6
TAM
6
XAM XAMI XAMD
LXY
6
6
6
0111
7
−
TI1A
−
−
−
TAPU0
−
−
−
−
−
TMA
7
TAM
7
XAM XAMI XAMD
LXY
7
7
7
1000
8
TPU3A
−
TFR0A
−
−
−
−
−
−
−
TC1A
TMA
8
TAM
8
XAM XAMI XAMD
LXY
8
8
8
1001
9
TRGA
−
TFR1A
−
−
TAK1
−
−
−
−
TC2A
TMA
9
TAM
9
XAM XAMI XAMD
LXY
9
9
9
1010
A
TL1A
−
TFR2A
−
TAL1 TAK2
−
−
SNZV
D
−
TPAA
TMA
10
TAM
10
XAM XAMI XAMD
LXY
10
10
10
1011
B
TL2A TK0A TFR3A
−
TAW1 TAK3
−
−
−
−
−
TMA
11
TAM
11
XAM XAMI XAMD
LXY
11
11
11
1100
C
TL3A
−
TK3A
−
TAW2
−
−
RCP DWDT
−
TMA
12
TAM
12
XAM XAMI XAMD
LXY
12
12
12
1101
D
TLCA
−
TPU0A
−
TAW3 TAPU3
−
−
SCP
−
−
TMA
13
TAM
13
XAM XAMI XAMD
LXY
13
13
13
1110
E
TW1A
−
TPU1A
−
TAW4 TAPU1
−
−
−
−
−
TMA
14
TAM
14
XAM XAMI XAMD
LXY
14
14
14
1111
F
TW2A
−
TPU2A TR1AB TAW5 TAPU2
−
−
−
−
−
TMA
15
TAM
15
XAM XAMI XAMD
LXY
15
15
15
TAMR IAP2
−
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order
4 bits of the machine language code, and D 9– D 4 show the high-order 6 bits of the machine language code. The hexadecimal
representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each
instruction is shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are
described below.
BL
BML
BLA
BMLA
SEA
SZD
The second word
10 paaa aaaa
10 paaa aaaa
10 pp00 pppp
10 pp00 pppp
00 0111 nnnn
00 0010 1011
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 139 of 146
455A Group
Electrical characteristics
Absolute maximum ratings
Table 30 Absolute maximum ratings
Symbol
Parameter
VDD
Supply voltage
VI
Input voltage
VO
Output voltage P0, P1, P2, P3, D0–D7, RESET
VO
Output voltage C/CNTR, XOUT, XCOUT
VO
Output voltage SEG0 to SEG31, COM0 to COM3
Conditions
Ratings
Unit
-
−0.3 to 6.5
V
-
−0.3 to VDD+0.3
V
Output transistors in cut-off
state
-
−0.3 to VDD+0.3
V
−0.3 to VDD+0.3
V
-
−0.3 to VDD+0.3
V
P0, P1, P2, P3, D0-D7, RESET, XIN,
XCIN, INT, CNTR
Ta = 25 °C
Pd
Power dissipation
300
mW
Topr
Operating temperature range
-
−20 to 85
°C
Tstg
Storage temperature range
-
−40 to 125
°C
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 140 of 146
455A Group
Recommended operating conditions
Table 31 Recommended operating conditions 1 (Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
Symbol
Parameter
VDD
Supply voltage
(with a ceramic resonator)
VDD
Supply voltage
(when an external clock is
used)
VDD
Supply voltage
(when quartz-crystal oscillation
is used)
Supply voltage
(Low-speed/High-speed onchip oscillator is used)
RAM back-up voltage
Supply voltage
LCD power supply (Note 1)
“H” level input voltage
VDD
VRAM
VSS
VLC3
VIH
Conditions
Min.
4
2.7
2
1.8
4
2.7
2
1.8
1.8
f(STCK) ≤ 6MHz
f(STCK) ≤ 4.4MHz
f(STCK) ≤ 2.2MHz
f(STCK) ≤ 1.1MHz
f(STCK) ≤ 4.8MHz
f(STCK) ≤ 3.2MHz
f(STCK) ≤ 1.6MHz
f(STCK) ≤ 0.8MHz
f(STCK) ≤ 50 kHz
1.8
(at RAM back-up)
1.6
“L” level input voltage
P0, P1, P2, P3, D0–D7
XIN, XCIN
INT
CNTR
P0, P1, P2, P3, D0–D7
XIN, XCIN
RESET
IOH(peak)
“H” level peak output current
INT
CNTR
P0, P1, P2, P3, D0–D5
C/CNTR
IOH(avg)
“H” level average output current P0, P1, P2, P3, D0–D5
(Note 2)
C/CNTR
IOL(peak)
“L” level peak output current
P0, P1, P2, P3, D0–D7, C/CNTR
RESET
IOL(avg)
“L” level average output current P0, P1, P2, P3, D0–D7, C/CNTR
(Note 2)
RESET
ΣIOH(avg)
“H” level total average current
ΣIOL(avg)
“L” level total average current
P0, C/CNTR
P1, P2, P3, D0−D5
P0, C/CNTR
P1, P2, P3, D0−D7, RESET
Note 1. At 1/2 bias: VLC1 = VLC2 = (1/2)•VLC3
At 1/3 bias: VLC1 = (1/3)•VLC3, VLC2 = (2/3)•VLC3
Note 2. The average output current is the average value during 100ms.
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Max.
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
Page 141 of 146
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
Unit
V
V
V
5.5
V
5.5
V
V
V
V
0
RESET
VIL
Limits
Typ.
1.8
0.8VDD
0.7VDD
0.85VDD
VDD
VDD
VDD
VDD
0.85VDD
VDD
0.8VDD
0
0
0
VDD
0.2VDD
0.3VDD
0.3VDD
0
0.15VDD
0
0.15VDD
−20
−10
−30
−15
−10
−5
−20
−10
24
12
10
4
15
7
5
2
−40
−40
40
40
V
mA
mA
mA
mA
mA
mA
455A Group
Table 32 Recommended operating conditions 2 (Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
Symbol
f(XIN)
Parameter
Conditions
Oscillation frequency
(with a ceramic resonator)
f(STCK) = f(XIN)
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)/4, f(XIN)/8
f(XIN)
Oscillation frequency
(with an external clock input)
f(STCK) = f(XIN)
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)/4, f(XIN)/8
f(XCIN)
f(CNTR)
tw(CNTR)
TPON
Oscillation frequency
(at quarts-crystal oscillation)
Timer external input frequency
Timer external input period
(“H” and “L” pulse width)
Power-on reset circuit valid
supply voltage rising time
(Note 1)
Min.
VDD = 4.0 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 2 V to 5.5 V
VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 2 V to 5.5 V
VDD = 1.8 V to 5.5 V
VDD = 2 V to 5.5 V
VDD = 1.8 V to 5.5 V
VDD = 4 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 2 V to 5.5 V
VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 2 V to 5.5 V
VDD = 1.8 V to 5.5 V
VDD = 2 V to 5.5 V
VDD = 1.8 V to 5.5 V
Quartz-crystal oscillator
CNTR
CNTR
Limits
Typ.
Max.
6
4.4
2.2
1.1
6
4.4
2.2
6
4.4
MHz
4.8
3.2
1.6
0.8
4.8
3.2
1.6
4.8
3.2
50
MHz
f(STCK)/6
Hz
s
100
µs
3/f(STCK)
VDD = 0 → 1.8V
Unit
kHz
Note 1. If the rising time exceeds the maximum rating value, connect a capacitor between the RESET pin and Vss at the shortest
distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage.
with a ceramic resonator
at external clock oscillation
f(STCK)
[MHz]
f(STCK)
[MHz]
6
4.8
4.4
3.2
2.2
1.6
1.1
Recommended
operating conditions
1.8 2
2.7
4
Recommended
operating conditions
0.8
1.8 2
5.5 VDD
[V]
2.7
4
5.5 VDD
[V]
at quartz-crystal oscillation
f(STCK)
[kHz]
50
Recommended
operating conditions
1.8
Fig 80. System clock (STCK) operating condition map
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 142 of 146
5.5 VDD
[V]
455A Group
Electrical characteristics
Table 33 Electrical characteristics 1 (Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
Symbol
VOH
Parameter
“H” level output voltage P0, P1, P2, P3, D0–D5
Test conditions
VDD = 5V
VDD = 3V
VOH
“H” level output voltage C/CNTR
VDD = 5V
VDD = 3V
VOL
“L” level output voltage
P0, P1, P2, P3, D0–D7
C/CNTR
VDD = 5V
VDD = 3V
VOL
“L” level output voltage
RESET
IIH
“H” level input current
IIL
“L” level input current
RPU
Pull-up resistor value
P0, P1, P2, P3, D0–D7
RESET, XIN, XCIN, INT
CNTR
P0, P1, P2, P3, D0–D7
RESET, XIN, XCIN, INT
CNTR
P0, P1, P2, P3, D0 to D7
RESET
VT+ −VT−
Hysteresis
RESET
VT+ −VT−
Hysteresis
INT
VT+ −VT−
Hysteresis
CNTR
f(HSOCO)
High-speed on-chip oscillator clock frequency
f(LSOCO)
Low-speed on-chip oscillator clock frequency
RCOM
COM output impedance
(Note 1)
RSEG
SEG output impedance
(Note 1)
RVLC
Internal resistor for LCD power supply
VDD = 5V
VDD = 3V
VI = VDD
VI = 0V
P0, P1, P2, P3, D0 to D7
No pull-up
VI = 0V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
When dividing resistor 2r × 3 selected
When dividing resistor 2r × 2 selected
When dividing resistor r × 3 selected
When dividing resistor r × 2 selected
Note 1. The impedance state is the resistor value of the output voltage.
at VLC3 level output: VO = 0.8 VLC3
at VLC2 level output: VO = 0.8 VLC2
at VLC1 level output: VO = 0.2 VLC2 + VLC1
at VSS level output: VO = 0.2 VLC1
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 143 of 146
IOH = −10mA
IOH = −3mA
IOH = −5mA
IOH = −1mA
IOH = −20mA
IOH = −6mA
IOH =−10mA
IOH = −3mA
IOL = 15mA
IOL = 5mA
IOL = 9mA
IOL = 3mA
IOL = 5mA
IOL = 1mA
IOL = 2mA
Min.
3
4.1
2.1
2.4
3
4.1
2.1
2.4
30
50
400
200
40
20
300
200
150
100
Limits
Typ. Max.
Unit
V
V
2
0.9
1.4
0.9
2
0.6
0.9
2
µA
−2
µA
60
125
120
250
1
0.4
0.6
0.3
0.2
0.2
1000 1600
500
700
100
160
50
70
1.5
7.5
2
10
1.5
7.5
2
10
600 1200
400
800
300
600
200
400
V
V
kΩ
V
V
V
kHz
kHz
kΩ
kΩ
kΩ
455A Group
Table 34 Electrical characteristics 2 (Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
Symbol
IDD
Parameter
Supply current
Test conditions
at active mode
VDD = 5V
(with a ceramic oscillator) f(XIN) = 6MHz
(1, 2)
f(HSOCO) = stop
f(XCIN) = stop
f(LSOCO) = stop
VDD = 5V
f(XIN) = 4MHz
f(HSOCO) = stop
f(XCIN) = stop
f(LSOCO) = stop
VDD = 3V
f(XIN) = 4MHz
f(HSOCO) = stop
f(XCIN) = stop
f(LSOCO) = stop
at active mode
VDD = 5V
(with a quartz-crystal
f(XIN) = stop
f(HSOCO) = stop
oscillator)(1, 2)
f(XCIN) = 32 kHz
f(LSOCO) = stop
VDD = 3V
f(XIN) = stop
f(HSOCO) = stop
f(XCIN) = 32 kHz
f(LSOCO) = stop
at active mode
VDD = 5V
(with a high-speed
f(XIN) = stop
on-chip oscillator
f(HSOCO) = active
f(XCIN) = stop
f(HSOCO))(1, 2)
f(LSOCO) = stop
VDD = 3V
f(XIN) = stop
f(HSOCO) = active
f(XCIN) = stop
f(LSOCO) = stop
at active mode
VDD = 5V
(with a low-speed on-chip f(XIN) = stop
oscillator f(LSOCO))(1, 2) f(HSOCO) = stop
f(XCIN) = stop
f(LSOCO) = active
VDD = 3V
f(XIN) = stop
f(HSOCO) = stop
f(XCIN) = stop
f(LSOCO) = active
at clock operation mode
f(XCIN) = 32 kHz
(POF instruction
execution)
(1, 2)
f(LSOCO) = active
f(STCK) = f(XIN)/8
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)
Min.
Limits
Typ. Max.
1.2
2.4
1.3
2.6
1.6
3.2
2.2
4.4
Unit
mA
f(STCK) = f(XIN)/8
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)
0.9
1
1.2
1.6
1.8
2
2.4
3.2
mA
f(STCK) = f(XIN)/8
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)
0.3
0.4
0.5
0.7
0.6
0.8
1
1.4
mA
f(STCK) = f(XCIN)/8
f(STCK) = f(XCIN)/4
f(STCK) = f(XCIN)/2
f(STCK) = f(XCIN)
7
8
10
14
14
16
20
28
µA
f(STCK) = f(XCIN)/8
f(STCK) = f(XCIN)/4
f(STCK) = f(XCIN)/2
f(STCK) = f(XCIN)
5
6
7
8
10
12
14
16
µA
f(STCK) = f(HSOCO)/8
f(STCK) = f(HSOCO)/4
f(STCK) = f(HSOCO)/2
f(STCK) = f(HSOCO)
50
70
110
190
100
140
220
380
µA
f(STCK) = f(HSOCO)/8
f(STCK) = f(HSOCO)/4
f(STCK) = f(HSOCO)/2
f(STCK) = f(HSOCO)
12
18
30
54
24
36
60
108
µA
f(STCK) = f(LSOCO)/8
f(STCK) = f(LSOCO)/4
f(STCK) = f(LSOCO/2
f(STCK) = f(LSOCO)
10
12
16
24
20
24
32
48
µA
f(STCK) = f(LSOCO)/8
f(STCK) = f(LSOCO)/4
f(STCK) = f(LSOCO)/2
f(STCK) = f(LSOCO)
3
4
5
7
6
8
10
14
µA
6
5
20
5
0.1
12
10
40
10
3
10
6
µA
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
Ta = 25°C
µA
VDD = 5V
VDD = 3V
Note 1. The voltage drop detection circuit operation current (IRST) is added.
Note 2. When the internal dividing resistors for LCD power are used, the current values according to using resistor values are added.
at RAM back-up mode
(POF2 instruction
execution)(1)
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 144 of 146
455A Group
Voltage drop detection circuit characteristics
Table 35 Voltage drop detection circuit characteristics (Ta = –20 °C to 85 °C, unless otherwise noted)
Symbol
VRST-
Detection voltage
(reset occurs) (Note 1)
VRST+
Detection voltage
(reset release) (Note 2)
Detection voltage
(skip occurs) (Note 3)
VSKIP
VRST+ −VRSTIRST
TRST
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Parameter
Test conditions
Min.
Ta = 25°C
−20°C≤ Ta < 0°C
0°C≤ Ta < 50°C
50°C≤ Ta ≤ 85°C
Ta = 25°C
−20°C≤ Ta < 0°C
0°C≤ Ta < 50°C
50°C≤ Ta ≤ 85°C
Limits
Typ.
1.7
1.6
1.3
1.1
Max.
V
2.2
2.1
1.8
1.8
1.7
1.4
1.2
Ta = 25°C
−20°C≤ Ta < 0°C
0°C≤ Ta < 50°C
50°C≤ Ta ≤ 85°C
V
2.3
2.2
1.9
2
1.9
1.6
1.4
Detection voltage hysteresis
Operation current (Note 4)
Unit
V
2.5
2.4
2.1
0.1
V
VDD = 5V
30
60
µA
VDD = 3V
15
30
VDD = 1.8V
6
12
Detection time (Note 5)
VDD → (VRST- −0.1V)
0.2
1.2
ms
The detection voltage (VRST−) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling.
The detection voltage (VRST+) is defined as the voltage when reset is released when the supply voltage (VDD) is rising from reset
occurs.
When the supply voltage goes lower than the detection voltage (VSKIP), the voltage drop detection circuit interrupt request flag
(VDF) is set to “1“.
Voltage drop detection circuit operation current (IRST) is added to IDD (power current) when voltage drop detection circuit is used.
The detection time (TRST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST- −0.1V].
Basic timing diagram
Machine cycle
Parameter
Pin name
System clock
STCK
Port output
D0 to D7
P00 to P03
P10 to P13
P20 to P23
P30 to P33, C
Port input
D0 to D7
P00 to P03
P10 to P13
P20 to P23
P30 to P33
Interrupt input
INT
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
Page 145 of 146
Mi
Mi + 1
455A Group
PACKAGE OUTLINE
JEITA Package Code
P-LQFP52-10x10-0.65
RENESAS Code
PLQP0052JA-A
Previous Code
52P6A-A
MASS[Typ.]
0.3g
Under development
HD
*1
D
39
27
40
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
26
bp
c1
c
E
*2
HE
b1
Reference
Symbol
14
1
Terminal cross section
ZE
52
13
ZD
Index mark
A
A1
A2
c
F
e
y
*3
L
bp
Page 146 of 146
Min
9.9
9.9
Nom
10.0
10.0
1.4
11.8 12.0
11.8 12.0
0.05
0.27
0.09
0°
L1
x
Detail F
Rev.1.01 Feb 15, 2008
REJ03B0224-0101
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
Dimension in Millimeters
e
x
y
ZD
ZE
L
L1
0.35
Max
10.1
10.1
12.2
12.2
1.7
0.1 0.15
0.32 0.37
0.30
0.145 0.20
0.125
8°
0.65
0.13
0.10
1.1
1.1
0.5 0.65
1.0
REVISION
REVISIONHISTORY
HISTORY
455A Group Datasheet
Rev.
Date
Description
1.00
Oct 18, 2007
-
First edition issued
1.01
Feb 15, 2008
-
Delete the “PRELIMINARY” note
7
Table 6: "The key-on wakeup function is invalid." is added to “Usage Condition”
column of “XCOUT/D7”- “Open”, “D0-D4”-“Open”, and “D5/INT”-“Open”.
28
Table 15: Revised
50
Figure 48: Revised
58
Figure 56: Revised whole
76
Interrupt control register I1:
At the “INT pin timer 1 count start synchronous circuit selection bit” value is “0”
“Timer 1 disabled” → “Timer 1 count start synchronous circuit not selected”
At the “INT pin timer 1 count start synchronous circuit selection bit” value is “1”
“Timer 1 enabled” → “Timer 1 count start synchronous circuit selected”
89
The second word “D8” value of “BL p, a” instruction: “0” → “p6”
Note: “p=0 to 47” → ”M3455AG8: p=0 to 63 p6=0
M3455AGC: p=0 to 95”
Page
Summary
The second word “D8” value of “BLA p” instruction: “0” → “p6”
Note: “p=0 to 47” → ”M3455AG8: p=0 to 63 p6=0
M3455AGC: p=0 to 95”
90
The second word “D8” value of “BML p, a” instruction: “0” → “p6”
Note: “p=0 to 47” → ”M3455AG8: p=0 to 63 p6=0
M3455AGC: p=0 to 95”
The second word “D8” value of “BMLA p” instruction: “0” → “p6”
Note: “p=0 to 47” → ”M3455AG8: p=0 to 63 p6=0
M3455AGC: p=0 to 95”
98
The “RBK” instruction order is changed to next of the ”RBj” instruction
126
The second word “D8” value of “BL p, a” instruction: “0” → “p6”
The second word “D8” value of “BLA p” instruction: “0” → “p6”
The second word “D8” value of “BML p, a” instruction: “0” → “p6”
The second word “D8” value of “BMLA p” instruction: “0” → “p6”
Note: ”M3455AG8: p6=0” is added
144
Table 34: All “f(STCK)=f(XIN)“ are changed to “f(STCK)=f(LSOCO)” at active mode
(with a low-speed on-chip oscillator f(LSOCO))“
(1/1)
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