RENESAS M34286G2

4286 Group
REJ03B0251-0100
Rev.1.00
Aug 06, 2008
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 4286 Group is a 4-bit single-chip microcomputer designed
with CMOS technology for single-function remote control
transmitters. The computer is equipped with an 8-bit timer (has
two reload registers) can be set various carrier wave and an 8bit timer (has a reload register) can be control the carrier wave
output automatically.
The various microcomputers in the 4286 Group include variations
of type as shown in the table below.
FEATURES
• Number of basic instructions ............................................. 72
• Minimum instruction execution time ............................ 2.0 µs
(at f(XIN) = 4.0 MHz, system clock = f(XIN)/2)
• Supply voltage ................................................. 1.8 V to 3.6 V
• Subroutine nesting ..................................................... 4 levels
• Timer
Timer 1 ................................................................... 8-bit timer
(This has a reload register and carrier wave output auto-control
function)
Timer 2 ................................................................... 8-bit timer
(This has two reload registers and carrier wave output function)
• Logic operation function (XOR, OR, AND)
• RAM back-up function
• Key-on wakeup function (ports D0–D7, E0–E2, G0–G3) .... 15
• I/O port (ports D, E, G, CARR) .......................................... 16
• Oscillation circuit ..................................... Ceramic resonance
• Watchdog timer
• Power-on reset circuit
• Voltage drop detection circuit
Before CLVD instruction execution
Reset occurrence ............................... 1.5 V (Ta=25 °C)
Reset release .................................... 1.7 V (Ta=25 °C)
After CLVD instruction execution
Reset occurrence/Reset release ........ 1.7 V (Ta=25 °C)
APPLICATION
Consumer remote control transmitters
ROM size
RAM size
(× 9 bits)
(× 4 bits)
M34286G2-XXXGP
2048 words
64 words
PLSP0020JB-A (20P2F-A)
QzROM
M34286G2GP
2048 words
64 words
PLSP0020JB-A (20P2F-A)
QzROM (blank)
Part number
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 1 of 64
Package
ROM type
4286 Group
PIN CONFIGURATION (TOP VIEW)
1
20
VDD
E2
2
19
CARR
E1
3
18
D0
XI N
4
17
D1
XOUT
5
16
D2
E0
6
15
D3
G0
7
14
D4
G1
8
13
D5
G2
9
12
D6
G3
10
11
D7
M34286G2-XXXGP
M34286G2GP
VSS
Outline: PLSP0020JB-A (20P2F-A)
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
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Rev.1.00 Aug 06, 2008
REJ03B0251-0100
Port E
2
page 3 of 64
Watchdog timer (14 bits)
Timer 2 (8 bits, carrier wave generation)
ALU(4 bits)
720 series
CPU core
Port G
4
Register A (4 bits)
Register B (4 bits)
Register E (8 bits)
Register D (3 bits)
Stack register SK (4 levels)
Timer 1 (8 bits, carrier wave output control)
Timer/Remote-control carrier-wave output
Internal peripheral function
I/O port
1
Port D
8
(64 words ✕ 4 bits)
RAM
(2048 words ✕ 9 bits)
ROM
Memory
Power-on reset circuit
Voltage drop detection circuit
XIN -XOUT
System clock generation circuit
Port CARR
1
4286 Group
BLOCK DIAGRAM
4286 Group
PERFORMANCE OVERVIEW
Parameter
Function
Number of basic instructions
72
Minimum instruction execution time 2.0 µs (f(XIN) = 4.0 MHz, system clock = f(XIN)/2, VDD = 3.0 V)
2048 words ✕ 9 bits
Memory sizes ROM
Input/Output
ports
Timer
RAM
64 words ✕ 4 bits
D0–D7 I/O
E0–E2 I/O
Eight 1-bit I/O ports with the pull-down function and key-on wakeup function
G0–G3 I/O
CARR Output
4-bit I/O port with the pull-down function and key-on wakeup function
Timer 1
8-bit timer with a reload register
3-bit I/O port with the pull-down function and key-on wakeup function
1-bit output port; CMOS output
Timer 2
Subroutine nesting
8-bit timer with two reload registers
Device structure
CMOS silicon gate
Package
20-pin plastic molded LSSOP (PLSP0020JB-A (20P2F-A))
Operating temperature range
Supply voltage
Power
Active mode
dissipation
(typical value) RAM back-up mode
–40 to 85 °C
4 levels (However, only 3 levels can be used when the TABP p instruction is executed)
1.8 V to 3.6 V
400 µA (VDD = 3 V, STCK=f(XIN)/8, f(XIN) = 4 MHz)
0.1 µA (Ta = 25 °C, VDD = 3 V)
PIN DESCRIPTION
Pin
Name
Input/Output
Function
VDD
Power supply
—
Connected to a plus power supply.
VSS
Ground
—
Connected to a 0 V power supply.
XIN
System clock input
XOUT
System clock output
D0–D7
I/O port D
Input
Output
I/O
I/O pins of the system clock generating circuit. Connect a ceramic resonator
between pins XIN and XOUT. The feedback resistor is built-in between pins XIN
and XOUT.
1-bit I/O port. For input use, set the latch of the specified bit to “0.” When the builtin pull-down transistor is turned on, the key-on wakeup function using “H” level
sense and the pull-down transistor become valid. The output structure is P-channel
open-drain.
E0–E2
Output
I/O port E
Input
2-bit (E0, E1) output port. The output structure is P-channel open-drain.
3-bit input port. For input use (E0, E1), set the latch of the specified bit to “0.”
When the built-in pull-down transistor is turned on, the key-on wakeup function
using “H” level sense and the pull-down transistor become valid. Port E2 has an
input-only port and has a key-on wakeup function using “H” level sense and pulldown transistor.
G0–G3
I/O
I/O port G
4-bit I/O port. For input use, set the latch of the specified bit to “0.” The output structure
is P-channel open-drain. When the built-in pull-down transistor is turned on, the keyon wakeup function using “H” level sense and pull-down transistor become valid.
CARR
Carrier wave output
Output
for remote control
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REJ03B0251-0100
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Carrier wave output pin for remote control. The output structure is CMOS circuit.
4286 Group
CONNECTIONS OF UNUSED PINS
Connection
Pin
Usage condition
Open (Set the output latch to “1” ).
D0–D7
Pull-down transistor OFF.
Open (Set the output latch to “0” ).
E 0, E 1
Connect to VDD.
Pull-down transistor OFF.
Open (Set the output latch to “1” ).
Pull-down transistor OFF.
Open (Set the output latch to “0” ).
Connect to VDD.
Pull-down transistor OFF.
Open.
E2
Connect to VSS.
Open (Set the output latch to “1” ).
G0–G3
Pull-down transistor OFF.
Open (Set the output latch to “0” ).
Connect to VDD.
Pull-down transistor OFF.
Open.
CARR
(Note when connecting to VSS and VDD)
• Connect the unused pins to VSS or VDD at the shortest distance and use the thick wire against noise.
PORT FUNCTION
Port
Port D
Pin
D0–D7
Input/
Output structure
Output
I/O
P-channel open-drain
Control
Control
Control
bits
instructions
registers
1 bit
SD
(8)
PU1, PU2
Remark
Pull-down function and
RD
key-on wakeup function
CLD
(programmable)
SZD
Port E
E0
I/O
E1
(2)
P-channel open-drain
Output: OEA
2 bits
PU0
IAE
key-on wakeup function
Input:
E2
Input
Pull-down function and
(programmable)
3 bits
IAE
4 bits
OGA
(1)
Port G
G0–G3
I/O
P-channel open-drain
(4)
IAG
PU0
Pull-down function and
key-on wakeup function
(programmable)
Port CARR
CARR
Output CMOS
(1)
1 bit
SCAR
RCAR
DEFINITION OF CLOCK AND CYCLE
• System clock (STCK)
The system clock is the source clock for controlling this product.
It can be selected as shown below whether to use the
Oscillation dividing instruction.
CCK, CCK2, or CCK4 instruction can be executed only once.
After one of their instruction is executed once, the operation is
same as the NOP instruction though the same or another
frequency dividing instruction is executed.
The system clock returns to its initial state (f(X IN)/8) when
system is returnd from RAM back-up mode.
Oscillation dividing
instruction
System clock
Instruction clock
No use
f(XIN)/8
f(XIN)/32
CCK used
f(XIN)
f(XIN)/4
CCK2 used
f(XIN)/2
f(XIN)/8
CCK4 used
f(XIN)/4
f(XIN)/16
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• Instruction clock (INSTCK)
The instruction clock is a signal derived by dividing the system
clock by 4, and is the basic clock for controlling CPU. The one
instruction clock cycle is equivalent to one machine cycle.
• Machine cycle
The machine cycle is the cycle required to execute the
instruction.
4286 Group
PORT BLOCK DIAGRAMS
Register Y
Decoder
(Note 1)
SD instruction
S Q
RD instruction
R
Ports D0–D3 (Note 5)
CLD instruction
Skip decision (SZD instruction)
(Note 1)
Key-on wakeup
Pull-down transistor
PU2i
(Note 3)
Register Y
Decoder
(Note 1)
SD instruction
S
RD instruction
R
Q
Ports D4–D7 (Note 5)
CLD instruction
Skip decision (SZD instruction)
Key-on wakeup
Pull-down transistor
(Note 2) PU1i
Register A
Aj
(Note 3)
(Note 1)
Q
D
OEA
instruction
IAE instruction
Ports E0, E1 (Note 5)
T
Aj
Pull-down
transistor
Key-on wakeup input
(Note 3) PU0j
IAE instruction
Register A
A2
Port E2 (Note 5)
Key-on wakeup input
Pull-down
transistor
(Note 1)
Register A
OGA
instruction
(Note 1)
Q
D
Aj
(Note 3)
T
Ports G0, G1 (Note 5)
IAG instruction
Aj
Key-on wakeup input
Pull-down transistor
PU02
Register A
(Note 1)
(Note 4)
Q
D
Ak
OGA
instruction
T
Ports G2, G3 (Note 5)
IAG instruction
Ak
Key-on wakeup input
Pull-down transistor
PU03
CAR flag
SCAR instruction
S Q
RCAR instruction
R
CARRY
(to timer 1)
CARRYD
(from timer 2)
Timer 1 underflow signal
Port CARR
D Q
V12
(Note 1)
T R
Carrier wave output control signal
V10
Notes 1:
This symbol represents a parasitic diode.
2: i represents bits 0 to 3.
3: j represents bits 0, 1.
4: k represents bits 2, 3.
5: Applied voltage must be less than VDD.
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4286 Group
FUNCTION BLOCK OPERATIONS
CPU
<Carry>
(CY)
(1) Arithmetic logic unit (ALU)
The arithmetic logic unit ALU performs 4-bit arithmetic such
as 4-bit data addition, comparison, and bit manipulation.
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer,
exchange, and I/O operation.
Carry flag CY is a 1-bit flag that is set to “1” when there is a
carry with the AMC instruction (Figure 1).
It is unchanged with both A n instruction and AM instruction.
The value of A 0 is stored in carry flag CY with the RAR
instruction (Figure 2).
Carry flag CY can be set to “1” with the SC instruction and
cleared to “0” with the RC instruction.
(M(DP))
Addition
(A)
<Result>
Fig. 1 AMC instruction execution example
<Set>
SC instruction
<Clear>
RC instruction
CY
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4bit data, and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data
transfer with register B used as the high-order 4 bits and
register A as the low-order 4 bits (Figure 3).
(4) Register D
Register D is a 3-bit register.
It is used to store a 7-bit ROM address together with register
A and is used as a pointer within the specified page when the
TABP p, BLA p, or BMLA p instruction is executed (Figure 4).
ALU
A3 A2 A1 A0
<Rotation>
RAR instruction
A0
CY A3 A2 A1
Fig. 2 RAR instruction execution example
TAB instruction
Register B
B3 B2 B1 B0
Register A
A3 A2 A1 A0
TEAB instruction
Register E ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0
TABE instruction
B3 B2 B1 B0
Register B
A3 A2 A1 A0
TBA instruction Register A
Fig. 3 Registers A, B and register E
ROM
TABP p instruction
4
8
Specifying address
0
Low-order 4 bits
p3
PCH
p2 p1 p0
PCL
DR2 DR1 DR0 A3 A2 A1 A0
Register A (4)
Middle-order 4 bits
Register B (4)
Immediate field
value p
The contents
of register D
The contents
of register A
Most significant 1 bit
Carry flag CY (1)
URS flag (1)
URSC instruction
Fig. 4 TABP p instruction execution example
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4286 Group
(5) Most significant ROM code reference enable flag (URS)
URS flag controls whether to refer to the contents of the most
significant 1 bit (bit 8) of ROM code when executing the TABP
p instruction. If URS flag is “0,” the contents of the most
significant 1 bit of ROM code is not referred even when
executing the TABP p instruction. However, if URS flag is “1,”
the contents of the most significant 1 bit of ROM code is set to
flag CY when executing the TABP p instruction (Figure 4).
URS flag is “0” after system is released from reset and returned
from RAM back-up mode. It can be set to “1” with the URSC
instruction, but cannot be cleared to “0.”
(6) Stack registers (SKs) and stack pointer (SP)
Stack registers (SKs) are used to temporarily store the contents
of program counter (PC) just before branching until returning
to the original routine when;
• performing a subroutine call, or
• executing the table reference instruction (TABP p).
Stack registers (SKs) are four identical registers, so that
subroutines can be nested up to 4 levels. However, one of
stack registers is used when executing a table reference
instruction. Accordingly, be careful not to over the stack. The
contents of registers SKs are destroyed when 4 levels are
exceeded.
The register SK nesting level is pointed automatically by 2-bit
stack pointer (SP).
Figure 5 shows the stack registers (SKs) structure.
Figure 6 shows the example of operation at subroutine call.
(7) Skip flag
Skip flag controls skip decision for the conditional skip
instructions and continuous described skip instructions.
Note : The 4286 Group just invalidates the next instruction
when a skip is performed. The contents of program
counter is not increased by 2. Accordingly, the number
of cycles does not change even if skip is not performed.
However, the cycle count becomes “1” if the TABP p,
RT, or RTS instruction is skipped.
Program counter (PC)
Executing BM
instruction
Executing RT
instruction
SK0
(SP) = 0
SK1
(SP) = 1
SK2
(SP) = 2
SK3
(SP) = 3
Stack pointer (SP) points “3” at reset or
returning from RAM back-up mode. It points “0”
by executing the first BM instruction, and the
contents of program counter is stored in SK0.
When the BM instruction is executed after four
stack registers are used ((SP) = 3), (SP) = 0
and the contents of SK0 is destroyed.
Fig. 5 Stack registers (SKs) structure
(SP) ← 0
(SK0) ← 000116
(PC) ← SUB1
Subroutine
Main program
Address
SUB1 :
000016 NOP
NOP
·
·
·
RT
000116 BM SUB1
000216 NOP
(PC) ← (SK0)
(SP) ← 3
Note: Returning to the BM instruction execution
address with the RT instruction, and the BM
instruction is equivalent to the NOP instruction.
Fig. 6 Example of operation at subroutine call
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4286 Group
(8) Program counter (PC)
Program counter (PC) is used to specify a ROM address (page
and address). It determines a sequence in which instructions
stored in ROM are read. It is a binary counter that increments
the number of instruction bytes each time an instruction is
executed. However, the value changes to a specified address
when branch instructions, subroutine call instructions, return
instructions, or the table reference instruction (TABP p) is
executed.
Program counter consists of PCH (most significant bit to bit 7)
which specifies to a ROM page and PCL (bits 6 to 0) which
specifies an address within a page. After it reaches the last
address (address 127) of a page, it specifies address 0 of the
next page (Figure 7).
Make sure that the PCH does not exceed after the last page of
the built-in ROM.
Program counter (PC)
p3 p2 p1 p0
PCH
Specifying
page
a6 a5 a4 a3 a2 a1 a0
PCL
Specifying address
Fig. 7 Program counter (PC) structure
Data pointer (DP)
X1 X0 Y3 Y2 Y1 Y0
(9) Data pointer (DP)
Data pointer (DP) is used to specify a RAM address and consists
of registers X and Y. Register X specifies a file and register Y
specifies a RAM digit (Figure 8).
Register Y is also used to specify the port D bit position.
When using port D, set the port D bit position to register Y
certainly and execute the SD, RD, or SZD instruction (Figure 9).
Register Y (4)
Specifying
RAM digit
Specifying RAM file
Register X (2)
Fig. 8 Data pointer (DP) structure
Specifying bit position
Set
D7
0
1 0 1
Register Y (4)
D5
1
Port D output latch
Fig. 9 SD instruction execution example
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D0
4286 Group
PROGRAM MEMORY (ROM)
The program memory is a mask ROM. 1 word of ROM is
composed of 9 bits. ROM is separated every 128 words by the
unit of page (addresses 0 to 127).
Table 1 ROM size and pages
Part number
ROM size (✕ 9 bits)
Pages
M34286G2
2048 words
16 (0 to 15)
Page 2 (addresses 010016 to 017F16) is the special page for
subroutine calls. Subroutines written in this page can be called
from any page with the 1-word instruction (BM). Subroutines
extending from page 2 to another page can also be called with
the BM instruction when it starts on page 2.
ROM pattern of all addresses can be used as data areas with
the TABP p instruction.
DATA MEMORY (RAM)
8
000016
007 F16
008016
00FF16
010016
017 F16
018016
7
6
5
4
3
2
1 0
Page 0
Page 1
Subroutine special page
Page 2
Page 3
Page 15
07FF16
Fig. 10 ROM map of M34286G2
RAM 64 words ✕ 4 bits (256 bits)
1 word of RAM is composed of 4 bits, but 1-bit manipulation
(with the SB j, RB j, and SZB j instructions) is enabled for the
entire memory area. A RAM address is specified by a data
pointer. The data pointer consists of registers X and Y. Set a
value to the data pointer certainly when executing an instruction
to access RAM.
Table 2 shows the RAM size. Figure 11 shows the RAM map.
RAM size
M34286G2
64 words ✕ 4 bits (256 bits)
Register Y
Table 2 RAM size
Part number
Register X
0 1
2
3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
64 words
M34286G2
Fig. 11 RAM map
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4286 Group
TIMERS
The 4286 Group has the programmable timer.
• Programmable timer
The programmable timer has a reload register and enables
the frequency dividing ratio to be set. It is decremented from a
setting value n. When it underflows (count to n + 1), a timer 1
underflow flag is set to “1,” new data is loaded from the reload
register, and count continues (auto-reload function).
FF16
n: Counter initial value
Count starts
Reload
Reload
n
The contents of counter
1st underflow
2nd underflow
0016
Time
n+1 count
n+1 count
Timer 1 underflow flag “1”
“0”
A skip instruction is executed
Fig. 12 Auto-reload function
The 4286 Group timer consists of the following circuit.
• Timer 1 : 8-bit programmable timer
• Timer 2 : 8-bit programmable timer
These timers can be controlled with the timer control registers
V1 and V2.
Each timer function is described below.
Table 3 Function related timer
Circuit
Timer 1
Timer 2
14-bit timer
Structure
Count source
Frequency
dividing ratio
V1
1 to 256
• Carrier wave output
V2
16384
• Watchdog timer
• Carrier wave output (CARRY) 1 to 256
binary down counter
• Bit 5 of watchdog timer
8-bit programmable
• f(XIN)
binary down counter
• f(XIN)/2
• Timer 1 count source
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Control
register
• Carrier wave output control
8-bit programmable
14-bit fixed frequency • Instruction clock
Use of output signal
4286 Group
SNZT1 instruction
V10 (Note 1)
V11
CARRY
0
0
Timer 1 (8)
1
1
T1F
Timer 1 underflow signal
(to port CARR)
Reload register R1 (8)
(T1AB)(Note 2)
(TAB1)
Register B Register A
Register B
(TAB1)
Register A
(T2HAB)
Reload register R2H (8)
V20 (Note 1)
V21
XIN
0
0
1/2
Timer 2(8)
1
1
Reload control circuit
V23
T
Q
R
(Note 3) (T2R2L)
(T2AB)
CARRYD
(to port CARR)
V22
Reload register R2L (8)
T2F
T2F
(T2AB)
(TAB2)
SNZT2
instruction
Register B
(TAB2)
Register A
CAR flag
SCAR instruction
S Q
RCAR instruction
R
CARRY
(to timer 1)
Port CARR
Timer 1 underflow signal
Carrier wave output control signal
D Q
V12
T R
V10
Initializing signal (Note 4)
System reset
14-bit timer (WDT)
INSTCK
0
5
WRST instruction
Initializing signal
(Note 4)
Fig. 13 Timers structure
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13
WDF1 WDF2
Notes 1: Counting is stopped by clearing to “0.”
2: When the T1AB instruction is executed after V10 is set to “1,”
writing is performed only to reload register R1.
3: The data of reload register R2L set with the T2AB instruction
can be also written to timer 2 with the T2R2L instruction.
4: The initializing signal is output at reset or RAM back-up mode.
4286 Group
Table 4 Control registers related to timer
Timer control register V1
V12
Carrier wave output auto-control bit
V11
Timer 1 count source selection bit
V10
Timer 1 control bit
at reset : 0002
0
Auto-control output by timer 1 is invalid
1
Auto-control output by timer 1 is valid
0
Carrier wave output (CARRY)
1
Bit 5 of watchdog timer (WDT)
0
Stop (Timer 1 state retained)
1
Operating
Timer control register V2
V23
Carrier wave “H” interval expansion bit
V22
Carrier wave generation function control bit
V21
V20
Timer 2 count source selection bit
Timer 2 control bit
at RAM back-up : 0002
at reset : 00002
W
at RAM back-up : 00002
W
0
To expand “H” interval is invalid
1
To expand “H” interval is valid (when V22=1 selected)
0
Carrier wave generation function invalid
1
Carrier wave generation function valid
0
f(XIN)
1
f(XIN)/2
0
Stop (Timer 2 state retained)
1
Operating
Note: “W” represents write enabled.
(2) Precautions
Note the following for the use of timers.
• Count source
Stop timer 1 or timer 2 counting to change its count source.
• Reading the count value
Stop timer 1 or 2 counting and then execute the data read
instruction (TAB1, TAB2) to read its data.
• Watchdog timer
Be sure that the timing to execute the WRST instruction in
order to operate WDT efficiently.
• Writing to reload register R1
When writing data to reload register R1 while timer 1 is
operating, avoid a timing when timer 1 underflows.
• Timer 1 count operation
When the bit 5 of the watchdog timer (WDT) is selected as
the timer 1 count source, the error of maximum ± 64 µs (at
the minimum instruction execution time : 2 µs) is generated
from timer 1 start until timer 1 underflow. When
programming, be careful about this error.
• Stop of timer 2
Avoid a timing when timer 2 underflows to stop timer 2.
• Writing to reload register R2H
When writing data to reload register R2H while timer 2 is
operating, avoid a timing when timer underflows.
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• Timer 2 carrier wave output function
When to expand “H” interval of carrier wave is valid, set “1”
or more to reload register R2H.
• Timer 1 and timer 2 carrier wave output function
Count starts from the rising edge ➁ in Fig. 14 after the first
falling edge of the count source, after timer 1 and timer 2
operations start ① in Fig. 14.
Time to first underflow ③ in Fig. 14 is different from time
among next underflow ④ in Fig. 14 by the timing to start the
timer and count source operations after count starts.
➁
Count source
3
Timer value
2
1
0
3
2
1
0
Timer underflow signal
→
(1) Control registers related to timer
• Timer control register V1
Register V1 controls the timer 1 count source and autocontrol function of carrier wave output from port CARR by
timer 1. Set the contents of this register through register A
with the TV1A instruction.
• Timer control register V2
Register V2 controls the timer 2 count source and the carrier
wave generation function by timer. Set the contents of this
register through register A with the TV2A instruction.
➂
➃
➀ Timer start
Fig. 14 Count start time and count time when operation
starts (T1, T2)
3
4286 Group
(3) Timer 1
Timer 1 is an 8-bit binary down counter with the timer 1 reload
register (R1).
When timer is stopped, data can be set simultaneously in timer
1 and the reload register (R1) with the T1AB instruction.
When timer is operating, data can be set to only reload register
R1 with the T1AB instruction.
When setting the next count data to reload register R1 at
operating, set data before timer 1 underflows.
Timer 1 starts counting after the following process;
➀ set data in timer 1,
➁ select the count source with the bit 1 of register V1, and
➂ set the bit 0 of register V1 to “1.”
Once count is started, when timer 1 underflows (the next count
pulse is input after the contents of timer 1 becomes “0”), the
timer 1 underflow flag (T1F) is set to “1,” new data is loaded
from reload register R1, and count continues (auto-reload
function).
When a value set in reload register R1 is n, timer 1 divides the
count source signal by n + 1 (n = 0 to 255).
When the bit 2 of register V1 is set to “1,” the carrier wave
output enable/disable interval of port CARR is alternately
generated each timer 1 underflows (Figure 15).
Data can be read from timer 1 to registers A and B. When
reading the data, stop the counter and then execute the TAB1
instruction.
(4) Timer 2
Timer 2 is an 8-bit binary down counter with the timer 2 reload
registers (R2H and R2L).
Data can be set simultaneously in timer 2 and the reload
register (R2L) with the T2AB instruction.
The contents of reload register (R2L) set with the T2AB
instruction can be set again to timer 2 with the T2R2L
instruction. Data can be set to reload register (R2H) with the
T2HAB instruction.
Timer 2 starts counting after the following process;
➀ set data in timer 2,
➁ select the count source with the bit 1 of register V2, and
➂ select the valid/invalid of the carrier wave generation
function by bit 2 of register V1 (when this function is valid,
select the valid/invalid of the carrier wave “H” interval
expansion by bit 3), and
➃ set the bit 0 of register V1 to “1.”
When the carrier wave generation function is invalid (V22=“0”),
the following operation is performed;
Once count is started, when timer 2 underflows (the next count
pulse is input after the contents of timer 2 becomes “0”), the
timer 2 underflow flag (T2F) is set to “1,” new data is loaded
from reload register R2L, and count continues (auto-reload
function).
When a value set in reload register R2L is n, timer 2 divides
the count source signal by n + 1 (n = 0 to 255).
When the carrier wave generation function is valid (V22=“1”),
the carrier wave which has the “L” interval set to the reload
register R2L and “H” interval set to the reload register R2H
can be output (Figure 16).
After the count of the “L” interval of carrier wave is started,
timer 2 underflows and the timer 2 underflow flag (T2F) is set
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 14 of 64
to “1”. Then, the “H” interval data of carrier wave is reloaded
from the reload register R2H, and count continues.
When timer underflows again after auto-reload, the T2F flag
is set to “1”. And then, the “L” interval data of carrier wave is
reloaded from the reload register R2L, and count continues.
After that, each timer underflows, data is reloaded from reload
register R2H and R2L alternately.
When a value set in reload register R2H is n, “H” interval of
carrier wave is as follows;
➀ When to expand “H” interval is invalid (V23 = “0”),
Count source ✕ (n+1), n = 0 to 255
➁ When to expand “H” interval is valid (V23 = “1”),
Count source ✕ (n+1.5), n = 1 to 255
When a value set in reload register R2L is m, “L” interval of
carrier wave is as follows;
Count source ✕ (m+1), m = 0 to 255
Data can be read from timer 2 to registers A and B. When
reading the data, stop the counter and then execute the TAB2
instruction.
(5) Timer underflow flags (T1F, T2F)
Timer 1 underflow flag or timer 2 underflow flag is set to “1”
when the timer 1 or timer 2 underflows. The state of flags T1F
and T2F can be examined with the skip instruction (SNZT1,
SNZT2).
Flags T1F and T2F are cleared to “0” when the next instruction
is skipped with a skip instruction.
4286 Group
Timer 1 starts
Timer 1 underflow
(V10)←1
“1”
“0”
“H”
Port CARR output “L”
a
b
c
▲
▲
▲
Set the interval “a” to timer 1. Set the interval “b”
Set the interval “c”
to reload register R1. to reload register R1.
Count source CARRY selected
▲
Set the interval “d”
to reload register R1.
d
(V11)←0
Auto-control valid
Carrier wave output start
(V12)←1
Timer 1 stop
(V10)←0
Timer 1 underflow
“1”
“0”
“H”
CARRY “L”
(Note)
Port CARR output
“H”
“L”
Register V12 “1”
“0”
Auto-control invalid
Carrier wave output start
Auto-control invalid
Carrier wave output stop
Note: When timer 1 is stopped, the port CARR output auto-control is terminated regardless of bit 2 (V12) of register V1.
Fig. 15 Port CARR output control by timer 1
● In this case, the following is set;
• Timer 2 carrier wave generation function is valid (V22=“1”),
• “L” interval (0316) of carrier wave is set to reload register R2L
• “H” interval (0216) of carrier wave is set to reload register R2H
To expand “H” interval of carrier wave is invalid (V23=“0”)
[Count source: 4.0 MHz, Resolution: 250 ns]
Timer 2 count source
Timer 2 count value 0316
(Reload register)
0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116
(R2L)
(R2H)
(R2L)
(R2H)
(R2L)
(R2H)
Timer 2 underflow signal
3 clocks
interval
CARRYD
3 clocks
interval
Carrier wave period:
7 clocks
Timer 2 starts
Carrier wave period:
7 clocks
To expand “H” interval of carrier wave is valid (V23=“1”)
(When count source is 4.0 MHz, carrier wave is expanded for 125 ns]
Timer 2 count source
Timer 2 count value 0316
(Reload register)
0216 0116 0016
0216
0116 0016 0316 0216 0116 0016
0216
0116 0016 0316 0216 0116 0016
(R2H)
(R2L)
(R2H)
(R2L)
Timer 2 underflow signal
CARRYD
3.5 clocks
interval
Timer 2 starts
Carrier wave period:
7.5 clocks
3.5 clocks
interval
Carrier wave period:
7.5 clocks
Note: When to expand “H” interval of the carrier wave is valid, set “0116” or more to reload register R2H.
Fig. 16 Carrier wave generation example by timer 2
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REJ03B0251-0100
0216
(R2L)
page 15 of 64
(R2H)
4286 Group
● In this case, the following is set;
• To expand “H” interval of carrier wave is invalid (V23 = “0”),
• Timer 2 carrier wave generation function is valid (V22=“1”),
• Count source XIN/2 selected (V21=“1”),
• “L” interval (0316) of carrier wave is set to reload register R2L
• “H” interval (0216) of carrier wave is set to reload register R2H
Timer 2 count start timing
Machine cycle Mi
Mi + 1
Mi + 2
TV2A instruction execution cycle (V20) ←1
Instruction clock
=f(XIN)/8
XIN
XIN/2
(Count source selected)
Register V20
Timer 2 count value
0316
(Reload register)
(R2L)
0216 0116 0016 0216 0116 0016 0316 0216
(R2H)
(R2L)
Timer 2 underflow signal
CARRYD
Timer 2 count start timing
Timer 2 count stop timing
Machine cycle Mi
Mi + 1
Mi + 2
TV2A instruction execution cycle (V20)←0
Instruction clock
=f(XIN)/8
XIN
XIN/2
(Count source selected)
Register V20
Timer 2 count value
(Reload register)
0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016
(R2L)
(R2H)
(R2L)
0216
(R2H)
Timer 2 underflow signal
CARRYD
(Note 1)
Timer 2 count stop timing
Notes 1: When the carrier wave generation function is valid (V22=“1”), avoid a timing
when timer 2 underflows to stop timer 2. When the timer 2 count stop occurs
at the same timing with the timer 2 underflows, hazard may occur in the carrier
wave output waveform.
2: When the timer 2 is stopped during “H” output of carrier wave while the carrier
wave generation function is valid, it is stopped after the “H” interval set by
reload register R2H is output.
Fig. 17 Timer 2 count start/stop timing
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4286 Group
WATCHDOG TIMER
Watchdog timer provides a method to reset and restart the system
when a program runs wild. Watchdog timer consists of 14-bit
timer (WDT) and watchdog timer flags (WDF1, WDF2).
Watchdog timer downcounts the instruction clock (INSTCK) as
the count source immediately after system is released from reset.
When the timer WDT count value becomes 000016 and underflow
occurs, the WDF1 flag is set to “1.” Then, when the WRST
instruction is not executed before the timer WDT counts 16383,
WDF2 flag is set to “1” and internal reset signal is generated and
system reset is performed.
Execute the WRST instruction at period of 16383 machine cycle
or less to keep the microcomputer operation normal.
Timer WDT is also used for generation of oscillation stabilization
time. When system is returned from reset and from RAM backup mode by key-input, software starts after the stabilization
oscillation time until timer WDT downcounts to 3E0016 elapses.
Software start
• Watchdog timer
Be sure that the timing to execute the WRST instruction in
order to operate WDT efficiently.
Software start
Software start
3FFF16
3E0016
Value of timer WDT
0000 16
“1”
“0”
WDF1 flag
“1”
“0”
WDF2 flag
Internal reset signal
“H”
“L”
System
reset
POF
instruction
execution
Return
WRST
instruction
execution
System
reset
Fig. 18 Watchdog timer function
LOGIC OPERATION FUNCTION
The 4286 Group has the 4-bit logic operation function. The logic
operation between the contents of register A and the low-order 4
bits of register E is performed and its result is stored in register A.
Each logic operation can be selected by setting logic operation
selection register LO.
Set the contents of this register through register A with the TLOA
instruction. The logic operation selected by register LO is
executed with the LGOP instruction.
Table 5 shows the logic operation selection register LO.
Table 5 Logic operation selection register LO
Logic operation selection register LO
LO1
Logic operation selection bits
LO0
Note: “W” represents write enabled.
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REJ03B0251-0100
page 17 of 64
at reset : 002
LO1
0
0
1
1
LO0
0
1
0
1
at RAM back-up : 002
Logic operation function
Exclusive logic OR operation (XOR)
OR operation (OR)
AND operation (AND)
Not available
W
4286 Group
RESET FUNCTION
The 4286 Group has the power-on reset circuit, though it does
not have RESET pin. System reset is performed automatically
at power-on, and software starts program from address 0 in page
0.
In order to make the built-in power-on reset circuit operate
efficiently, set the voltage rising time until VDD= 0 to 2.2 V is
obtained at power-on 1ms or less (Ta = –20 °C to 85 °C).
Note on Power-on reset
Under the following condition, the system reset occurs by the
built-in the power-on reset circuit of this product;
- when the supply voltage (VDD) rises from 0 V to 2.2 V, within
1 ms (Ta = –20 °C to 85 °C).
Also, note that system reset does not occur under the
following conditions;
- when the supply voltage (VDD) rises from the voltage higher
than 0V, or
- when it takes more than 1 ms for the supply voltage (VDD)
to rise from 0 V to 2.2 V (Ta = –20 °C to 85 °C).
f(XIN)
Internal reset signal “H”
“L”
f(X IN) 16384 pulses
Software operation starts
(address 0 in page 0)
Fig. 19 Reset release timing
VDD
Power-on reset circuit
output voltage
Internal reset signal
Power-on reset circuit
Reset state
Voltage drop detection circuit
Watchdog timer output
Internal reset signal
Reset released
Power-on
Fig. 20 Power-on reset operation
(1) Internal state at reset
Table 6 shows port state at reset, and Figure 21 shows internal
state at reset (they are retained after system is released from
reset).
The contents of timers, registers, flags and RAM except shown
in Figure 21 are undefined, so set the initial value to them.
Table 6 Port state at reset
State at reset
Name
D0–D7
High impedance state (Pull-down transistor OFF)
G0–G3
High impedance state (Pull-down transistor OFF)
E 0 , E1
High impedance state (Pull-down transistor OFF)
CARR
“L” output
Note: The contents of all output latch is initialized to “0.”
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 18 of 64
4286 Group
• Program counter (PC) ..............................................................
Address 0 in page 0 is set to program counter.
• Power down flag (P) .................................................................
• Timer 1 underflow flag (T1F) ...................................................
• Timer 2 underflow flag (T2F) ...................................................
• Timer control register V1 ..........................................................
• Timer control register V2 ..........................................................
• Port CARR output flag (CAR) ..................................................
• Pull-down control register PU0 ................................................
• Pull-down control register PU1 ................................................
• Pull-down control register PU2 ................................................
• Logic operation selection register LO ......................................
• Most significant ROM code reference enable flag (URS)
• Carry flag (CY) .........................................................................
• Register A .................................................................................
• Register B .................................................................................
• Register X .................................................................................
• Register Y .................................................................................
• Stack pointer (SP) ....................................................................
Fig. 21 Internal state at reset
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
✕
✕
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 1 1
1 1 1
✕
✕ ✕ ✕
1
0
0
0
0
“✕” represents undefined.
VOLTAGE DROP DETECTION CIRCUIT
System reset is performed when the supply voltage goes the
reset occurrence voltage or less.
When the supply voltage goes reset release voltage or more,
the oscillation circuit goes to be in the operating enabled state
and system reset is released.
The reset occurrence voltage value is selectable by the CLVD
instruction execution.
Refer to the electrical characteristics for reset occurrence value
and reset release voltage value.
The voltage drop detection circuit is stopped and power
dissipation is reduced in the RAM back-up mode with the
initialized CPU stopped.
Note on voltage drop detection circuit
The voltage drop detection circuit detection voltage of this
product is set up lower than the minimum value of the supply
voltage of the recommended operating conditions.
As the actual operating minimum voltage is lower than the
reset generation voltage, the MCU will operate correctly unless
oscillation stops before the supply voltage reaches the reset
generation voltage during CPU operation.
When designing a system, test the operation thoroughly by
confirming the oscillation stop voltage and frequency of the
oscillator.
VDD
Recommended operating
condition min.value
Oscillation is stopped
incorrectly.
VDET
Even if the voltage re-goes up to
the recommended operating voltage,
MCU may not operate correctly.
→ Normal operation
VDD
Recommended
operating condition
min.value
VDET
Reset
Fig. 23 VDD and VDET
VDD
Reset occurrence/release voltage TYP = 1.7V
Reset occurrence voltage TYP = 1.5V
Internal reset signal
(Note)
(Note)
CLVD instruction
Note: Microcomputer starts operation after f(XIN) is counted to 16384 times.
Fig. 22 Voltage drop detection circuit operation waveform
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4286 Group
RAM BACK-UP MODE
Table 7 Functions and states retained at RAM back-up
The 4286 Group has the RAM back-up mode.
When the POF instruction is executed, system enters the RAM
back-up state.
As oscillation stops retaining RAM, the functions and states of
reset circuit at RAM back-up mode, power dissipation can be
reduced without losing the contents of RAM. Table 7 shows the
function and states retained at RAM back-up. Figure 24 shows
the state transition.
(1) Warm start condition
When the external wakeup signal is input after the system
enters the RAM back-up state by executing the POF
instruction, the CPU starts executing the software from address
0 in page 0. In this case, the P flag is “1.”
(2) Cold start condition
The CPU starts executing the software from address 0 in page
0 when any of the following conditions is satisfied .
• reset by power-on reset circuit is performed
• reset by watchdog timer is performed
• reset by voltage drop detection circuit is performed
In this case, the P flag is “0.”
(3) Identification of the start condition
Warm start (return from the RAM back-up state) or cold start
(return from the normal reset state) can be identified by
examining the state of the power down flag (P) with the SNZP
instruction.
A
carry flag (CY), stack pointer (SP) (Note 2)
✕
Contents of RAM
O
Port CARR
✕
Ports D0–D7
O
Ports E0, E1
O
Port G
O
Timer control registers V1, V2
✕
Pull-down control registers PU0, PU1, PU2
O
Logic operation selection register LO
✕
Timer 1 function, Timer 2 function
✕
Timer underflow flags (T1F, T2F)
✕
Watchdog timer (WDT)
✕
Watchdog timer flags (WDF1, WDF2)
✕
Most significant ROM code reference enable
flag (URS)
✕
Notes 1: “O” represents that the function can be retained, and
“✕” represents that the function is initialized.
Registers and flags other than the above are undefined
at RAM back-up, and set an initial value after returning.
2:The stack pointer (SP) points the level of the stack
register and is initialized to “112” at RAM back-up.
POF instruction
is executed
B
f(XIN) stop
(Stabilizing time a )
Reset
RAM back-up
Function
Program counter (PC), registers A, B,
f(XIN) oscillation
Return input
(Stabilizing time a )
(RAM back-up
mode)
Stabilizing time a : Microcomputer starts its operation after f(XIN) is counted to16384 times.
Fig. 24 State transition
Power down flag P
POF instruction
S
Reset input
R
Q
Software start
P = “1”
?
Yes
No
● Set source
● Clear source
POF instruction is executed
Reset input
Fig. 25 Set source and clear source of the P flag
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page 20 of 64
Cold start
Warm start
Fig. 26 Start condition identified example using the SNZP
instruction
4286 Group
(4) Return signal
An external wakeup signal is used to return from the RAM
back-up mode. Table 8 shows the return condition for each
return source.
Table 8 Return source and return condition
Return source
Ports D0–D7
Return condition
input.
Ports E0, E1, G
turned ON by register PU1 and PU2 are valid.
Return by an external “H” level Only key-on wakeup function of the port whose pull-down transistor is
input.
Port E2
Remarks
Return by an external “H” level Only key-on wakeup function of the port whose pull-down transistor is
turned ON by register PU0 is valid.
Return by an external “H” level Key-on wakeup function is always valid.
input.
(5) Pull-down control register
Registers PU0, PU1, and PU2 are 4-bit registers and control
the ON/OFF of pull-down transistor and key-on wakeup
function for ports E0, E1, G and ports D0–D7.
Set the contents of register PU0, PU1, or PU2 through register
A with the TPU0A, TPU1A, or TPU2A instruction, respectively.
Table 9 Pull-down control registers
Pull-down control register PU0
PU03
PU02
PU01
PU00
at reset : 00002
Ports G2, G3 pull-down transistor control
0
Pull-down transistor OFF, key-on wakeup invalid
bit
1
Pull-down transistor ON, key-on wakeup valid
Ports G0, G1 pull-down transistor control
0
Pull-down transistor OFF, key-on wakeup invalid
bit
1
Pull-down transistor ON, key-on wakeup valid
0
Pull-down transistor OFF, key-on wakeup invalid
1
Pull-down transistor ON, key-on wakeup valid
0
Pull-down transistor OFF, key-on wakeup invalid
1
Pull-down transistor ON, key-on wakeup valid
Port E1 pull-down transistor control bit
Port E0 pull-down transistor control bit
Pull-down control register PU1
PU13
PU12
Port D7 pull-down transistor control bit
Port D6 pull-down transistor control bit
PU11
Port D5 pull-down transistor control bit
PU10
Port D4 pull-down transistor control bit
at reset : 00002
Port D3 pull-down transistor control bit
PU22
Port D2 pull-down transistor control bit
PU21
Port D1 pull-down transistor control bit
PU20
Port D0 pull-down transistor control bit
Note: “W” represents write enabled.
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 21 of 64
at RAM back-up : state retained
0
Pull-down transistor OFF, key-on wakeup invalid
1
Pull-down transistor ON, key-on wakeup valid
0
Pull-down transistor OFF, key-on wakeup invalid
1
Pull-down transistor ON, key-on wakeup valid
0
Pull-down transistor OFF, key-on wakeup invalid
1
Pull-down transistor ON, key-on wakeup valid
0
Pull-down transistor OFF, key-on wakeup invalid
1
Pull-down transistor ON, key-on wakeup valid
Pull-down control register PU2
PU23
at RAM back-up : state retained
at reset : 00002
at RAM back-up : state retained
0
Pull-down transistor OFF, key-on wakeup invalid
1
Pull-down transistor ON, key-on wakeup valid
0
Pull-down transistor OFF, key-on wakeup invalid
1
Pull-down transistor ON, key-on wakeup valid
0
Pull-down transistor OFF, key-on wakeup invalid
1
Pull-down transistor ON, key-on wakeup valid
0
Pull-down transistor OFF, key-on wakeup invalid
1
Pull-down transistor ON, key-on wakeup valid
W
W
W
4286 Group
CLOCK CONTROL
The clock control circuit consists of the following circuits.
• System clock generating circuit
• Control circuit to stop the clock oscillation
• Control circuit to return from the RAM back-up state
CCK/CCK2/CCK4 instruction
XIN
OSC
XOUT
Frequency
divider
(divided by 8)
Frequency
divider
(divided by 4)
Frequency
divider
(divided by 2)
Frequency divider
(divided by 4)
INSTCK
Instruction clock
STCK
Multiplexer
Frequency
divider
(through mode)
Internal power-on reset circuit
POF instruction
R
S
Q
Pull-down control
register PU0
Ports E0,E1,G0–G3
Pull-down control
register PU1, PU2
Ports D0–D7
Port E2
CCK, CCK2, or CCk4 instruction can be executed only once.
After one of their instruction is executed once, the operation is same as the NOP instruction
though the same or another frequency dividing instruction is executed.
Fig. 27 Clock control circuit structure
System clock signal f(XIN) is obtained by externally connecting a
ceramic resonator. Connect this external circuit to pins XIN and
XOUT at the shortest distance as shown Figure 28.
A feedback resistor is built-in between XIN pin and XOUT pin.
4286
XIN
4
CIN
Use the resonator manufacturer’s
recommended value because
constants such as capacitance
depend on the resonator.
XOUT
5
COUT
Fig. 28 Ceramic resonator external circuit
Rev.1.00 Aug 06, 2008
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page 22 of 64
4286 Group
LIST OF PRECAUTIONS
➀ Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
• connect a bypass capacitor (approx. 0.01 µF) between pins
VDD and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use the thickest wire.
• Port E2 is also used as VPP pin. Connect this pin to VSS
through the resistor about 5kΩ which is assigned to E2/VPP
pin as close as possible at the shortest distance.
➁ Register initial values 1
The initial value of the following registers are undefined after
system is released from reset. After system is released from
reset, set initial values.
• Register D (3 bits)
• Register E (8 bits)
➂ Register initial values 2
The initial value of the following registers are undefined at RAM
backup. After system is returned from RAM back-up, set initial
values.
• Register X (4 bits)
• Register Y (4 bits)
• Register D (3 bits)
• Register E (8 bits)
➃ Stack registers (SKS)
Stack registers (SK s) are four identical registers, so that
subroutines can be nested up to 4 levels. However, one of
stack registers is used when executing a table reference
instruction. Accordingly, be careful not to over the stack. The
contnts of registers SK s are destroyed when 4 levels are
exceeded.
➅ Timer
• Count source
Stop timer 1 or timer 2 counting to change its count source.
• Reading the count value
Stop timer 1 or 2 counting and then execute the data read
instruction (TAB1, TAB2) to read its data.
• Watchdog timer
Be sure that the timing to execute the WRST instruction in
order to operate WDT efficiently.
• Writing to reload register R1
When writing data to reload register R1 while timer 1 is
operating, avoid a timing when timer 1 underflows.
• Timer 1 count operation
When the bit 5 of the watchdog timer (WDT) is selected as
the timer 1 count source, the error of maximum ± 64 µs (at
the minimum instruction execution time : 2 µs) is generated
from timer 1 start until timer 1 underflow. When
programming, be careful about this error.
• Stop of timer 2
Avoid a timing when timer 2 underflows to stop timer 2.
• Writing to reload register R2H
When writing data to reload register R2H while timer 2 is
operating, avoid a timing when timer underflows.
• Timer 2 carrier wave output function
When to expand “H” interval of carrier wave is valid, set “1”
or more to reload register R2H.
• Timer 1 and timer 2 carrier wave output function
Count starts from the rising edge ➁ in Fig. 29 after the first
falling edge of the count source, after timer 1 and timer 2
operations start ① in Fig. 29.
Time to first underflow ③ in Fig. 29 is different from time
among next underflow ④ in Fig. 29 by the timing to start the
timer and count source operations after count starts.
➁
➄ Notes on unused pins
Count source
Connection
Usage condition
Open (Set the output latch to “0” ).
Connect to VDD.
Connect to VDD.
0
3
2
1
0
3
➂
➃
➀ Timer start
Pull-down transistor OFF.
Fig. 29 Count start time and count time when operation
starts (T1, T2)
Open.
Connect to VSS.
G0–G3 Open (Set the output latch to “1” ). Pull-down transistor OFF.
Open (Set the output latch to “0” ).
Pull-down transistor OFF.
CARR Open.
(Note when connecting to VSS and VDD)
• Connect the unused pins to VSS and VDD at the shortest
distance and use the thick wire against noise.
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
1
Timer underflow signal
Open (Set the output latch to “0” ).
Connect to VDD.
2
Pull-down transistor OFF.
E0, E1 Open (Set the output latch to “1” ). Pull-down transistor OFF.
E2
3
Timer value
→
Pin
D0–D7 Open (Set the output latch to “1” ). Pull-down transistor OFF.
page 23 of 64
➆ Program counter
Make sure that the program counter does not specify after the
last page of the built-in ROM.
4286 Group
➇ Power-on reset
Under the following condition, the system reset occurs by the
built-in the power-on reset circuit of this product;
- when the supply voltage (VDD) rises from 0 V to 2.2 V, within
1 ms (Ta = –20 °C to 85 °C).
Also, note that system reset does not occur under the
following conditions;
- when the supply voltage (VDD) rises from the voltage higher
than 0V, or
- when it takes more than 1 ms for the supply voltage (VDD)
to rise from 0 V to 2.2 V (Ta = –20 °C to 85 °C).
⑨ Voltage drop detection circuit
The voltage drop detection circuit detection voltage of this
product is set up lower than the minimum value of the supply
voltage of the recommended operating conditions.
As the actual operating minimum voltage is lower than the
reset generation voltage, the MCU will operate correctly unless
oscillation stops before the supply voltage reaches the reset
generation voltage during CPU operation.
When designing a system, test the operation thoroughly by
confirming the oscillation stop voltage and frequency of the
oscillator.
VDD
Recommended operating
condition min.value
Oscillation is stopped
incorrectly.
VDET
Even if the voltage re-goes up to
the recommended operating voltage,
MCU may not operate correctly.
→ Normal operation
VDD
Recommended
operating condition
min.value
VDET
Reset
Fig. 30 VDD and VDET
➉ Note on Power Source Voltage
When the power source voltage value of a microcomputer is
less than the value which is indicated as the recommended
operating conditions, the microcomputer does not operate
normally and may perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned
off, reset a microcomputer when the supply voltage is less
than the recommended operating conditions and design a
system not to cause errors to the system by this unstable
operation.
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 24 of 64
11
QzROM
(1) Be careful not to apply overvoltage to MCU. The contents
of QzROM may be overwritten because of overvoltage.
Take care especially at turning on the power.
(2) As for the product shipped in blank, Renesas does not perform the writing test to user ROM area after the assembly
process though the QzROM writing test is performed
enough before the assembly process. Therefore, a writing
error of approx.0.1 % may occur. Moreover, please note
the contact of cables and foreign bodies on a socket, etc.
because a writing environment may cause some writing errors.
12
Notes On ROM Code Protect
(QzROM product shipped after writing)
As for the QzROM product shipped after writing, the ROM
code protect is specified according to the ROM option setup
data in the mask file which is submitted at ordering.
The ROM option setup data in the mask file is “0016” for protect enabled or “FF16” for protect disabled.
Note that the mask file which has nothing at the ROM option
data or has the data other than “0016” and “FF16” can not be
accepted.
4286 Group
INSTRUCTIONS
The 4286 Group has the 72 instructions. Each instruction is
described as follows;
(1) List of instruction function
(2) Machine instructions (index by alphabet)
(3) Machine instructions (index by function)
(4) Instruction code table
SYMBOL
The symbols shown below are used in the following list of
instruction function and the machine instructions.
Contents
Symbol
Contents
Symbol
A
Register A (4 bits)
D
Port D (8 bits)
B
Register B (4 bits)
E
Port E (3 bits)
DR
Register D (3 bits)
G
Port G (4 bits)
ER
Register E (8 bits)
CARR
Port CARR (1 bit)
V1
Timer control register V1 (3 bits)
CAR
CAR flag (1 bit)
V2
Timer control register V2 (4 bits)
PU0
Pull-down control register PU0 (4 bits)
x
Hexadecimal variable
PU1
Pull-down control register PU1 (4 bits)
y
Hexadecimal variable
PU2
Pull-down control register PU2 (4 bits)
LO
Logic operation selection register LO (2 bits)
p
Hexadecimal variable
n
Hexadecimal constant which represents the
X
Register X (2 bits)
Y
Register Y (4 bits)
DP
Data pointer (6 bits)
(It consists of registers X and Y)
immediate value
Hexadecimal constant which represents the
j
immediate value
A 3A2 A1 A0
Binary notation of hexadecimal variable A
(same for others)
PC
Program counter (11 bits)
PCH
High-order 4 bits of program counter
PCL
Low-order 7 bits of program counter
←
Direction of data movement
SK
Stack register (11 bits ✕ 4)
↔
Data exchange between a register and memory
SP
Stack pointer (2 bits)
?
Decision of state shown before “?”
CY
Carry flag
( )
Contents of registers and memories
R1
Timer 1 reload register
—
Negate, Flag unchanged after executing
T1
Timer 1
T1F
Timer 1 underflow flag
M(DP)
R2H
Timer 2 reload register
a
Label indicating address a6 a5 a4 a3 a2 a1 a0
R2L
Timer 2 reload register
p, a
Label indicating address a6 a5 a4 a3 a2 a1 a0
T2
Timer 2
T2F
Timer 2 underflow flag
C
Hex. number C + Hex. number x (also same for
WDT
Watchdog timer
+
others)
WDF1
Watchdog timer flag 1
x
WDF2
Watchdog timer flag 2
URS
Most significant ROM code reference enable flag
P
Power down flag
STCK
System clock
INSTCK
Instruction clock
instruction
RAM address pointed by the data pointer
in page p3 p2 p1 p0
Note : The 4286 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not
increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count
becomes “1” if the TABP p, RT, or RTS instruction is skipped.
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 25 of 64
4286 Group
LIST OF INSTRUCTION FUNCTION
Function
Grouping Mnemonic
Page
TAB
(A) ← (B)
41
TBA
(B) ← (A)
43
TAY
(A) ← (Y)
43
Function
Grouping Mnemonic
LA n
(A) ← n
Page
34
n = 0 to 15
Register to register transfer
TABP p
(SP) ← (SP) + 1
42
(SK(SP)) ← (PC)
(PCH) ← p p=0 to 15
TYA
(Y) ← (A)
45
TEAB
(ER7–ER4) ← (B)
43
(PCL) ← (DR2–DR0, A3–A0)
When URS=0
(B) ← (ROM(PC))7 to 4
(A) ← (ROM(PC))3 to 0
(ER3–ER0) ← (A)
When URS=1
TABE
(B) ← (ER7–ER4)
(CY) ← (ROM(PC))8
42
(B) ← (ROM(PC))7 to 4
(A) ← (ER3–ER0)
(A) ← (ROM(PC))3 to 0
TDA
(DR2–DR0) ← (A2–A0)
(PC) ← (SK(SP))
43
(SP) ← (SP) – 1
(X) ← x, x = 0 to 3
34
(Y) ← y, y = 0 to 15
INY
(Y) ← (Y) + 1
33
DEY
(Y) ← (Y) – 1
33
TAM j
(A) ← (M(DP))
42
Arithmetic operation
RAM addresses
LXY x, y
AM
(A) ← (A) + (M(DP))
29
AMC
(A) ← (A) + (M(DP)) + (CY)
29
(CY) ← Carry
An
(A) ← (A) + n
29
n = 0 to 15
(X) ← (X) EXOR(j)
j = 0 to 3
XAM j
(A) ←→ (M(DP))
46
SC
(CY) ← 1
37
RC
(CY) ← 0
36
SZC
(CY) = 0 ?
40
CMA
(A) ← (A)
32
RAR
→ CY → A3A2A1A0
35
LGOP
Logic operation
34
(X) ← (X) EXOR(j)
j = 0 to 3
RAM to register transfer
XAMD j
(A) ←→ (M(DP))
46
(X) ← (X) EXOR(j)
j = 0 to 3
(Y) ← (Y) – 1
XAMI j
(A) ←→ (M(DP))
46
instruction
XOR, OR, AND
(X) ← (X) EXOR(j)
j = 0 to 3
(Y) ← (Y) + 1
SB j
(Mj(DP)) ← 1
37
Bit operation
j = 0 to 3
RB j
(Mj(DP)) ← 0
SZB j
(Mj(DP)) = 0 ?
j = 0 to 3
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REJ03B0251-0100
page 26 of 64
36
j = 0 to 3
39
4286 Group
Function
operation
Comparison
Grouping Mnemonic
Page
Grouping Mnemonic
Function
Page
SEAM
(A) = (M(DP)) ?
38
TV1A
(V12–V10) ← (A2–A0)
45
SEA n
(A) = n ?
38
TAB1
(B) ← (T17–T14)
41
n = 0 to 15
(A) ← (T13–T10)
Ba
(PCL) ← a6–a0
29
BL p, a
(PCH) ← p
30
T1AB
at timer 1 stop (V10=0):
40
Branch operation
(R17–R14) ← (B)
(T17–T14) ← (B)
(PCL) ← a6–a0
(R13–R10) ← (A)
(T13–T10) ← (A)
BA a
(PCL) ← (a6–a4, A3–A0)
30
at timer 1 operating (V10=1):
BLA p, a
(PCH) ← p
30
(R13–R10) ← (A)
(R17–R14) ← (B)
(PCL) ← (a6–a4, A3–A0)
SNZT1
BM a
(SP) ← (SP) + 1
30
(T1F) = 1 ?
39
(T1F) ← 0
(SK(SP)) ← (PC)
(PCH) ← 2
TV2A
(V23–V20) ← (A3–A0)
45
TAB2
(B) ← (T27–T24)
42
BML p, a (SP) ← (SP) + 1
(SK(SP)) ← (PC)
31
(PCH) ← p p= 0 to 15
(PCL) ← a6–a0
BMLA p, (SP) ← (SP) + 1
(SK(SP)) ← (PC)
a
31
(PCH) ← p p= 0 to 15
(A) ← (T23–T20)
Timer operation
Subroutine operation
(PCL) ← a6–a0
T2AB
Return operation
(PC) ← (SK(SP))
(T23–T20) ← (A)
T2HAB
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 27 of 64
(R2H7–R2H4) ← (B)
41
(R2H3–R2H0) ← (A)
37
T2R2L
(SP) ← (SP) – 1
RTS
40
(R2L3–R2L0) ← (A)
(PCL) ← (a6–a4, A3–A0)
RT
(R2L7–R2L4) ← (B)
(T27–T24) ← (B)
(T27–T24) ← (R2L7–R2L4)
41
(T23–T20) ← (R2L3–R2L0)
37
SNZT2
(T2F) = 1 ?
(T2F) ← 0
39
4286 Group
LIST OF INSTRUCTION FUNCTION (CONTINUED)
Grouping Mnemonic
Function
Page
CLD
(D) ← 0
32
RD
(D(Y)) ← 0
36
(Y) = 0 to 7
(D(Y)) ← 1
38
(Y) = 0 to 7
SZD
(D(Y)) = 0 ?
40
control operation
(Y) = 0 to 7
Other operation
Carrier wave
Input/Output operation
SD
OEA
(E1, E0) ← (A1, A0)
35
IAE
(A2–A0) ← (E2–E0)
33
OGA
(G) ← (A)
35
IAG
(A) ← (G)
33
SCAR
(CAR) ← 1
38
RCAR
(CAR) ← 0
36
NOP
(PC) ← (PC) + 1
34
POF
RAM back-up
35
SNZP
(P) = 1 ?
39
CCK
STCK changes to f(XIN)
31
CCK2
STCK changes to f(XIN)/2
31
CCK4
STCK changes to f(XIN)/4
32
CLVD
Reset occurrence voltage value changes
32
TLOA
(LO1, LO0) ← (A1, A0)
44
URSC
(URS) ← 1
45
TPU0A
(PU03–PU00) ← (A3–A0)
44
TPU1A
(PU13–PU10) ← (A3–A0)
44
TPU2A
(PU23–PU20) ← (A3–A0)
44
WRST
(WDF1) ← 0
46
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 28 of 64
4286 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET)
A n (Add n and accumulator)
Instruction
D8
code
0
Operation:
D0
1
0
1
0
n3 n2 n1 n0
2
0
A
n
Number of
cycles
Flag CY
1
1
–
16
Skip condition
Overflow = 0
Grouping:
Arithmetic operation
Description: Adds the value n in the immediate field to
register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no
overflow as the result of operation.
(A) + (M(DP))
(A)
Number of
words
n = 0 to 15
AM (Add accumulator and Memory)
Instruction
D8
code
0
Operation:
D0
0
(A)
0
0
0
1
0
1
0
2
0
0
A
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
(A) + (M(DP))
Arithmetic operation
Description: Adds the contents of M(DP) to register A.
Stores the result in register A. The contents
of carry flag CY remains unchanged.
AMC (Add accumulator, Memory and Carry)
Instruction
code
Operation:
D8
0
D0
0
0
0
0
1
0
1
1
2
0
0
B
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
0/1
–
Grouping:
(A)
(A) + (M(DP)) + (CY)
Carry
(CY)
Arithmetic operation
Description: Adds the contents of M(DP) and carry flag
CY to register A. Stores the result in register A and carry flag CY.
B a (Branch to address a)
Instruction
code
Operation:
D8
1
D0
1
(PCL)
a6 a5 a4 a3 a2 a1 a0
a6–a0
2
1
8
+a
a
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Branch operation
Description: Branch within a page : Branches to address
a in the identical page.
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 29 of 64
4286 Group
BA a (Branch to address a + Accumulator)
Instruction
D8
code
0
1
Operation:
D0
0
0
1
(PCL)
0
0
0
0
0
1
a6 a5 a4 a3 a2 a1 a0
2
2
0
0
1
1
8
+a
a
16
16
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
Grouping:
Branch operation
Description: Branch within a page : Branches to address
(a6 a5 a4 A3 A2 A1 A0) determined by replacing the low-order 4 bits of the address a in
the identical page with register A.
a6–a4, A3–A0
BL p, a (Branch Long to address a in page p)
Instruction
D8
code
0
1
Operation:
D0
0
0
1
1
1
p3 p2 p1 p0
a6 a5 a4 a3 a2 a1 a0
(PCH)
(PCL)
2
2
0
3
1
8
+a
p
a
16
16
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
Grouping:
Branch operation
Description: Branch out of a page : Branches to address
a in page p.
Note:
p is 0 to 15.
(P)
a6–a0
BLA p, a (Branch Long to address a in page p)
Instruction
code
D8
0
1
Operation:
D0
0
0
1
0
1
0
0
0
0
a6 a5 a4 p3 p2 p1 p0
(PCH)
(PCL)
2
2
0
1
1
8
+a
0
p
16
16
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
Grouping:
Branch operation
Description: Branch within a page : Branches to address
(a6 a5 a4 A3 A2 A1 A0) determined by replacing the low-order 4 bits of the address a in
page p with register A.
p is 0 to 15.
Note:
(P)
(a6–a4, A3–A0)
BM a (Branch and Mark to address a in page 2)
Instruction
code
Operation:
D8
1
D0
0
a6 a5 a4 a3 a2 a1 a0
(SK(SP))
(SP)
(PC)
(SP) + 1
(PCH)
2
(PCL)
a6-a0
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REJ03B0251-0100
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2
1
a
a
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Subroutine call operation
Description: Call the subroutine in page 2 : Calls the
subroutine at address a in page 2.
4286 Group
BML p, a
(Branch and Mark Long to address a in page p)
Instruction
D8
code
0
0
1
1
0
a6 a5 a4 a3 a2 a1 a0
Operation:
D0
1
1
p3 p2 p1 p0
2
2
0
7
p
1
a
a
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
16
16
Grouping:
Subroutine call operation
Description: Call the subroutine : Calls the subroutine at
address a in page p.
Note:
p is 0 to 15.
(SK(SP))
(PC)
(SP)
(SP) + 1
p
(PCH)
(PCL)
a6–a0
BMLA p, a (Branch and Mark Long to address a in page p)
Instruction
code
0
1
Operation:
D0
D8
0
0
1
0
1
0
0
0
0
a6 a5 a4 p3 p2 p1 p0
2
2
0
1
5
a
0
p
16
16
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
Grouping:
Subroutine call operation
Description: Call the subroutine : Calls the subroutine at
address (a6 a5 a4 A3 A2 A1 A0) determined
by replacing the low-order 4 bits of address
a in page p with register A.
Note:
p is 0 to 15.
(SK(SP))
(PC)
(SP)
(SP) + 1
(PCH)
p
(a6–a4, A3–A0)
(PCL)
CCK (Change system Clock to f(XIN))
Instruction
code
Operation:
D8
0
D0
0
1
0
1
1
0
0
1
2
0
5
9
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Change to STCK = f(XIN)
Other operation
Description: Changes system clock (STCK) from f(XIN)/8
to f(XIN).
CCK2 (Change system Clock to f(XIN)/2)
Instruction
code
Operation:
D8
0
D0
0
0
0
1
1
0
Change to STCK = f(XIN)/2
0
1
0
1
9
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Changes system clock (STCK) from f(XIN)/8
to f(XIN)/2.
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
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4286 Group
CCK4 (Change system Clock to f(XIN)/4)
Instruction
D8
code
0
Operation:
D0
0
0
1
0
1
1
0
1
0
2
D
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Change to STCK = f(XIN)/4
Other operation
Description: Changes system clock (STCK) from f(XIN)/8
to f(XIN)/4.
CLD (CLear port D)
Instruction
code
Operation:
D8
0
D0
0
(D)
0
0
1
0
0
0
1
2
0
1
1
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
0
Input/Output operation
Description: Clears (0) to port D (high-impedance state).
CLVD (Change Voltage Drop Detection)
Instruction
code
Operation:
D8
0
D0
0
0
1
0
1
1
Reset occurrence voltage 1.5
1
0
0
2
E
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
1.7V
Other operation
Description: Change reset occurrence voltage from1.5V
to 1.7V (Ta = 25°C, Typ).
CMA (CoMplement of Accumulator)
Instruction
code
Operation:
D0
D8
0
(A)
0
0
0
1
1
1
0
0
2
0
1
C
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
(A)
Arithmetic operation
Description: Stores the one’s complement for register
A’s contents in register A.
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
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4286 Group
DEY (DEcrement register Y)
Instruction
code
Operation:
D8
0
(Y)
D0
0
0
0
1
0
1
1
1
2
0
1
7
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 15
Grouping:
(Y) – 1
RAM addresses
Description: Subtracts 1 from the contents of register Y.
As a result of subtraction, when the contents of register Y is 15, the next instruction
is skipped.
IAE (Input Accumulator from port E)
Instruction
code
Operation:
D8
0
D0
0
1
(A2–A0)
0
1
0
1
1
0
2
0
5
6
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
(E2–E0)
Input/Output operation
Description: Transfers the contents of port E to register
A.
IAG (Input Accumulator from port G)
Instruction
code
Operation:
D8
0
D0
0
(A)
0
1
0
1
0
0
0
2
0
2
8
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
(G)
Input/Output operation
Description: Transfers the contents of port G to register
A.
INY (INcrement register Y)
Instruction
code
Operation:
D8
0
(Y)
D0
0
0
0
1
0
0
1
1
2
0
1
3
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 0
Grouping:
(Y) + 1
RAM addresses
Description: Adds 1 to the contents of register Y. As a result of addition, when the contents of
register Y is 0, the next instruction is
skipped.
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REJ03B0251-0100
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4286 Group
LA n (Load n in Accumulator)
Instruction
code
Operation:
D8
0
D0
1
0
1
1
n3 n2 n1 n0
2
0
B
n
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
Continuous
description
Grouping:
(A)
n
n = 0 to 15
Arithmetic operation
Description: Loads the value n in the immediate field to
register A.
When the LA instructions are continuously
coded and executed, only the first LA instruction is executed and other LA
instructions coded continuously are
skipped.
LGOP (LoGic OPeration between accumulator and register E)
Instruction
code
Operation:
D8
0
D0
0
1
0
0
0
0
0
1
2
0
4
1
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Logic operation XOR, OR, AND
Arithmetic operation
Description: Executes the logic operation selected by
logic operation selection register LO between the contents of register A and
register E, and stores the result in register
A.
LXY x, y (Load register X and Y with x and y)
Instruction
code
Operation:
D0
D8
0
1
(X)
(Y)
1
x1 x0 y3 y2 y1 y0
2
0
C
+x
y
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
Continuous
description
Grouping:
x, x = 0 to 3
y, y = 0 to 15
RAM addresses
Description: Loads the value x in the immediate field to
register X, and the value y in the immediate
field to register Y. When the LXY instructions are continuously coded and executed,
only the first LXY instruction is executed
and other LXY instructions coded continuously are skipped.
NOP (No OPeration)
Instruction
code
Operation:
D0
D8
0
(PC)
0
0
0
0
0
0
(PC) + 1
0
0
2
0
0
0
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: No operation
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 34 of 64
4286 Group
OEA (Output port E from Accumulator)
Instruction
code
Operation:
D8
0
D0
1
0
(E1, E0)
0
0
0
1
0
0
2
0
8
4
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
(A1, A0)
Input/Output operation
Description: Outputs the contents of register A to port E.
OGA (Output port G from Accumulator)
Instruction
D8
code
0
Operation:
D0
1
(G)
0
0
0
0
0
0
0
2
0
8
0
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
(A)
Input/Output operation
Description: Outputs the contents of register A to port G.
POF (Power OFf1)
Instruction
code
Operation:
D0
D8
0
0
0
0
0
1
1
0
1
2
0
0
D
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
RAM back-up
Other operation
Description: Puts the system in RAM back-up state
RAR (Rotate Accumulator Right)
Instruction
code
Operation:
D8
0
D0
0
CY
0
0
1
1
1
A 3A 2A 1A 0
0
1
2
0
1
D
16
Number of
words
Number of
cycles
1
1
Grouping:
Flag CY
0/1
Skip condition
–
Arithmetic operation
Description: Rotates 1 bit of the contents of register A including the contents of carry flag CY to the
right.
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
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4286 Group
RB j (Reset Bit)
Instruction
code
Operation:
D0
D8
0
0
1
(Mj(DP))
j = 0 to 3
0
0
1
1
j1
j0
2
0
4
C
+j 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
0
Bit operation
Description: Clears (0) the contents of bit j (bit specified
by the value j in the immediate field) of
M(DP).
RC (Reset Carry flag)
Instruction
D8
code
0
Operation:
D0
0
(CY)
0
0
0
0
1
1
0
2
0
0
6
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
0
–
Grouping:
0
Arithmetic operation
Description: Clears (0) to carry flag CY.
RCAR (Reset CAR flag)
Instruction
D8
code
0
Operation:
D0
1
(CAR)
0
0
0
0
1
1
0
2
0
8
6
16
0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Carrier wave control operation
Description: Clears (0) to port CARR output flag.
RD (Reset port D specified by register Y)
Instruction
code
Operation:
D0
D8
0
0
0
0
1
0
1
0
2
0
1
4
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
(D(Y))
0
However,
(Y) = 0 to 7
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
0
Input/Output operation
Description: Clears (0) to a bit of port D specified by register Y (high-impedance state).
page 36 of 64
4286 Group
RT (ReTurn from subroutine)
Instruction
code
Operation:
D8
0
D0
0
(SP)
(PC)
1
0
0
0
1
0
0
2
0
4
4
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
2
–
–
Grouping:
(SP) – 1
(SK(SP))
Return operation
Description: Returns from subroutine to the routine
called the subroutine.
RTS (ReTurn form subroutine and Skip)
Instruction
D8
code
0
Operation:
D0
0
(SP)
(PC)
1
0
0
0
1
0
1
2
0
4
5
16
Number of
words
Number of
cycles
Flag CY
1
2
–
Grouping:
(SP) – 1
(SK(SP))
Skip condition
Skip at uncondition
Return operation
Description: Returns from subroutine to the routine
called the subroutine, and skips the next instruction at uncondition.
SB j (Set Bit)
Instruction
code
Operation:
D8
0
D0
0
1
(Mj(DP))
j = 0 to 3
0
1
1
1
j1
j0
2
0
5
C
+j 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
1
Bit operation
Description: Sets (1) the contents of bit j (bit specified by
the value j in the immediate field) of M(DP).
SC (Set Carry flag)
Instruction
code
Operation:
D0
D8
0
(CY)
0
0
0
0
0
1
1
1
2
0
0
7
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
1
–
Grouping:
1
Arithmetic operation
Description: Sets (1) to carry flag CY.
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 37 of 64
4286 Group
SCAR (Set CAR flag)
Instruction
D8
code
0
Operation:
D0
1
(CAR)
0
0
0
0
1
1
1
2
0
8
7
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
1
Carrier wave control operation
Description: Sets (1) to port CARR output flag (CAR).
SD (Set port D specified by register Y)
Instruction
D8
code
0
Operation:
D0
0
0
0
1
0
1
0
1
2
0
1
5
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
(D(Y))
1
(Y) = 0 to 7
Input/Output operation
Description: Sets (1) to a bit of port D specified by register Y.
SEA n (Skip Equal, Accumulator with immediate data n)
Instruction
D8
code
0
0
Operation:
D0
0
1
0
0
1
1
0
1
0
1
0
1
n3 n2 n1 n0
2
2
0
0
2
B
5
n
16
16
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
(A) = n, n = 0 to 15
Grouping:
Comparison operation
Description: Skips the next instruction when the contents of register A is equal to the value n in
the immediate field.
(A) = n ?
n = 0 to 15
SEAM (Skip Equal, Accumulator with Memory)
Instruction
code
Operation:
D0
D8
0
0
0
1
0
0
1
(A) = (M(DP)) ?
1
0
2
0
2
6
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(A) = (M(DP))
Grouping:
Comparison operation
Description: Skips the next instruction when the contents of register A is equal to the contents of
M(DP).
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 38 of 64
4286 Group
SNZP (Skip if Non Zero condition of Power down flag)
Instruction
D8
code
0
Operation:
D0
0
0
0
0
0
0
1
1
2
0
0
3
Number of
words
Number of
cycles
Flag CY
1
1
–
16
Grouping:
(P) = 1 ?
Skip condition
(P) = 1
Other operation
Description: Skips the next instruction when P flag is "1".
After skipping, P flag remains unchanged.
SNZT1 (Skip if Non Zero condition of Timer 1 underflow flag)
Instruction
D8
code
0
Operation:
D0
0
1
0
0
0
0
1
0
2
0
4
2
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(T1F) = 1
16
Grouping:
(T1F) = 1 ?
(T1F)
0
Timer operation
Description: Clears T1F flag and skips the next instruction when the contents of T1F flag is “1.”
SNZT2 (Skip if Non Zero condition of Timer 2 interrupt request flag)
Instruction
code
Operation:
D8
0
D0
0
1
0
1
0
0
1
0
2
0
5
2
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(T2F) = 1
Grouping:
(T2F) = 1 ?
(T2F)
0
Timer operation
Description: Clears T2F flag and skips the next instruction when the contents of T2F flag is “1.”
SZBj (Skip if Zero, Bit)
Instruction
code
Operation:
D8
0
D0
0
0
1
0
0
0
(Mj(DP)) = 0 ?
j = 0 to 3
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 39 of 64
j1
j0
2
0
2
j
16
Number of
words
Number of
cycles
Flag CY
1
1
–
Grouping:
Skip condition
(Mj(DP)) = 0
j = 0 to 3
Bit operation
Description: Skips the next instruction when the contents of bit j (bit specified by the value j in
the immediate field) of M(DP) is "0."
4286 Group
SZC (Skip if Zero, Carry flag)
Instruction
D8
code
0
Operation:
D0
0
0
1
0
1
1
1
1
2
0
2
F
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(CY) = 0
Grouping:
(CY) = 0 ?
Arithmetic operation
Description: Skips the next instruction when the contents of carry flag CY is “0.”
SZD (Skip if Zero, port D specified by register Y)
Instruction
D8
code
0
0
Operation:
D0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
2
2
0
0
2
2
4
B
16
Number of
words
Number of
cycles
Flag CY
2
2
–
Skip condition
(D(Y)) = 0
(Y) = 0 to 7
16
Grouping:
(D(Y)) = 0 ?
(Y) = 0 to 7
Input/Output operation
Description: Skips the next instruction when a bit of port
D specified by register Y is “0.”
T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B)
Instruction
D8
code
0
Operation:
D0
0
1
0
0
0
1
at timer 1 stop (V10=0)
(B), (R13–R10)
(R17–R14)
(T17–T14)
(B), (T13–T10)
at timer 1 operating (V10=1)
(R17–R14)
(B), (R13–R10)
1
1
2
0
4
7
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: At timer 1 stop (V10 = 0), transfers the contents of register A and register B to timer 1
and reload register R1.
At timer 1 operating (V10 = 1), transfers the
contents of register A and register B to reload register R1.
(A)
(A)
(A)
T2AB (Transfer data to timer 2 and register R2L from Accumulator and register B)
Instruction
code
Operation:
D0
D8
0
1
0
0
0
1
0
(R2L7–R2L4)
(B)
(R2L3–R2L0)
(A)
(T27–T24)
(B)
(A)
(T23–T20)
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 40 of 64
0
0
2
0
8
8
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of registers A and B
to timer 2 and timer 2 reload register R2L.
4286 Group
T2HAB (Transfer data to register R2H Accumulator from register B)
Instruction
code
Operation:
D8
0
D0
1
0
0
(R2H7–R2H4)
(R2H3–R2H0)
0
1
0
0
1
2
0
8
9 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
(B)
(A)
Timer operation
Description: Transfers the contents of register A and
register B to reload register R2H.
T2R2L (Transfer data to timer 2 from register R2L)
Instruction
code
Operation:
D8
0
D0
0
1
(T27–T24)
(T23–T20)
0
1
0
0
1
1
2
0
5
3
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
Grouping:
(R2L7–R2L4)
(R2L3–R2L0)
Timer operation
Description: Transfers the contents of reload register
R2L to timer 2.
TAB (Transfer data to Accumulator from register B)
Instruction
code
Operation:
D8
0
D0
0
(A)
0
0
1
1
1
1
0
2
0
1
E
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
Grouping:
(B)
Register to register transfer
Description: Transfers the contents of register B to register A.
TAB1 (Transfer data to Accumulator and register B from timer 1)
Instruction
code
Operation:
D8
0
(B)
(A)
D0
0
1
0
1
0
1
(T17–T14)
(T13–T10)
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 41 of 64
1
1
2
0
5
7
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer 1 to registers A and B.
4286 Group
TAB2 (Transfer data to Accumulator and register B from timer 2)
Instruction
code
Operation:
D0
D8
0
0
1
0
0
0
0
0
0
2
0
4
0
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
Grouping:
(T27–T24)
(T23–T20)
(B)
(A)
Number of
words
Timer operation
Description: Transfers the contents of timer 2 to registers A and B.
TABE (Transfer data to Accumulator and register B from register E)
Instruction
code
Operation:
D8
0
D0
0
(B)
(A)
0
1
0
1
0
1
0
2
0
2
A
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
(ER7–ER4)
(ER3–ER0)
Register to register transfer
Description: Transfers the contents of register E to registers A and B.
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
Instruction
code
Operation:
D8
0
Number of
words
D0
1
0
0
1
p3 p2 p1 p0
2
0
9
p
16
SK(SP))
(PC) , (SP)
(SP) + 1
(PCH)
p, (Note), (PC L)
(DR 2 –DR0, A3–A0)
When URS = 0,
(ROM(PC))3 to 0
(B)
(ROM(PC))7 to 4, (A)
When URS = 1,
(CY)
(ROM(PC))8
(B)
(ROM(PC))7 to 4, (A)
(ROM(PC))3 to 0
(SP)
(SP) – 1, (PC)
(SK(SP))
Number of
cycles
Flag CY
Skip condition
–
–
0/1
Grouping:
Arithmetic operation
Description: Transfers bits 7 to 4 to register B and bits 3
to 0 to register A when URS flag is cleared to
“0”. These bits 7 to 0 are the ROM pattern in
address (DR2 DR1 DR0 A3 A2 A1 A0) specified
by registers A and D in page p.
Transfers bit 8 ROM pattern is transferred
CY=0/1:
to flag CY when URS flag is set to “1”.
(after the URSC instruction is executed).
(One of stack is used when the TABP p
instruction is executed.)
p is 0 to 15.
Note:
1
3
Number of
words
Number of
cycles
TAMj (Transfer data to Accumulator from Memory)
Instruction
code
Operation:
D0
D8
0
0
1
1
0
0
1
(A)
(M(DP))
(X)
(X)EXOR(j)
j = 0 to 3
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 42 of 64
j1
j0
2
0
6
4
+j 16
1
Grouping:
1
Flag CY
–
Skip condition
–
RAM to register transfer
Description: After transferring the contents of M(DP) to
register A, an exclusive OR operation is
performed between register X and the value
j in the immediate field, and stores the result in register X.
4286 Group
TAY (Transfer data to Accumulator from register Y)
Instruction
code
Operation:
D8
0
(A)
D0
0
0
0
1
1
1
1
1
2
0
1
F
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
Grouping:
Register to register transfer
Description: Transfers the contents of register Y to register A.
(Y)
TBA (Transfer data to register B from Accumulator)
Instruction
D8
code
0
Operation:
D0
0
(B)
0
0
0
1
1
1
0
2
0
0
E
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
Grouping:
(A)
Register to register transfer
Description: Transfers the contents of register A to register B.
TDA (Transfer data to register D from Accumulator)
Instruction
code
Operation:
D8
0
D0
0
0
(DR2–DR0)
1
0
1
0
0
1
2
0
2
9
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
Grouping:
(A2–A0)
Register to register transfer
Description: Transfers the contents of register A to register D.
TEAB (Transfer data to register E from Accumulator and register B)
Instruction
code
Operation:
D8
0
D0
0
0
0
1
1
0
1
0
2
0
1
A
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
(ER 7–ER 4)
(B)
Grouping:
(ER 3–ER 0)
(A)
Description: Transfers the contents of register A and
register B to register E.
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
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Register to register transfer
4286 Group
TLOA (Transfer data to register LO from Accumulator)
Instruction
code
Operation:
D8
0
D0
0
1
(LO1, LO0)
0
1
1
0
0
0
2
0
5
8
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
(A1, A0)
Other operation
Description: Transfers the contents of register A to logic
operation selection register LO.
TPU0A (Transfer data to register PU0 from Accumulator)
Instruction
code
Operation:
D8
0
D0
1
0
0
(PU03–PU00)
0
1
1
1
1
2
0
8
F
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
(A3–A0)
Other operation
Description: Transfers the contents of register A to pullup control register PU0.
TPU1A (Transfer data to register PU1 from Accumulator)
Instruction
code
Operation:
D8
0
D0
1
0
0
(PU13–PU10)
0
1
1
1
0
2
0
8
E
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Transfers the contents of register A to pullup control register PU1.
(A3–A0)
TPU2A (Transfer data to register PU2 from Accumulator)
Instruction
code
Operation:
D0
D8
0
1
0
(PU23–PU20)
0
0
1
1
(A3–A0)
0
1
2
0
8
D
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Transfers the contents of register A to pullup control register PU2.
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 44 of 64
4286 Group
TV1A (Transfer data to register V1 from Accumulator)
Instruction
D8
code
0
Operation:
D0
0
1
(V12–V10)
0
1
0
1
1
1
2
0
5
B
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
(A2–A0)
Timer operation
Description: Transfers the contents of register A to register V1.
TV2A (Transfer data to register V2 from Accumulator)
Instruction
code
Operation:
D0
D8
0
0
1
(V23–V20)
0
1
1
0
1
0
2
0
5
A
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
(A3–A0)
Timer operation
Description: Transfers the contents of register A to register V2.
TYA (Transfer data to regiser Y from Accumulator)
Instruction
code
Operation:
D8
0
D0
0
0
0
0
1
1
0
0
2
0
0
C
16
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
(A)
(Y)
Number of
words
Register to register transfer
Description: Transfers the contents of register A to register Y.
URSC (Sets Upper ROM Code reference enable flag)
Instruction
code
Operation:
D8
0
D0
1
(URS)
0
0
0
0
0
1
0
2
0
8
2
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
1
Other operation
Description: Sets the most significant ROM code reference enable flag (URS) to “1.”
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 45 of 64
4286 Group
WRST (Watchdog timer ReSeT)
Instruction
code
Operation:
D8
0
D0
0
0
(WDF1)
0
0
1
1
1
1
2
0
0
F
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
0
Other operation
Description: Initializes the watchdog timer flag (WDF1).
XAM j (eXchange Accumulator and Memory data)
Instruction
code
Operation:
D0
D8
0
0
1
1
0
0
0
j1
j0
2
0
6
j
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
(A)
(M(DP))
(X)
(X)EXOR(j)
j = 0 to 3
RAM to register transfer
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between register X and the value j in the immediate field,
and stores the result in register X.
XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip)
Instruction
code
Operation:
D8
0
D0
0
1
1
0
1
1
j1
j0
2
0
6
C
+j 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 15
Grouping:
RAM to register transfer
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between register X and the value j in the immediate field,
and stores the result in register X.
Subtracts 1 from the contents of register Y.
As a result of subtraction, when the contents of register Y is 15, the next instruction
is skipped.
(A)
(M(DP))
(X)
(X)EXOR(j)
j = 0 to 3
(Y) – 1
(Y)
XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip)
Instruction
code
Operation:
D8
0
D0
0
1
1
0
1
0
(A)
(M(DP))
(X)
(X)EXOR(j)
j = 0 to 3
(Y) + 1
(Y)
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REJ03B0251-0100
page 46 of 64
j1
j0
2
0
6
8
+j 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 0
Grouping:
RAM to register transfer
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between register X and the value j in the immediate field,
and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition, when the contents of
register Y is 0, the next instruction is
skipped.
4286 Group
INSTRUCTION CODE TABLE
D8–D4
D3–D0
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111
Hex.
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10000 11000
10111 11111
10–17 18–1F
notation
0000
0
NOP
BLA
SZB
0
BL
TAB2 BMLA
XAM
0
BML
OGA TABP
0
A
0
LA
0
LXY
0,0
LXY
1,0
LXY
2,0
LXY
3,0
BM
B
0001
1
BA
CLD
SZB
1
BL
LGOP
XAM
1
BML
TABP
1
A
1
LA
1
LXY
0,1
LXY
1,1
LXY
2,1
LXY
3,1
BM
B
0010
2
SZB
2
BL
SNZT1 SNZT2
XAM
2
BML
URSC TABP
2
A
2
LA
2
LXY
0,2
LXY
1,2
LXY
2,2
LXY
3,2
BM
B
0011
3
INY
SZB
3
BL
T2R2L XAM
BML
TABP
3
A
3
LA
3
LXY
0,3
LXY
1,3
LXY
2,3
LXY
3,3
BM
B
0100
4
RD
SZD
BL
RT
TAM
0
BML
OEA TABP
4
A
4
LA
4
LXY
0,4
LXY
1,4
LXY
2,4
LXY
3,4
BM
B
0101
5
SD
SEAn
BL
RTS
TAM
1
BML
TABP
5
A
5
LA
5
LXY
0,5
LXY
1,5
LXY
2,5
LXY
3,5
BM
B
0110
6
RC
SEAM
BL
TAM
2
BML RCAR
TABP
6
A
6
LA
6
LXY
0,6
LXY
1,6
LXY
2,6
LXY
3,6
BM
B
0111
7
SC
TAM
3
BML SCAR
TABP
7
A
7
LA
7
LXY
0,7
LXY
1,7
LXY
2,7
LXY
3,7
BM
B
1000
8
1001
9
1010
A
AM
1011
B
AMC
1100
C
TYA
CMA
BL
1101
D
POF
RAR CCK4
1110
E
TBA
TAB
1111
F
SNZP
3
IAE
BL
T1AB TAB1
IAG
BL
TLOA
XAMI
BML
0
T2AB
TABP
8
A
8
LA
8
LXY
0,8
LXY
1,8
LXY
2,8
LXY
3,8
BM
B
CCK2 TDA
BL
CCK
XAMI
BML
1
T2HAB
TABP
9
A
9
LA
9
LXY
0,9
LXY
1,9
LXY
2,9
LXY
3,9
BM
B
TEAB TABE
BL
TV2A
XAMI
BML
2
TABP
10
A
10
LA
10
LXY
0,10
LXY
1,10
LXY
2,10
LXY
3,10
BM
B
BL
TV1A
XAMI
BML
3
TABP
11
A
11
LA
11
LXY
011
LXY
1,11
LXY
2,11
LXY
3,11
BM
B
RB
0
SB
0
XAMD
BML
0
TABP
12
A
12
LA
12
LXY
0,12
LXY
1,12
LXY
2,12
LXY
3,12
BM
B
BL
RB
1
SB
1
XAMD
BML
1
TPU2A TABP
A
13
LA
13
LXY
0,13
LXY
1,13
LXY
2,13
LXY
3,13
BM
B
CLVD
BL
RB
2
SB
2
XAMD BML
2
TPU1A TABP
14
A
14
LA
14
LXY
0,14
LXY
1,14
LXY
2,14
LXY
3,14
BM
B
SZC
BL
RB
3
SB
3
XAMD
BML
3
TABP
15
A
15
LA
15
LXY
0,15
LXY
1,15
LXY
2,15
LXY
3,15
BM
B
DEY
WRST TAY
13
TPU0A
The above table shows the relationship between machine language codes and machine language instructions. D3–D0
show the low-order 4 bits of the machine language code, and D8–D4 show the high-order 5 bits of the machine language
code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word
instructions, but only the first word of each instruction is shown. Do not use the code marked “–.”
The codes for the second word of a two-word instruction are described below.
BL
BML
BA
BLA
BMLA
SEA
SZD
The second word
1 1aaa aaaa
1 0aaa aaaa
1 1aaa aaaa
1 1aaa pppp
1 0aaa pppp
0 1011 nnnn
0 0010 1011
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 47 of 64
4286 Group
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (INDEX BY FUNCTION)
TAB
0
0
0
0
1
1
1
1
0
0 1
E
1
1
(A) ← (B)
TBA
0
0
0
0
0
1
1
1
0
0 0
E
1
1
(B) ← (A)
TAY
0
0
0
0
1
1
1
1
1
0 1
F
1
1
(A) ← (Y)
TYA
0
0
0
0
0
1
1
0
0
0 0
C
1
1
(Y) ← (A)
TEAB
0
0
0
0
1
1
0
1
0
0 1
A
1
1
(ER7–ER4) ← (B) (ER3–ER0) ← (A)
TABE
0
0
0
1
0
1
0
1
0
0 2
A
1
1
(B) ← (ER7–ER4) (A) ← (ER3–ER0)
TDA
0
0
0
1
0
1
0
0
1
0 2
9
1
1
(DR2–DR0) ← (A2–A0)
LXY x, y
0
1
1
x1 x0 y3 y2 y1 y0
0 C y
1
1
(X) ← x, x = 0 to 3
Instruction code
Parameter
Mnemonic
D8 D7 D6 D5 D4 D3 D2 D1 D0
Register to register transfer
Type of
instructions
Hexadecimal
notation
(Y) ← y, y = 0 to 15
+x
RAM addresses
Function
1
1
(Y) ← (Y) + 1
0 1 7
1
1
(Y) ← (Y) – 1
0 6
1
1
(A) ← (M(DP))
INY
0
0
0
0
1
0
0
1
1
0 1
DEY
0
0
0
0
1
0
1
1
1
TAM j
0
0
1
1
0
0
1
j1
j0
3
4
(X) ← (X) EXOR(j)
+j
j = 0 to 3
XAM j
0
0
1
1
0
0
0
j1
j0
0 6
j
1
1
(A) ←→ (M(DP))
RAM to register transfer
(X) ← (X) EXOR(j)
j = 0 to 3
XAMD j
0
0
1
1
0
1
1
j1
j0
0 6
C
1
1
(A) ←→ (M(DP))
(X) ← (X) EXOR(j)
+j
j = 0 to 3
(Y) ← (Y) – 1
XAMI j
0
0
1
1
0
1
0
j1
j0
0 6
8
+j
1
1
(A) ←→ (M(DP))
(X) ← (X) EXOR(j)
j = 0 to 3
(Y) ← (Y) + 1
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 48 of 64
Skip condition
Carry flag CY
4286 Group
–
–
Transfers the contents of register B to register A.
–
–
Transfers the contents of register A to register B.
–
–
Transfers the contents of register Y to register A.
–
–
Transfers the contents of register A to register Y.
–
–
Transfers the contents of registers A and B to register E.
–
–
Transfers the contents of register E to registers A and B.
–
–
Transfers the contents of register A to register D.
Continuous
–
Loads the value x in the immediate field to register X, and the value y in the immediate field to register
description
Detailed description
Y.
When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed
and other LXY instructions coded continuously are skipped.
(Y) = 0
–
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the
next instruction is skipped.
(Y) = 15
–
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y
is 15, the next instruction is skipped.
–
–
After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between
register X and the value j in the immediate field, and stores the result in register X.
–
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
(Y) = 15
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y
is 15, the next instruction is skipped.
(Y) = 0
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the
next instruction is skipped.
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 49 of 64
4286 Group
Mnemonic
D8 D7 D6 D5 D4 D3 D2 D1 D0
Type of
instructions
LA n
0
1
0
1
1
n3 n2 n1 n0
Hexadecimal
notation
0 B n
Number of
cycles
Instruction code
Parameter
Number of
words
MACHINE INSTRUCTIONS (CONTINUED)
1
1
Function
(A) ← n
n = 0 to 15
TABP p
0
1
0
0
1
p3 p2 p1 p0
0 9
p
1
3
(SK(SP)) ← (PC)
(SP) ← (SP) + 1
(PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
When URS=0,
(B) ← (ROM(PC))7 to 4
(A) ← (ROM(PC))3 to 0
When URS=1,
(CY) ← (ROM(PC))8
(B) ← (ROM(PC))7 to 4
(A) ← (ROM(PC))3 to 0
(SP) ← (SP) – 1
Arithmetic operation
(PC) ← (SK(SP))
AM
0
0
0
0
0
1
0
1
0
0 0
A
1
1
(A) ← (A) + (M(DP))
AMC
0
0
0
0
0
1
0
1
1
0 0
B
1
1
(A) ← (A) + (M(DP))+ (CY)
(CY) ← Carry
An
0
1
0
1
0
n3 n2 n1 n0
0 A n
1
1
(A) ← (A) + n
n = 0 to 15
SC
0
0
0
0
0
0
1
1
1
0 0
7
1
1
(CY) ← 1
RC
0
0
0
0
0
0
1
1
0
0 0
6
1
1
(CY) ← 0
SZC
0
0
0
1
0
1
1
1
1
0 2
F
1
1
(CY) = 0 ?
CMA
0
0
0
0
1
1
1
0
0
0 1
C
1
1
(A) ← (A)
RAR
0
0
0
0
1
1
1
0
1
0 1
D
1
1
→ CY → A3A2A1A0
LGOP
0
0
1
0
0
0
0
0
1
0 4
1
1
1
Logic operation instruction XOR, OR, AND
Note: p is 0 to 15.
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
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Skip condition
Carry flag CY
4286 Group
Continuous
–
description
Detailed description
Loads the value n in the immediate field to register A.
When the LA instructions are continuously coded and executed, only the first LA instruction is executed
and other LA instructions coded continuously are skipped.
–
–
Transfers bits 7 to 4 to register B and bits 3 to 0 to register A when URS flag is cleared to “0.” These bits
7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0) specified by registers A and D in
page p.
0/1 Transfers bit 8 of ROM pattern is transferred to flag CY when URS flag is set to “1” (after the URSC
instruction is executed).
(One of stack is used when the TABP p instruction is executed.)
–
–
Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY
remains unchanged.
–
0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag
CY.
Overflow = 0
–
Adds the value n in the immediate field to register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no overflow as the result of operation.
–
1
Sets (1) to carry flag CY.
–
0
Clears (0) to carry flag CY.
(CY) = 0
–
Skips the next instruction when the contents of carry flag CY is “0.”
–
–
Stores the one‘s complement for register A‘s contents in register A.
–
–
0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right.
–
Executes the logic operation selected by logic operation selection register LO between the contents of
register A and register E, and stores the result in register A.
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 51 of 64
4286 Group
Mnemonic
D8 D7 D6 D5 D4 D3 D2 D1 D0
Type of
instructions
SB j
0
0
1
0
1
1
1
j1
j0
Hexadecimal
notation
0 5
C
Number of
cycles
Instruction code
Parameter
Number of
words
MACHINE INSTRUCTIONS (CONTINUED)
1
1
Bit operation
+j
RB j
0
0
1
0
0
1
1
j1
j0
0 4
C
0
0
0
1
0
0
0
j1
j0
0 2
j
(Mj(DP)) ← 1
j = 0 to 3
1
1
+j
SZB j
Function
(Mj(DP)) ← 0
j = 0 to 3
1
1
(Mj(DP)) = 0 ?
operation
Comparison
j = 0 to 3
SEAM
0
0
0
1
0
0
1
1
0
0 2
6
1
1
(A) = (M(DP)) ?
SEA n
0
0
0
1
0
0
1
0
1
0 2
5
2
2
(A) = n ?
0
1
0
1
1
n3 n2 n1 n0
1
1
a6 a5 a4 a3 a2 a1 a0
n = 0 to 15
Ba
0 B n
1
8
a
1
1
p
2
2
(PCL) ← a6–a0
+a
BL p, a
0
0
0
1
1
p3 p2 p1 p0
0 3
(PCH) ← p
(PCL) ← a6–a0
Branch operation
(Note)
1
1
a6 a5 a4 a3 a2 a1 a0
1 8
a
+a
BA a
0
0
0
0
0
0
0
0
1
1
1
a6 a5 a4 a3 a2 a1 a0
0 0
1
1 8
a
2
2
2
2
(PCL) ← (a6–a4, A3–A0)
+a
BLA p, a
0
0
0
0
1
0
0
0
0
0 1
0
(PCH) ← p
(PCL) ← (a6–a4, A3–A0)
1
1
a6 a5 a4 p3 p2 p1 p0
1 8
+a
Note: p is 0 to 15.
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 52 of 64
p
(Note)
Skip condition
Carry flag CY
4286 Group
–
–
Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
–
–
Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
(Mj(DP)) = 0
–
Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field)
Detailed description
of M(DP) is “0.”
j = 0 to 3
(A) = (M(DP))
–
Skips the next instruction when the contents of register A is equal to the contents of M(DP).
(A) = n
–
Skips the next instruction when the contents of register A is equal to the value n in the immediate field.
–
–
Branch within a page : Branches to address a in the identical page.
–
–
Branch out of a page : Branches to address a in page p.
–
–
Branch within a page : Branches to address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the low-
n = 0 to 15
order 4 bits of the address a in the identical page with register A.
–
–
Branch out of a page : Branches to address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the loworder 4 bits of the address a in page p with register A.
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 53 of 64
4286 Group
Mnemonic
Type of
instructions
BM a
D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecimal
notation
1
1
0
a6 a5 a4 a3 a2 a1 a0
a
a
Number of
cycles
Instruction code
Parameter
Number of
words
MACHINE INSTRUCTIONS (CONTINUED)
1
1
Function
(SK(SP)) ← (PC)
(SP) ← (SP) + 1
(PCH) ← 2
Subroutine operation
(PCL) ← a6–a0
BML p, a
0
0
1
1
1
p3 p2 p1 p0
0 7
p
2
2
(SK(SP)) ← (PC)
(SP) ← (SP) + 1
(PCH) ← p
1
0
a6 a5 a4 a3 a2 a1 a0
1 a a
(PCL) ← a6–a0
(Note)
BMLA p, a 0
0
1
0
1
0
0
0
0
1
0
a6 a5 a4 p3 p2 p1 p0
0 5
0
1 a
p
2
2
(SK(SP)) ← (PC)
(SP) ← (SP) + 1
(PCH) ← p
(PCL) ← (a6–a4, A3–A0)
Return operation
(Note)
RT
0
0
1
0
0
0
1
0
0
0 4
4
1
2
(SP) ← (SP) – 1
(PC) ← (SK(SP))
RTS
0
0
1
0
0
0
1
0
1
0 4
5
1
2
(SP) ← (SP) – 1
(PC) ← (SK(SP))
T1AB
0
0
1
0
0
0
1
1
1
0 4 7
1
1
at timer 1 stop (V10=0)
(R17–R14) ← (B), (R13–R10) ← (A)
(T17–T14) ← (B), (T13–T10) ← (A)
at timer 1 operating (V10=1)
(R17–R14) ← (B), (R13–R10) ← (A)
TAB1
0
0
1
0
1
0
1
1
1
0 5 7
1
1
(B) ← (T17–T14)
Timer operation
(A) ← (T13–T10)
TV1A
0
0
1
0
1
1
0
1
1
0 5 B
1
1
(V12–V10) ← (A2–A0)
SNZT1
0
0
1
0
0
0
0
1
0
0 4 2
1
1
(T1F) = 1 ?
(T1F) ← 0
T2AB
0
1
0
0
0
1
0
0
0
0 8 8
1
1
(R2L7–R2L4) ← (B)
(R2L3–R2L0) ← (A)
(T27–T24) ← (B),
(T23–T20) ← (A)
Note : p is 0 to 15.
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 54 of 64
Skip condition
Carry flag CY
4286 Group
–
–
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
–
–
Call the subroutine : Calls the subroutine at address a in page p.
–
–
Call the subroutine : Calls the subroutine at address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the
Detailed description
low-order 4 bits of address a in page p with register A.
–
–
Returns from subroutine to the routine called the subroutine.
Skip at uncondition
–
Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
–
–
At timer 1 stop (V10 = 0), transfers the contents of register A and register B to timer 1 and reload
register R1.
At timer 1 operating (V10 = 1), transfers the contents of register A and register B to reload register R1.
–
–
Transfers the contents of timer 1 to registers A and B.
–
–
Transfers the contents of register A to registers V1.
(T1F) = 1
–
Clears T1F flag and skips the next instruction when the contents of T1F flag is “1.”
–
–
Transfers the contents of register A and register B to timer 2 and reload register R2L.
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 55 of 64
4286 Group
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (CONTINUED)
TAB2
0
0
1
0
0
0
0
0
0
0 4 0
1
1
(B) ← (T27–T24), (A) ← (T23–T20)
TV2A
0
0
1
0
1
1
0
1
0
0 5 A
1
1
(V23–V20) ← (A3–A0)
SNZT2
0
0
1
0
1
0
0
1
0
0 5 2
1
1
(T2F) = 1 ?
Instruction code
Parameter
Mnemonic
D8 D7 D6 D5 D4 D3 D2 D1 D0
Timer operation
Type of
instructions
Hexadecimal
notation
Function
(T2F) ← 0
T2HAB
0
1
0
0
0
1
0
0
1
0 8 9
1
1
(R2H7–R2H4) ← (B)
(R2H3–R2H0) ← (A)
T2R2L
0
0
1
0
1
0
0
1
1
0 5 3
1
1
(T27–T24) ← (R2L7–R2L4)
Carrier wave
control operation
(T23–T20) ← (R2L3–R2L0)
SCAR
0
1
0
0
0
0
1
1
1
0 8 7
1
1
(CAR) ← 1
RCAR
0
1
0
0
0
0
1
1
0
0 8 6
1
1
(CAR) ← 0
CLD
0
0
0
0
1
0
0
0
1
0 1 1
1
1
(D) ← 0
RD
0
0
0
0
1
0
1
0
0
0 1 4
1
1
(D(Y)) ← 0
(Y) = 0 to 7
SD
0
0
0
0
1
0
1
0
1
0 1 5
1
1
(D(Y)) ← 1
(Y) = 0 to 7
0
0
0
1
0
0
1
0
0
0 2 4
0
0
0
1
0
1
0
1
1
0 2 B
OEA
0
1
0
0
0
0
1
0
0
0 8 4
1
1
(E1, E0) ← (A1, A0)
IAE
0
0
1
0
1
0
1
1
0
0 5 6
1
1
(A2–A0) ← (E2–E0)
OGA
0
1
0
0
0
0
0
0
0
0 8 0
1
1
(G) ← (A)
IAG
0
0
0
1
0
1
0
0
0
0 2 8
1
1
(A) ← (G)
Input/Output operation
SZD
2
2
(D(Y)) = 0 ?
(Y) = 0 to 7
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 56 of 64
Skip condition
Carry flag CY
4286 Group
–
–
Transfers the contents of timer 2 to registers A and B.
–
–
Transfers the contents of register A to registers V2.
(T2F) = 1
–
Clears T2F flag and skips the next instruction when the contents of T2F flag is “1.”
–
–
Transfers the contents of register A and register B to reload register R2H.
–
–
Transfers the contents of reload register R2L to timer 2.
–
–
Sets (1) to port CARR output flag (CAR).
–
–
Clears (0) to port CARR output flag (CAR).
–
–
Clears (0) to port D (high-impedance state).
–
–
Clears (0) to a bit of port D specified by register Y (high-impedance state).
–
–
Sets (1) to a bit of port D specified by register Y.
(D(Y)) = 0
–
Skips the next instruction when a bit of port D specified by register Y is “0.”
–
–
Outputs the contents of register A to port E.
–
–
Transfers the contents of port E to register A.
–
–
Outputs the contents of register A to port G.
–
–
Transfers the contents of port G to register A.
Detailed description
(Y) = 0 to 7
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 57 of 64
Number of
words
Number of
cycles
4286 Group
NOP
0
0
0
0
0
0
0
0
0
0 0 0
1
1
(PC) ← (PC) + 1
POF
0
0
0
0
0
1
1
0
1
0 0
D
1
1
RAM back-up
SNZP
0
0
0
0
0
0
0
1
1
0 0
3
1
1
(P) = 1 ?
CCK
0
0
1
0
1
1
0
0
1
0 5
9
1
1
STCK changes to f(XIN)
CCK2
0
0
0
0
1
1
0
0
1
0 1
9
1
1
STCK changes to f(XIN)/2
CCK4
0
0
0
1
0
1
1
0
1
0 2
D
1
1
STCK changes to f(XIN)/4
CLVD
0
0
0
1
0
1
1
1
0
0 2
E
1
1
Reset occurrence voltage 1.5V → 1.7V
TLOA
0
0
1
0
1
1
0
0
0
0 5
8
1
1
(LO1, LO0) ← (A1, A0)
URSC
0
1
0
0
0
0
0
1
0
0 8
2
1
1
(URS) ← 1
TPU0A
0
1
0
0
0
1
1
1
1
0 8
F
1
1
(PU03–PU00) ← (A3–A0)
TPU1A
0
1
0
0
0
1
1
1
0
0 8
E
1
1
(PU13–PU10) ← (A3–A0)
TPU2A
0
1
0
0
0
1
1
0
1
0 8
D
1
1
(PU23–PU20) ← (A3–A0)
WRST
0
0
0
0
0
1
1
1
1
0 0
F
1
1
(WDF1) ← 0
Instruction code
Parameter
Mnemonic
D8 D7 D6 D5 D4 D3 D2 D1 D0
Other operation
Type of
instructions
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 58 of 64
Hexadecimal
notation
Function
Skip condition
Carry flag CY
4286 Group
–
–
No operation
–
–
Puts the system in RAM back-up state.
(P) = 1
–
Skips the next instruction when P flag is “1”.
Detailed description
After skipping, P flag remains unchanged.
–
–
System clock (STCK) changes to f(XIN) from f(XIN)/8.
–
–
System clock (STCK) changes to f(XIN) /2from f(XIN)/8.
–
–
System clock (STCK) changes to f(XIN) /4from f(XIN)/8.
–
–
Change detection voltage from 1.5V to 1.7V (Ta = 25°C, Typ).
–
–
Transfers the contents of register A to the logic operation selection register LO.
–
–
Sets the most significant ROM code reference enable flag (URS) to “1.”
–
–
Transfers the contents of register A to register PU0.
–
–
Transfers the contents of register A to register PU1.
–
–
Transfers the contents of register A to register PU2.
–
–
Initializes the watchdog timer flag (WDF1).
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 59 of 64
4286 Group
REGISTER STRUCTURE
Timer control register V1
V12
V11
V10
Carrier wave output auto-control bit
Timer 1 count source selection bit
Timer 1 control bit
at reset : 0002
0
Auto-control output by timer 1 is invalid
1
Auto-control output by timer 1 is valid
0
Carrier wave output (CARRY)
1
Bit 5 of watchdog timer (WDT)
0
Stop (Timer 1 state retained)
1
Operating
Timer control register V2
V23
V22
Carrier wave “H” interval expansion bit
Carrier wave generation function control bit
V21
Timer 2 count source selection bit
V20
Timer 2 control bit
at reset : 00002
0
PU02
To expand “H” interval is valid (when V22=1 selected)
0
Carrier wave generation function invalid
1
Carrier wave generation function valid
0
f(XIN)
1
f(XIN)/2
0
Stop (Timer 2 state retained)
1
Operating
at reset : 00002
Pull-down transistor OFF, key-on wakeup invalid
bit
1
Pull-down transistor ON, key-on wakeup valid
Ports G0, G1 pull-down transistor control
0
Pull-down transistor OFF, key-on wakeup invalid
bit
1
Pull-down transistor ON, key-on wakeup valid
0
Pull-down transistor OFF, key-on wakeup invalid
1
Pull-down transistor ON, key-on wakeup valid
0
Pull-down transistor OFF, key-on wakeup invalid
1
Pull-down transistor ON, key-on wakeup valid
PU00
Port E0 pull-down transistor control bit
Pull-down control register PU1
Port D7 pull-down transistor control bit
PU12
Port D6 pull-down transistor control bit
PU11
Port D5 pull-down transistor control bit
PU10
at RAM back-up : state retained
0
Port E1 pull-down transistor control bit
Port D4 pull-down transistor control bit
Note: “W” represents write enabled.
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 60 of 64
W
W
To expand “H” interval is invalid
Ports G2, G3 pull-down transistor control
PU01
PU13
at RAM back-up : 00002
1
Pull-down control register PU0
PU03
at RAM back-up : 0002
at reset : 00002
at RAM back-up : state retained
0
Pull-down transistor OFF, key-on wakeup invalid
1
Pull-down transistor ON, key-on wakeup valid
0
Pull-down transistor OFF, key-on wakeup invalid
1
Pull-down transistor ON, key-on wakeup valid
0
Pull-down transistor OFF, key-on wakeup invalid
1
Pull-down transistor ON, key-on wakeup valid
0
Pull-down transistor OFF, key-on wakeup invalid
1
Pull-down transistor ON, key-on wakeup valid
W
W
4286 Group
Pull-down control register PU2
PU23
Port D3 pull-down transistor control bit
PU22
Port D2 pull-down transistor control bit
PU21
Port D1 pull-down transistor control bit
PU20
Port D0 pull-down transistor control bit
Logic operation selection register LO
0
Pull-down transistor OFF, key-on wakeup invalid
1
Pull-down transistor ON, key-on wakeup valid
0
Pull-down transistor OFF, key-on wakeup invalid
1
Pull-down transistor ON, key-on wakeup valid
0
Pull-down transistor OFF, key-on wakeup invalid
1
Pull-down transistor ON, key-on wakeup valid
0
Pull-down transistor OFF, key-on wakeup invalid
1
Pull-down transistor ON, key-on wakeup valid
at reset : 002
LO1 LO0
0
LO1
Logic operation selection bits
0
1
LO0
1
Note: “W” represents write enabled.
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 61 of 64
at RAM back-up : state retained
at reset : 00002
at RAM back-up : 002
Logic operation function
0 Exclusive logic OR operation (XOR)
1 OR operation (OR)
0 AND operation (AND)
1 Not available
W
W
4286 Group
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Ratings
Conditions
Unit
VDD
Supply voltage
–0.3 to 5
V
VI
Input voltage
–0.3 to VDD+0.3
V
VO
Output voltage
–0.3 to VDD+0.3
Pd
Power dissipation
Topr
Tstg
V
300
mW
Operating temperature range
–40 to 85
°C
Storage temperature range
–65 to 125
°C
Ta = 25 °C
RECOMMENDED OPERATING CONDITIONS
(Ta = –40 to 85 °C, VDD = 1.8 V to 3.6 V, unless otherwise noted)
Symbol
Parameter
Conditions
Limits
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.8
VRAM
RAM back-up voltage (at RAM back-up mode)
1.1
VSS
Supply voltage
VIH
“H” level input voltage Ports D, E, G
VDD = 3.0 V
0.7VDD
VDD
V
VIH
“H” level input voltage XIN
VDD = 3.0 V
0.8VDD
VDD
V
VIL
“L” level input voltage Ports D, E, G
VDD = 3.0 V
0
0.2VDD
V
VIL
“L” level input voltage XIN
VDD = 3.0 V
0
3.6
V
3.6
V
0
V
0.2VDD
V
IOH(peak) “H” level peak output current Ports D, E1, G
VDD = 3.0 V
–4
mA
IOH(peak) “H” level peak output current Port E0
IOH(peak) “H” level peak output current CARR
VDD = 3.0 V
–24
mA
VDD = 3.0 V
–20
mA
IOL(peak) “L” level peak output current CARR
VDD = 3.0 V
4
mA
IOH(avg) “H” level average output current Ports D, E1, G
IOH(avg) “H” level average output current Port E0
IOH(avg) “H” level average output current CARR
VDD = 3.0 V
–2
mA
VDD = 3.0 V
–12
mA
VDD = 3.0 V
–10
mA
IOL(avg) “L” level average output current CARR
VDD = 3.0 V
2
mA
4
MHz
2
MHz
f(XIN)
VDET
when STCK = f(XIN)/8, f(XIN)/4, f(XIN)/2 selected Ceramic resonance
clock frequency
Ceramic resonance
when STCK = f(XIN) selected
Detection voltage
(before CLVD
instruction execution)
Ta = 25 °C
Reset occurrence/
Reset release
Voltage drop detection circuit low voltage
determination time
Power-on reset circuit valid power source rising time
When supply voltage passes
the detected voltage at ±50V/s.
Ta = –20 °C to 85 °C
VDD = 0 → 2.2 V
Ta = –40 °C to 85 °C
Note: The average output current ratings are the average current value during 100 ms.
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 62 of 64
1.5
1.6
1.6
1.56
V
2.2
1.7
1.76
1.7
1.76
0.2
1.2
ms
1
ms
100
µs
1.2
Ta = 25 °C
VDD = 0 → 2.2 V
TPON
1.4
1.9
1.2
Reset release
Ta = 25 °C
Detection voltage
(after CLVD
instruction execution)
TDET
Reset occurrence
1.1
2.2
V
4286 Group
ELECTRICAL CHARACTERISTICS
(Ta = –40 °C to 85 °C, VDD = 3 V, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Min.
Typ.
Max.
Unit
VOL
“L” level output voltage Port CARR
IOL = 2 mA
0.9
V
VOL
“L” level output voltage XOUT
IOL = 0.2 mA
0.9
V
VOH
“H” level output voltage Ports D, E1, G
IOH = –2 mA
2.1
V
VOH
“H” level output voltage Port E0
IOH = –12 mA
1.5
V
VOH
“H” level output voltage CARR
IOH = –10 mA
1.0
V
VOH
“H” level output voltage XOUT
IOH = –0.2 mA
2.1
IIL
“L” level input current Ports D, E, G
VI = VSS
–1
IIH
“H” level input current Ports E0, E1
VI = VDD
1
V
µA
µA
Pull-down transistor in off-state
IOZ
Output current at off-state Ports D, E0, E1, G VO = VSS
Supply current (when operating)
IDD
Supply current (at RAM back-up)
RPH
Pull-down resistor value Ports D, G, E
ROSC
Feedback resistor value between XIN–XOUT
–1
f(XIN) = 4.0 MHz
400
800
f(XIN) = 2.0 MHz
350
700
f(XIN) = 1.0 MHz
300
600
f(XIN) = 500 kHz
250
500
Ta = 25 °C
VI = 3V
75
700
1
3
0.1
0.5
150
300
3200
µA
µA
µA
µA
µA
µA
µA
kΩ
kΩ
BASIC TIMING DIAGRAM
Machine cycle
Parameter
Pin name
System clock
STCK
Ports D, E, G output
D0–D7,E0,E1
G0–G3
Ports D, E, G input
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
D0–D7
E0–E2
G0–G3
page 63 of 64
Mi
Mi+1
4286 Group
PACKAGE OUTLINE
JEITA Package Code
P-LSSOP20-4.4x6.5-0.65
RENESAS Code
PLSP0020JB-A
MASS[Typ.]
0.1g
11
*1
E
20
HE
Previous Code
20P2F-A
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
F
1
Index mark
10
c
A1
Reference
Symbol
D
A
L
*2
A2
*3
e
y
bp
Detail F
D
E
A2
A
A1
bp
c
HE
e
y
L
Rev.1.00 Aug 06, 2008
REJ03B0251-0100
page 64 of 64
Dimension in Millimeters
Min
6.4
4.3
Nom Max
6.5 6.6
4.4 4.5
1.15
1.45
0.1 0.2
0
0.17 0.22 0.32
0.13 0.15 0.2
0°
10°
6.2 6.4 6.6
0.53 0.65 0.77
0.10
0.3 0.5 0.7
4286 Group Datasheet
REVISION HISTORY
Rev.
Date
Description
Summary
Page
1.00 Aug. 06, 2008
-
First edition issued.
All trademarks and registered trademarks are the property of their respective owners.
(1/1)
Sales Strategic Planning Div.
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Notes:
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes
warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property
rights or any other rights of Renesas or any third party with respect to the information in this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a
result of errors or omissions in the information included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability
of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular
application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications
or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality
and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or
undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall
have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as
swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.
Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have
any other inquiries.
http://www.renesas.com
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2377-3473
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2008. Renesas Technology Corp., All rights reserved. Printed in Japan.
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