ETC 4556

PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
REJ03B0025-0101Z
Rev.1.01
2003.09.17
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 4556 Group is a 4-bit single-chip microcomputer designed with
CMOS technology. Its CPU is that of the 4500 series using a
simple, high-speed instruction set. The computer is equipped with
two 8-bit timers (each timer has one or two reload register), a 16-bit
timer for clock count, interrupts, and oscillation circuit switch function.
The various microcomputers in the 4556 Group include variations
of the built-in memory size as shown in the table below.
FEATURES
●Minimum instruction execution time .................................. 0.5 µs
(at 6 MHz oscillation frequency, in through-mode)
●Supply voltage
Mask ROM version ...................................................... 1.8 to 5.5 V
One Time PROM version ............................................. 2.5 to 5.5 V
(It depends on operation source clock, oscillation frequency and operation mode)
●Timers
Timer 1 ...................................... 8-bit timer with a reload register
Timer 2 ................................. 8-bit timer with two reload registers
Timer 3 .............................. 16-bit timer (fixed dividing frequency)
4556 Group
Part number
M34556M4-XXXFP
M34556M8-XXXFP
M34556G8FP (Note)
M34556M4H-XXXFP
M34556M8H-XXXFP
M34556G8HFP (Note)
ROM (PROM) size
(✕ 10 bits)
4096 words
8192 words
8192 words
4096 words
8192 words
8192 words
Note: Shipped in blank.
Rev.1.01
Sep 17, 2003
page 1 of 130
●Interrupt ........................................................................ 4 sources
●Key-on wakeup function pins ..................................................... 9
● LCD control circuit
Segment output ........................................................................ 23
Common output .......................................................................... 4
●Voltage drop detection circuit (only H version)
Reset occurrence .................................... Typ. 1.8 V (Ta = 25 °C)
Reset release .......................................... Typ. 1.9 V (Ta = 25 °C)
●Watchdog timer
●Clock generating circuit
Built-in clock
(built-in ring oscillator)
Main clock
(ceramic resonator/RC oscillation)
Sub-clock
(quartz-crystal oscillation)
●LED drive directly enabled (port D)
APPLICATION
Remote control transmitter
RAM size
(✕ 4 bits)
288 words
288 words
288 words
288 words
288 words
288 words
Package
ROM type
42P2R-A
42P2R-A
42P2R-A
42P2R-A
42P2R-A
42P2R-A
Mask ROM
Mask ROM
One Time PROM
Mask ROM
Mask ROM
One Time PROM
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
PIN CONFIGURATION
1
42
VSS
2
41
VDD
CNVSS
3
40
C/CNTR
XCIN/D6
4
39
D5/INT
XCOUT/D7
5
38
D4
RESET
6
37
D3
COM0
7
36
D2
COM1
8
35
D1
COM2
9
34
D0
COM3
10
33
P13/SEG28
SEG0/VLC3
11
32
P12/SEG27
SEG1/VLC2
12
31
P11/SEG26
SEG2/VLC1
13
30
P10/SEG25
SEG3
14
29
P03/SEG24
SEG4
15
28
P02/SEG23
SEG5
16
27
P01/SEG22
SEG6
17
26
P00/SEG21
SEG7
18
25
P23/SEG20
SEG8
19
24
P22/SEG19
SEG9
20
23
P21/SEG18
SEG10
21
22
P20/SEG17
Pin configuration (top view) (4556 Group)
Rev.1.01
Sep 17, 2003
page 2 of 130
M34556Mx-XXXFP
M34556G8FP
M34556MxH-XXXFP
M34556G8HFP
XIN
XOUT
Rev.1.01
Port P0
4
Port P1
Sep 17, 2003
Block diagram (4556 Group)
page 3 of 130
4
Note: The voltage drop detection circuit is equipped with only H version
23
Common output
ALU(4 bits)
.
Register A (4 bits)
Register B (4 bits)
Register E (8 bits)
Register D (3 bits)
Stack register SK (8 levels)
Interrupt stack register SDP (1 level)
ROM
1
Port C
2
Port D
288 words ✕ 4 bits
LCD display RAM
including 23 words ✕ 4 bits
RAM
4096, 8192 words
✕ 10 bits
6
4556 Group
Segment output
LCD drive control circuit
(Max.23 segments ✕ 4 common)
Voltage drop detection circuit
Watchdog timer (16 bits)
4500 series
CPU core
XIN -XOUT
(Ceramic/RC)
XCIN -XCOUT
(Quartz-crystal)
Built-in ring oscillator
Timer 1(8 bits)
Timer 2(8 bits)
Timer 3(16 bits)
Memory
System clock generation circuit
Port P2
4
Timer
Internal peripheral functions
I/O por t
4
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
PERFORMANCE OVERVIEW
Parameter
Number of basic M34556M4/M8/G8
instructions M34556M4H/M8H/G8H
Minimum instruction execution time
Memory sizes ROM M34556M4
Function
123
124
0.5 µs (at 6 MHz oscillation frequency, in through mode)
4096 words ✕ 10 bits
M34556M4H
8192 words ✕ 10 bits
M34556M8/G8
M34556M8H/G8H
RAM M34556M4/M8/G8 288 words ✕ 4 bits (including LCD display RAM 23 words ✕ 4 bits)
M34556M4H/M8H/G8H
I/O
Input/Output D0–D5
Six independent I/O ports.
ports
Input is examined by skip decision.
The output structure can be switched by software.
Port D5 is also used as INT pin.
Output
Two independent output ports.
D 6, D 7
Ports D6 and D7 are also used as XCIN and XCOUT, respectively.
4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched
P00–P03 I/O
by software. Ports P00–P03 are also used as SEG21–SEG24, respectively.
4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched
P10–P13 I/O
by software. Ports P10–P13 are also used as SEG25–SEG28, respectively.
4-bit I/O port; The output structure can be switched by software. Ports P20–P23 are also used
P20–P23 I/O
as SEG17–SEG20, respectively.
Output
1-bit output; Port C is also used as CNTR pin.
C
Timers
8-bit programmable timer with a reload register and has an event counter.
Timer 1
8-bit programmable timer with two reload registers and PWM output function.
Timer 2
16-bit timer, fixed dividing frequency (timer for clock count)
Timer 3
4-bit timer with a reload register (for LCD clock)
Timer LC
16-bit timer (fixed dividing frequency) (for watchdog)
Watchdog timer
LCD control Selective bias value
1/2, 1/3 bias
circuit
2, 3, 4 duty
Selective duty value
4
Common output
23
Segment output
2r ✕ 3, 2r ✕ 2, r ✕ 3, r ✕ 2 (r = 80 kΩ, (Ta = 25 °C, Typical value))
Internal resistor for
power supply
Interrupt
4 (one for external, three for timer )
Sources
1 level
Nesting
Subroutine nesting
8 levels
Device structure
CMOS silicon gate
Package
42-pin plastic molded SSOP (42P2R-A)
Operating temperature range
–20 °C to 85 °C
Supply
1.8 to 5.5 V (It depends on operation source clock, oscillation frequency and operation mode)
Mask ROM version
voltage
One Time PROM version 2.5 to 5.5 V (It depends on operation source clock, oscillation frequency and operation mode)
Power
2.2 mA (at room temperature, VDD = 5 V, f(XIN) = 6 MHz, f(XCIN) = stop, f(RING) = stop,
Active mode
dissipation
f(STCK) = f(XIN)/1)
(Typ.value)
At clock operating mode 6 µA (at room temperature, VDD = 5 V, f(XCIN) = 32 kHz)
0.1 µA (at room temperature, VDD = 5 V, output transistor is cut-off state)
At RAM back-up
Rev.1.01
Sep 17, 2003
page 4 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
PIN DESCRIPTION
Pin
VDD
VSS
CNVSS
RESET
Name
Power supply
Ground
CNVSS
Reset input/output
XIN
Main clock input
XOUT
Main clock output
Input/Output
—
—
—
I/O
Input
Output
XCIN
Sub-clock input
Input
XCOUT
Sub-clock output
Output
D0–D5
I/O port D
Input is examined by
skip decision.
I/O
D 6, D 7
Output port D
P00–P03
I/O port P0
I/O
P10–P13
I/O port P1
I/O
P20–P23
I/O port P2
I/O
Port C
COM0–
COM3
SEG0–SEG10
SEG17–SEG28
(Note)
CNTR
Output port C
Common output
Output
Output
Segment output
Output
INT
Interrupt input
Output
Timer input/output
I/O
Input
Function
Connected to a plus power supply.
Connected to a 0 V power supply.
Connect CNVSS to VSS and apply “L” (0V) to CNVSS certainly.
An N-channel open-drain I/O pin for a system reset. When the watchdog timer or the
voltage drop detection circuit cause the system to be reset, the RESET pin outputs
“L” level.
I/O pins of the main clock generating circuit. When using a ceramic resonator, connect it between pins X IN and XOUT. A feedback resistor is built-in between them.
When using the RC oscillation, connect a resistor and a capacitor to XIN, and leave
XOUT pin open.
I/O pins of the sub-clock generating circuit. Connect a 32.768 kHz quartz-crystal oscillator between pins XCIN and XCOUT. A feedback resistor is built-in between them. XCIN and
XCOUT pins are also used as ports D6 and D7, respectively.
Each pin of port D has an independent 1-bit wide I/O function. The output structure
can be switched to N-channel open-drain or CMOS by software. For input use, set
the latch of the specified bit to “1” and select the N-channel open-drain. Port D 5 is
also used as INT pin.
Each pin of port D has an independent 1-bit wide output function. The output structure is N-channel open-drain. Ports D6 and D7 are also used as XCIN pin and XCOUT
pin, respectively.
Port P0 serves as a 4-bit I/O port. The output structure can be switched to N-channel
open-drain or CMOS by software. For input use, set the latch of the specified bit to
“1” and select the N-channel open-drain. Port P0 has a key-on wakeup function and
a pull-up function. Both functions can be switched by software. Ports P0 0–P03 are
also used as SEG21–SEG24, respectively.
Port P1 serves as a 4-bit I/O port. The output structure can be switched to N-channel
open-drain or CMOS by software. For input use, set the latch of the specified bit to
“1” and select the N-channel open-drain. Port P1 has a key-on wakeup function and
a pull-up function. Both functions can be switched by software. Ports P1 0–P13 are
also used as SEG25–SEG28, respectively.
Port P2 serves as a 4-bit I/O port. The output structure can be switched to N-channel
open-drain or CMOS by software. For input use, set the latch of the specified bit to
“1” and select the N-channel open-drain.
Ports P20–P23 are also used as SEG17–SEG20, respectively.
1-bit output port. The output structure is CMOS. Port C is also used as CNTR pin.
LCD common output pins. Pins COM0 and COM1 are used at 1/2 duty, pins COM0–
COM2 are used at 1/3 duty and pins COM0–COM3 are used at 1/4 duty.
LCD segment output pins. SEG0–SEG2 pins are used as VLC3–VLC1 pins, respectively. SEG 17 –SEG 28 pins are used as Ports P20 –P23, Ports P0 0 –P03 and Ports
P10–P13, respectively.
CNTR pin has the function to input the clock for the timer 1 event counter and to output the PWM signal generated by timer 2.CNTR pin is also used as Port C.
INT pin accepts external interrupts. They have the key-on wakeup function which can
be switched by software. INT pin is also used as Port D5.
Note: SEG11 to SEG16 pins are not existed in the 4556 Group.
MULTIFUNCTION
Pin
XCIN
XCOUT
P00
P01
P02
P03
P10
P11
P12
P13
Multifunction
D6
D7
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
Pin
D6
D7
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
Multifunction
XCIN
XCOUT
P00
P01
P02
P03
P10
P11
P12
P13
Pin
P20
P21
P22
P23
D5
C
SEG0
SEG1
SEG2
Multifunction
SEG17
SEG18
SEG19
SEG20
INT
CNTR
VLC3
VLC2
VLC1
Pin
SEG17
SEG18
SEG19
SEG20
INT
CNTR
VLC3
VLC2
VLC1
Notes 1: Pins except above have just single function.
2: The input/output of D5 can be used even when INT is selected.
The threshold value is different between port D5 and INT. Accordingly, be careful when the input of both is used.
3: The port C “H” output function can be used even when CNTR (output) is selected.
Rev.1.01
Sep 17, 2003
page 5 of 130
Multifunction
P20
P21
P22
P23
D5
C
SEG0
SEG1
SEG2
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
DEFINITION OF CLOCK AND CYCLE
● Operation source clock
The operation source clock is the source clock to operate this
product. In this product, the following clocks are used.
• Clock (f(XIN)) by the external ceramic resonator
• Clock (f(XIN)) by the external RC oscillation
• Clock (f(XIN)) by the external input
• Clock (f(RING)) of the ring oscillator which is the internal oscillator
• Clock (f(XCIN)) by the external quartz-crystal oscillation
Table Selection of system clock
Register MR
MR2
MR3
MR1
MR0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
● System clock (STCK)
The system clock is the basic clock for controlling this product.
The system clock is selected by the clock control register MR
shown as the table below.
● Instruction clock (INSTCK)
The instruction clock is the basic clock for controlling CPU. The
instruction clock (INSTCK) is a signal derived by dividing the
system clock (STCK) by 3. The one instruction clock cycle generates the one machine cycle.
● Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
System clock
Operation mode
f(STCK) = f(RING)/8
f(STCK) = f(RING)/4
f(STCK) = f(RING)/2
f(STCK) = f(RING)
f(STCK) = f(XIN)/8
Internal frequency divided by 8 mode
Internal frequency divided by 4 mode
Internal frequency divided by 2 mode
Internal frequency through mode
High-speed frequency divided by 8 mode
High-speed frequency divided by 4 mode
High-speed frequency divided by 2 mode
High-speed through mode
Low-speed frequency divided by 8 mode
Low-speed frequency divided by 4 mode
Low-speed frequency divided by 2 mode
Low-speed through mode
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)
f(STCK) = f(XCIN)/8
f(STCK) = f(XCIN)/4
f(STCK) = f(XCIN)/2
f(STCK) = f(XCIN)
Note: The f(RING)/8 is selected after system is released from reset.
PORT FUNCTION
Port
Port D
Input
Output
I/O
(6)
Pin
D0–D4, D5/INT
Output structure
N-channel open-drain/
CMOS
I/O
unit
1
Control
Control
instructions registers
SD, RD
FR1, FR2
SZD
I1, K2
CLD
Output
(2)
I/O
(4)
N-channel open-drain
N-channel open-drain/
CMOS
4
OP0A
IAP0
FR0, PU0
K0
C1
Port P1 P10/SEG25–P13/SEG28
I/O
(4)
N-channel open-drain/
CMOS
4
OP1A
IAP1
FR0, PU1
K0, K1
C2
Port P2 P20/SEG17–P23/SEG20
I/O
(4)
Output
(1)
N-channel open-drain/
CMOS
CMOS
4
OP2A
IAP2
RCP
SCP
FR2
L3
W1
XCIN/D6, XCOUT/D7
Port P0 P00/SEG21–P03/SEG24
Port C
Rev.1.01
C/CNTR
Sep 17, 2003
page 6 of 130
Remark
Output structure selection
function (programmable)
RG
1
Built-in pull-up functions, key-on
wakeup functions and output
structure selection function
(programmable)
Built-in pull-up functions, key-on
wakeup functions and output
structure selection function
(programmable)
Output structure selection func
tion (programmable)
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
CONNECTIONS OF UNUSED PINS
Connection
Connect to VSS.
Open.
Connect to VSS.
Open.
Open.
Connect to VSS.
Open.
Connect to VSS.
Pin
XIN
XOUT
XCIN/D6
XCOUT/D7
D0–D4
D5/INT
C/CNTR
P00/SEG21–
P03/SEG24
Open.
Open.
Connect to VSS.
P10/SEG25–
P13/SEG28
Open.
Connect to Vss.
P20/SEG17–
P23/SEG20
Open.
Connect to Vss.
COM0–COM3
SEG0/VLC3
SEG1/VLC2
SEG2/VLC1
SEG3–SEG10
(Note)
Open.
Open.
Open.
Open.
Open.
Usage condition
RC oscillator is not selected
N-channel open-drain is selected for the output structure.
INT pin input is disabled.
N-channel open-drain is selected for the output structure.
CNTR input is not selected for timer 1 count source.
The key-on wakeup function is invalid.
Segment output is not selected.
N-channel open-drain is selected for the output structure.
Pull-up transistor is OFF.
The key-on wakeup function is invalid.
The key-on wakeup function is invalid.
Segment output is not selected.
N-channel open-drain is selected for the output structure.
Pull-up transistor is OFF.
The key-on wakeup function is invalid.
Segment output is not selected.
N-channel open-drain is selected for the output structure.
SEG0 pin is selected.
SEG1 pin is selected.
SEG2 pin is selected.
Note: SEG11 to SEG16 pins are not existed in the 4556 Group.
(Note when connecting to VSS and VDD)
● Connect the unused pins to VSS and VDD using the thickest wire at the shortest distance against noise.
Rev.1.01
Sep 17, 2003
page 7 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
PORT BLOCK DIAGRAMS
Skip decision
Register Y
Decoder
CLD
instruction
SZD instruction
(Note 3) FR1i
(Note 1)
S
D0—D3 (Note 2)
SD instruction
(Note 1)
R Q
RD instruction
Skip decision
Register Y
Decoder
CLD
instruction
SZD instruction
FR20
(Note 1)
S
D4
SD instruction
(Note 1)
R Q
RD instruction
(Note 2)
Skip decision
Register Y
Decoder
CLD
instruction
SZD instruction
FR21
(Note 1)
S
D5/INT (Note 2)
SD instruction
RD instruction
(Note 1)
R Q
(Note 4)
External 0 interrupt
External 0 interrupt circuit
Key-on wakeup input
Timer 1 count start synchronous circuit input
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
3: i represents bits 0 to 3.
4: As for details, refer to the external interrupt structure.
Port block diagram (1)
Rev.1.01
Sep 17, 2003
page 8 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
Register Y
Decoder
CLD
instruction
(Note 1)
S
SD instruction
XCIN/D6 (Note 2)
RG2
R Q
RD instruction
(Note 1)
1
0
Quartz-crystal
oscillation circuit
Sub-clock input
Register Y
Decoder
RG2
CLD
instruction
(Note 1)
S
SD instruction
XCOUT/D7 (Note 2)
RG2
R Q
RD instruction
(Note 1)
1
0
Clock input for timer 1 event count
Timer 1 underflow signal
W41
D
T
R
Q
(Note 1)
W12
C/CNTR
PWMOD
(Note 1)
SCP instruction
S Q
RCP instruction
R
W10
W11
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
Port block diagram (2)
Rev.1.01
Sep 17, 2003
page 9 of 130
(Note 2)
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
LCD power supply
C1j
0
LCD control
signal
1
(Note 1)
P00/SEG21, P01/SEG22
(Note 1)
C1j
key-on
wakeup
input
LCD power
supply
K00
Edge detection circuit
Register A
IAP0
instruction
Aj
Pull-up transistor
FR00
PU0j
D
Aj
OP0A instruction
T Q
LCD power supply
C1k
0
LCD control
signal
1
(Note 1)
P02/SEG23, P03/SEG24
(Note 1)
C1k
key-on
wakeup
input
LCD power
supply
K01
Edge detection circuit
Register A
IAP0
instruction
Ak
FR01
Pull-up transistor
PU0K
Ak
D
OP0A instruction
T Q
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
3: j represents bits 0 and 1.
4: k represents bits 2 and 3.
Port block diagram (3)
Rev.1.01
Sep 17, 2003
page 10 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
LCD power supply
C2j
0
LCD control
signal
1
(Note 1)
P10/SEG25, P11/SEG26
(Note 1)
key-on
wakeup
input
K11
0
1
Edge detection
circuit
Level detection
circuit
K10
C2j
K02
LCD power
supply
0
1
Register A
IAP1
instruction
Aj
Pull-up transistor
FR02
PU1j
D
Aj
OP1A instruction
T Q
LCD power supply
C2k
0
LCD control
signal
1
(Note 1)
P12/SEG27, P13/SEG28
(Note 1)
K13
key-on
wakeup
input
0
1
Edge detection
circuit
Level detection
circuit
K12
C2k
K03
0
LCD power
supply
1
Register A
IAP1
instruction
Ak
FR03
Pull-up transistor
PU1k
Ak
OP1A instruction
D
T Q
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
3: j represents bits 0 and 1.
4: k represents bits 2 and 3.
Port block diagram (4)
Rev.1.01
Sep 17, 2003
page 11 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
(Note 3)
LCD power supply
L3j
0
LCD control
signal
1
(Note 1)
P20/SEG17, P21/SEG18
(Note 2)
(Note 1)
(Note 3)
L3j
(Note 3)
Register A
LCD power
supply
IAP2
instruction
Aj
FR22
D
Aj
OP2A instruction
T Q
(Note 4)
LCD power supply
L3k
0
LCD control
signal
1
(Note 1)
P22/SEG19, P23/SEG20
(Note 2)
(Note 1)
(Note 4)
L3k
(Note 4)
Register A
LCD power
supply
IAP2
instruction
Ak
FR23
D
Ak
OP2A instruction
T Q
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
3: j represents bits 0 and 1.
4: k represents bits 2 and 3.
Port block diagram (5)
Rev.1.01
Sep 17, 2003
page 12 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
LCD power supply
LCD control signal
(Note 1)
SEG3–SEG10
SEG17 –SEG28
(Note 1)
LCD control signal
LCD power supply
LCD power supply
LCD control signal
(Note 1)
(Note 1)
COM0–COM3
(Note 2)
LCD control signal
LCD power supply
LCD power supply
LCD control signal
LCD control signal
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
Port block diagram (6)
Rev.1.01
Sep 17, 2003
page 13 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
LCD power supply
L23
1
LCD control
signal
0
(Note 1)
SEG0/VLC3 (Note 2)
(Note 1)
L23
LCD power
supply
LCD power supply
(VLC3)
LCD power supply
LCD control
signal
L22
1
0
(Note 1)
SEG1/VLC2 (Note 2)
(Note 1)
L22
LCD power
supply
LCD power supply
(VLC2)
LCD control
signal
L21
LCD power
supply
L21
1
0
(Note 1)
SEG2/VLC1 (Note 2)
(Note 1)
L21
LCD power
supply
LCD power supply
(VLC1)
L13
L20
Reset signal
L12
EPOF+POF2 instruction
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
Port block diagram (7)
Rev.1.01
Sep 17, 2003
page 14 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
One-sided edge
detection circuit
I12
(Note 1)
0
Timer 1 count start
synchronization
circuit input
External 0
EXF0
interrupt
I11
0
D5/INT
1
(Note 1)
1
Both edges
detection circuit
SNZI0 instruction
I13
Skip decision
K20
•
Block diagram of external interrupt
Rev.1.01
Sep 17, 2003
page 15 of 130
K21
Level detection circuit
0
Edge detection circuit
1
Key-on wakeup
input
This symbol represents a parasitic diode on the port.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
FUNCTION BLOCK OPERATIONS
CPU
<Carry>
(CY)
(1) Arithmetic logic unit (ALU)
(M(DP))
The arithmetic logic unit ALU performs 4-bit arithmetic such as 4bit data addition, comparison, AND operation, OR operation, and
bit manipulation.
ALU
Addition
(A)
<Result>
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation.
Carry flag CY is a 1-bit flag that is set to “1” when there is a carry
with the AMC instruction (Figure 1).
It is unchanged with both A n instruction and AM instruction. The value
of A0 is stored in carry flag CY with the RAR instruction (Figure 2).
Carry flag CY can be set to “1” with the SC instruction and cleared
to “0” with the RC instruction.
Fig. 1 AMC instruction execution example
<Set>
SC instruction
<Clear>
RC instruction
CY
A3 A2 A1 A0
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4-bit
data, and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data transfer
with register B used as the high-order 4 bits and register A as the
low-order 4 bits (Figure 3).
Register E is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value.
<Rotation>
RAR instruction
A0
Fig. 2 RAR instruction execution example
Register B
TAB instruction
B3 B2 B1 B0
(4) Register D
Register D is a 3-bit register.
It is used to store a 7-bit ROM address together with register A and
is used as a pointer within the specified page when the TABP p,
BLA p, or BMLA p instruction is executed (Figure 4).
Also, when the TABP p instruction is executed at UPTF flag = “1”,
the high-order 2 bits of ROM reference data is stored to the low-order 2 bits of register D, the high-order 1 bit of register D is “0”.
When the TABP p instruction is executed at UPTF flag = “0”, the
contents of register D remains unchanged. The UPTF flag is set to
“1” with the SUPT instruction and cleared to “0” with the RUPT instruction. The initial value of UPTF flag is “0”.
Register D is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value.
TABP p instruction
PCH
p4 p3 p2 p1 p0
Register A
A3 A2 A1 A0
TEAB instruction
Register E E7 E6 E5 E4 E3 E2 E1 E0
TABE instruction
A3 A2 A1 A0
B3 B2 B1 B0
Register B
TBA instruction
Register A
Fig. 3 Registers A, B and register E
ROM
Specifying address
p6 p5
C Y A3 A2 A1
PCL
DR2 DR1DR0 A3 A2 A1 A0
8
4
0
Low-order 4bits
Register A (4)
Middle-order 4 bits
Register B (4)
Immediate field
value p
The contents of The contents of
register D
register A
High-order 2 bits
Register D (3)
* UPTF=1, high-order 1 bit of register D is “0”.
UPTF=0, data is not transferred to register D.
Fig. 4 TABP p instruction execution example
Rev.1.01
Sep 17, 2003
page 16 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
(5) Stack registers (SKS) and stack pointer (SP)
Stack registers (SKs) are used to temporarily store the contents of
program counter (PC) just before branching until returning to the
original routine when;
• branching to an interrupt service routine (referred to as an interrupt service routine),
• performing a subroutine call, or
• executing the table reference instruction (TABP p).
Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers
is used respectively when using an interrupt service routine and
when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations
together. The contents of registers SKs are destroyed when 8 levels are exceeded.
The register SK nesting level is pointed automatically by 3-bit
stack pointer (SP). The contents of the stack pointer (SP) can be
transferred to register A with the TASP instruction.
Figure 5 shows the stack registers (SKs) structure.
Figure 6 shows the example of operation at subroutine call.
(6) Interrupt stack register (SDP)
Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the
contents of data pointer, carry flag, skip flag, register A, and register B just before an interrupt until returning to the original routine.
Unlike the stack registers (SKs), this register (SDP) is not used
when executing the subroutine call instruction and the table reference instruction.
Program counter (PC)
Executing BM
instruction
Executing RT
instruction
SK0
(SP) = 0
SK1
(SP) = 1
SK2
(SP) = 2
SK3
(SP) = 3
SK4
(SP) = 4
SK5
(SP) = 5
SK6
(SP) = 6
SK7
(SP) = 7
Stack pointer (SP) points “7” at reset or
returning from RAM back-up mode. It points “0”
by executing the first BM instruction, and the
contents of program counter is stored in SK0.
When the BM instruction is executed after eight
stack registers are used ((SP) = 7), (SP) = 0
and the contents of SK0 is destroyed.
Fig. 5 Stack registers (SKs) structure
(SP) ← 0
(SK0) ← 000116
(PC) ← SUB1
Main program
Subroutine
Address
(7) Skip flag
Skip flag controls skip decision for the conditional skip instructions
and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt
stack register (SDP) and the skip condition is retained.
SUB1 :
000016 NOP
NOP
·
·
·
RT
000116 BM SUB1
000216 NOP
(PC) ← (SK0)
(SP) ← 7
Note : Returning to the BM instruction execution
address with the RT instruction, and the BM
instruction becomes the NOP instruction.
Fig. 6 Example of operation at subroutine call
Rev.1.01
Sep 17, 2003
page 17 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
(8) Program counter (PC)
Program counter (PC) is used to specify a ROM address (page and
address). It determines a sequence in which instructions stored in
ROM are read. It is a binary counter that increments the number of
instruction bytes each time an instruction is executed. However,
the value changes to a specified address when branch instructions,
subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed.
Program counter consists of PC H (most significant bit to bit 7)
which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address
(address 127) of a page, it specifies address 0 of the next page
(Figure 7).
Make sure that the PCH does not specify after the last page of the
built-in ROM.
Program counter
p6 p5 p4 p3 p2 p1 p0
a6 a5 a4 a3 a2 a1 a0
PCH
Specifying page
PCL
Specifying address
Fig. 7 Program counter (PC) structure
Data pointer (DP)
Z 1 Z 0 X3 X2 X1 X0 Y3 Y2 Y1 Y 0
(9) Data pointer (DP)
Data pointer (DP) is used to specify a RAM address and consists
of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure
8).
Register Y is also used to specify the port D bit position.
When using port D, set the port D bit position to register Y certainly
and execute the SD, RD, or SZD instruction (Figure 9).
• Note
Register Z of data pointer is undefined after system is released
from reset.
Also, registers Z, X and Y are undefined in the RAM back-up. After
system is returned from the RAM back-up, set these registers.
Specifying
RAM digit
Register Y (4)
Register X (4)
Register Z (2)
Specifying RAM file
Specifying RAM file group
Fig. 8 Data pointer (DP) structure
Specifying bit position
Set
D3
0
0
0
D2
1
Register Y (4)
Sep 17, 2003
page 18 of 130
D0
1
Port D output latch
Fig. 9 SD instruction execution example
Rev.1.01
D1
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
PROGRAM MEMORY (ROM)
The program memory is a mask ROM. 1 word of ROM is composed
of 10 bits. ROM is separated every 128 words by the unit of page
(addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 10 shows the ROM map of M34556ED.
Table 1 ROM size and pages
Part number
M34556M4
M34556M4H
M34556M8
M34556M8H
M34556G8
M34556G8H
ROM (PROM) size
(✕ 10 bits)
4096 words
32 (0 to 31)
8192 words
64 (0 to 63)
Pages
9 8 7 6 5 4 3 2 1 0
000016
007F16
008016
00FF16
010016
017F16
018016
Page 0
Interrupt address page
Page 1
Subroutine special page
Page 2
Page 3
Page 63
1FFF16
A part of page 1 (addresses 008016 to 00FF16) is reserved for interrupt addresses (Figure 11). When an interrupt occurs, the
address (interrupt address) corresponding to each interrupt is set
in the program counter, and the instruction at the interrupt address
is executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt
address.
Page 2 (addresses 010016 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from
any page with the 1-word instruction (BM). Subroutines extending
from page 2 to another page can also be called with the BM instruction when it starts on page 2.
ROM pattern (bits 7 to 0) of all addresses can be used as data areas with the TABP p instruction.
Fig. 10 ROM map of M34556M8/M8H/G8/G8H
9
008016
8 7 6 5 4 3 2 1 0
External 0 interrupt address
008216
008416
Timer 1 interrupt address
008616
Timer 2 interrupt address
008816
Timer 3 interrupt address
008A16
008C16
008E16
00FF16
Fig. 11 Page 1 (addresses 008016 to 00FF16) structure
Rev.1.01
Sep 17, 2003
page 19 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
DATA MEMORY (RAM)
Table 2 RAM size
1 word of RAM is composed of 4 bits, but 1-bit manipulation (with
the SB j, RB j, and SZB j instructions) is enabled for the entire
memory area. A RAM address is specified by a data pointer. The
data pointer consists of registers Z, X, and Y. Set a value to the
data pointer certainly when executing an instruction to access
RAM (also, set a value after system returns from RAM back-up).
RAM includes the area for LCD.
When writing “1” to a bit corresponding to displayed segment, the
segment is turned on.
Table 2 shows the RAM size. Figure 12 shows the RAM map.
Part number
M34556M4/M4H
M34556M8/M8H
M34556G8/G8H
RAM size
288 words ✕ 4 bits (1152 bits)
• Note
Register Z of data pointer is undefined after system is released
from reset.
Also, registers Z, X and Y are undefined in the RAM back-up. After
system is returned from the RAM back-up, set these registers.
RAM 288 words ✕ 4 bits (1152 bits)
Register Z
Register X
0
1 2
0
1
3 ... 12 13 14 15 0 1 2 3
Register Y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0 8
1 9
2 10
3
4
5
6
7
24
17 25
18 26
19 27
20 28
21
22
23
Note: The numbers in the shaded area indicate the corresponding segment output pin numbers.
Fig. 12 RAM map
Rev.1.01
Sep 17, 2003
page 20 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an individual
address (interrupt address) according to each interrupt source. An
interrupt occurs when the following 3 conditions are satisfied.
• An interrupt activated condition is satisfied (request flag = “1”)
• Interrupt enable bit is enabled (“1”)
• Interrupt enable flag is enabled (INTE = “1”)
Table 3 shows interrupt sources. (Refer to each interrupt request
flag for details of activated conditions.)
Table 3 Interrupt sources
Priority
Interrupt name
Activated condition
level
1
External 0 interrupt Level change of INT
pin
2
Timer 1 interrupt
Timer 1 underflow
3
Timer 2 interrupt
Timer 2 underflow
4
Timer 3 interrupt
Timer 3 underflow
Interrupt
address
Address 0
in page 1
Address 4
in page 1
Address 6
in page 1
Address 8
in page 1
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to
“1” with the EI instruction and disabled when INTE flag is cleared to
“0” with the DI instruction. When any interrupt occurs, the INTE flag
is automatically cleared to “0,” so that other interrupts are disabled
until the EI instruction is executed.
(2) Interrupt enable bit
Use an interrupt enable bit of interrupt control registers V1 and V2
to select the corresponding interrupt or skip instruction.
Table 4 shows the interrupt request flag, interrupt enable bit and
skip instruction.
Table 5 shows the interrupt enable bit function.
(3) Interrupt request flag
When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to “1.” Each interrupt
request flag is cleared to “0” when either;
• an interrupt occurs, or
• the next instruction is skipped with a skip instruction.
Each interrupt request flag is set when the activated condition is
satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set
until a clear condition is satisfied.
Accordingly, an interrupt occurs when the interrupt disable state is
released while the interrupt request flag is set.
If more than one interrupt request flag is set when the interrupt disable state is released, the interrupt priority level is as follows
shown in Table 3.
Rev.1.01
Sep 17, 2003
page 21 of 130
Table 4 Interrupt request flag, interrupt enable bit and skip instruction
Interrupt name
External 0 interrupt
Timer 1 interrupt
Timer 2 interrupt
Timer 3 interrupt
Request flag
EXF0
T1F
T2F
T3F
Skip instruction
SNZ0
SNZT1
SNZT2
SNZT3
Enable bit
V10
V12
V13
V20
Table 5 Interrupt enable bit function
Interrupt enable bit
1
0
Occurrence of interrupt
Enabled
Disabled
Skip instruction
Invalid
Valid
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is as follows (Figure 14).
• Program counter (PC)
An interrupt address is set in program counter. The address to be
executed when returning to the main routine is automatically
stored in the stack register (SK).
• Interrupt enable flag (INTE)
INTE flag is cleared to “0” so that interrupts are disabled.
• Interrupt request flag
Only the request flag for the current interrupt source is cleared to
“0.”
• Data pointer, carry flag, skip flag, registers A and B
The contents of these registers and flags are stored automatically
in the interrupt stack register (SDP).
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address is executed after branching a data store sequence to stack register.
Write the branch instruction to an interrupt service routine at an interrupt address.
Use the RTI instruction to return from an interrupt service routine.
Interrupt enabled by executing the EI instruction is performed after
executing 1 instruction (just after the next instruction is executed).
Accordingly, when the EI instruction is executed just before the RTI
instruction, interrupts are enabled after returning the main routine.
(Refer to Figure 13)
Main
routine
Interrupt
service routine
Interrupt
occurs
Interrupt is
enabled
: Interrupt enabled state
: Interrupt disabled state
Fig. 13 Program example of interrupt processing
Sep 17, 2003
• Stack register (SK)
The address of main routine to be
....................................................................................................
executed when returning
• Interrupt enable flag (INTE)
.................................................................. 0 (Interrupt disabled)
• Interrupt request flag (only the flag for the current interrupt
source) ................................................................................... 0
• Data pointer, carry flag, registers A and B, skip flag
........ Stored in the interrupt stack register (SDP) automatically
Fig. 14 Internal state when interrupt occurs
Activated
condition
INT pin interrupt
waveform input
Request flag Enable bit
(state retained)
page 22 of 130
Enable flag
EXF0
V10
Address 0
in page 1
T1F
V12
Address 4
in page 1
Timer 2
underflow
T2F
V13
Address 6
in page 1
Timer 3
underflow
T3F
V20
Timer 1
underflow
Fig. 15 Interrupt system diagram
•
•
•
•
EI
R TI
Rev.1.01
• Program counter (PC)
............................................................... Each interrupt address
INTE
Address 8
in page 1
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
(6) Interrupt control registers
• Interrupt control register V1
Interrupt enable bits of external 0, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through
register A with the TV1A instruction. The TAV1 instruction can be
used to transfer the contents of register V1 to register A.
• Interrupt control register V2
The timer 3 interrupt enable bit is assigned to register V2. Set the
contents of this register through register A with the TV2A instruction. The TAV2 instruction can be used to transfer the contents of
register V2 to register A.
Table 6 Interrupt control registers
Interrupt control register V1
V13
Timer 2 interrupt enable bit
V12
Timer 1 interrupt enable bit
V11
Not used
V10
External 0 interrupt enable bit
at reset : 00002
0
1
0
1
0
1
0
1
Interrupt control register V2
V23
Not used
V22
Not used
V21
Not used
V20
Timer 3 interrupt enable bit
Note: “R” represents read enabled, and “W” represents write enabled.
Rev.1.01
Sep 17, 2003
page 23 of 130
R/W
TAV1/TV1A
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
at reset : 00002
0
1
0
1
0
1
0
1
at power down : 00002
at power down : 00002
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid)
R/W
TAV2/TV2A
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt enable bits (V10, V12, V13, V20), and interrupt request flag are “1.”
The interrupt actually occurs 2 to 3 machine cycles after the cycle
in which all three conditions are satisfied. The interrupt occurs after
3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle instructions (Refer to
Figure 16).
● When an interrupt request flag is set after its interrupt is enabled (Note 1)
1 machine cycle
T1
T2
T3
T1
T2
T3
T1
T2
T3
T1
T2
T3
T1
T2
System clock
(STCK)
EI instruction execution cycle
Interrupt enable
flag (INTE)
Interrupt disabled state
Interrupt enabled state
Retaining level of system
clock for 4 periods or more
is necessary.
INT
External
interrupt
EXF0
Interrupt activated
condition is satisfied.
Timer 1,
Timer 2,
Timer 3
interrupts
T1F,T2F,T3F
Flag cleared
2 to 3 machine cycles
(Notes 1, 2)
Notes 1: The address is stacked to the last cycle.
2: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.
Fig. 16 Interrupt sequence
Rev.1.01
Sep 17, 2003
page 24 of 130
The program starts
from the interrupt
address.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
EXTERNAL INTERRUPTS
The 4556 Group has the external 0 interrupt.
An external interrupt request occurs when a valid waveform is input
to an interrupt input pin (edge detection).
The external interrupt can be controlled with the interrupt control
register I1.
Table 7 External interrupt activated conditions
Name
Input pin
External 0 interrupt
D5/INT
Valid waveform
selection bit
I11
I12
Activated condition
When the next waveform is input to D5/INT pin
• Falling waveform (“H”→“L”)
• Rising waveform (“L”→“H”)
• Both rising and falling waveforms
I12
Falling
(Note 1)
0
One-sided edge
detection circuit
I11
0
D5/INT
External 0
interrupt
EXF0
1
Rising
I13
Both edges
detection circuit
1
(Note 2)
Level detection circuit
K20
(Note 3)
Edge detection circuit
Timer 1 count start
synchronous circuit
K21
0
Key-on wakeup
1
Skip decision
(SNZI0 instruction)
This symbol represents a parasitic diode on the port.
Notes 1:
2: I12 (I22) = 0: “L” level detected
I12 (I22) = 1: “H” level detected
3: I12 (I22) = 0: Falling edge detected
I12 (I22) = 1: Rising edge detected
Fig. 17 External interrupt circuit structure
Rev.1.01
Sep 17, 2003
page 25 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
(1) External 0 interrupt request flag (EXF0)
(2) External interrupt control registers
External 0 interrupt request flag (EXF0) is set to “1” when a valid
waveform is input to D5/INT pin.
The valid waveforms causing the interrupt must be retained at their
level for 4 clock cycles or more of the system clock (Refer to Figure 16).
The state of EXF0 flag can be examined with the skip instruction
(SNZ0). Use the interrupt control register V1 to select the interrupt
or the skip instruction. The EXF0 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip
instruction.
• Interrupt control register I1
Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the
TI1A instruction. The TAI1 instruction can be used to transfer the
contents of register I1 to register A.
• External 0 interrupt activated condition
External 0 interrupt activated condition is satisfied when a valid
waveform is input to D5/INT pin.
The valid waveform can be selected from rising waveform, falling
waveform or both rising and falling waveforms. An example of
how to use the external 0 interrupt is as follows.
➀ Set the bit 3 of register I1 to “1” for the INT pin to be in the input
enabled state.
➁ Select the valid waveform with the bits 1 and 2 of register I1.
➂ Clear the EXF0 flag to “0” with the SNZ0 instruction.
➃ Set the NOP instruction for the case when a skip is performed
with the SNZ0 instruction.
➄ Set both the external 0 interrupt enable bit (V10) and the INTE
flag to “1.”
The external 0 interrupt is now enabled. Now when a valid waveform is input to the D5/INT pin, the EXF0 flag is set to “1” and the
external 0 interrupt occurs.
Table 8 External interrupt control register
Interrupt control register I1
I13
I12
INT pin input control bit (Note 2)
Interrupt valid waveform for INT pin/
return level selection bit (Note 2)
I11
INT pin edge detection circuit control bit
I10
INT pin Timer 1 count start synchronous
circuit selection bit
at reset : 00002
0
1
0
1
0
1
0
1
at power down : state retained
INT pin input disabled
INT pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI0
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI0
instruction)
One-sided edge detected
Both edges detected
Timer 1 count start synchronous circuit not selected
Timer 1 count start synchronous circuit selected
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of these bits (I12 , I13) are changed, the external interrupt request flag (EXF0) may be set.
Rev.1.01
Sep 17, 2003
page 26 of 130
R/W
TAI1/TI1A
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
(3) Notes on External 0 interrupts
➂ Note on bit 2 of register I1
When the interrupt valid waveform of the D5/INT pin is changed
with the bit 2 of register I1 in software, be careful about the following notes.
• Depending on the input state of the D5/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 18➀)
and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag
to “0” after executing at least one instruction (refer to Figure 18➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 18➂).
• Depending on the input state of the D5/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 20➀)
and then, change the bit 2 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag
to “0” after executing at least one instruction (refer to Figure 20➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 20➂).
•••
•••
➀ Note [1] on bit 3 of register I1
When the input of the INT pin is controlled with the bit 3 of register I1 in software, be careful about the following notes.
LA
4
TV1A
LA
8
TI1A
NOP
SNZ0
LA
4
TV1A
LA
12
TI1A
NOP
SNZ0
; Interrupt valid waveform is changed
........................................................... ➁
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... ➂
•••
NOP
; (✕✕✕02)
; The SNZ0 instruction is valid ........... ➀
•••
NOP
; (✕✕✕02)
; The SNZ0 instruction is valid ........... ➀
; (1✕✕✕2)
; Control of INT pin input is changed
........................................................... ➁
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... ➂
✕ : these bits are not used here.
✕ : these bits are not used here.
Fig. 18 External 0 interrupt program example-1
➁ Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared to “0”, the RAM back-up
mode is selected and the input of INT pin is disabled, be careful
about the following notes.
•••
• When the key-on wakeup function of INT pin is not used (register
K20 = “0”), clear bits 2 and 3 of register I1 before system enters
to the RAM back-up mode. (refer to Figure 19➀).
; (00✕✕2)
; Input of INT disabled ........................ ➀
; RAM back-up
•••
LA
0
TI1A
DI
EPOF
POF2
✕ : these bits are not used here.
Fig. 19 External 0 interrupt program example-2
Rev.1.01
Sep 17, 2003
page 27 of 130
Fig. 20 External 0 interrupt program example-3
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
TIMERS
• Fixed dividing frequency timer
The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to “1” after every n
count of a count pulse.
The 4556 Group has the following timers.
• Programmable timer
The programmable timer has a reload register and enables the
frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt
request flag is set to “1,” new data is loaded from the reload register, and count continues (auto-reload function).
FF16
n : Counter initial value
Count starts
Reload
Reload
The contents of counter
n
1st underflow
2nd underflow
0016
Time
n+1 count
n+1 count
Timer interrupt “1”
“0”
request flag
An interrupt occurs or
a skip instruction is executed.
Fig. 21 Auto-reload function
The 4556 Group timer consists of the following circuits.
• Prescaler : 8-bit programmable timer
• Timer 1 : 8-bit programmable timer
• Timer 2 : 8-bit programmable timer
• Timer 3 : 16-bit fixed dividing frequency timer
• Timer LC : 4-bit programmable timer
• Watchdog timer : 16-bit fixed dividing frequency timer
(Timers 1, 2, and 3 have the interrupt function, respectively)
Prescaler and timers 1, 2, 3 and LC can be controlled with the
timer control registers PA, W1 to W4. The watchdog timer is a free
counter which is not controlled with the control register.
Each function is described below.
Rev.1.01
Sep 17, 2003
page 28 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
Table 9 Function related timers
Prescaler
8-bit programmable
• Instruction clock (INSTCK)
Frequency
dividing ratio
1 to 256
Timer 1
binary down counter
8-bit programmable
• PWM output (PWMOUT)
1 to 256
Circuit
Count source
Structure
binary down counter
(link to INT input)
• Prescaler output (ORCLK)
• Timer 3 underflow
Use of output signal
• Timer 1, 2, 3 and LC count sources
• CNTR output control
Control
register
PA
W1
• Timer 1 interrupt
(T3UDF)
• CNTR input
Timer 2
8-bit programmable
binary down counter
(PWM output function)
Timer 3
16-bit fixed dividing
• XIN input
1 to 256
• Prescaler output (ORCLK)
divided by 2
• XCIN input
frequency
• Timer 1 count source
W2
• CNTR output
• Timer 2 interrupt
8192
• Timer 1 count source
16384
32768
• Timer 3 interrupt
W3
65536
Timer LC
4-bit programmable
• Bit 4 of timer 3
1 to 16
• LCD clock
binary down counter
• System clock (STCK)
• Instruction clock (INSTCK)
65534
• System reset (count twice)
Watchdog
16-bit fixed dividing
timer
frequency
Rev.1.01
Sep 17, 2003
• WDF flag decision
page 29 of 130
W4
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MR3, MR2
11
Division circuit
Divided by 8
Multiplexer
RC oscillation
(CRCK)
Divided by 2
00
01
10
Internal clock
generating circuit
(divided by 3)
01
MR1, MR0
Ceramic resonance
XIN
10
Divided by 4
Ring oscillator
System clock (STCK)
00
Instruction clock
(INSTCK)
Quartz-crystal oscillation
XCIN
Prescaler (8)
PA0
ORCLK
Reload register RPS (8)
(TPSAB)
(TABPS)
Register B
I12
D5/INT
I10
1
0
S Q
I13
1
(TABPS)
Register A
I11
One-sided edge
detection circuit
0
(TPSAB)
(TPSAB)
1
Both edges
detection circuit
0
R
I10
W13
T1UDF
W11, W10
00
PWMOUT
01
ORCLK
Reload register R1 (8)
10
T3UDF
C/CNTR
Timer 1
interrupt
T1F
Timer 1 (8)
(T1AB)
11
(TAB1)
0
(T1AB)
(T1AB)
Register B Register A
(TAB1)
Timer 1 underflow signal
(T1UDF)
W12
1
W40
Port C output
PWMOUT
W12
W10 W11
Q
D
R
T
T1UDF
W41
Register B Register A
(T2HAB)
W20
ORCLK
Reload control circuit
Timer 2 (8)
1
1/2
W21
“H” interval expansion
(T2R2L)
(T2AB)
Sep 17, 2003
(T2AB)
Register B Register A
Fig. 22 Timer structure (1)
Rev.1.01
(T2AB)
page 30 of 130
W22
(TAB2)
R
1
T2F
0
Reload register R2L (8)
(TAB2)
Q
PWMOD
Reload register R2H (8)
0
XIN
T
W23
Timer 2
interrupt
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
XCIN
ORCLK
W33
0
Timer 3 (16)
1
1 - - 4 - - - - - - - - 13 14 15 16
W32
W31, W30
11
10
01
Timer 3
interrupt
T3F
00
Timer 3 underflow signal (T3UDF)
W42
0
STCK
Timer LC (4)
1
W43
1/2
LCD
clock
Reload register RLC (4)
(TLCA)
(TLCA)
Register A
INSTCK
Watchdog timer
1 - - - - - - - - - - - - - - 16
S
Q
WDF1
WRST instruction
R
RESET signal
S
Q
WEF
DWDT instruction R
+
WRST instruction
Fig. 23 Timer structure (2)
Rev.1.01
Sep 17, 2003
page 31 of 130
D
Q
T
R
Watchdog reset signal
RESET signal
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
Table 10 Timer related registers
Timer control register PA
PA0
Prescaler control bit
Timer 1 count auto-stop circuit selection
bit (Note 2)
W12
Timer 1 control bit
W11
W10
Timer 1 count source selection bits
(Note 3)
at reset : 00002
CNTR pin output control bit
W22
PWM signal interrupt valid waveform/
return level selection bit
W21
Timer 2 control bit
W20
Timer 2 count soruce selection bit
Timer 3 count auto-stop circuit selection
bit
W32
Timer 3 control bit
W31
Timer 3 count source selection bits
W30
Timer LC control bit
W42
Timer LC count source selection bit
W41
CNTR output auto-control circuit
selection bit
W40
CNTR pin input count edge selection bit
at power down : 00002
at reset : 00002
Prescaler output (ORCLK)/2 signal output
at reset : 00002
0
1
0
1
at power down : state retained
Count source
Underflow occurs every 8192 counts
Underflow occurs every 16384 counts
Underflow occurs every 32768 counts
Underflow occurs every 65536 counts
at reset : 00002
at power down : state retained
Stop (state retained)
Operating
Bit 4 (T34) of timer 3
System clock (STCK)
CNTR output auto-control circuit not selected
CNTR output auto-control circuit selected
Falling edge
Rising edge
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”).
3: Port C output is invalid when CNTR input is selected for the timer 1 count source.
Rev.1.01
Sep 17, 2003
page 32 of 130
R/W
TAW3/TW3A
XCIN input
Prescaler output (ORCLK)
Stop (Initial state)
Operating
W31 W30
0
0
0
1
1
0
1
1
0
1
0
1
0
1
0
1
R/W
TAW2/TW2A
CNTR pin output invalid
CNTR pin output valid
PWM signal “H” interval expansion function invalid
PWM signal “H” interval expansion function valid
Stop (state retained)
Operating
XIN input
0
1
0
1
0
1
0
1
Timer control register W4
W43
R/W
TAW1/TW1A
Timer 1 count auto-stop circuit not selected
Timer 1 count auto-stop circuit selected
Stop (state retained)
Operating
W11 W10
Count source
0
PWM signal (PWMOUT)
0
0
Prescaler output (ORCLK)
1
1
Timer 3 underflow signal (T3UDF)
0
1
CNTR input
1
Timer control register W3
W33
at power down : state retained
0
1
0
1
Timer control register W2
W23
W
TPAA
Stop (state initialized)
Operating
0
1
Timer control register W1
W13
at power down : 02
at reset : 02
R/W
TAW4/TW4A
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
(1) Timer control registers
(2) Prescaler (interrupt function)
• Timer control register PA
Register PA controls the count operation of prescaler. Set the
contents of this register through register A with the TPAA instruction.
• Timer control register W1
Register W1 controls the selection of timer 1 count auto-stop circuit, and the count operation and count source of timer 1. Set the
contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents
of register W1 to register A.
• Timer control register W2
Register W2 controls the CNTR output, the expansion of “H” interval of PWM output, and the count operation and count source
of timer 2. Set the contents of this register through register A with
the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A.
• Timer control register W3
Register W3 controls the count operation and count source of
timer 3. Set the contents of this register through register A with
the TW5A instruction. The TAW3 instruction can be used to transfer the contents of register W3 to register A.
• Timer control register W4
Register W4 controls the operation and count source of timer LC,
the selection of CNTR output auto-control circuit and the count
edge of CNTR input. Set the contents of this register through register A with the TW4A instruction. The TAW4 instruction can be
used to transfer the contents of register W4 to register A..
Prescaler is an 8-bit binary down counter with the prescaler reload
register PRS. Data can be set simultaneously in prescaler and the
reload register RPS with the TPSAB instruction. Data can be read
from reload register RPS with the TABPS instruction.
Stop counting and then execute the TPSAB or TABPS instruction
to read or set prescaler data.
Prescaler starts counting after the following process;
➀ set data in prescaler, and
➁ set the bit 0 of register PA to “1.”
When a value set in reload register RPS is n, prescaler divides the
count source signal by n + 1 (n = 0 to 255).
Count source for prescaler is the instruction clock (INSTCK).
Once count is started, when prescaler underflows (the next count
pulse is input after the contents of prescaler becomes “0”), new
data is loaded from reload register RPS, and count continues
(auto-reload function).
The output signal (ORCLK) of prescaler can be used for timer 1, 2,
3 and LC count sources.
(3) Timer 1 (interrupt function)
Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). Data can be set simultaneously in timer 1 and the reload
register (R1) with the T1AB instruction. Data can be written to reload register (R1) with the TR1AB instruction. Data can be read
from timer 1 with the TAB1 instruction.
Stop counting and then execute the T1AB or TAB1 instruction to
read or set timer 1 data.
When executing the TR1AB instruction to set data to reload register R1 while timer 1 is operating, avoid a timing when timer 1
underflows.
Timer 1 starts counting after the following process;
➀ set data in timer 1
➁ set count source by bits 0 and 1 of register W1, and
➂ set the bit 2 of register W1 to “1.”
When a value set in reload register R1 is n, timer 1 divides the
count source signal by n + 1 (n = 0 to 255).
Once count is started, when timer 1 underflows (the next count
pulse is input after the contents of timer 1 becomes “0”), the timer
1 interrupt request flag (T1F) is set to “1,” new data is loaded from
reload register R1, and count continues (auto-reload function).
INT pin input can be used as the start trigger for timer 1 count operation by setting the bit 0 of register I1 to “1.”
Also, in this time, the auto-stop function by timer 1 underflow can
be performed by setting the bit 3 of register W1 to “1.”
Rev.1.01
Sep 17, 2003
page 33 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
(4) Timer 2 (interrupt function)
(5) Timer 3 (interrupt function)
Timer 2 is an 8-bit binary down counter with two timer 2 reload registers (R2L, R2H). Data can be set simultaneously in timer 2 and
the reload register R2L with the T2AB instruction. Data can be set
in the reload register R2H with the T2HAB instruction. The contents
of reload register R2L set with the T2AB instruction can be set to
timer 2 again with the T2R2L instruction. Data can be read from
timer 2 with the TAB2 instruction.
Stop counting and then execute the T2AB or TAB2 instruction to
read or set timer 2 data.
When executing the T2HAB instruction to set data to reload register R2H while timer 2 is operating, avoid a timing when timer 2
underflows.
Timer 2 starts counting after the following process;
➀ set data in timer 2
➁ set count source by bit 0 of register W2, and
➂ set the bit 1 of register W2 to “1.”
Timer 3 is a 16-bit binary down counter.
Timer 3 starts counting after the following process;
➀ set count value by bits 0 and 1 of register W3,
➁ set count source by bit 3 of register W3, and
➂ set the bit 2 of register W3 to “1.”
Once count is started, when timer 3 underflows (the set count
value is counted), the timer 3 interrupt request flag (T3F) is set to
“1,” and count continues.
Bit 4 of timer 3 can be used as the timer LC count source for the
LCD clock generating.
When bit 2 of register W3 is cleared to “0”, timer 3 is initialized to
“FFFF16” and count is stopped.
Timer 3 can be used as the counter for clock because it can be operated at clock operating mode (POF instruction execution). When
timer 3 underflow occurs at clock operating mode, system returns
from the power down state.
When a value set in reload register R2L is n, timer 2 divides the
count source signal by n + 1 (n = 0 to 255).
Once count is started, when timer 2 underflows (the next count
pulse is input after the contents of timer 2 becomes “0”), the timer
2 interrupt request flag (T2F) is set to “1,” new data is loaded from
reload register R2L, and count continues (auto-reload function).
When bit 3 of register W2 is set to “1”, timer 2 reloads data from reload register R2L and R2H alternately each underflow.
Timer 2 generates the PWM signal (PWMOUT) of the “L” interval
set as reload register R2L, and the “H” interval set as reload register R2H. The PWM signal (PWMOUT) is output from CNTR pin.
When bit 2 of register W2 is set to “1” at this time, the interval
(PWM signal “H” interval) set to reload register R2H for the counter
of timer 2 is extended for a half period of count source.
In this case, when a value set in reload register R2H is n, timer 2
divides the count source signal by n + 1.5 (n = 1 to 255).
When this function is used, set “1” or more to reload register R2H.
When bit 1 of register W4 is set to “1”, the PWM signal output to
CNTR pin is switched to valid/invalid each timer 1 underflow. However, when timer 1 is stopped (bit 2 of register W1 is cleared to “0”),
this function is canceled.
Even when bit 1 of a register W2 is cleared to “0” in the “H” interval
of PWM signal, timer 2 does not stop until it next timer 2 underflow.
When clearing bit 1 of register W2 to “0” to stop timer 2, avoid a
timing when timer 2 underflows.
(6) Timer LC
Rev.1.01
Sep 17, 2003
page 34 of 130
Timer LC is a 4-bit binary down counter with the timer LC reload
register (RLC). Data can be set simultaneously in timer LC and the
reload register (RLC) with the TLCA instruction. Data cannot be
read from timer LC. Stop counting and then execute the TLCA instruction to set timer LC data.
Timer LC starts counting after the following process;
➀ set data in timer LC,
➁ select the count source with the bit 2 of register W4, and
➂ set the bit 3 of register W4 to “1.”
When a value set in reload register RLC is n, timer LC divides the
count source signal by n + 1 (n = 0 to 15).
Once count is started, when timer LC underflows (the next count
pulse is input after the contents of timer LC becomes “0”), new data
is loaded from reload register RLC, and count continues (auto-reload function).
Timer LC underflow signal divided by 2 can be used for the LCD
clock.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
(7) Timer input/output pin
(C/CNTR pin)
CNTR pin is used to input the timer 1 count source and output the
PWM signal generated by timer 2. When the PWM signal is output
from C/CNTR pin, set “0” to the output latch of port C.
The selection of CNTR output signal can be controlled by bit 3 of
register W2.
When the CNTR input is selected for timer 1 count source, timer 1
counts the waveform of CNTR input selected by bit 0 of register
W4. Also, when the CNTR input is selected, the output of port C is
invalid (high-impedance state).
(10) Count auto-stop circuit (timer 1)
Timer 1 has the count auto-stop circuit which is used to stop timer
1 automatically by the timer 1 underflow when the count start synchronous circuit is used.
The count auto-stop cicuit is valid by setting the bit 3 of register W1
to “1”. It is cleared by the timer 1 underflow and the count source to
timer 1 is stopped.
This function is valid only when the timer 1 count start synchronous
circuit is selected.
(11) Precautions
Note the following for the use of timers.
(8) Timer interrupt request flags (T1F, T2F, T3F)
Each timer interrupt request flag is set to “1” when each timer
underflows. The state of these flags can be examined with the skip
instructions (SNZT1, SNZT2, SNZT3).
Use the interrupt control register V1, V2 to select an interrupt or a
skip instruction.
An interrupt request flag is cleared to “0” when an interrupt occurs
or when the next instruction is skipped with a skip instruction.
• Prescaler
Stop counting and then execute the TABPS instruction to read
from prescaler data.
Stop counting and then execute the TPSAB instruction to set
prescaler data.
• Timer count source
Stop timer 1, 2, and LC counting to change its count source.
(9) Count start synchronization circuit (timer 1)
Timer 1 has the count start synchronous circuit which synchronizes
the input of INT pin, and can start the timer count operation.
Timer 1 count start synchronous circuit function is selected by setting the bit 0 of register I1 to “1” and the control by INT pin input
can be performed.
When timer 1 count start synchronous circuit is used, the count
start synchronous circuit is set, the count source is input to each
timer by inputting valid waveform to INT pin.
The valid waveform of INT pin to set the count start synchronous
circuit is the same as the external interrupt activated condition.
Once set, the count start synchronous circuit is cleared by clearing
the bit I10 to “0” or reset.
However, when the count auto-stop circuit is selected, the count
start synchronous circuit is cleared (auto-stop) at the timer 1 underflow.
• Reading the count value
Stop timer 1 or 2 counting and then execute the data read instruction (TAB1, TAB2) to read its data.
• Writing to the timer
Stop timer 1, 2 or LC counting and then execute the data write instruction (T1AB, T2AB, TLCA) to write its data.
• Writing to reload register R1, R2H
When writing data to reload register R1 or reload regiser R2H
while timer 1 or timer 2 is operating, avoid a timing when timer 1
or timer 2 underflows.
• Timer 2
Avoid a timing when timer 2 underflows to stop timer 2 at PWM
output function used.
When “H” interval extension function of the PWM signal is set to
be “valid”, set “1” or more to reload register R2H.
• Timer 3
Stop timer 3 counting to change its count source.
• Timer input/output pin
Set the port C output latch to “0” to output the PWM signal from
C/CNTR pin.
Rev.1.01
Sep 17, 2003
page 35 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
● CNTR output: invalid (W23 = “0”)
Timer 2 count source
Timer 2 count value
(Reload
register)
0316
0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016
(R2L)
(R2L)
(R2L)
(R2L)
(R2L)
Timer 2 underflow signal
PWM signal (output invalid)
PWM signal “L”
fixed
Timer 2 start
● CNTR output: valid (W23 = “1”)
PWM signal “H” interval extension function: invalid (W22 = “0”)
Timer 2 count source
Timer 2 count value
(Reload
register)
0316
0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116
(R2L)
(R2H)
(R2L)
(R2H)
(R2L)
(R2H)
Timer 2 underflow signal
PWM
signal
3 clock
3 clock
PWM period 7 clock
PWM period 7 clock
Timer 2 start
● CNTR output: valid (W23 = “1”)
PWM signal “H” interval extension function: valid (W22 = “1”) (Note)
Timer 2 count source
Timer 2 count value
(Reload
register)
0316
0216 0116 0016
0216
0116 0016 0316 0216 0116 0016
0216
0116 0016 0316 0216 0116 0016 0216
(R2L)
(R2H)
(R2L)
(R2H)
(R2L)
Timer 2 underflow signal
3.5 clock
PWM
signal
Timer 2 start
PWM period 7.5 clock
Note: At PWM signal “H” interval extension function: valid, set “0116” or more to reload register R2H.
Fig. 24 Timer 2 operation (reload register R2L: “0316”, R2H: “0216”)
Rev.1.01
Sep 17, 2003
page 36 of 130
3.5 clock
PWM period 7.5 clock
(R2H)
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
CNTR output auto-control circuit by timer 1 is selected.
● CNTR output: valid (W23 = “1”)
CNTR output auto-control circuit selected (W41 = “1”)
PWM
signal
Timer 1 underflow signal
Timer 1 start
CNTR output
CNTR output start
● CNTR output auto-control function
PWM
signal
Timer 1 underflow signal
Timer 1 start
➀
➁
Timer 1
stop
➂
Register W41
CNTR output
CNTR output start
➀
➁
➂
When the CNTR output auto-control function is set to be invalid while the CNTR output is invalid,
the CNTR output invalid state is retained.
When the CNTR output auto-control function is set to be invalid while the CNTR output is valid,
the CNTR output valid state is retained.
When timer 1 is stopped, the CNTR output auto-control function becomes invalid.
Note: When the PWM signal is output from C/CNTR pin, set the output latch of port C to “0”.
Fig. 25 CNTR output auto-control function by timer 1
Rev.1.01
Sep 17, 2003
page 37 of 130
CNTR output stop
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
●Waveform extension function of CNTR output “H” interval: Invalid (W22 = “0”),
CNTR output: valid (W23 = “1”),
Count source: XIN input selected (W20 = “0”),
Reload register R2L: “0316”
Reload register R2H: “0216”
Timer 2 count start timing
Machine cycle
Mi
Mi+1
Mi+2
TW2A instruction execution cycle (W21) ← 1
System clock
f(STCK)=f(XIN)/4
XIN input
(count source selected)
Register W21
Timer 2 count value
(Reload register)
0316
0216 0116 0016 0216 0116 0016 0316 0216 0116
(R2L)
(R2H)
(R2L)
Timer 2
underflow signal
PWM signal
Timer 2 count start timing
Timer 2 count stop timing
Machine cycle
Mi
Mi+1
Mi+2
TW2A instruction execution cycle (W21) ← 0
System clock
f(STCK)=f(XIN)/4
XIN input
(count source selected)
Register W21
Timer 2 count value
(Reload register)
0216 0116 0016 0216 0116 0016 0316 0216 0116 0016
(R2H)
(R2L)
0216
(R2H)
Timer 2
underflow signal
(Note 1)
PWM signal
Timer 2 count stop timing
Notes 1: In order to stop timer 2 at CNTR output valid (W23 = “1”), avoid a timing when timer 2 underflows.
If these timings overlap, a hazard may occur in a CNTR output waveform.
2: At CNTR output valid, timer 2 stops after “H” interval of PWM signal set by reload register R2H is output.
Fig. 26 Timer 2 count start/stop timing
Rev.1.01
Sep 17, 2003
page 38 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
WATCHDOG TIMER
Watchdog timer provides a method to reset the system when a program run-away occurs. Watchdog timer consists of timer
WDT(16-bit binary counter), watchdog timer enable flag (WEF),
and watchdog timer flags (WDF1, WDF2).
The timer WDT downcounts the instruction clocks as the count
source from “FFFF16” after system is released from reset.
After the count is started, when the timer WDT underflow occurs
(after the count value of timer WDT reaches “000016,” the next
count pulse is input), the WDF1 flag is set to “1.”
If the WRST instruction is never executed until the timer WDT underflow occurs (until timer WDT counts 65534), WDF2 flag is set to
“1,” and the RESET pin outputs “L” level to reset the microcomputer.
Execute the WRST instruction at each period of 65534 machine
cycle or less by software when using watchdog timer to keep the
microcomputer operating normally.
When the WEF flag is set to “1” after system is released from reset,
the watchdog timer function is valid.
When the DWDT instruction and the WRST instruction are executed continuously, the WEF flag is cleared to “0” and the
watchdog timer function is invalid.
However, in order to set the WEF flag to “1” again once it has
cleared to “0”, execute system reset.
The WRST instruction has the skip function. When the WRST instruction is executed while the WDF1 flag is “1”, the WDF1 flag is
cleared to “0” and the next instruction is skipped.
When the WRST instruction is executed while the WDF1 flag is “0”,
the next instruction is not skipped.
The skip function of the WRST instruction can be used even when
the watchdog timer function is invalid.
FFFF1 6
Value of 16-bit timer (WDT)
000016
➁
WDF1 flag
➁
65534 count
(Note)
➃
WDF2 flag
RESET pin output
➀ Reset
released
➂ WRST instruction
executed
(skip executed)
➄ System reset
➀ After system is released from reset (= after program is started), timer WDT starts count down.
➁ When timer WDT underflow occurs, WDF1 flag is set to “1.”
➂ When the WRST instruction is executed, WDF1 flag is cleared to “0,” the next instruction is skipped.
➃ When timer WDT underflow occurs while WDF1 flag is “1,” WDF2 flag is set to “1” and the
watchdog reset signal is output.
➄ The output transistor of RESET pin is turned “ON” by the watchdog reset signal and system reset is
executed.
Note: The number of count is equal to the number of cycle because the count source of watchdog timer
is the instruction clock.
Fig. 27 Watchdog timer function
Rev.1.01
Sep 17, 2003
page 39 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
; WDF1 flag cleared
•••
WRST
; Watchdog timer function enabled/disabled
; WEF and WDF1 flags cleared
•••
DWDT
WRST
•••
Fig. 28 Program example to start/stop watchdog timer
WRST
; WDF1 flag cleared
NOP
DI
; Interrupt disabled
EPOF
; POF instruction enabled
POF
↓
Oscillation stop
•••
When the watchdog timer is used, clear the WDF1 flag at the period of 65534 machine cycles or less with the WRST instruction.
When the watchdog timer is not used, execute the DWDT instruction and the WRST instruction continuously (refer to Figure 28).
The watchdog timer is not stopped with only the DWDT instruction.
The contents of WDF1 flag and timer WDT are initialized at the
power down mode.
When using the watchdog timer and the power down mode, initialize the WDF1 flag with the WRST instruction just before the
microcomputer enters the power down state (refer to Figure 29).
The watchdog timer function is valid after system is returned from
the power down. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously
every system is returned from the power down, and stop the watchdog timer function.
•••
4556 Group
Fig. 29 Program example to enter the mode when using the
watchdog timer
Rev.1.01
Sep 17, 2003
page 40 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
LCD FUNCTION
(2) LCD clock control
The 4556 Group has an LCD (Liquid Crystal Display) controller/
driver. When the proper voltage is applied to LCD power supply input pins (V LC1–V LC3) and data are set in timer control register
(W4), timer LC, LCD control registers (L1, L2, L3, C1, C2), and
LCD RAM, the LCD controller/driver automatically reads the display data and controls the LCD display by setting duty and bias.
4 common signal output pins and 23 segment signal output pins
can be used to drive the LCD. By using these pins, up to 92 segments (when 1/4 duty and 1/3 bias are selected) can be controlled
to display. The LCD power input pins (VLC1–VLC3) are also used as
pins SEG 0–SEG 2. When SEG 0–SEG2 are selected, the internal
power (VDD) is used for the LCD power.
The LCD clock is determined by the timer LC count source selection bit (W4 2 ), timer LC control bit (W4 3 ), and timer LC.
Accordingly, the frequency (F) of the LCD clock is obtained by the
following formula. Numbers (➀ to ➂) shown below the formula correspond to numbers in Figure 30, respectively.
(1) Duty and bias
• When using the bit 4 of timer 3 as timer LC count source (W42=“0”)
• When using the prescaler output (ORCLK) as timer LC count
source (W42=“1”)
F = ORCLK ✕
1
✕
LC + 1
➀
There are 3 combinations of duty and bias for displaying data on
the LCD. Use bits 0 and 1 of LCD control register (L1) to select the
proper display method for the LCD panel being used.
F = T34
➁
• 1/2 duty, 1/2 bias
• 1/3 duty, 1/3 bias
• 1/4 duty, 1/3 bias
✕
➁
1
2
➂
[LC: 0 to 15]
The frame frequency and frame period for each display method
can be obtained by the following formula:
Table 11 Duty and maximum number of displayed pixels
Duty
1/2
1/3
1/4
➂
1
✕ LC + 1
➀
1
2
F
n
Frame frequency =
Maximum number of displayed pixels
Used COM pins
46 segments
COM0, COM1 (Note)
69 segments
COM0–COM2 (Note)
92 segments
COM0–COM3
n
F
Frame period =
(Hz)
(s)
F: LCD clock frequency
1/n: Duty
Note: Leave unused COM pins open.
(Note)
W43
W42
T34
STCK
0
0
➁
Timer LC
➂
(4 )
1
1
➀
Reload register RLC
( TLCA )
( TLCA )
Register A
Note: Count source is stopped by setting “0” to this bit.
Fig. 30 LCD clock control circuit structure
Rev.1.01
Sep 17, 2003
1/2
page 41 of 130
(4 )
LCD clock
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
SEG0/VLC3
SEG2/VLC1
SEG3 to
SEG17 to
SEG1
/VLC2
COM3
COM1
COM2
COM0
SEG10
SEG28
r
r
SEG0 to SEG2
output
r
.........
r
Multiplexer
r
r
Control
signal
Segment
Bias control
Common driver
driver
Selector
Decoder
...
Segment
driver
... Selector
...
RAM
RAM
LCD clock
(from timer block)
1/2,1/3,1/4 counter
LCD ON/
OFF
control
L23 L22 L21 L20
L13 L12 L11 L10
Register A
Fig. 31 LCD controller/driver
(3) LCD RAM
(4) LCD drive waveform
RAM contains areas corresponding to the liquid crystal display.
When “1” is written to this LCD RAM, the display pixel corresponding to the bit is automatically displayed.
When “1” is written to a bit in the LCD RAM data, the voltage difference between common pin and segment pin which correspond to
the bit automatically becomes lVLC3l and the display pixel at the
cross section turns on.
When returning from reset, and in the RAM back-up mode, a display pixel turns off because every segment output pin and
common output pin becomes VLC3 level.
Z
X
1
Bits
Y
1
0
3
2
1
0
2
3
2
1
0
3
2
1
0
3
2
1
0
8
9
10
SEG0 SEG0 SEG0 SEG0 SEG8 SEG8 SEG8 SEG8
SEG24 SEG24 SEG24 SEG24
SEG1 SEG1 SEG1 SEG1 SEG9 SEG9 SEG9 SEG9 SEG17 SEG17 SEG17 SEG17 SEG25 SEG25 SEG25 SEG25
SEG2 SEG2 SEG2 SEG2 SEG10 SEG10 SEG10 SEG10 SEG18 SEG18 SEG18 SEG18 SEG26 SEG26 SEG26 SEG26
11
12
13
SEG3 SEG3 SEG3 SEG3
SEG4 SEG4 SEG4 SEG4
SEG5 SEG5 SEG5 SEG5
14
15
COM
SEG19
SEG20
SEG21
SEG22
SEG19 SEG19
SEG20 SEG20
SEG21 SEG21
SEG22 SEG22
SEG19 SEG27 SEG27 SEG27 SEG27
SEG20 SEG28 SEG28 SEG28 SEG28
SEG21
SEG22
SEG6 SEG6 SEG6 SEG6
SEG7 SEG7 SEG7 SEG7
SEG23 SEG23 SEG23 SEG23
COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
Note: The area marked “
” is not the LCD display RAM.
Fig. 32 LCD RAM map
Rev.1.01
3
Sep 17, 2003
page 42 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
Table 12 LCD control registers (1)
at reset : 00002
LCD control register L1
L13
Internal dividing resistor for LCD power
supply selection bit (Note 2)
L12
LCD control bit
L11
LCD duty and bias selection bits
L10
SEG0/VLC3 pin function switch bit (Note 3)
L22
SEG1/VLC2 pin function switch bit (Note 4)
L21
SEG2/VLC1 pin function switch bit (Note 4)
L20
Internal dividing resistor for LCD power
supply control bit
P23/SEG20 pin function switch bit
L32
P22/SEG19 pin function switch bit
L31
P21/SEG18 pin function switch bit
L30
P20/SEG17 pin function switch bit
1/2
1/3
1/4
Sep 17, 2003
page 43 of 130
at power down : state retained
W
TL2A
VLC3
SEG1
VLC2
SEG2
VLC1
Internal dividing resistor valid
Internal dividing resistor invalid
SEG20
P23
SEG19
P22
SEG18
P21
SEG17
P20
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: “r (resistor) multiplied by 3” is used at 1/3 bias, and “r multiplied by 2” is used at 1/2 bias.
3: VLC3 is connected to VDD internally when SEG0 pin is selected.
4: Use internal dividing resistor when SEG1 and SEG 2 pins are selected.
Rev.1.01
1/2
1/3
1/3
SEG0
at reset : 11112
0
1
0
1
0
1
0
1
Bias
Not available
at reset : 00002
LCD control register L3
L33
Duty
L11 L10
0
0
0
1
1
0
1
1
0
1
0
1
0
1
0
1
R/W
TAL1/TL1A
2r ✕ 3, 2r ✕ 2
r ✕ 3, r ✕ 2
Stop
Operating
0
1
0
1
LCD control register L2
L23
at power down : state retained
at power down : state retained
W
TL3A
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
Table 12 LCD control registers (2)
at reset : 11112
LCD control register C1
C13
P03/SEG24 pin function switch bit
C12
P02/SEG23 pin function switch bit
C11
P01/SEG22 pin function switch bit
C10
P00/SEG21 pin function switch bit
0
1
0
1
0
1
0
1
C23
P13/SEG28 pin function switch bit
C22
P12/SEG27 pin function switch bit
C21
P11/SEG26 pin function switch bit
C20
P10/SEG25 pin function switch bit
0
1
0
1
0
1
0
1
Note: “R” represents read enabled, and “W” represents write enabled.
Rev.1.01
Sep 17, 2003
page 44 of 130
W
TC1A
at power down : state retained
W
TC2A
SEG24
P03
SEG23
P02
SEG22
P01
SEG21
P00
at reset : 11112
LCD control register C2
at power down : state retained
SEG28
P13
SEG27
P12
SEG26
P11
SEG25
P10
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
1/2 Duty, 1/2 Bias: When writing (XX10)2 to address M (1, 2, 9) in RAM.
1 flame (2/F)
M (1, 2, 9)
COM0
0 (bit 0)
COM1
1
1/F
Voltage level
VLC3
VLC1=VLC2
VSS
COM1
X
COM0
X (bit 3)
VLC3
VLC1=VLC2
VSS
SEG17
SEG17
COM1
SEG17
COM0
SEG17
ON
OFF
1/3 Duty, 1/3 Bias: When writing (X101)2 to address M (1, 2, 9) in RAM.
1 flame (3/F)
M (1, 2, 9)
COM0
1 (bit 0)
COM1
0
COM2
1
1/F
Voltage level
VLC3
VLC2
VLC1
VSS
COM2
X (bit 3)
COM1
SEG17
COM0
SEG17
COM2
SEG17
COM1
SEG17
ON
OFF
COM0
SEG17
VLC3
VLC2
VLC1
VSS
ON
1/4 Duty, 1/3 Bias: When writing (1010)2 to address M (1, 2, 9) in RAM.
1 flame (4/F)
M (1, 2, 9)
COM0
COM1
COM2
COM3
1/F
Voltage level
0 (bit 0)
VLC3
VLC2
VLC1
VSS
COM3
1
0
COM2
1 (bit 3)
SEG17
COM1
COM0
F : LCD clock frequency
SEG17
X: Set an arbitrary value.
(These bits are not related to
set the drive waveform at each duty.)
Fig. 33 LCD controller/driver structure
Rev.1.01
Sep 17, 2003
page 45 of 130
COM3
SEG17
COM2
SEG17
COM1
SEG17
COM0
SEG17
ON
OFF
ON
OFF
VLC3
VLC2
VLC1
VSS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
(5) LCD power supply circuit
Select the LCD power supply circuit suitable for the using LCD
panel.
The LCD power supply circuit is fixed by the followings;
• The internal dividing resistor is controlled by bit 0 of register L2.
• The internal dividing resistor is selected by bit 3 of register L1.
• The bias condition is selected by bits 0 and 1 of register L1.
●Internal dividing resistor
The 4556 Group has the internal dividing resistor for LCD power
supply.
When bit 0 of register L2 is set to “1”, the internal dividing resistor is valid. However, when the LCD is turned off by setting bit 2
of register L1 to “0”, the internal dividing resistor is turned off.
The same six resistor (r) is prepared for the internal dividing resistor. According to the setting value of bit 3 of register L1 and
using bias condition, the resistor is prepared as follows;
• L13 = “0”, 1/3 bias used: 2r ✕ 3 = 6r
• L13 = “0”, 1/2 bias used: 2r ✕ 2 = 4r
• L13 = “1”, 1/3 bias used: r ✕ 3 = 3r
• L13 = “1”, 1/2 bias used: r ✕ 2 = 2r
●VLC3/SEG0 pin
The selection of VLC3/SEG0 pin function is controlled with the bit
3 of register L2.
When the VLC3 pin function is selected, apply voltage of VLC3 <
VDD to the pin externally.
When the SEG0 pin function is selected, VLC3 is connected to
VDD internally.
● VLC2/SEG1, VLC1/SEG2 pin
The selection of VLC2/SEG1 pin function is controlled with the bit
2 of register L2.
The selection of VLC1/SEG2 pin function is controlled with the bit
1 of register L2.
When the VLC2 pin and VLC1 pin functions are selected and the
internal dividing resistor is not used, apply voltage of
0<VLC1<VLC2<VLC3 to these pins. Short the V LC2 pin and VLC1
pin at 1/2 bias.
When the VLC2 pin and VLC1 pin functions are selected and the
internal dividing resistor is used, the dividing voltage value generated internally is output from the VLC1 pin and VLC2 pin. The
VLC2 pin and VLC1 pin have the same electric potential at 1/2 bias.
When SEG1 and SEG2 pin functions are selected, use the internal dividing resistor. In this time, VLC2 and VLC1 are connected to
the generated dividingg voltage.
VLC3
SEG0
VLC3
VLC3
VLC2
SEG1
VLC2
SEG1
VLC1
VLC1
SEG2
SEG2
b) Register L2=(1000)2
a) Register L2=(0000)2
VLC3
VLC2
VLC1
VLC3
VLC2
VLC1
c) Register L2=(1110)2
Fig. 34 LCD power supply circuit example (1/3 bias condition selected)
Rev.1.01
Sep 17, 2003
page 46 of 130
VLC3
VLC2
VLC1
d) Register L2=(1111)2
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
RESET FUNCTION
System reset is performed by applying “L” level to RESET pin for
1 machine cycle or more when the following condition is satisfied;
the value of supply voltage is the minimum value or more of the
recommended operating conditions.
Then when “H” level is applied to RESET pin, software starts from
address 0 in page 0.
f(XIN)
RESET
Ring oscillator (internal oscillator)
Program starts
(address 0 in page 0)
is counted 5400 to 5424 times.
Note: The number of clock cycles depends on the internal state of
the microcomputer when reset is performed.
Fig. 35 Reset release timing
=
Reset input
Ring oscillator (internal oscillator) is
1 machine cycle or more
0.85VDD
counted 5400 to 5424 times.
Program starts
(address 0 in page 0)
RESET
0.3VDD
(Note)
Note: Keep the value of supply voltage to the minimum value
or more of the recommended operating conditions.
Fig. 36 RESET pin input waveform and reset operation
Rev.1.01
Sep 17, 2003
page 47 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
(1) Power-on reset (only for H version)
Reset can be automatically performed at power on (power-on reset) by the built-in power-on reset circuit. When the built-in
power-on reset circuit is used, the time for the supply voltage to
rise from 0 V must be set to 100 µs or less. If the rising time ex-
ceeds 100 µs, connect a capacitor between the RESET pin and
VSS at the shortest distance, and input “L” level to RESET pin until
the value of supply voltage reaches the minimum operating voltage.
100 µs or less
Pull-up transistor
VDD (Note 3)
Power-on reset
circuit output
(Note 1)
(Note 2)
RESET pin
Internal reset signal
Power-on reset circuit
(Note 1)
Voltage drop detection circuit
Internal reset signal
Watchdog reset signal
WEF
Reset
state
SRST instruction
Power-on
Reset released
This symbol represents a parasitic diode.
Notes 1:
2: Applied potential to RESET pin must be VDD or less.
3: Keep the value of supply voltage to the minimum value
or more of the recommended operating conditions.
Fig. 37 Power-on reset circuit example
Table 13 Port state at reset
Name
State
Function
D0–D4
D0–D4
High-impedance (Notes 1, 2)
D5/INT
XCIN/D6, XCOUT/D7
D5
High-impedance (Notes 1, 2)
Sub-clock input
P00/SEG21–P03/SEG24
XCIN, XCOUT
P00–P03
P10/SEG25–P13/SEG28
P10–P13
High-impedance (Notes 1, 2, 3)
P20/SEG17–P23/SEG20
P20–P23
High-impedance (Notes 1, 2, 3)
SEG0/VLC3–SEG2/VLC1
SEG0–SEG2
VLC3 (VDD) level
SEG3–SEG10
COM0–COM3
SEG3–SEG10
VLC3 (VDD) level
VLC3 (VDD) level
C/CNTR
COM0–COM3
C
Notes 1: Output latch is set to “1.”
2: Output structure is N-channel open-drain.
3: Pull-up transistor is turned OFF.
Rev.1.01
Sep 17, 2003
page 48 of 130
High-impedance (Notes 1, 2, 3)
“L” (VSS) level
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
(2) Internal state at reset
Figure 38 shows internal state at reset (they are the same after system is released from reset). The contents of timers, registers, flags
and RAM except shown in Figure 38 are undefined, so set the initial value to them.
• Program counter (PC) ..........................................................................................................
0 0 0 0 0 0
Address 0 in page 0 is set to program counter.
• Interrupt enable flag (INTE) .................................................................................................. 0
• Power down flag (P) ............................................................................................................. 0
• External 0 interrupt request flag (EXF0) .............................................................................. 0
0 0 0 0
• Interrupt control register V1 ..................................................................................................
• Interrupt control register V2 ..................................................................................................
0 0 0 0
0 0 0 0
• Interrupt control register I1 ...................................................................................................
• Timer 1 interrupt request flag (T1F) ..................................................................................... 0
• Timer 2 interrupt request flag (T2F) ..................................................................................... 0
• Timer 3 interrupt request flag (T3F) ..................................................................................... 0
• Watchdog timer flags (WDF1, WDF2) .................................................................................. 0
• Watchdog timer enable flag (WEF) ...................................................................................... 1
• Timer control register PA ...................................................................................................... 0
0 0 0 0
• Timer control register W1 .....................................................................................................
• Timer control register W2 .....................................................................................................
0 0 0 0
0 0 0 0
• Timer control register W3 .....................................................................................................
0 0 0 0
• Timer control register W4 .....................................................................................................
• Clock control register MR .....................................................................................................
1 1 0 0
0 0 0
• Clock control register RG .....................................................................................................
• LCD control register L1 ........................................................................................................
0 0 0 0
• LCD control register L2 ........................................................................................................
0 0 0 0
1 1 1 1
• LCD control register L3 ........................................................................................................
• LCD control register C1 ........................................................................................................
1 1 1 1
• LCD control register C2 ........................................................................................................
1 1 1 1
0 0 0 0
• Key-on wakeup control register K0 ......................................................................................
• Key-on wakeup control register K1 ......................................................................................
0 0 0 0
• Key-on wakeup control register K2 ......................................................................................
0 0 0 0
0 0 0 0
• Pull-up control register PU0 .................................................................................................
• Pull-up control register PU1 .................................................................................................
0 0 0 0
• Port output structure control register FR0 ...........................................................................
0 0 0 0
0 0 0 0
• Port output structure control register FR1 ...........................................................................
• Port output structure control register FR2 ...........................................................................
0 0 0 0
• Carry flag (CY) ...................................................................................................................... 0
• High-order bit reference enable flag (UPTF) ....................................................................... 0
• Register A .............................................................................................................................
0 0 0 0
• Register B .............................................................................................................................
0 0 0 0
✕ ✕ ✕
• Register D .............................................................................................................................
• Register E .............................................................................................................................
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Register X .............................................................................................................................
0 0 0 0
0 0 0 0
• Register Y .............................................................................................................................
• Register Z .............................................................................................................................
✕ ✕
• Stack pointer (SP) ................................................................................................................
1 1 1
• Operation source clock ............................................................... Ring oscillator (operating)
• Ceramic resonator circuit ..................................................................................... Operating
• RC oscillation circuit ...................................................................................................... Stop
0
0
0
0
0
0
0
0
(Interrupt disabled)
(Interrupt disabled)
(Interrupt disabled)
(Prescaler stopped)
(Timer 1 stopped)
(Timer 2 stopped)
(Timer 3 stopped)
(Timer LC stopped)
“✕” represents undefined.
Fig. 38 Internal state at reset
Rev.1.01
Sep 17, 2003
page 49 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
(1) SVDE instruction
When the SVDE instruction is executed, the voltage drop deteciton
circuit is valid even after system enters into the power down mode.
The SVDE instruction can be executed only once.
In order to release the execution of the SVDE instruction, the system reset is required.
VOLTAGE DROP DETECTION CIRCUIT
(only for H version)
The built-in voltage drop detection circuit is designed to detect a
drop in voltage and to reset the microcomputer if the supply voltage
drops below a set value.
S
Q
R
Q
S
SVDE instruction
R
Internal reset signal
Internal reset signal
T3F flag
Key-on wakeup signal
Voltage drop detection circuit
Reset signal
–
+
VRST
EPOF instruction +POF instruction
EPOF instruction +POF2 instruction
Voltage drop detection circuit
Fig. 39 Voltage drop detection reset circuit
VDD
+
VRST (reset release voltage)
VRST -(reset occurrence voltage)
Voltage drop detection circuit
Reset signal
Microcomputer starts operation after
ring oscillator (internal oscillator)
clock is counted 1376 times.
RESET pin
Note: Detection voltage hysteresis of voltage drop detection circuit is 0.2 V (Typ).
Fig. 40 Voltage drop detection circuit operation waveform
(2) Note on voltage drop detection circuit
The voltage drop detection circuit detection voltage of this product is set up lower than the minimum value of the supply voltage
of the recommended operating conditions.
When the supply voltage of a microcomputer falls below to the
minimum value of recommended operating conditions and regoes up (ex. battery exchange of an application product),
depending on the capacity value of the bypass capacitor added
to the power supply pin, the following case may cause program
failure (Figure 41);
supply voltage does not fall below to VRST-, and
its voltage re-goes up with no reset.
In such a case, please design a system which supply voltage is
once reduced below to VRST- and re-goes up after that.
VDD
Recommended
operatng condition
min.value
+
VRST
–
VRST
Sep 17, 2003
page 50 of 130
→ Normal operation
VDD
Recommended
operatng condition
min.value
+
VRST
–
VRST
Reset
Fig. 41 VDD and VRST–
Rev.1.01
No reset
Program failure may occur.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
POWER DOWN FUNCTION
The 4556 Group has 2-type power down functions.
System enters into each power down state by executing the following instructions.
• Clock operating mode ...................... EPOF and POF instructions
• RAM back-up mode ....................... EPOF and POF2 instructions
When the EPOF instruction is not executed before the POF or
POF2 instruction is executed, these instructions are equivalent to
the NOP instruction.
Table 15 Functions and states retained at power down
Power down mode
Function
Clock
operating
RAM
back-up
✕
✕
Contents of RAM
O
O
Interrupt control registers V1, V2
✕
✕
Interrupt control register I1
Selected oscillation circuit
O
O
O
O
O
(Note 3)
O
(Note 3)
O
O
O
(Note 3)
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
Clock control register MR, RG
Timer 1 to timer 2 functions
(1) Clock operating mode
Timer 3 function
The following functions and states are retained.
• RAM
• Reset circuit
• XCIN–XCOUT oscillation
• LCD display
• Timer 3
Timer LC function
(2) RAM back-up mode
The following functions and states are retained.
• RAM
• Reset circuit
(3) Warm start condition
The system returns from the power down state when;
• External wakeup signal is input
• Timer 3 underflow occurs
in the power down mode.
In either case, the CPU starts executing the software from address
0 in page 0. In this case, the P flag is “1.”
(4) Cold start condition
The CPU starts executing the software from address 0 in page 0
when;
• reset pulse is input to RESET pin,
• reset by watchdog timer is performed, or
• reset by the voltage drop detection circuit is performed.
In this case, the P flag is “0.”
(5) Identification of the start condition
Warm start or cold start can be identified by examining the state of
the power down flag (P) with the SNZP instruction. The warm start
condition from the clock operating mode can be identified by examining the state of T3F flag.
Rev.1.01
Sep 17, 2003
page 51 of 130
Watchdog timer function
Timer control registers PA
Timer control registers W1 to W4
LCD display function
✕ (Note 4) ✕ (Note 4)
✕
✕
O
O
O
(Note 5)
O
O
Voltage drop detection circuit
(Note 6)
(Note 6)
Port level
Pull-up control registers PU0, PU1
(Note 7)
(Note 7)
O
O
O
O
O
O
✕
✕
(Note 3)
(Note 3)
O
✕
O
✕
LCD control registers L1 to L3, C1, C2
Key-on wakeup control registers K0 to K2
Port output format control registers
FR0 to FR2
External interrupt request flag
(EXF0)
Timer interrupt request flags (T1F, T2F)
Timer interrupt request flag (T3F)
Interrupt enable flag (INTE)
Watchdog timer flags (WDF1, WDF2)
✕ (Note 4) ✕ (Note 4)
Watchdog timer enable flag (WEF)
✕ (Note 4) ✕ (Note 4)
Notes 1:“O” represents that the function can be retained, and “✕” represents that the function is initialized.
Registers and flags other than the above are undefined at RAM
back-up, and set an initial value after returning.
2: The stack pointer (SP) points the level of the stack register and is
initialized to “7” at RAM back-up.
3: The state of the timer is undefined.
4: Initialize the watchdog timer with the WRST instruction, and then
go into the power down state.
5: LCD is turned off.
6: When the SVDE instruction is executed, this function is valid at
power down.
7: In the RAM back-up mode, C/CNTR pin outputs “L” level.
However, when the CNTR input is selected (W11, W1 0=“11”), C/
CNTR pin is in an input enabled state (output = high-impedance).
Other ports retain their respective output levels.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
(6) Return signal
An external wakeup signal or timer 3 interrupt request flag (T3F) is
used to return from the clock operating mode.
An external wakeup signal is used to return from the RAM back-up
mode because the oscillation is stopped.
Table 16 shows the return condition for each return source.
(7) Control registers
• Key-on wakeup control register K0
Register K0 controls the ports P0 and P1 key-on wakeup function. Set the contents of this register through register A with the
TK0A instruction. In addition, the TAK0 instruction can be used to
transfer the contents of register K0 to register A.
• Key-on wakeup control register K1
Register K1 controls the return condition and the selection of
valid waveform/level of port P1. Set the contents of this register
through register A with the TK1A instruction. In addition, the TAK1
instruction can be used to transfer the contents of register K0 to
register A.
• Key-on wakeup control register K2
Register K2 controls the INT pin key-on wakeup function and the
selection of return codition. Set the contents of this register
through register A with the TK2A instruction. In addition, the TAK2
instruction can be used to transfer the contents of register K2 to
register A.
• Pull-up control register PU0
Register PU0 controls the ON/OFF of the port P0 pull-up transistor. Set the contents of this register through register A with the
TPU0A instruction. In addition, the TAPU0 instruction can be
used to transfer the contents of register PU0 to register A.
• Pull-up control register PU1
Register PU1 controls the ON/OFF of the port P1 pull-up transistor. Set the contents of this register through register A with the
TPU1A instruction. In addition, the TAPU1 instruction can be
used to transfer the contents of register PU1 to register A.
• External interrupt control register I1
Register I1 controls the valid waveform of the external 0 interrupt, the input control of INT pin and the return input level. Set
the contents of this register through register A with the TI1A instruction. In addition, the TAI1 instruction can be used to transfer
the contents of register I1 to register A.
External wakeup signal
Table 16 Return source and return condition
Return source
Return condition
Ports P00–P03 Return by an external falling edge
(“H”→“L”).
Ports P10–P13 Return by an external “H” level or “L”
level input, or rising edge (“L”→“H”)
or falling edge (“H”→“L”).
Return by an external “L” level input.
INT pin
Return by an external “H” level or “L”
level input, or rising edge (“L”→“H”)
or falling edge (“H”→“L”).
When the return level is input, the interrupt request flag (EXF0) is not set.
Remarks
The key-on wakeup function can be selected by two port unit.
The key-on wakeup function can be selected by two port unit. Select the return level (“L” level or “H” level) and return condition (return by level or
edge) with register K1 according to the external state before going into the
power down state.
Select the return level (“L” level or “H” level) with register I1 and return condition (return by level or edge) with register K2 according to the external
state before going into the power down state.
Timer 3 interrupt Return by timer 3 underflow or by
request flag (T3F)
setting T3F to “1”.
Clear T3F with the SNZT3 instruction before system enters into the power
down state.
It can be used in the clock operating
mode.
When system enters into the power down state while T3F is “1”, system returns from the state immediately because it is recognized as return
condition.
Rev.1.01
Sep 17, 2003
page 52 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
High-speed mode
E
F
CRCK instruction no execution
Clock operating mode
POF instruction
execution
POF2 instruction
execution
B
Operation state
Key-on wakeup
(Stabilizing time c )
• Operation source clock: f(XIN)
• Oscillation circuit:
Ceramic resonator
RAM back-up mode
Key-on wakeup
(Stabilizing time c )
CRCK instruction execution
POF instruction
execution
MR1, MR0←00
Internal mode
POF instruction
execution
(Stabilizing time a )
Key-on wakeup
(Stabilizing time b )
A
Operation state
• Operation source clock:
f(RING)
• Oscillation circuit:
Ring oscillator
MR1, MR0←10
Key-on wakeup
(Stabilizing time d )
MR1, MR0←10
MR1, MR0←01
MR1, MR0←01
Key-on wakeup
(Stabilizing time d )
Reset
POF2 instruction
execution
C
Operation state
• Operation source clock: f(XIN)
• Oscillation circuit:
RC oscillation
POF2 instruction
execution
Key-on wakeup
(Stabilizing time b )
MR1, MR0←00
Low-speed mode
POF instruction
execution
f(RING): stop
f(XIN): stop
f(XCIN): operating
Stabilizing time
Stabilizing time
Stabilizing time
Stabilizing time
Stabilizing time
Key-on wakeup
(Stabilizing time e )
D
Operation state
• Operation source clock:
f(XCIN)
• Oscillation circuit:
Quartz-crystal oscillation
POF2 instruction
execution
Key-on wakeup
(Stabilizing time e )
f(RING): stop
f(XIN): stop
f(XCIN): stop
a : Microcomputer starts its operation after counting the f(RING) to 1376 times.
b : Microcomputer starts its operation after counting the f(RING) to (system clock division ratio ✕ 15) times.
c : Microcomputer starts its operation after counting the f(XIN) to (system clock division ratio ✕ 171) times.
d : Microcomputer starts its operation after counting the f(XIN) to (system clock division ratio ✕ 15) times.
e : Microcomputer starts its operation after counting the f(XCIN) to (system clock division ratio ✕ 171) times.
Notes 1: Continuous execution of the EPOF instruction and the POF instruction is required to go into the clock operating state.
2: Continuous execution of the EPOF instruction and the POF2 instruction is required to go into the RAM back-up state.
3: The state after system is released from reset;
• A ceramic resonator is selected as the main clock (f(XIN)).
• Main clock (f(XIN)) and Suc-clock (f(XCIN)) are valid.
4: When the RC oscillation circuit is used, executing the CRCK instruction is required.
If the CRCK instruction is not executed, the ceramic resonator is selected as the main clock f(XIN).
5: When the unoperating clock is selected as the system clock, turn it on by the clock control register RG,
and generate the wait time until the oscillation is stabilized, and then, switch the system clock.
Fig. 42 State transition
POF or
EPOF instruction + POF2
instruction
Power down flag P
S
Q
R
Reset input
POF or
EPOF instruction + POF2
instruction
● Clear source • • • • • • Reset input
● Set source
Sep 17, 2003
P = “1”
?
Yes
page 53 of 130
Warm start
No
Cold start
•••••••
Fig. 43 Set source and clear source of the P flag
Rev.1.01
Program start
T3F = “1”
?
Yes
No
Return from
timer 3 underflow
Return from
external wakeup signal
Fig. 44 Start condition identified example using the SNZP instruction
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
Table 17 Key-on wakeup control register, pull-up control register and interrupt control register
Key-on wakeup control register K0
K03
K02
K01
K00
Port P12, P13 key-on wakeup
at reset : 00002
control bit
0
1
Port P10, P11 key-on wakeup
0
Key-on wakeup used
Key-on wakeup not used
control bit
Port P02, P03 key-on wakeup
1
Key-on wakeup used
0
Key-on wakeup not used
control bit
1
Key-on wakeup used
Port P00, P01 key-on wakeup
0
1
Key-on wakeup not used
control bit
Key-on wakeup control register K1
K13
K12
K11
K10
at power down : state retained
Returned by edge
1
Returned by level
Ports P12, P13 valid waveform/level
0
Falling waveform/“L” level
selection bit
1
0
Rising waveform/“H” level
1
Ports P10, P11 return condition selection bit
0
Returned by level
Falling waveform/“L” level
selection bit
1
Rising waveform/“H” level
at reset : 00002
0
Not used
K22
Not used
K21
INT pin return condition selection bit
1
INT pin key-on wakeup control bit
Sep 17, 2003
page 54 of 130
at power down : state retained
This bit has no function, but read/write is enabled.
0
1
This bit has no function, but read/write is enabled.
0
Returned by level
1
Returned by edge
0
Key-on wakeup invalid
1
Key-on wakeup valid
Note: “R” represents read enabled, and “W” represents write enabled.
R/W
TAK1/
TK1A
Returned by edge
Ports P10, P11 valid waveform/level
K23
Rev.1.01
Key-on wakeup used
0
Ports P12, P13 return condition selection bit
R/W
TAK0/
TK0A
Key-on wakeup not used
at reset : 00002
Key-on wakeup control register K2
K20
at power down : state retained
R/W
TAK2/
TK2A
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
Pull-up control register PU0
PU03
PU02
PU01
PU00
Port P03 pull-up transistor
at reset : 00002
0
1
Pull-up transistor OFF
Port P02 pull-up transistor
control bit
0
Pull-up transistor OFF
1
Pull-up transistor ON
Port P01 pull-up transistor
0
control bit
1
Pull-up transistor OFF
Pull-up transistor ON
Port P00 pull-up transistor
0
1
control bit
control bit
PU13
PU12
PU11
PU10
I13
0
1
Port P12 pull-up transistor
0
1
Pull-up transistor OFF
Port P11 pull-up transistor
control bit
0
Pull-up transistor OFF
1
Pull-up transistor ON
Port P10 pull-up transistor
0
control bit
1
Pull-up transistor OFF
Pull-up transistor ON
I12
INT pin input control bit (Note 2)
Interrupt valid waveform for INT pin/
return level selection bit (Note 2)
I11
INT pin edge detection circuit control bit
I10
INT pin Timer 1 count start synchronous
circuit selection bit
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor ON
at reset : 00002
0
1
0
1
0
1
0
1
R/W
TAPU1/
TPU1A
Pull-up transistor ON
Port P13 pull-up transistor
Interrupt control register I1
at power down : state retained
Pull-up transistor OFF
control bit
control bit
R/W
TAPU0/
TPU0A
Pull-up transistor ON
at reset : 00002
Pull-up control register PU1
at power down : state retained
at power down : state retained
INT pin input disabled
INT pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI0
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI0
instruction)
One-sided edge detected
Both edges detected
Timer 1 count start synchronous circuit not selected
Timer 1 count start synchronous circuit selected
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 and I13 are changed, the external interrupt request flag (EXF0) may be set.
Rev.1.01
Sep 17, 2003
page 55 of 130
R/W
TAI1/TI1A
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
CLOCK CONTROL
The system clock and the instruction clock are generated as the
source clock for operation by these circuits.
Figure 45 shows the structure of the clock control circuit.
The 4556 Group operates by the ring oscillator clock (f(RING))
which is the internal oscillator after system is released from reset.
Also, the ceramic resonator or the RC oscillation can be used for
the main clock (f(XIN)) of the 4556 Group.
The quartz-crystal oscillator can be used for sub-clock (f(XCIN)).
The clock control circuit consists of the following circuits.
• Ring oscillator (internal oscillator)
• Ceramic resonator
• RC oscillation circuit
• Quartz-crystal oscillation circuit
• Multi-plexer (clock selection circuit)
• Frequency divider
• Internal clock generating circuit
Division circuit
MR3, MR2
11
System clock (STCK)
Divided by 8
Ring oscillator
(internal oscillator)
MR1, MR0
00
01
10
Divided by 4
Divided by 2
Internal clock
generating circuit
(divided by 3)
01
00
Instruction clock
(INSTCK)
10
RG0
XIN
XOUT
Ceramic
resonance
Multiplexer
RC oscillation
XCIN
XCOUT
Q S
RG1
Q R
Q S
Quartz-crystal
oscillation
CRCK instruction
R
Internal reset signal
T3F signal
Key-on wakeup signal
EPOF instruction + POF instruction
Q S
RG2
R
Fig. 45 Clock control circuit structure
Rev.1.01
Sep 17, 2003
page 56 of 130
EPOF instruction + POF2 instruction
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
(1) Ring oscillator operation
Main clock (f(XIN))
After system is released from reset, the MCU starts operation by
the clock output from the ring oscillator which is the internal oscillator.
The clock frequency of the ring oscillator depends on the supply
voltage and the operation temperature range.
Be careful that variable frequencies when designing application
products.
• Ceramic resonator circuit valid
• RC oscillation circuit invalid
Reset
CRCK
(2) Main clock generating circuit (f(XIN))
When the MCU operates by the ceramic resonator or the RC oscillator as the main clock (f(XIN)).
After system is released from reset, the ceramic oscillation is valid
for main clock.
The ceramic oscillation is invalid and the RC oscillation circuit is
valid with the CRCK instruction.
The CRCK instruction can be executed only once.
Execute the CRCK instruction in the initial setting routine (executing it in address 0 in page 0 is recommended).
When the main clock (f(X IN)) is not used, connect XIN pin to VSS
and leave XOUT pin open, and do not execute the CRCK instruction
(Figure 46).
(3) Ceramic resonator
When the ceramic resonator is used as the main clock (f(XIN)), connect the ceramic resonator and the external circuit to pins XIN and
X OUT at the shortest distance. A feedback resistor is built in between pins X IN and XOUT (Figure 47). Do not execute the CRCK
instruction in program.
• Ceramic resonator circuit invalid
• RC oscillation circuit valid
Fig. 46 Switch to ceramic resonance/RC oscillation
M34556
XIN
* Do not use the CRCK instruction in program.
XOUT
Fig. 47 Handling of XIN and XOUT when operating ring oscillator
M34556
XIN
XOUT
Note: Externally connect a damping
resistor Rd depending on the
oscillation frequency.
Rd
(A feedback resistor is built-in.)
Use the resonator manufacturer’s recommended value
COUT
because constants such as capacitance depend on the
resonator.
(4) RC oscillation
When the RC oscillation is used as the main clock (f(XIN)), connect
the XIN pin to the external circuit of resistor R and the capacitor C
at the shortest distance and leave XOUT pin open. Then, execute
the CRCK instruction (Figure 48).
The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency
limits.
not execute the CRCK in* Do
struction in program.
CIN
Fig. 48 Ceramic resonator external circuit
M34556
R
XIN
XOUT
the CRCK
* Execute
instruction in program.
C
Fig. 49 External RC oscillation circuit
Rev.1.01
Sep 17, 2003
page 57 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
(5) External clock
When the external clock signal is used as the main clock (f(XIN)),
connect the XIN pin to the clock source and leave XOUT pin open.
(Figure 49). Do not execute the CRCK instruction.
Be careful that the maximum value of the oscillation frequency
when using the external clock differs from the value when using the
ceramic resonator (refer to the recommended operating condition).
Also, note that the power down mode (POF and POF2 instructions)
cannot be used when using the external clock.
not use the CRCK instruction
* Do
in program.
M34556
XIN
XOUT
VDD
VSS
External oscillation circuit
Fig. 50 External clock input circuit
(6) Sub-clock generating circuit f(XCIN)
Sub-clock signal f(X CIN) is obtained by externally connecting a
quartz-crystal oscillator. Connect this external circuit and a quartzcrystal oscillator to pins XCIN and XCOUT at the shortest distance. A
feedback resistor is built in between pins XCIN and XCOUT (Figure 50).
XCIN pin and XCOUT pin are also used as ports D6 and D7, respectively. The sub-clock oscillation circuit is invalid and the function of
ports D6 and D7 are valid by setting bit 2 of register RG to “1”.
When sub-clock, ports D6 and D7 are not used, connect XCIN/D6 to
VSS and leave XCOUT/D7 open.
M34556
Fig. 51 External quartz-crystal circuit
Register MR controls system clock. Set the contents of this register
through register A with the TMRA instruction. In addition, the TAMR
instruction can be used to transfer the contents of register MR to
register A.
ROM ORDERING METHOD
1.Mask ROM Order Confirmation Form*
2.Mark Specification Form*
3.Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk.
(8) Clock control register RG
Register RG controls the start/stop of each oscillation circuit. Set
the contents of this register through register A with the TRGA instruction.
* For the mask ROM confirmation and the mark specifications, refer to the “Renesas Technology Corp.” Homepage
(http://www.renesas.com/en/rom).
Table 18 Clock control registers
at reset : 11002
Clock control register MR
Operation mode selection bits
MR2
MR3
System clock selection bits (Note 3)
MR2
MR3 MR2
0
0
0
1
1
0
1
1
MR1 MR0
0
0
0
1
1
0
1
1
Clock control register RG
RG2
Sub-clock (f(XCIN)) control bit (Note 2)
RG1
Main-clock (f(XIN)) control bit (Note 2)
RG0
Ring oscillator (f(RING)) control bit
(Note 2)
Sep 17, 2003
page 58 of 130
R/W
TAMR/
TMRA
Operation mode
Frequency divided by 2 mode
Frequency divided by 4 mode
Frequency divided by 8 mode
System clock
f(RING)
f(XIN)
f(XCIN)
Not available (Note 2)
W
TRGA
Sub-clock (f(XCIN)) oscillation available, ports D6 and D7 not selected
Sub-clock (f(XCIN)) oscillation stop, ports D6 and D7 selected
Main clock (f(XIN)) oscillation available
Main clock (f(XIN)) oscillation stop
Ring oscillator (f(RING)) oscillation available
Ring oscillator (f(RING)) oscillation stop
at reset : 0002
0
1
0
1
0
1
at power down : state retained
Through mode
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: “11” cannot be set to the low-order 2 bits (MR1, MR0) of register MR.
Rev.1.01
XCOUT
CIN
(7) Clock control register MR
MR3
Note: Externally connect a damping
resistor Rd depending on the
oscillation frequency.
(A feedback resistor is built-in.)
Use the quartz-crystal manuRd
facturer’s recommended value
because constants such as capacitance depend on the
COUT
resonator.
XCIN
at power down : state retained
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
LIST OF PRECAUTIONS
➀Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
• connect a bypass capacitor (approx. 0.1 µF) between pins VDD
and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use relatively thick wire.
In the One Time PROM version, CNVSS pin is also used as VPP
pin. Accordingly, when using this pin, connect this pin to VSS
through a resistor about 5 kΩ (connect this resistor to CNVSS/
VPP pin as close as possible).
➁Register initial values 1
The initial value of the following registers are undefined after system is released from reset. After system is released from reset,
set initial values.
• Register Z (2 bits)
• Register D (3 bits)
• Register E (8 bits)
➂Register initial values 2
The initial value of the following registers are undefined at RAM backup. After system is returned from RAM back-up, set initial values.
• Register Z (2 bits)
• Register X (4 bits)
• Register Y (4 bits)
• Register D (3 bits)
• Register E (8 bits)
➃ Stack registers (SKS)
Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack
registers is used respectively when using an interrupt service
routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these
operations together.
➄Prescaler
Stop counting and then execute the TABPS instruction to read
from prescaler data.
Stop counting and then execute the TPSAB instruction to set
prescaler data.
➅Timer count source
Stop timer 1, 2 and LC counting to change its count source.
➆Reading the count value
Stop timer 1 or 2 counting and then execute the data read instruction (TAB1, TAB2) to read its data.
➇Writing to the timer
Stop timer 1, 2 or LC counting and then execute the data write instruction (T1AB, T2AB, TLCA) to write its data.
Rev.1.01
Sep 17, 2003
page 59 of 130
➈Writing to reload register R1, R2H
When writing data to reload register R1, reload register R2H
while timer 1 or timer 2 is operating, avoid a timing when timer 1
or timer 2 underflows.
10
Timer 2
Avoid a timing when timer 2 underflows to stop timer 2 at PWM
output function used.
When “H” interval extension function of the PWM signal is set to
be “valid”, set “1” or more to reload register R2H.
11
Timer 3
Stop timer 3 counting to change its count source.
12
Timer input/output pin
Set the port C output latch to “0” to output the PWM signal from
C/CNTR pin.
13 Watchdog timer
• The watchdog timer function is valid after system is released
from reset. When not using the watchdog timer function, execute
the DWDT instruction and the WRST instruction continuously,
and clear the WEF flag to “0” to stop the watchdog timer function.
• The watchdog timer function is valid after system is returned from
the power down state. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction
continuously every system is returned from the power down
state, and stop the watchdog timer function.
• When the watchdog timer function and power down function are
used at the same time, execute the WRST instruction before system enters into the power down state and initialize the flag
WDF1.
14 Multifunction
• Be careful that the output of port D5 can be used even when INT
pin is selected.
The threshold value is different between port D5 and INT. Accordingly, be careful when the input of both is used.
• Be careful that the “H” output of port C can be used even when
output of CNTR pin are selected.
15
Program counter
Make sure that the PCH does not specify after the last page of
the built-in ROM.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
D5/INT pin
❶ Note [1] on bit 3 of register I1
When the input of the INT pin is controlled with the bit 3 of register I1 in software, be careful about the following notes.
❸ Note on bit 2 of register I1
When the interrupt valid waveform of the D5/INT pin is changed
with the bit 2 of register I1 in software, be careful about the following notes.
• Depending on the input state of the D5/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 51➀)
and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction (refer to Figure 51➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 51➂).
• Depending on the input state of the D5/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 53➀)
and then, change the bit 2 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction (refer to Figure 53➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 53➂).
•••
•••
16
LA
4
TV1A
LA
8
TI1A
NOP
SNZ0
LA
4
TV1A
LA
12
TI1A
NOP
SNZ0
; Interrupt valid waveform is changed
........................................................... ➁
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... ➂
•••
NOP
; (✕✕✕02)
; The SNZ0 instruction is valid ........... ➀
•••
NOP
; (✕✕✕02)
; The SNZ0 instruction is valid ........... ➀
; (1✕✕✕2)
; Control of INT pin input is changed
........................................................... ➁
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... ➂
✕ : these bits are not used here.
✕ : these bits are not used here.
Fig. 51 External 0 interrupt program example-1
❷ Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared to “0”, the RAM back-up
mode is selected and the input of INT pin is disabled, be careful
about the following notes.
•••
• When the key-on wakeup function of INT pin is not used (register
K20 = “0”), clear bits 2 and 3 of register I1 before system enters
to the RAM back-up mode. (refer to Figure 52➀).
; (00✕✕2)
; Input of INT disabled ........................ ➀
; RAM back-up
•••
LA
0
TI1A
DI
EPOF
POF2
✕ : these bits are not used here.
Fig. 52 External 0 interrupt program example-2
Rev.1.01
Sep 17, 2003
page 60 of 130
Fig. 53 External 0 interrupt program example-3
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
17
POF and POF2 instructions
When the POF or POF2 instruction is executed continuously after the EPOF instruction, system enters the power down state.
Note that system cannot enter the power down state when executing only the POF or POF2 instruction.
Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction and the POF or POF2
instruction continuously.
18
Power-on reset
When the built-in power-on reset circuit is used, the time for the
supply voltage to rise from 0 V to 2.0 V must be set to 100 µs or
less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and VSS at the shortest distance, and input
“L” level to RESET pin until the value of supply voltage reaches
the minimum operating voltage.
19
Voltage drop detection circuit (only in H version)
The voltage drop detection circuit detection voltage of this product is set up lower than the minimum value of the supply voltage
of the recommended operating conditions.
When the supply voltage of a microcomputer falls below to the
minimum value of recommended operating conditions and regoes up (ex. battery exchange of an application product),
depending on the capacity value of the bypass capacitor added
to the power supply pin, the following case may cause program
failure (Figure 55);
supply voltage does not fall below to VRST-, and
its voltage re-goes up with no reset.
In such a case, please design a system which supply voltage is
once reduced below to VRST- and re-goes up after that.
VDD
Recommended
operatng condition
min.value
+
VRST
–
VRST
No reset
Program failure may occur.
→ Normal operation
VDD
Recommended
operatng condition
min.value
+
VRST
–
VRST
Reset
Fig. 55 VDD and VRST–
Rev.1.01
Sep 17, 2003
page 61 of 130
20
21
22
23
Clock control
Execute the CRCK instruction in the initial setting routine of program (executing it in address 0 in page 0 is recommended).
The oscillation circuit by the CRCK instruction can be selected
only once.
Ring oscillator
The clock frequency of the ring oscillator depends on the supply
voltage and the operation temperature range.
Be careful that variable frequencies when designing application
products.
Also, the oscillation stabilize wait time after system is released
from reset is generated by the ring oscillator clock. When considering the oscillation stabilize wait time after system is released
from reset, be careful that the variable frequency of the ring oscillator clock.
External clock
When the external signal clock is used as the source oscillation
(f(XIN)), note that the power down mode (POF and POF2 instructions) cannot be used.
Difference between Mask ROM version and One Time PROM version
Mask ROM version and One Time PROM version have some difference of the following characteristics within the limits of an
electrical property by difference of a manufacture process, builtin ROM, and a layout pattern.
• a characteristic value
• a margin of operation
• the amount of noise-proof
• noise radiation, etc.,
Accordingly, be careful of them when swithcing.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
CONTROL REGISTERS
Interrupt control register V1
V13
Timer 2 interrupt enable bit
V12
Timer 1 interrupt enable bit
V11
Not used
V10
External 0 interrupt enable bit
at reset : 00002
0
1
0
1
0
1
0
1
Interrupt control register V2
V23
Not used
V22
Not used
V21
Not used
V20
Timer 3 interrupt enable bit
I12
I11
I10
INT pin input control bit (Note 2)
Interrupt valid waveform for INT pin/
return level selection bit (Note 3)
INT pin edge detection circuit control bit
INT pin Timer 1 count start synchronous
circuit selection bit
Clock control register MR
MR3
Operation mode selection bits
MR2
MR3
System clock selection bits (Note 3)
MR2
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
at power down : 00002
0
1
0
1
0
1
0
1
Sep 17, 2003
page 62 of 130
R/W
TAV2/TV2A
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid)
at reset : 00002
0
1
at power down : state retained
R/W
TAI1/TI1A
INT pin input disabled
INT pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI0
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI0
0
1
instruction)
0
1
0
1
One-sided edge detected
Both edges detected
Timer 1 count start synchronous circuit not selected
Timer 1 count start synchronous circuit selected
at reset : 11002
MR3 MR2
0
0
0
1
1
0
1
1
MR1 MR0
0
0
0
1
1
0
1
1
at power down : state retained
Operation mode
Through mode
Frequency divided by 2 mode
Frequency divided by 4 mode
Frequency divided by 8 mode
System clock
f(RING)
f(XIN)
f(XCIN)
Not available (Note 4)
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 and I13 are changed, the external interrupt request flag (EXF0) may be set.
3: The stopped clock cannot be selected for system clock.
4: “11” cannot be set to the low-order 2 bits (MR1, MR0) of register MR.
Rev.1.01
R/W
TAV1/TV1A
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
at reset : 00002
Interrupt control register I1
I13
at power down : 00002
R/W
TAMR/
TMRA
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
Clock control register RG
RG2
Sub-clock (f(XCIN)) control bit (Note 2)
RG1
Main-clock (f(XIN)) control bit (Note 2)
RG0
Ring oscillator (f(RING)) control bit
(Note 2)
Prescaler control bit
Timer 1 count auto-stop circuit selection
bit (Note 3)
W12
Timer 1 control bit
W11
W10
Timer 1 count source selection bits
(Note 4)
CNTR pin output control bit
W22
PWM signal interrupt valid waveform/
return level selection bit
W21
Timer 2 control bit
W20
Timer 2 count soruce selection bit
Timer 3 count auto-stop circuit selection
bit
W32
Timer 3 control bit
W31
Timer 3 count source selection bits
W30
W
TPAA
at power down : state retained
R/W
TAW1/TW1A
Stop (state initialized)
Operating
0
1
0
1
Timer 1 count auto-stop circuit not selected
Timer 1 count auto-stop circuit selected
Stop (state retained)
Operating
W11 W10
Count source
0
PWM signal (PWMOUT)
0
0
Prescaler output (ORCLK)
1
1
Timer 3 underflow signal (T3UDF)
0
1
CNTR input
1
at power down : 00002
at reset : 00002
0
1
0
1
0
1
0
1
Timer control register W3
W33
at power down : 02
at reset : 00002
Timer control register W2
W23
at reset : 02
0
1
Timer control register W1
W13
at power down : state retained
0
1
0
1
0
1
Timer control register PA
PA0
W
TRGA
Sub-clock (f(XCIN)) oscillation available, ports D6 and D7 not selected
Sub-clock (f(XCIN)) oscillation stop, ports D6 and D7 selected
Main clock (f(XIN)) oscillation available
Main clock (f(XIN)) oscillation stop
Ring oscillator (f(RING)) oscillation available
Ring oscillator (f(RING)) oscillation stop
at reset : 0002
CNTR pin output invalid
CNTR pin output valid
PWM signal “H” interval expansion function invalid
PWM signal “H” interval expansion function valid
Stop (state retained)
Operating
XIN input
Prescaler output (ORCLK)/2 signal output
at reset : 00002
0
1
0
1
W31 W30
0
0
0
1
1
0
1
1
at power down : state retained
XCIN input
Prescaler output (ORCLK)
Stop (Initial state)
Operating
Count source
Underflow occurs every 8192 counts
Underflow occurs every 16384 counts
Underflow occurs every 32768 counts
Underflow occurs every 65536 counts
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: The oscillation circuit selected for system clock cannot be stopped.
3: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”).
4: Port C output is invalid when CNTR input is selected for the timer 1 count source.
Rev.1.01
Sep 17, 2003
page 63 of 130
R/W
TAW2/TW2A
R/W
TAW3/TW3A
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
Timer control register W4
W43
Timer LC control bit
W42
Timer LC count source selection bit
W41
CNTR output auto-control circuit
selection bit
W40
CNTR pin input count edge selection bit
Internal dividing resistor for LCD power
supply selection bit (Note 2)
L12
LCD control bit
L11
LCD duty and bias selection bits
L10
at reset : 00002
L23
SEG0/VLC3 pin function switch bit (Note 3)
L22
SEG1/VLC2 pin function switch bit (Note 4)
L21
SEG2/VLC1 pin function switch bit (Note 4)
L20
Internal dividing resistor for LCD power
supply control bit
P23/SEG20 pin function switch bit
L32
P22/SEG19 pin function switch bit
L31
P21/SEG18 pin function switch bit
L30
P20/SEG17 pin function switch bit
Duty
L11 L10
0
0
0
1
1
0
1
1
0
1
0
1
0
1
0
1
Sep 17, 2003
page 64 of 130
1/2
1/3
1/3
at power down : state retained
W
TL2A
SEG0
VLC3
SEG1
VLC2
SEG2
VLC1
Internal dividing resistor valid
Internal dividing resistor invalid
SEG20
P23
SEG19
P22
SEG18
P21
SEG17
P20
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: “r (resistor) multiplied by 3” is used at 1/3 bias, and “r multiplied by 2” is used at 1/2 bias.
3: VLC3 is connected to VDD internally when SEG0 pin is selected.
4: Use internal dividing resistor when SEG1 and SEG2 pins are selected.
Rev.1.01
Bias
1/2
1/3
1/4
at reset : 11112
0
1
0
1
0
1
0
1
R/W
TAL1/TL1A
Not available
at reset : 00002
LCD control register L3
L33
at power down : state retained
2r ✕ 3, 2r ✕ 2
r ✕ 3, r ✕ 2
Stop
Operating
0
1
0
1
LCD control register L2
R/W
TAW4/TW4A
Stop (state retained)
Operating
Bit 4 (T34) of timer 3
System clock (STCK)
CNTR output auto-control circuit not selected
CNTR output auto-control circuit selected
Falling edge
Rising edge
0
1
0
1
0
1
0
1
LCD control register L1
L13
at power down : state retained
at reset : 00002
at power down : state retained
W
TL3A
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
at reset : 11112
LCD control register C1
C13
P03/SEG24 pin function switch bit
C12
P02/SEG23 pin function switch bit
C11
P01/SEG22 pin function switch bit
C10
P00/SEG21 pin function switch bit
0
1
0
1
0
1
0
1
C23
P13/SEG28 pin function switch bit
C22
P12/SEG27 pin function switch bit
C21
P11/SEG26 pin function switch bit
C20
P10/SEG25 pin function switch bit
0
1
0
1
0
1
0
1
PU02
PU01
PU00
Port P03 pull-up transistor
0
control bit
1
0
Port P02 pull-up transistor
PU12
PU11
PU10
SEG28
P13
SEG27
P12
SEG26
P11
SEG25
P10
Pull-up transistor ON
Pull-up transistor OFF
control bit
1
Port P00 pull-up transistor
0
Pull-up transistor ON
Pull-up transistor OFF
control bit
1
Pull-up transistor ON
at reset : 00002
Port P13 pull-up transistor
0
Pull-up transistor OFF
control bit
1
Port P12 pull-up transistor
0
Pull-up transistor ON
Pull-up transistor OFF
control bit
1
0
Pull-up transistor ON
control bit
Port P10 pull-up transistor
1
Pull-up transistor ON
0
Pull-up transistor OFF
control bit
1
Pull-up transistor ON
Sep 17, 2003
page 65 of 130
R/W
TAPU0/
TPU0A
at power down : state retained
R/W
TAPU1/
TPU1A
Pull-up transistor OFF
0
Port P11 pull-up transistor
at power down : state retained
Pull-up transistor OFF
Pull-up transistor ON
1
Note: “W” represents write enabled.
Rev.1.01
W
TC2A
control bit
Port P01 pull-up transistor
Pull-up control register PU1
PU13
at power down : state retained
SEG21
P00
at reset : 00002
Pull-up control register PU0
PU03
W
TC1A
SEG24
P03
SEG23
P02
SEG22
P01
at reset : 11112
LCD control register C2
at power down : state retained
Pull-up transistor OFF
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
at reset : 00002
Port output structure control register FR0
FR03
FR02
FR01
FR00
Ports P12, P13 output structure selection
0
N-channel open-drain output
bit
1
Ports P10, P11 output structure selection
0
CMOS output
N-channel open-drain output
bit
1
0
CMOS output
bit
Ports P00, P01 output structure selection
1
CMOS output
0
N-channel open-drain output
bit
1
CMOS output
Ports P02, P03 output structure selection
Port output structure control register FR1
FR13
Port D3 output structure selection bit
FR12
Port D2 output structure selection bit
FR11
Port D1 output structure selection bit
FR10
Port D0 output structure selection bit
FR22
Ports P22, P23 output structure selection bit
Ports P20, P21 output structure selection bit
FR21
Port D5 output structure selection bit
FR20
Port D4 output structure selection bit
Note: “W” represents write enabled.
Rev.1.01
Sep 17, 2003
page 66 of 130
at power down : state retained
0
N-channel open-drain output
1
CMOS output
0
N-channel open-drain output
CMOS output
1
0
1
N-channel open-drain output
0
N-channel open-drain output
1
CMOS output
at power down : state retained
0
1
N-channel open-drain output
0
N-channel open-drain output
1
CMOS output
0
N-channel open-drain output
CMOS output
0
1
W
TFR1A
CMOS output
at reset : 00002
1
W
TFR0A
N-channel open-drain output
at reset : 00002
Port output structure control register FR2
FR23
at power down : state retained
CMOS output
N-channel open-drain output
CMOS output
W
TFR2A
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
Key-on wakeup control register K0
K03
K02
K01
K00
at reset : 00002
Port P12, P13 key-on wakeup
0
Key-on wakeup not used
control bit
Port P10, P11 key-on wakeup
1
Key-on wakeup used
0
Key-on wakeup not used
control bit
1
Key-on wakeup used
Port P02, P03 key-on wakeup
Key-on wakeup not used
control bit
0
1
Port P00, P01 key-on wakeup
0
Key-on wakeup used
Key-on wakeup not used
control bit
1
Key-on wakeup used
at reset : 00002
Key-on wakeup control register K1
K13
K12
Returned by edge
Returned by level
Ports P12, P13 valid waveform/level
1
0
selection bit
1
0
Rising waveform/“H” level
Returned by edge
1
Returned by level
0
Falling waveform/“L” level
1
Rising waveform/“H” level
Ports P10, P11 return condition selection bit
K10
Ports P10, P11 valid waveform/level
selection bit
0
1
K23
Not used
K22
Not used
K21
INT pin return condition selection bit
0
1
INT pin key-on wakeup control bit
Sep 17, 2003
page 67 of 130
This bit has no function, but read/write is enabled.
Returned by level
1
Returned by edge
Key-on wakeup invalid
Note: “R” represents read enabled, and “W” represents write enabled.
at power down : state retained
This bit has no function, but read/write is enabled.
0
0
1
R/W
TAK0/
TK0A
R/W
TAK1/
TK1A
Falling waveform/“L” level
at reset : 00002
Key-on wakeup control register K2
Rev.1.01
at power down : state retained
0
Ports P12, P13 return condition selection bit
K11
K20
at power down : state retained
Key-on wakeup valid
R/W
TAK2/
TK2A
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
INSTRUCTIONS
SYMBOL
The 4556 Group has the 124 (123) instructions. Each instruction is
described as follows;
(1) Index list of instruction function
(2) Machine instructions (index by alphabet)
(3) Machine instructions (index by function)
(4) Instruction code table
The symbols shown below are used in the following list of instruction function and the machine instructions.
Symbol
A
B
DR
E
V1
V2
I1
MR
RG
PA
W1
W2
W3
W4
L1
L2
L3
C1
C2
PU0
PU1
FR0
FR1
FR2
K0
K1
K2
X
Y
Z
DP
PC
PCH
PCL
SK
SP
CY
UPTF
RPS
R1
R3
R2L
R2H
RLC
Contents
Register A (4 bits)
Register B (4 bits)
Register DR (3 bits)
Register E (8 bits)
Interrupt control register V1 (4 bits)
Interrupt control register V2 (4 bits)
Interrupt control register I1 (4 bits)
Clock control register MR (4 bits)
Clock control register RG (3 bits)
Timer control register PA (1 bit)
Timer control register W1 (4 bits)
Timer control register W2 (4 bits)
Timer control register W3 (4 bits)
Timer control register W4 (4 bits)
LCD control register L1 (4 bits)
LCD control register L2 (4 bits)
LCD control register L3 (4 bits)
LCD control register C1 (4 bits)
LCD control register C2 (4 bits)
Pull-up control register PU0 (4 bits)
Pull-up control register PU1 (4 bits)
Port output format control register FR0 (4 bits)
Port output format control register FR1 (4 bits)
Port output format control register FR2 (4 bits)
Key-on wakeup control register K0 (4 bits)
Key-on wakeup control register K1 (4 bits)
Key-on wakeup control register K2 (4 bits)
Register X (4 bits)
Register Y (4 bits)
Register Z (2 bits)
Data pointer (10 bits)
(It consists of registers X, Y, and Z)
Program counter (14 bits)
High-order 7 bits of program counter
Low-order 7 bits of program counter
Stack register (14 bits ✕ 8)
Stack pointer (3 bits)
Carry flag
High-order bit reference enable flag
Prescaler reload register (8 bits)
Timer 1 reload register (8 bits)
Timer 3 reload register (8 bits)
Timer 2 reload register (8 bits)
Timer 2 reload register (8 bits)
Timer LC reload register (4 bits)
Symbol
PS
T1
T2
T3
TLC
T1F
T2F
T3F
WDF1
WEF
INTE
EXF0
P
Contents
Prescaler
Timer 1
Timer 2
Timer 3
Timer LC
Timer 1 interrupt request flag
Timer 2 interrupt request flag
Timer 3 interrupt request flag
Watchdog timer flag
Watchdog timer enable flag
Interrupt enable flag
External 0 interrupt request flag
Power down flag
D
P0
P1
P2
C
Port D (8 bits)
Port P0 (4 bits)
Port P1 (4 bits)
Port P2 (4 bits)
Port C (1 bit)
x
y
z
p
n
i
j
A 3 A 2A 1A 0
Hexadecimal variable
Hexadecimal variable
Hexadecimal variable
Hexadecimal variable
Hexadecimal constant
Hexadecimal constant
Hexadecimal constant
Binary notation of hexadecimal variable A
(same for others)
←
↔
?
( )
—
M(DP)
a
p, a
Direction of data movement
Data exchange between a register and memory
Decision of state shown before “?”
Contents of registers and memories
Negate, Flag unchanged after executing instruction
RAM address pointed by the data pointer
Label indicating address a6 a5 a4 a3 a2 a1 a0
Label indicating address a6 a5 a4 a3 a2 a1 a0
in page p5 p4 p3 p2 p1 p0
Hex. C + Hex. number x
C
+
x
Note : Some instructions of the 4556 Group has the skip function to unexecute the next described instruction. The 4556 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip
is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped.
Rev.1.01
Sep 17, 2003
page 68 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
INDEX LIST OF INSTRUCTION FUNCTION
Register to register transfer
TAB
Function
(A) ← (B)
Page
GroupMnemonic
ing
88, 104
TBA
(B) ← (A)
95, 104
TAY
(A) ← (Y)
94, 104
TYA
(Y) ← (A)
102, 104
TEAB
(E7–E4) ← (B)
96, 104
XAMI j
RAM to register transfer
GroupMnemonic
ing
(E3–E0) ← (A)
TABE
(B) ← (E7–E4)
TDA
(DR2–DR0) ← (A2–A0)
96, 104
TAD
(A2–A0) ← (DR2–DR0)
90, 104
j = 0 to 15
(Y) ← (Y) + 1
TMA j
94, 104
TASP
(A2–A0) ← (SP2–SP0)
92, 104
78, 104
RAM addresses
(Y) ← y y = 0 to 15
Arithmetic operation
(A) ← (X)
(A3) ← 0
LA n
(A) ← n
n = 0 to 15
78, 106
TABP p
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
at (UPTF) = 0
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
at (UPTF) = 1
(DR2) ← (0)
(DR1, DR0) ← (ROM(PC))9, 8
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
89, 106
AM
(A) ← (A) + (M(DP))
73, 106
AMC
(A) ← (A) + (M(DP)) + (CY)
73, 106
(CY) ← Carry
An
(A) ← (A) + n
73, 106
n = 0 to 15
LZ z
(Z) ← z z = 0 to 3
79, 104
INY
(Y) ← (Y) + 1
78, 104
AND
(A) ← (A) AND (M(DP))
73, 106
DEY
(Y) ← (Y) – 1
76, 104
OR
(A) ← (A) OR (M(DP))
80, 106
TAM j
(A) ← (M(DP))
91, 104
SC
(CY) ← 1
83, 106
RC
(CY) ← 0
81, 106
SZC
(CY) = 0 ?
87, 106
CMA
(A) ← (A)
75, 106
RAR
→ CY → A3A2A1A0
81, 106
(X) ← (X)EXOR(j)
RAM to register transfer
99, 104
j = 0 to 15
95, 104
TAX
(X) ← x x = 0 to 15
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
(A3, A2) ← 0
LXY x, y
103, 104
(X) ← (X)EXOR(j)
(A3) ← 0
(A1, A0) ← (Z1, Z0)
(A) ← → (M(DP))
Page
89, 104
(A) ← (E3–E0)
TAZ
Function
j = 0 to 15
XAM j
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
103, 104
j = 0 to 15
XAMD j
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1
Note: p is 0 to 31 for M34556M4/M4H.
p is 0 to 63 for M34556M8/M8H/G8/G8H.
Rev.1.01
Sep 17, 2003
page 69 of 130
103, 104
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Branch operation
Page
GroupMnemonic
ing
DI
(INTE) ← 0
76, 110
EI
(INTE) ← 1
77, 110
SNZ0
V10 = 0: (EXF0) = 1 ?
84, 110
SB j
(Mj(DP)) ← 1
j = 0 to 3
83, 106
RB j
(Mj(DP)) ← 0
81, 106
j = 0 to 3
SZB j
(Mj(DP)) = 0 ?
j = 0 to 3
87, 106
SEAM
(A) = (M(DP)) ?
84, 106
SEA n
(A) = n ?
84, 106
After skipping, (EXF0) ← 0
V10 = 1: NOP
SNZI0
I12 = 1 : (INT) = “H” ?
85, 110
I12 = 0 : (INT) = “L” ?
93, 110
TV1A
(V1) ← (A)
101, 110
TAV2
(A) ← (V2)
93, 110
TV2A
(V2) ← (A)
101, 110
TAI1
(A) ← (I1)
90, 110
TI1A
(I1) ← (A)
97, 110
(SK(SP)) ← (PC)
TPAA
(PA) ← (A)
99, 112
(PCH) ← 2
(PCL) ← a6–a0
TAW1
(A) ← (W1)
93, 112
TW1A
(W1) ← (A)
101, 112
TAW2
(A) ← (W2)
93, 112
TW2A
(W2) ← (A)
102, 112
TAW3
(A) ← (W3)
94, 112
TW3A
(W3) ← (A)
102, 112
TAW4
(A) ← (W4)
94, 112
TW4A
(W4) ← (A)
102, 112
(B) ← (TPS7–TPS4)
90, 112
(PCL) ← a6–a0
74, 108
BL p, a
(PCH) ← p
74, 108
(PCL) ← a6–a0
(PCH) ← p
74, 108
(PCL) ← (DR2–DR0, A3–A0)
BML p, a
(SP) ← (SP) + 1
(SP) ← (SP) + 1
74, 108
75, 108
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← a6–a0
BMLA p
(SP) ← (SP) + 1
75, 108
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
RTI
(PC) ← (SK(SP))
82, 108
(SP) ← (SP) – 1
(PC) ← (SK(SP))
RT
Timer operation
(SK(SP)) ← (PC)
82, 108
(SP) ← (SP) – 1
Return operation
Page
(A) ← (V1)
Ba
BLA p
Function
TAV1
n = 0 to 15
BM a
Subroutine operation
Function
Interrupt operation
Comparison
operation
Bit operation
GroupMnemonic
ing
TABPS
(A) ← (TPS3–TPS0)
RTS
(PC) ← (SK(SP))
(SP) ← (SP) – 1
TPSAB
(RPS7–RPS4) ← (B)
(TPS7–TPS4) ← (B)
(RPS3–RPS0) ← (A)
(TPS3–TPS0) ← (A)
Note: p is 0 to 31 for M34556M4/M4H.
p is 0 to 63 for M34556M8/M8H/G8/G8H.
Rev.1.01
82, 108
Sep 17, 2003
page 70 of 130
100, 112
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Grouping Mnemonic
TAB1
Function
(B) ← (T17–T14)
Page
GroupMnemonic
ing
89, 112
Function
Page
CLD
(D) ← 1
75, 114
RD
(D(Y)) ← 0
(Y) = 0 to 7
82, 114
SD
(D(Y)) ← 1
84, 114
(A) ← (T13–T10)
T1AB
(R17–R14) ← (B)
87, 112
(T17–T14) ← (B)
(R13–R10) ← (A)
(T13–T10) ← (A)
TAB2
(B) ← (T27–T24)
(Y) = 0 to 7
89, 112
SZD
(D(Y)) = 0 ?
(Y) = 0 to 7
87, 114
88, 112
RCP
(C) ← 0
81, 114
SCP
(C) ← 1
83, 114
TAPU0
(A) ← (PU0)
92, 114
TPU0A
(PU0) ← (A)
100, 114
TAPU1
(A) ← (PU1)
92, 114
TPU1A
(PU1) ← (A)
100, 114
TAK0
(A) ← (K0)
90, 114
TK0A
(K0) ← (A)
97, 114
TAK1
(A) ← (K1)
91, 114
TK1A
(K1) ← (A)
97, 114
TAK2
(A) ← (K2)
91, 114
TK2A
(K2) ← (A)
98, 114
TFR0A
(FR0) ← (A)
96, 114
TFR1A
(FR1) ← (A)
96, 114
TFR2A
(FR2) ← (A)
97, 114
CRCK
RC oscillator selected
76, 116
TAMR
(A) ← (MR)
92, 116
TMRA
(MR) ← (A)
99, 116
TRGA
(RG) ← (A)
101, 116
(A) ← (T23–T20)
T2AB
(R27–R24) ← (B)
(T27–T24) ← (B)
(R23–R20) ← (A)
(T23–T20) ← (A)
(R2H7–R2H4) ← (B)
88, 112
(R2H3–R2H0) ← (A)
TR1AB
(R17–R14) ← (B)
100, 112
(R13–R10) ← (A)
T2R2L
TLCA
(T27–T24) ← (R2L7–R2L4)
(T23–T20) ← (R2L3–R2L0)
88, 112
(LC) ← (A)
99, 112
Input/Output operation
Timer operation
T2HAB
(RLC) ← (A)
SNZT1
V12 = 0: (T1F) = 1 ?
After skipping, (T1F) ← 0
85, 112
V12 = 1: NOP
SNZT2
V13 = 0: (T2F) = 1 ?
85, 112
After skipping, (T2F) ← 0
V13 = 1: NOP
SNZT3
V20 = 0: (T3F) = 1 ?
86, 112
After skipping, (T3F) ← 0
IAP0
(A) ← (P0)
77, 114
OP0A
(P0) ← (A)
79, 114
IAP1
(A) ← (P1)
77, 114
OP1A
(P1) ← (A)
79, 114
IAP2
(A) ← (P2)
78, 114
OP2A
(P2) ← (A)
80, 114
Rev.1.01
Sep 17, 2003
page 71 of 130
Clock operation
Input/Output operation
V20 = 1: NOP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Other operation
LCD operation
Grouping Mnemonic
Function
Page
TAL1
(A) ← (L1)
91, 116
TL1A
(L1) ← (A)
98, 116
TL2A
(L2) ← (A)
98, 116
TL3A
(L3) ← (A)
98, 116
TC1A
(C1) ← (A)
95, 116
TC2A
(C2) ← (A)
95, 116
NOP
(PC) ← (PC) + 1
79, 116
POF
Transition to clock operating mode
80, 116
POF2
Transition to RAM back-up mode
80, 116
EPOF
POF, POF2 instructions valid
77, 116
SNZP
(P) = 1 ?
85, 116
DWDT
Stop of watchdog timer function
enabled
76, 116
SRST
System reset
86,116
WRST
(WDF1) = 1 ?
103, 116
After skipping, (WDF1) ← 0
RUPT
(UPTF) ← 0
83, 116
SUPT
(UPTF) ← 1
86, 116
SVDE
At power down mode, voltage
drop detection circuit valid
86, 116
(Note)
Note: The SVDE instruction can be used only for the H version.
Rev.1.01
Sep 17, 2003
page 72 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET)
A n (Add n and accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
1
1
0
n
n
n
n
2
0
6
n
16
(A) ← (A) + n
n = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
Overflow = 0
Grouping:
Arithmetic operation
Description: Adds the value n in the immediate field to
register A, and stores a result in register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no
overflow as the result of operation.
Executes the next instruction when there is
overflow as the result of operation.
AM (Add accumulator and Memory)
Instruction
code
Operation:
D0
D9
0
0
0
0
0
0
1
0
1
0
2
0
0
A
16
(A) ← (A) + (M(DP))
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Arithmetic operation
Description: Adds the contents of M(DP) to register A.
Stores the result in register A. The contents
of carry flag CY remains unchanged.
AMC (Add accumulator, Memory and Carry)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
1
0
1
1
2
0
0
B
16
(A) ← (A) + (M(DP)) + (CY)
(CY) ← Carry
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
0/1
–
Grouping:
Arithmetic operation
Description: Adds the contents of M(DP) and carry flag
CY to register A. Stores the result in register A and carry flag CY.
AND (logical AND between accumulator and memory)
Instruction
code
Operation:
Rev.1.01
D9
0
D0
0
0
0
0
1
1
(A) ← (A) AND (M(DP))
Sep 17, 2003
page 73 of 130
0
0
0
2
0
1
8
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Arithmetic operation
Description: Takes the AND operation between the contents of register A and the contents of
M(DP), and stores the result in register A.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
B a (Branch to address a)
Instruction
code
Operation:
D9
0
D0
1
1
a6 a5 a4 a3 a2 a1 a0
2
1
8
+a
a
16
(PCL) ← a6 to a0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Branch operation
Description: Branch within a page : Branches to address
a in the identical page.
Note:
Specify the branch address within the page
including this instruction.
BL p, a (Branch Long to address a in page p)
Instruction
code
D9
0
1
Operation:
D0
0
0
1
1
1
p4 p3 p2 p1 p0
2
p5 a6 a5 a4 a3 a2 a1 a0 2
0
E
+p
p
2
p
+a
a 16
0
1
0
2
p
p 16
16
(PCH) ← p
(PCL) ← a6 to a0
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
Grouping:
Branch operation
Description: Branch out of a page : Branches to address
a in page p.
Note:
p is 0 to 31 for M34556M4/M4H and p is 0
to 63 for M34556M8/M8H/G8/G8H.
BLA p (Branch Long to address (D) + (A) in page p)
Instruction
code
Operation:
D9
D0
0
0
0
0
0
1
0
0
0
0
1
0
p5 p4 0
0
p3 p2 p1 p0 2
2
16
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
Grouping:
Branch operation
Description: Branch out of a page : Branches to address
(DR2 DR 1 DR 0 A3 A2 A 1 A0 )2 specified by
registers D and A in page p.
Note:
p is 0 to 31 for M34556M4/M4H and p is 0
to 63 for M34556M8/M8H/G8/G8H.
BM a (Branch and Mark to address a in page 2)
Instruction
code
Operation:
Rev.1.01
D9
0
D0
1
0
a6 a5 a4 a3 a2 a1 a0
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
(PCL) ← a6–a0
Sep 17, 2003
page 74 of 130
2
1
a
a
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Subroutine call operation
Description: Call the subroutine in page 2 : Calls the
subroutine at address a in page 2.
Note:
Subroutine extending from page 2 to another page can also be called with the BM
instruction when it starts on page 2.
Be careful not to over the stack because the
maximum level of subroutine nesting is 8.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
BML p, a (Branch and Mark Long to address a in page p)
Instruction
code
D9
0
1
Operation:
D0
0
0
1
1
0
p4 p3 p2 p1 p0
2
p5 a6 a5 a4 a3 a2 a1 a0 2
0
C
+p
p
2
p
+a
a 16
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
16
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← a6–a0
Grouping:
Subroutine call operation
Description: Call the subroutine : Calls the subroutine at
address a in page p.
Note:
p is 0 to 31 for M34556M4/M4H and p is 0
to 63 for M34556M8/M8H/G8/G8H.
Be careful not to over the stack because the
maximum level of subroutine nesting is 8.
BMLA p (Branch and Mark Long to address (D) + (A) in page p)
Instruction
code
Operation:
D0
D9
0
0
0
0
1
1
0
0
0
0
1
0
p5 p4 0
0
p3 p2 p1 p0 2
2
0
3
0
2
p
p 16
16
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
Grouping:
Subroutine call operation
Description: Call the subroutine : Calls the subroutine at
address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p.
Note:
p is 0 to 31 for M34556M4/M4H and p is 0
to 63 for M34556M8/M8H/G8/G8H.
Be careful not to over the stack because the
maximum level of subroutine nesting is 8.
CLD (CLear port D)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
0
0
0
1
2
0
1
1
16
(D) ← 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Sets (1) to port D.
CMA (CoMplement of Accumulator)
Instruction
code
Operation:
Rev.1.01
D9
0
D0
0
0
0
0
1
1
(A) ← (A)
Sep 17, 2003
1
0
0
2
0
1
C
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Arithmetic operation
Description: Stores the one’s complement for register
A’s contents in register A.
page 75 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
CRCK (Clock select: Rc oscillation ClocK)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
1
1
0
1
1
2
2
9
B 16
RC oscillation circuit selected
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Clock control operation
Description: Selects the RC oscillation circuit for main
clock f(XIN).
DEY (DEcrement register Y)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
0
1
1
1
2
0
1
7
16
(Y) ← (Y) – 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 15
Grouping:
RAM addresses
Description: Subtracts 1 from the contents of register Y.
As a result of subtraction, when the contents of register Y is 15, the next instruction
is skipped. When the contents of register Y
is not 15, the next instruction is executed.
DI (Disable Interrupt)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
1
0
0
2
0
0
4
16
(INTE) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt control operation
Description: Clears (0) to interrupt enable flag INTE, and
disables the interrupt.
Note:
Interrupt is disabled by executing the DI instruction after executing 1 machine cycle.
DWDT (Disable WatchDog Timer)
Instruction
code
Operation:
Rev.1.01
D9
1
D0
0
1
0
0
1
1
1
0
0
Stop of watchdog timer function enabled
Sep 17, 2003
page 76 of 130
2
2
9
C
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Stops the watchdog timer function by the
WRST instruction after executing the
DWDT instruction.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
EI (Enable Interrupt)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
1
0
1
2
0
0
5 16
(INTE) ← 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt control operation
Description: Sets (1) to interrupt enable flag INTE, and
enables the interrupt.
Note:
Interrupt is enabled by executing the EI instruction after executing 1 machine cycle.
EPOF (Enable POF instruction)
Instruction
code
Operation:
D0
D9
0
0
0
1
0
1
1
0
1
1
2
0
5
B
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Makes the immediate after POF instruction
or POF2 instruction valid by executing the
EPOF instruction.
POF instruction, POF2 instruction valid
IAP0 (Input Accumulator from port P0)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
0
0
0
0
0
2
2
6
0
16
(A) ← (P0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the input of port P0 to register A.
IAP1 (Input Accumulator from port P1)
Instruction
code
Operation:
Rev.1.01
D9
1
D0
0
0
1
1
0
0
(A) ← (P1)
Sep 17, 2003
0
0
1
2
2
6
1
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the input of port P1 to register A.
page 77 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
IAP2 (Input Accumulator from port P2)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
0
0
0
1
0
2
2
6
2 16
(A) ← (P2)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the input of port P2 to register A.
INY (INcrement register Y)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
0
0
1
1
2
0
1
3
16
(Y) ← (Y) + 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 0
Grouping:
RAM addresses
Description: Adds 1 to the contents of register Y. As a result of addition, when the contents of
register Y is 0, the next instruction is
skipped. When the contents of register Y is
not 0, the next instruction is executed.
LA n (Load n in Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
1
1
1
n
n
n
n
2
0
7
n
16
(A) ← n
n = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
Continuous
description
Grouping:
Arithmetic operation
Description: Loads the value n in the immediate field to
register A.
When the LA instructions are continuously
coded and executed, only the first LA instruction is executed and other LA
instructions coded continuously are
skipped.
LXY x, y (Load register X and Y with x and y)
Instruction
code
Operation:
Rev.1.01
D9
1
D0
1
x3 x2 x1 x0 y3 y2 y1 y0
(X) ← x x = 0 to 15
(Y) ← y y = 0 to 15
Sep 17, 2003
page 78 of 130
2
3
x
y
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
Continuous
description
Grouping:
RAM addresses
Description: Loads the value x in the immediate field to
register X, and the value y in the immediate
field to register Y. When the LXY instructions are continuously coded and executed,
only the first LXY instruction is executed
and other LXY instructions coded continuously are skipped.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
LZ z (Load register Z with z)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
0
1
0
z1 z0
2
0
4
8
+z 16
(Z) ← z z = 0 to 3
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
RAM addresses
Description: Loads the value z in the immediate field to
register Z.
NOP (No OPeration)
Instruction
code
Operation:
D0
D9
0
0
0
0
0
0
0
0
0
0
2
0
0
0
16
(PC) ← (PC) + 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: No operation; Adds 1 to program counter
value, and others remain unchanged.
OP0A (Output port P0 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
0
0
0
0
2
2
2
0
16
(P0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Outputs the contents of register A to port
P0.
OP1A (Output port P1 from Accumulator)
Instruction
code
Operation:
Rev.1.01
D9
1
D0
0
0
0
1
0
0
(P1) ← (A)
Sep 17, 2003
0
0
1
2
2
2
1
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Outputs the contents of register A to port
P1.
page 79 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
OP2A (Output port P2 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
0
0
1
0
2
2
2
2
16
(P2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Outputs the contents of register A to port
P2.
OR (logical OR between accumulator and memory)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
1
0
0
1 2
0
1
9 16
(A) ← (A) OR (M(DP))
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Arithmetic operation
Description: Takes the OR operation between the contents of register A and the contents of
M(DP), and stores the result in register A.
POF (Power OFf)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
0
1
0
2
0
0
2
16
Transition to clock operating mode
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Puts the system in clock operating mode by
executing the POF2 instruction after executing the EPOF instruction.
Note:
If the EPOF instruction is not executed before
executing this instruction, this instruction is
equivalent to the NOP instruction.
POF2 (Power OFf2)
Instruction
code
Operation:
Rev.1.01
D9
0
D0
0
0
0
0
0
1
0
Transition to RAM back-up mode
Sep 17, 2003
page 80 of 130
0
0
2
0
0
8
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Puts the system in RAM back-up state by
executing the POF2 instruction after executing the EPOF instruction.
Note:
If the EPOF instruction is not executed before
executing this instruction, this instruction is
equivalent to the NOP instruction.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
RAR (Rotate Accumulator Right)
Instruction
code
D9
D0
0
0
0
0
0
1
1
1
0
1
2
0
1
D
16
→ CY → A3A2A1A0
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
0/1
–
Grouping:
Arithmetic operation
Description: Rotates 1 bit of the contents of register A including the contents of carry flag CY to the
right.
RB j (Reset Bit)
Instruction
code
Operation:
D0
D9
0
0
0
1
0
0
1
1
j
j
2
0
4
C
+j 16
(Mj(DP)) ← 0
j = 0 to 3
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Bit operation
Description: Clears (0) the contents of bit j (bit specified
by the value j in the immediate field) of
M(DP).
RC (Reset Carry flag)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
1
1
0
2
0
0
6
16
(CY) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
0
–
Grouping:
Arithmetic operation
Description: Clears (0) to carry flag CY.
RCP (Reset Port C)
Instruction
code
Operation:
Rev.1.01
D9
1
D0
0
1
0
0
0
1
(C) ← 0
Sep 17, 2003
1
0
0
2
2
8
C
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
0
–
Grouping:
Input/Output operation
Description: Clears (0) to carry flag CY.
page 81 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
RD (Reset port D specified by register Y)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
0
1
0
0
2
0
1
4
16
(D(Y)) ← 0
However,
(Y) = 0 to 7
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Clears (0) to a bit of port D specified by register Y.
RT (ReTurn from subroutine)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
0
0
1
0
0
2
0
4
4
16
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
2
–
–
Grouping:
Return operation
Description: Returns from subroutine to the routine
called the subroutine.
RTI (ReTurn from Interrupt)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
0
0
1
1
0
2
0
4
6
16
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Return operation
Description: Returns from interrupt service routine to
main routine.
Returns each value of data pointer (X, Y, Z),
carry flag, skip status, NOP mode status by
the continuous description of the LA/LXY instruction, register A and register B to the
states just before interrupt.
RTS (ReTurn from subroutine and Skip)
Instruction
code
Operation:
Rev.1.01
D9
0
D0
0
0
1
0
0
0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Sep 17, 2003
page 82 of 130
1
0
1
2
0
4
5
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
2
–
Skip at uncondition
Grouping:
Return operation
Description: Returns from subroutine to the routine
called the subroutine, and skips the next instruction at uncondition.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
RUPT (Reset UPTF flag)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
1
0
0
0
2
0
5
8
16
(UPTF) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Clears (0) to the high-order bit reference
enable flag.
SB j (Set Bit)
Instruction
code
Operation:
D0
D9
0
0
0
1
0
1
1
1
j
j
2
0
5
C
+j 16
(Mj(DP)) ← 1
j = 0 to 3
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Bit operation
Description: Sets (1) the contents of bit j (bit specified by
the value j in the immediate field) of M(DP).
SC (Set Carry flag)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
1
1
1
2
0
0
7
16
(CY) ← 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
1
–
Grouping:
Arithmetic operation
Description: Sets (1) to carry flag CY.
SCP (Set Port C)
Instruction
code
Operation:
Rev.1.01
D9
1
D0
0
1
0
0
0
1
(C) ← 1
Sep 17, 2003
1
0
1
2
2
8
D
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Sets (1) to port C.
page 83 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SD (Set port D specified by register Y)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
0
1
0
1
2
0
1
5
16
(D(Y)) ← 1
(Y) = 0 to 7
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Sets (1) to a bit of port D specified by register Y.
SEA n (Skip Equal, Accumulator with immediate data n)
Instruction
code
D9
0
0
Operation:
D0
0
0
0
0
0
1
1
1
0
1
0
n
1
n
0
n
1
n
2
2
0
2
5
16
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
(A) = n
n = 0 to 15
0
7
n 16
Grouping:
Comparison operation
Description: Skips the next instruction when the contents of register A is equal to the value n in
the immediate field.
Executes the next instruction when the contents of register A is not equal to the value n
in the immediate field.
0
2
6
(A) = n ?
n = 0 to 15
SEAM (Skip Equal, Accumulator with Memory)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
0
0
1
1
0
2
16
(A) = (M(DP)) ?
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(A) = (M(DP))
Grouping:
Comparison operation
Description: Skips the next instruction when the contents of register A is equal to the contents of
M(DP).
Executes the next instruction when the contents of register A is not equal to the
contents of M(DP).
SNZ0 (Skip if Non Zero condition of external 0 interrupt request flag)
Instruction
code
Operation:
Rev.1.01
D9
0
D0
0
0
0
1
1
1
0
0
0
2
V10 = 0: (EXF0) = 1 ?
After skipping, (EXF0) ← 0
V10 = 1: SNZ0 = NOP
(V10 : bit 0 of the interrupt control register V1)
Sep 17, 2003
page 84 of 130
0
3
8
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V10 = 0: (EXF0) = 1
Grouping:
Interrupt operation
Description: When V10 = 0 : Skips the next instruction
when external 0 interrupt request flag EXF0
is “1.” After skipping, clears (0) to the EXF0
flag. When the EXF0 flag is “0,” executes
the next instruction.
When V1 0 = 1 : This instruction is equivalent to the NOP instruction.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SNZI0 (Skip if Non Zero condition of external 0 Interrupt input pin)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
1
1
0
1
0 2
0
3
A 16
Number of
words
Number of
cycles
Flag CY
1
1
–
Skip condition
I12 = 0 : (INT) = “L”
I12 = 1 : (INT) = “H”
Grouping:
Interrupt operation
Description: When I12 = 0 : Skips the next instruction
when the level of INT pin is “L.” Executes
the next instruction when the level of INT
pin is “H.”
When I12 = 1 : Skips the next instruction
when the level of INT pin is “H.” Executes
the next instruction when the level of INT
pin is “L.”
I12 = 0 : (INT) = “L” ?
I12 = 1 : (INT) = “H” ?
(I12 : bit 2 of the interrupt control register I1)
SNZP (Skip if Non Zero condition of Power down flag)
Instruction
code
Operation:
D0
D9
0
0
0
0
0
0
0
0
1
1
2
0
0
3
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(P) = 1
16
(P) = 1 ?
Grouping:
Other operation
Description: Skips the next instruction when the P flag is
“1”.
After skipping, the P flag remains unchanged.
Executes the next instruction when the P
flag is “0.”
SNZT1 (Skip if Non Zero condition of Timer 1 interrupt request flag)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
0
0
0
0
0
2
2
8
0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V12 = 0: (T1F) = 1
16
V12 = 0: (T1F) = 1 ?
After skipping, (T1F) ← 0
V12 = 1: SNZT1 = NOP
(V12 = bit 2 of interrupt control register V1)
Grouping:
Timer operation
Description: When V12 = 0 : Skips the next instruction
when timer 1 interrupt request flag T1F is
“1.” After skipping, clears (0) to the T1F
flag. When the T1F flag is “0,” executes the
next instruction.
When V12 = 1 : This instruction is equivalent to the NOP instruction.
SNZT2 (Skip if Non Zero condition of Timer 2 interrupt request flag)
Instruction
code
Operation:
Rev.1.01
D9
1
D0
0
1
0
0
0
0
0
0
1
V13 = 0: (T2F) = 1 ?
After skipping, (T2F) ← 0
V13 = 1: SNZT2 = NOP
(V13 = bit 3 of interrupt control register V1)
Sep 17, 2003
page 85 of 130
2
2
8
1
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V13 = 0: (T2F) = 1
Grouping:
Timer operation
Description: When V13 = 0 : Skips the next instruction
when timer 2 interrupt request flag T2F is
“1.” After skipping, clears (0) to the T2F
flag. When the T2F flag is “0,” executes the
next instruction.
When V13 = 1 : This instruction is equivalent to the NOP instruction.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SNZT3 (Skip if Non Zero condition of Timer 3 interrupt request flag)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
0
0
0
1
0
2
2
8
2
16
V20 = 0: (T3F) = 1 ?
After skipping, (T3F) ← 0
V20 = 1: SNZT3 = NOP
(V20 = bit 0 of interrupt control register V2)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V20 = 0: (T3F) = 1
Grouping:
Timer operation
Description: When V20 = 0 : Skips the next instruction
when timer 3 interrupt request flag T3F is
“1.” After skipping, clears (0) to the T3F
flag. When the T3F flag is “0,” executes the
next instruction.
When V20 = 1 : This instruction is equivalent to the NOP instruction.
SRST (System ReSeT)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
0
0
1
2
0
0
1
16
System reset occurrence
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: System reset occurs.
SUPT (Set UPTF flag)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
1
0
0
0
2
0
5
9 16
(UPTF) ← 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Sets (1) to high-order bit reference enable
flag.
SVDE (Se Voltage Detector Enable flag)
Instruction
code
Operation:
Rev.1.01
D9
1
D0
0
1
0
0
1
0
0
1
1
2
2
9
3 16
Voltage drop detection circuit valid at powerdown mode.
Sep 17, 2003
page 86 of 130
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Voltage drop detection circuit is valid at
powerdown mode (clock operating mode,
RAM back-up mode)
Note: This instruction can be used only for H version.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SZB j (Skip if Zero, Bit)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
0
0
0
j
j
2
0
2
j
16
(Mj(DP)) = 0 ?
j = 0 to 3
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Mj(DP)) = 0
j = 0 to 3
Grouping:
Bit operation
Description: Skips the next instruction when the contents of bit j (bit specified by the value j in
the immediate field) of M(DP) is “0.”
Executes the next instruction when the contents of bit j of M(DP) is “1.”
SZC (Skip if Zero, Carry flag)
Instruction
code
Operation:
D0
D9
0
0
0
0
1
0
1
1
1
1
2
0
2
F
16
(CY) = 0 ?
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(CY) = 0
Grouping:
Arithmetic operation
Description: Skips the next instruction when the contents of carry flag CY is “0.”
After skipping, the CY flag remains unchanged.
Executes the next instruction when the contents of the CY flag is “1.“
SZD (Skip if Zero, port D specified by register Y)
Instruction
code
Operation:
D9
D0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
1
0
1
1 2
2
0
2
4
0
2
B 16
16
Number of
words
Number of
cycles
Flag CY
2
2
–
Skip condition
(D(Y)) = 0
(Y) = 0 to 7
Grouping:
Input/Output operation
Description: Skips the next instruction when a bit of port
D specified by register Y is “0.” Executes the
next instruction when the bit is “1.”
(D(Y)) = 0 ?
(Y) = 0 to 7
T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B)
Instruction
code
Operation:
Rev.1.01
D9
1
D0
0
0
0
1
1
0
(T17–T14) ← (B)
(R17–R14) ← (B)
(T13–T10) ← (A)
(R13–R10) ← (A)
Sep 17, 2003
page 87 of 130
0
0
0
2
2
3
0
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 1 and timer 1 reload register R1. Transfers the contents of
register A to the low-order 4 bits of timer 1
and timer 1 reload register R1.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
T2AB (Transfer data to timer 2 and register R2 from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
0
0
0
1
2
2
3
1
16
(R2L7–R2L4) ← (B)
(T27–T24) ← (B)
(R2L3–R2L0) ← (A)
(T23–T20) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 2 and timer 2 reload register R2L. Transfers the contents of
register A to the low-order 4 bits of timer 2
and timer 2 reload register R2L.
T2HAB (Transfer data to register R2H from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
1
0
1
0
0
2
2
9
4 16
(R2H7–R2H4) ← (B)
(R2H3–R2H0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 2 and timer 2 reload register R2H. Transfers the contents of
register A to the low-order 4 bits of timer 2
and timer 2 reload register R2H.
T2R2L (Transfer data to timer 2 from register R2L)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
1
0
1
0
1 2
2
9
5 16
(T27–T20) ← (R2L7–R2L0)
Number of
words
Number of
cycles
Flag CY
1
1
–
Skip condition
–
Grouping:
Timer operation
Description: Transfers the contents of reload register
R2L to timer 2.
TAB (Transfer data to Accumulator from register B)
Instruction
code
Operation:
Rev.1.01
D9
0
D0
0
0
0
0
1
1
(A) ← (B)
Sep 17, 2003
1
1
0 2
0
1
E 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register B to register A.
page 88 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAB1 (Transfer data to Accumulator and register B from timer 1)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
1
0
0
0
0
2
2
7
0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
(B) ← (T17–T14)
(A) ← (T13–T10)
Grouping:
Timer operation
Description: Transfers the high-order 4 bits (T17–T14) of
timer 1 to register B.
Transfers the low-order 4 bits (T13–T10) of
timer 1 to register A.
TAB2 (Transfer data to Accumulator and register B from timer 2)
Instruction
code
Operation:
D0
D9
1
0
0
1
1
1
0
0
0
1
2
2
7
1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
(B) ← (T27–T24)
(A) ← (T23–T20)
Grouping:
Timer operation
Description: Transfers the high-order 4 bits (T27–T24) of
timer 2 to register B.
Transfers the low-order 4 bits (T23–T20) of
timer 2 to register A.
TABE (Transfer data to Accumulator and register B from register E)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
0
1
0
1
0 2
0
2
A 16
(B) ← (E7–E4)
(A) ← (E3–E0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the high-order 4 bits (E 7–E4 ) of
register E to register B, and low-order 4 bits
of register E to register A.
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
Instruction
code
D9
0
D0
0
1
0
p5 p4 p3 p2 p1 p0 2
Operation:
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
at (UPTF) = 0
at (UPTF) = 1
(B) ← (ROM(PC))7–4 (DR2) ← (0)
(A) ← (ROM(PC))3–0 (DR1, DR0) ← (ROM(PC))9, 8
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Rev.1.01
Sep 17, 2003
page 89 of 130
0
8
+p
p 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
3
–
–
Grouping:
Arithmetic operation
Description:
UPTF = 0: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits
9 to 0 are the ROM pattern in ad-dress (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by
registers A and D in page p.
UPTF = 1: Transfers bits 9, 8 to register D, bits 7 to 4 to register B and bits 3 to 0 to
register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2
A1 A0)2 specified by registers A and D in page p.
Note: p is 0 to 31 for M34556M4/M4H, and p is 0 to 63 for M34556M8/M8H/G8/G8H.
When this instruction is executed, be careful not to over the stack because 1
stage of stack register is used.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TABPS (Transfer data to Accumulator and register B from PreScaler)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
1
0
1
0
1 2
2
7
5 16
(B) ← (TPS7–TPS4)
(A) ← (TPS3–TPS0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the high-order 4 bits (TPS 7 –
TPS 4 ) of prescaler to register B, and
transfers the low-order 4 bits (TPS3–TPS0)
of prescaler to register A.
TAD (Transfer data to Accumulator from register D)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
0
0
0
1
2
0
5
1
16
(A2–A0) ← (DR2–DR0)
(A3) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register D to the
low-order 3 bits (A2–A0) of register A.
Note:
When this instruction is executed, “0” is
stored to the bit 3 (A3) of register A.
TAI1 (Transfer data to Accumulator from register I1)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
0
0
1
1
2
2
5
3
16
(A) ← (I1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of interrupt control
register I1 to register A.
TAK0 (Transfer data to Accumulator from register K0)
Instruction
code
Operation:
Rev.1.01
D9
1
D0
0
0
1
0
1
0
(A) ← (K0)
Sep 17, 2003
1
1
0
2
2
5
6
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of key-on wakeup
control register K0 to register A.
page 90 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAK1 (Transfer data to Accumulator from register K1)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
1
0
0
1
2
2
5
9
16
(A) ← (K1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of key-on wakeup
control register K1 to register A.
TAK2 (Transfer data to Accumulator from register K2)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
1
0
1
0
2
2
5
A
16
(A) ← (K2)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of key-on wakeup
control register K2 to register A.
TAL1 (Transfer data to Accumulator from register L1)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
1
0
1
0
2
2
4
A
16
(A) ← (L1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
LCD control operation
Description: Transfers the contents of LCD control register L1 to register A.
TAM j (Transfer data to Accumulator from Memory)
Instruction
code
Operation:
Rev.1.01
D9
1
D0
0
1
1
0
0
j
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
Sep 17, 2003
page 91 of 130
j
j
j
2
2
C
j
16
Number of
words
Number of
cycles
1
1
Flag CY
–
Skip condition
–
Grouping:
RAM to register transfer
Description: After transferring the contents of M(DP) to
register A, an exclusive OR operation is
performed between register X and the value
j in the immediate field, and stores the result in register X.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAMR (Transfer data to Accumulator from register MR)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
0
0
1
0
2
2
5
2
16
(A) ← (MR)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Clock operation
Description: Transfers the contents of clock control register MR to register A.
TAPU0 (Transfer data to Accumulator from register PU0)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
0
1
1
1 2
2
5
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
7 16
(A) ← (PU0)
Grouping:
Input/Output operation
Description: Transfers the contents of pull-up control
register PU0 to register A.
TAPU1 (Transfer data to Accumulator from register PU1)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
1
1
1
0 2
2
5
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
E 16
(A) ← (PU1)
Grouping:
Input/Output operation
Description: Transfers the contents of pull-up control
register PU1 to register A.
TASP (Transfer data to Accumulator from Stack Pointer)
Instruction
code
Operation:
Rev.1.01
D9
0
D0
0
0
1
0
1
0
(A2–A0) ← (SP2–SP0)
(A3) ← 0
Sep 17, 2003
page 92 of 130
0
0
0
2
0
5
0
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of stack pointer (SP)
to the low-order 3 bits (A2–A0) of register A.
Note:
After this instruction is executed, “0” is
stored to the bit 3 (A3) of register A.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAV1 (Transfer data to Accumulator from register V1)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
0
1
0
0
2
0
5
4
16
(A) ← (V1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of interrupt control
register V1 to register A.
TAV2 (Transfer data to Accumulator from register V2)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
0
1
0
1
2
0
5
5
16
(A) ← (V2)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of interrupt control
register V2 to register A.
TAW1 (Transfer data to Accumulator from register W1)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
1
0
1
1
2
2
4
B
16
(A) ← (W1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer control register W1 to register A.
TAW2 (Transfer data to Accumulator from register W2)
Instruction
code
Operation:
Rev.1.01
D9
1
D0
0
0
1
0
0
1
(A) ← (W2)
Sep 17, 2003
1
0
0
2
2
4
C
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer control register W2 to register A.
page 93 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAW3 (Transfer data to Accumulator from register W3)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
1
1
0
1
2
2
4
D 16
(A) ← (W3)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer control register W3 to register A.
TAW4 (Transfer data to Accumulator from register W4)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
1
1
1
0
2
2
4
E 16
(A) ← (W4)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer control register W4 to register A.
TAX (Transfer data to Accumulator from register X)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
0
0
1
0
2
0
5
2
16
(A) ← (X)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register X to register A.
TAY (Transfer data to Accumulator from register Y)
Instruction
code
Operation:
Rev.1.01
D9
0
D0
0
0
0
0
1
1
(A) ← (Y)
Sep 17, 2003
1
1
1
2
0
1
F
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register Y to register A.
page 94 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAZ (Transfer data to Accumulator from register Z)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
0
0
1
1 2
0
5
3 16
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register Z to the
low-order 2 bits (A1, A0) of register A.
Note:
After this instruction is executed, “0” is
stored to the high-order 2 bits (A3 , A2 ) of
register A.
TBA (Transfer data to register B from Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
1
1
1
0
2
0
0
E
16
(B) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register A to register B.
TC1A (Transfer data to register C1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
1
0
1
0
1
0
0
0
2
2
A
8
16
(C1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
LCD control operation
Description: Transfers the contents of register A to the
LCD control register C1.
TC2A (Transfer data to register C2 from Accumulator)
Instruction
code
Operation:
Rev.1.01
D9
1
D0
0
1
0
1
0
1
(C2) ← (A)
Sep 17, 2003
0
0
1
2
2
A
9
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
LCD control operation
Description: Transfers the contents of register A to the
LCD control register C2.
page 95 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TDA (Transfer data to register D from Accumulator and register B)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
0
1
0
0
1
2
0
2
9
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
(DR2–DR0) ← (A2–A0)
Grouping:
Register to register transfer
Description: Transfers the low-order 3 bits (A 2–A 0) of
register A to register D.
TEAB (Transfer data to register E from Accumulator and register B)
Instruction
code
Operation:
D9
0
Number of
words
D0
0
0
0
0
1
1
0
1
0
2
0
1
A
16
(E7–E4) ← (B)
(E3–E0) ← (A)
1
Number of
cycles
1
Flag CY
–
Skip condition
–
Grouping:
Register to register transfer
Description: Transfers the contents of register B to the
high-order 4 bits (E7–E4) of register E, and
the contents of register A to the low-order 4
bits (E3–E0) of register E.
TFR0A (Transfer data to register FR0 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
1
0
0
0
2
2
2
8
16
(FR0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to the
port output structure control register FR0.
TFR1A (Transfer data to register FR1 from Accumulator)
Instruction
code
Operation:
Rev.1.01
D9
1
D0
0
0
0
1
0
1
(FR1) ← (A)
Sep 17, 2003
0
0
1
2
2
2
9
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to the
port output structure control register FR1.
page 96 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TFR2A (Transfer data to register FR2 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
1
0
1
0
2
2
2
A 16
(FR2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to the
port output structure control register FR2.
TI1A (Transfer data to register I1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
1
1
1
2
2
1
7
16
(I1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of register A to interrupt control register I1.
TK0A (Transfer data to register K0 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
1
0
1
1
2
2
1
B
16
(K0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to keyon wakeup control register K0.
TK1A (Transfer data to register K1 from Accumulator)
Instruction
code
Operation:
Rev.1.01
D9
1
D0
0
0
0
0
1
0
(K1) ← (A)
Sep 17, 2003
1
0
0
2
2
1
4
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to keyon wakeup control register K1.
page 97 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TK2A (Transfer data to register K2 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
1
0
1
2
2
1
5
16
(K2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to keyon wakeup control register K2.
TL1A (Transfer data to register L1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
0
1
0
1
0
2
2
0
A
16
(L1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
LCD control operation
Description: Transfers the contents of register A to LCD
control register L1.
TL2A (Transfer data to register L2 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
0
1
0
1
1
2
2
0
B
16
(L2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
LCD control operation
Description: Transfers the contents of register A to LCD
control register L2.
TL3A (Transfer data to register L3 from Accumulator)
Instruction
code
Operation:
Rev.1.01
D9
1
D0
0
0
0
0
0
1
(L3) ← (A)
Sep 17, 2003
1
0
0
2
2
0
C
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
LCD control operation
Description: Transfers the contents of register A to LCD
control register L3.
page 98 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TLCA (Transfer data to register LC from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
0
1
1
0
1
2
2
0
D
16
(LC) ← (A)
(RLC) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to timer
LC and reload register RLC.
TMA j (Transfer data to Memory from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
1
0
1
1
j
j
j
j
2
2
B
j
16
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
RAM to register transfer
Description: After transferring the contents of register A
to M(DP), an exclusive OR operation is performed between register X and the value j
in the immediate field, and stores the result
in register X.
TMRA (Transfer data to register MR from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
1
1
0
2
2
1
6
16
(MR) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Transfers the contents of register A to clock
control register MR.
TPAA (Transfer data to register PA from Accumulator)
Instruction
code
Operation:
Rev.1.01
D9
1
D0
0
1
0
1
0
1
(PA0) ← (A0)
Sep 17, 2003
0
1
0
2
2
A
A
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of lowermost bit (A0)
register A to timer control register PA.
page 99 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TPSAB (Transfer data to Pre-Scaler from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
0
1
0
1
2
2
3
5
16
(RPS7–RPS4) ← (B)
(TPS7–TPS4) ← (B)
(RPS3–RPS0) ← (A)
(TPS3–TPS0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of prescaler and prescaler
reload register RPS, and transfers the contents of register A to the low-order 4 bits of
prescaler and prescaler reload register
RPS.
TPU0A (Transfer data to register PU0 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
1
1
0
1
2
2
2
D
16
(PU0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to pullup control register PU0.
TPU1A (Transfer data to register PU1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
1
1
1
0
2
2
2
E
16
(PU1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to pullup control register PU1.
TR1AB (Transfer data to register R1 from Accumulator and register B)
Instruction
code
Operation:
Rev.1.01
D9
1
D0
0
0
0
1
1
1
1
(R17–R14) ← (B)
(R13–R10) ← (A)
Sep 17, 2003
page 100 of 130
1
1
2
2
3
F
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits (R17–R14) of reload register R1, and the contents of register A to the
low-order 4 bits (R13–R10) of reload register R1.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TRGA (Transfer data to register RG from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
0
1
0
0
1
2
2
0
9
16
(RG) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Clock control operation
Description: Transfers the contents of register A to register RG.
TV1A (Transfer data to register V1 from Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
1
1
1
1
1
2
0
3
F
16
(V1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of register A to interrupt control register V1.
TV2A (Transfer data to register V2 from Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
1
1
1
1
0
2
0
3
E 16
(V2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of register A to interrupt control register V2.
TW1A (Transfer data to register W1 from Accumulator)
Instruction
code
Operation:
Rev.1.01
D9
1
D0
0
0
0
0
0
1
1
(W1) ← (A)
Sep 17, 2003
1
0
2
2
0
E
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to timer
control register W1.
page 101 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TW2A (Transfer data to register W2 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
0
1
1
1
1
2
2
0
F
16
(W2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to timer
control register W2.
TW3A (Transfer data to register W3 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
0
0
0
2
2
1
0
16
(W3) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to timer
control register W3.
TW4A (Transfer data to register W4 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
0
0
1
2
2
1
1
16
(W4) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to timer
control register W4.
TYA (Transfer data to register Y from Accumulator)
Instruction
code
Operation:
Rev.1.01
D9
0
D0
0
0
0
0
0
1
1
(Y) ← (A)
Sep 17, 2003
0
0
2
0
0
C
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register A to register Y.
page 102 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
WRST (Watchdog timer ReSeT)
Instruction
code
Operation:
D9
1
D0
0
1
0
1
0
0
0
0
0
2
2
A
0
16
(WDF1) = 1 ?
After skipping, (WDF1) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(WDF1) = 1
Grouping:
Other operation
Description: Skips the next instruction when watchdog
timer flag WDF1 is “1.” After skipping, clears
(0) to the WDF1 flag. When the WDF1 flag
is “0,” executes the next instruction. Also,
stops the watchdog timer function when executing the WRST instruction immediately
after the DWDT instruction.
XAM j (eXchange Accumulator and Memory data)
Instruction
code
Operation:
D9
1
D0
0
1
1
0
1
j
j
j
j
2
2
D
j
16
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
RAM to register transfer
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between register X and the value j in the immediate field,
and stores the result in register X.
XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip)
Instruction
code
Operation:
D9
1
D0
0
1
1
1
1
j
j
j
j
2
2
F
j
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 15
Grouping:
RAM to register transfer
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between register X and the value j in the immediate field,
and stores the result in register X.
Subtracts 1 from the contents of register Y.
As a result of subtraction, when the contents of register Y is 15, the next instruction
is skipped. When the contents of register Y
is not 15, the next instruction is executed.
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1
XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip)
Instruction
code
Operation:
Rev.1.01
D9
1
D0
0
1
1
1
0
j
j
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
Sep 17, 2003
page 103 of 130
j
j
2
2
E
j
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 0
Grouping:
RAM to register transfer
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between register X and the value j in the immediate field,
and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition, when the contents of
register Y is 0, the next instruction is
skipped. when the contents of register Y is
not 0, the next instruction is executed.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES)
Number of
words
Number of
cycles
Instruction code
TAB
0
0
0
0
0
1
1
1
1
0
0 1 E
1
1
(A) ← (B)
TBA
0
0
0
0
0
0
1
1
1
0
0 0 E
1
1
(B) ← (A)
TAY
0
0
0
0
0
1
1
1
1
1
0 1 F
1
1
(A) ← (Y)
TYA
0
0
0
0
0
0
1
1
0
0
0 0 C
1
1
(Y) ← (A)
TEAB
0
0
0
0
0
1
1
0
1
0
0 1 A
1
1
(E7–E4) ← (B)
(E3–E0) ← (A)
TABE
0
0
0
0
1
0
1
0
1
0
0 2 A
1
1
(B) ← (E7–E4)
(A) ← (E3–E0)
TDA
0
0
0
0
1
0
1
0
0
1
0 2 9
1
1
(DR2–DR0) ← (A2–A0)
TAD
0
0
0
1
0
1
0
0
0
1
0 5 1
1
1
(A2–A0) ← (DR2–DR0)
(A3) ← 0
TAZ
0
0
0
1
0
1
0
0
1
1
0 5 3
1
1
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
TAX
0
0
0
1
0
1
0
0
1
0
0 5 2
1
1
(A) ← (X)
TASP
0
0
0
1
0
1
0
0
0
0
0 5 0
1
1
(A2–A0) ← (SP2–SP0)
(A3) ← 0
LXY x, y
1
1
x3 x2 x1 x0 y3 y2 y1 y0
3 x y
1
1
(X) ← x x = 0 to 15
(Y) ← y y = 0 to 15
LZ z
0
0
0
1
0
0
1
0
z1 z0
0 4 8
+z
1
1
(Z) ← z z = 0 to 3
INY
0
0
0
0
0
1
0
0
1
1
0 1 3
1
1
(Y) ← (Y) + 1
DEY
0
0
0
0
0
1
0
1
1
1
0 1 7
1
1
(Y) ← (Y) – 1
TAM j
1
0
1
1
0
0
j
j
j
j
2 C j
1
1
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
XAM j
1
0
1
1
0
1
j
j
j
j
2 D j
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
XAMD j
1
0
1
1
1
1
j
j
j
j
2 F j
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1
XAMI j
1
0
1
1
1
0
j
j
j
j
2 E j
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
TMA j
1
0
1
0
1
1
j
j
j
j
2 B j
1
1
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
Parameter
Mnemonic
RAM to register transfer
RAM addresses
Register to register transfer
Type of
instructions
Rev.1.01
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Sep 17, 2003
page 104 of 130
Hexadecimal
notation
Function
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Skip condition
Carry flag CY
4556 Group
–
–
Transfers the contents of register B to register A.
–
–
Transfers the contents of register A to register B.
–
–
Transfers the contents of register Y to register A.
–
–
Transfers the contents of register A to register Y.
–
–
Transfers the contents of register B to the high-order 4 bits (E7–E4) of register E, and the contents of register A to the low-order 4 bits (E3–E0) of register E.
–
–
Transfers the high-order 4 bits (E7–E4) of register E to register B, and low-order 4 bits (E3–E0) of register E
to register A.
–
–
Transfers the contents of the low-order 3 bits (A2–A0) of register A to register D.
–
–
Transfers the contents of register D to the low-order 3 bits (A2–A0) of register A.
–
–
Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A.
–
–
Transfers the contents of register X to register A.
–
–
Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2–A0) of register A.
Continuous
description
–
Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y.
When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed
and other LXY instructions coded continuously are skipped.
–
–
Loads the value z in the immediate field to register Z.
(Y) = 0
–
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed.
(Y) = 15
–
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,
the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.
–
–
After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
–
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
(Y) = 15
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,
the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.
(Y) = 0
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed.
–
–
After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
Rev.1.01
Sep 17, 2003
Datailed description
page 105 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Arithmetic operation
Bit operation
Comparison
operation
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
notation
Number of
cycles
Mnemonic
Type of
instructions
Number of
words
Instruction code
Parameter
0 7 n
1
1
(A) ← n
n = 0 to 15
Hexadecimal
LA n
0
0
0
1
1
TABP p
0
0
1
0
p5 p4 p3 p2 p1 p0
0 8 p
+p
1
3
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
at (UPTF) = 0
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
at (UPTF) = 1
(DR2) ← (0)
(DR1, DR0) ← (ROM(PC))9, 8
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
AM
0
0
0
0
0
0
1
0
1
0
0 0 A
1
1
(A) ← (A) + (M(DP))
AMC
0
0
0
0
0
0
1
0
1
1
0 0 B
1
1
(A) ← (A) + (M(DP)) +(CY)
(CY) ← Carry
An
0
0
0
1
1
0
n
n
n
n
0 6 n
1
1
(A) ← (A) + n
n = 0 to 15
AND
0
0
0
0
0
1
1
0
0
0
0 1 8
1
1
(A) ← (A) AND (M(DP))
OR
0
0
0
0
0
1
1
0
0
1
0 1 9
1
1
(A) ← (A) OR (M(DP))
SC
0
0
0
0
0
0
0
1
1
1
0 0 7
1
1
(CY) ← 1
RC
0
0
0
0
0
0
0
1
1
0
0 0 6
1
1
(CY) ← 0
SZC
0
0
0
0
1
0
1
1
1
1
0 2 F
1
1
(CY) = 0 ?
CMA
0
0
0
0
0
1
1
1
0
0
0 1 C
1
1
(A) ← (A)
RAR
0
0
0
0
0
1
1
1
0
1
0 1 D
1
1
→ CY → A3A2A1A0
SB j
0
0
0
1
0
1
1
1
j
j
0 5 C
+j
1
1
(Mj(DP)) ← 1
j = 0 to 3
RB j
0
0
0
1
0
0
1
1
j
j
0 4 C
+j
1
1
(Mj(DP)) ← 0
j = 0 to 3
SZB j
0
0
0
0
1
0
0
0
j
j
0 2 j
1
1
(Mj(DP)) = 0 ?
j = 0 to 3
SEAM
0
0
0
0
1
0
0
1
1
0
0 2 6
1
1
(A) = (M(DP)) ?
SEA n
0
0
0
0
1
0
0
1
0
1
0 2 5
2
2
(A) = n ?
n = 0 to 15
0
0
0
1
1
1
n
n
n
n
0 7 n
1
n
n
n
n
Note: p is 0 to 31 for M34556M4/M4H. p is 0 to 63 for M34556M8/M8H/G8/G8H.
Rev.1.01
Function
Sep 17, 2003
page 106 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Skip condition
Carry flag CY
4556 Group
Datailed description
Continuous
description
–
Loads the value n in the immediate field to register A.
When the LA instructions are continuously coded and executed, only the first LA instruction is executed and
other LA instructions coded continuously are skipped.
–
–
UPTF = 0:
Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 9 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p.
When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used.
UPTF = 1:
Transfers bits 9, 8 to register D, bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are
the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p.
When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used.
–
–
Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged.
0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY.
–
Overflow = 0
–
Adds the value n in the immediate field to register A, and stores a result in register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no overflow as the result of operation.
Executes the next instruction when there is overflow as the result of operation.
–
–
Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A.
–
–
Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result
in register A.
–
1
Sets (1) to carry flag CY.
–
0
Clears (0) to carry flag CY.
(CY) = 0
–
Skips the next instruction when the contents of carry flag CY is “0.”
–
–
Stores the one’s complement for register A’s contents in register A.
0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right.
–
–
–
Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
–
–
Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
(Mj(DP)) = 0
j = 0 to 3
–
Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of
M(DP) is “0.”
Executes the next instruction when the contents of bit j of M(DP) is “1.”
(A) = (M(DP))
–
Skips the next instruction when the contents of register A is equal to the contents of M(DP).
Executes the next instruction when the contents of register A is not equal to the contents of M(DP).
(A) = n
–
Skips the next instruction when the contents of register A is equal to the value n in the immediate field.
Executes the next instruction when the contents of register A is not equal to the value n in the immediate
field.
Rev.1.01
Sep 17, 2003
page 107 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of
words
Number of
cycles
Instruction code
Ba
0
1
1
a6 a5 a4 a3 a2 a1 a0
1 8 a
+a
1
1
(PCL) ← a6–a0
BL p, a
0
0
1
1
p4 p3 p2 p1 p0
0 E p
+p
2
2
(PCH) ← p (Note)
(PCL) ← a6–a0
1
p6 p5 a6 a5 a4 a3 a2 a1 a0
2 p a
+p +a
0
0
0
1
0
0 1 0
2
2
(PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
1
p6 p5 p4 0
0
p3 p2 p1 p0
2 p p
+p
BM a
0
1
0
a6 a5 a4 a3 a2 a1 a0
1 a a
1
1
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
(PCL) ← a6–a0
BML p, a
0
0
1
1
p4 p3 p2 p1 p0
0 C p
+p
2
2
1
p6 p5 a6 a5 a4 a3 a2 a1 a0
2 p a
+p +a
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← a6–a0
0
0
1
1
0
0 3 0
2
2
1
p6 p5 p4 0
0
p3 p2 p1 p0
2 p p
+p
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← (DR2–DR0,A3–A0)
RTI
0
0
0
1
0
0
0
1
1
0
0 4 6
1
1
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RT
0
0
0
1
0
0
0
1
0
0
0 4 4
1
2
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RTS
0
0
0
1
0
0
0
1
0
1
0 4 5
1
2
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Parameter
Mnemonic
Return operation
Subroutine operation
Branch operation
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
BLA p
BMLA p
0
0
0
0
1
0
Note: p is 0 to 31 for M34556M4/M4H.
p is 0 to 63 for M34556M8/M8H/G8/G8H.
Rev.1.01
Sep 17, 2003
page 108 of 130
0
0
0
0
0
0
Hexadecimal
notation
Function
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Skip condition
Carry flag CY
4556 Group
–
–
Branch within a page : Branches to address a in the identical page.
–
–
Branch out of a page : Branches to address a in page p.
–
–
Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in
page p.
–
–
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
–
–
Call the subroutine : Calls the subroutine at address a in page p.
–
–
Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D
and A in page p.
–
–
Returns from interrupt service routine to main routine.
Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt.
–
–
Returns from subroutine to the routine called the subroutine.
Skip at uncondition
–
Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
Rev.1.01
Sep 17, 2003
Datailed description
page 109 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of
words
Number of
cycles
Instruction code
DI
0
0
0
0
0
0
0
1
0
0
0 0 4
1
1
(INTE) ← 0
EI
0
0
0
0
0
0
0
1
0
1
0 0 5
1
1
(INTE) ← 1
SNZ0
0
0
0
0
1
1
1
0
0
0
0 3 8
1
1
V10 = 0: (EXF0) = 1 ?
After skipping, (EXF0) ← 0
V10 = 1: SNZ0 = NOP
SNZI0
0
0
0
0
1
1
1
0
1
0
0 3 A
1
1
I12 = 1 : (INT) = “H” ?
Parameter
Mnemonic
Interrupt operation
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
notation
Function
I12 = 0 : (INT) = “L” ?
TAV1
0
0
0
1
0
1
0
1
0
0
0 5 4
1
1
(A) ← (V1)
TV1A
0
0
0
0
1
1
1
1
1
1
0 3 F
1
1
(V1) ← (A)
TAV2
0
0
0
1
0
1
0
1
0
1
0 5 5
1
1
(A) ← (V2)
TV2A
0
0
0
0
1
1
1
1
1
0
0 3 E
1
1
(V2) ← (A)
TAI1
1
0
0
1
0
1
0
0
1
1
2 5 3
1
1
(A) ← (I1)
TI1A
1
0
0
0
0
1
0
1
1
1
2 1 7
1
1
(I1) ← (A)
Note: p is 0 to 31 for M34556M4/M4H.
p is 0 to 63 for M34556M8/M8H/G8/G8H.
Rev.1.01
Hexadecimal
Sep 17, 2003
page 110 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Skip condition
Carry flag CY
4556 Group
–
–
Clears (0) to interrupt enable flag INTE, and disables the interrupt.
–
–
Sets (1) to interrupt enable flag INTE, and enables the interrupt.
V10 = 0: (EXF0) = 1
–
When V10 = 0 : Skips the next instruction when external 0 interrupt request flag EXF0 is “1.” After skipping,
clears (0) to the EXF0 flag. When the EXF0 flag is “0,” executes the next instruction.
When V10 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register V1)
(INT) = “H”
However, I12 = 1
–
When I12 = 1 : Skips the next instruction when the level of INT pin is “H.” (I12: bit 2 of interrupt control register I1)
(INT) = “L”
However, I12 = 0
–
When I12 = 0 : Skips the next instruction when the level of INT pin is “L.”
–
–
Transfers the contents of interrupt control register V1 to register A.
–
–
Transfers the contents of register A to interrupt control register V1.
–
–
Transfers the contents of interrupt control register V2 to register A.
–
–
Transfers the contents of register A to interrupt control register V2.
–
–
Transfers the contents of interrupt control register I1 to register A.
–
–
Transfers the contents of register A to interrupt control register I1.
Rev.1.01
Sep 17, 2003
Datailed description
page 111 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of
words
Number of
cycles
Instruction code
TPAA
1
0
1
0
1
0
1
0
1
0
2 A A
1
1
(PA) ← (A)
TAW1
1
0
0
1
0
0
1
0
1
1
2 4 B
1
1
(A) ← (W1)
TW1A
1
0
0
0
0
0
1
1
1
0
2 0 E
1
1
(W1) ← (A)
TAW2
1
0
0
1
0
0
1
1
0
0
2 4 C
1
1
(A) ← (W2)
TW2A
1
0
0
0
0
0
1
1
1
1
2 0 F
1
1
(W2) ← (A)
TAW3
1
0
0
1
0
0
1
1
0
1
2 4 D
1
1
(A) ← (W3)
TW3A
1
0
0
0
0
1
0
0
0
0
2 1 0
1
1
(W3) ← (A)
TAW4
1
0
0
1
0
0
1
1
1
0
2 4 E
1
1
(A) ← (W4)
TW4A
1
0
0
0
0
1
0
0
0
1
2 1 1
1
1
(W4) ← (A)
TABPS
1
0
0
1
1
1
0
1
0
1
2 7 5
1
1
(B) ← (TPS7–TPS4)
(A) ← (TPS3–TPS0)
TPSAB
1
0
0
0
1
1
0
1
0
1
2 3 5
1
1
(RPS7–RPS4) ← (B)
(TPS7–TPS4) ← (B)
(RPS3–RPS0) ← (A)
(TPS3–TPS0) ← (A)
0
0
1
1
1
0
0
0
0
2 7 0
1
1
(B) ← (T17–T14)
(A) ← (T13–T10)
Parameter
Mnemonic
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Timer operation
TAB1
Rev.1.01
1
Hexadecimal
notation
Function
T1AB
1
0
0
0
1
1
0
0
0
0
2 3 0
1
1
(R17–R14) ← (B)
(T17–T14) ← (B)
(R13–R10) ← (A)
(T13–T10) ← (A)
TAB2
1
0
0
1
1
1
0
0
0
1
2 7 1
1
1
(B) ← (T27–T24)
(A) ← (T23–T20)
T2AB
1
0
0
0
1
1
0
0
0
1
2 3 1
1
1
(R2L7–R2L4) ← (B)
(T27–T24) ← (B)
(R2L3–R2L0) ← (A)
(T23–T20) ← (A)
T2HAB
1
0
1
0
0
1
0
1
0
0
2 9 4
1
1
(R2H7–R2H4) ← (B)
(R2H3–R2H0) ← (A)
TR1AB
1
0
0
0
1
1
1
1
1
1
2 3 F
1
1
(R17–R14) ← (B)
(R13–R10) ← (A)
T2R2L
1
0
1
0
0
1
0
1
0
1
2 9 5
1
1
(T27–T20) ← (R2L7–R2L0)
TLCA
1
0
0
0
0
0
1
1
0
1
2 0 D
1
1
(LC) ← (A)
(RLC) ← (A)
SNZT1
1
0
1
0
0
0
0
0
0
0
2 8 0
1
1
V12 = 0: (T1F) = 1 ?
After skipping, (T1F) ← 0 V12 = 1: NOP
SNZT2
1
0
1
0
0
0
0
0
0
1
2 8 1
1
1
V13 = 0: (T2F) = 1 ?
After skipping, (T2F) ← 0 V13 = 1: NOP
SNZT3
1
0
1
0
0
0
0
0
1
0
2 8 2
1
1
V20 = 0: (T3F) = 1 ?
After skipping, (T3F) ← 0 V20 = 1: NOP
Sep 17, 2003
page 112 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Skip condition
Carry flag CY
4556 Group
Datailed description
–
–
Transfers the contents of register A to timer control register PA.
–
–
Transfers the contents of timer control register W1 to register A.
–
–
Transfers the contents of register A to timer control register W1.
–
–
Transfers the contents of timer control register W2 to register A.
–
–
Transfers the contents of register A to timer control register W2.
–
–
Transfers the contents of timer control register W3 to register A.
–
–
Transfers the contents of register A to timer control register W3.
–
–
Transfers the contents of timer control register W4 to register A.
–
–
Transfers the contents of register A to timer control register W4.
–
–
Transfers the high-order 4 bits of prescaler to register B, and transfers the low-order 4 bits of prescaler to
register A.
–
–
Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS,
and transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register
RPS.
–
–
Transfers the high-order 4 bits of timer 1 to register B, and transfers the low-order 4 bits of timer 1 to register A.
–
–
Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1, and
transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1.
–
–
Transfers the high-order 4 bits of timer 2 to register B, and transfers the low-order 4 bits of timer 2 to register A.
–
–
Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2L, and
transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2L.
–
–
Transfers the contents of register B to the high-order 4 bits of timer 2 reload register R2H, and transfers the
contents of register A to the low-order 4 bits of timer 2 reload register R2H.
–
–
Transfers the contents of register B to the high-order 4 bits of timer 1 reload register R1, and transfers the
contents of register A to the low-order 4 bits of timer 1 reload register R1.
–
–
Transfers the contents of timer 2 reload register R2L to timer 2.
–
–
Transfers the contents of register A to timer LC and timer LC reload register RLC.
V12 = 0: (T1F) = 1
–
Skips the next instruction when the contents of bit 2 (V12) of interrupt control register V1 is “0” and the contents of T1F flag is “1.” After skipping, clears (0) to T1F flag.
V13 = 0: (T2F) =1
–
Skips the next instruction when the contents of bit 3 (V13) of interrupt control register V1 is “0” and the contents of T2F flag is “1.” After skipping, clears (0) to T2F flag.
V20 = 0: (T3F) = 1
–
Skips the next instruction when the contents of bit 0 (V20) of interrupt control register V2 is “0” and the contents of T3F flag is “1.” After skipping, clears (0) to T3F flag.
Rev.1.01
Sep 17, 2003
page 113 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
Number of
words
Number of
cycles
Instruction code
IAP0
1
0
0
1
1
0
0
0
0
0
2 6 0
1
1
(A) ← (P0)
OP0A
1
0
0
0
1
0
0
0
0
0
2 2 0
1
1
(P0) ← (A)
IAP1
1
0
0
1
1
0
0
0
0
1
2 6 1
1
1
(A) ← (P1)
OP1A
1
0
0
0
1
0
0
0
0
1
2 2 1
1
1
(P1) ← (A)
IAP2
1
0
0
1
1
0
0
0
1
0
2 6 2
1
1
(A) ← (P2)
OP2A
1
0
0
0
1
0
0
0
1
0
2 2 2
1
1
(P2) ← (A)
CLD
0
0
0
0
0
1
0
0
0
1
0 1 1
1
1
(D) ← 1
RD
0
0
0
0
0
1
0
1
0
0
0 1 4
1
1
(D(Y)) ← 0
(Y) = 0 to 7
SD
0
0
0
0
0
1
0
1
0
1
0 1 5
1
1
(D(Y)) ← 1
(Y) = 0 to 7
SZD
0
0
0
0
1
0
0
1
0
0
0 2 4
1
1
(D(Y)) = 0 ?
(Y) = 0 to 7
0
0
0
0
1
0
1
0
1
1
0 2 B
1
1
RCP
1
0
1
0
0
0
1
1
0
0
2 8 C
1
1
(C) ← 0
SCP
1
0
1
0
0
0
1
1
0
1
2 8 D
1
1
(C) ← 1
TAPU0
1
0
0
1
0
1
0
1
1
1
2 5 7
1
1
(A) ← (PU0)
TPU0A
1
0
0
0
1
0
1
1
0
1
2 2 D
1
1
(PU0) ← (A)
TAPU1
1
0
0
1
0
1
1
1
1
0
2 5 E
1
1
(A) ← (PU1)
TPU1A
1
0
0
0
1
0
1
1
1
0
2 2 E
1
1
(PU1) ← (A)
TAK0
1
0
0
1
0
1
0
1
1
0
2 5 6
1
1
(A) ← (K0)
TK0A
1
0
0
0
0
1
1
0
1
1
2 1 B
1
1
(K0) ← (A)
TAK1
1
0
0
1
0
1
1
0
0
1
2 5 9
1
1
(A) ← (K1)
TK1A
1
0
0
0
0
1
0
1
0
0
2 1 4
1
1
(K1) ← (A)
TAK2
1
0
0
1
0
1
1
0
1
0
2 5 A
1
1
(A) ← (K2)
TK2A
1
0
0
0
0
1
0
1
0
1
2 1 5
1
1
(K2) ← (A)
TFR0A
1
0
0
0
1
0
1
0
0
0
2 2 8
1
1
(FR0) ← (A)
TFR1A
1
0
0
0
1
0
1
0
0
1
2 2 9
1
1
(FR1) ← (A)
TFR2A
1
0
0
0
1
0
1
0
1
0
2 2 A
1
1
(FR2) ← (A)
Parameter
Mnemonic
Input/Output operation
Type of
instructions
Rev.1.01
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Sep 17, 2003
page 114 of 130
Hexadecimal
notation
Function
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Skip condition
Carry flag CY
4556 Group
–
–
Transfers the input of port P0 to register A.
–
–
Outputs the contents of register A to port P0.
–
–
Transfers the input of port P1 to register A.
–
–
Outputs the contents of register A to port P1.
–
–
Transfers the input of port P2 to register A.
–
–
Outputs the contents of register A to port P2.
–
–
Sets (1) to all port D.
–
–
Clears (0) to a bit of port D specified by register Y.
–
–
Sets (1) to a bit of port D specified by register Y.
(D(Y)) = 0
However, (Y)=0 to 7
–
Skips the next instruction when a bit of port D specified by register Y is “0.” Executes the next instruction
when a bit of port D specified by register Y is “1.”
–
–
Clears (0) to port C.
–
–
Sets (1) to port C.
–
–
Transfers the contents of pull-up control register PU0 to register A.
–
–
Transfers the contents of register A to pull-up control register PU0.
–
–
Transfers the contents of pull-up control register PU1 to register A.
–
–
Transfers the contents of register A to pull-up control register PU1.
–
–
Transfers the contents of key-on wakeup control register K0 to register A.
–
–
Transfers the contents of register A to key-on wakeup control register K0.
–
–
Transfers the contents of key-on wakeup control register K1 to register A.
–
–
Transfers the contents of register A to key-on wakeup control register K1.
–
–
Transfers the contents of key-on wakeup control register K2 to register A.
–
–
Transfers the contents of register A to key-on wakeup control register K2.
–
–
Transferts the contents of register A to port output format control register FR0.
–
–
Transferts the contents of register A to port output format control register FR1.
–
–
Transferts the contents of register A to port output format control register FR2.
Rev.1.01
Sep 17, 2003
Datailed description
page 115 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of
words
Number of
cycles
Instruction code
TAL1
1
0
0
1
0
0
1
0
1
0
2 4 A
1
1
(A) ← (L1)
TL1A
1
0
0
0
0
0
1
0
1
0
2 0 A
1
1
(L1) ← (A)
TL2A
1
0
0
0
0
0
1
0
1
1
2 0 B
1
1
(L2) ← (A)
TL3A
1
0
0
0
0
0
1
1
0
0
2 0 C
1
1
(L3) ← (A)
TC1A
1
0
1
0
1
0
1
0
0
0
2 A 8
1
1
(C1) ← (A)
TC2A
1
0
1
0
1
0
1
0
0
1
2 A 9
1
1
(C2) ← (A)
CRCK
1
0
1
0
0
1
1
0
1
1
2 9 B
1
1
RC oscillator selected
TAMR
1
0
0
1
0
1
0
0
1
0
2 5 2
1
1
(A) ← (MR)
TMRA
1
0
0
0
0
1
0
1
1
0
2 1 6
1
1
(MR) ← (A)
TRGA
1
0
0
0
0
0
1
0
0
1
2 0 9
1
1
(RG) ← (A)
NOP
0
0
0
0
0
0
0
0
0
0
0 0 0
1
1
(PC) ← (PC) + 1
POF
0
0
0
0
0
0
0
0
1
0
0 0 2
1
1
Transition to clock operating mode
POF2
0
0
0
0
0
0
1
0
0
0
0 0 8
1
1
Transition to RAM back-up mode
EPOF
0
0
0
1
0
1
1
0
1
1
0 5 B
1
1
POF, POF2 instructions valid
SNZP
0
0
0
0
0
0
0
0
1
1
0 0 3
1
1
(P) = 1 ?
WRST
1
0
1
0
1
0
0
0
0
0
2 A 0
1
1
(WDF1) = 1 ?
After skipping, (WDF1) ← 0
DWDT
1
0
1
0
0
1
1
1
0
0
2 9 C
1
1
Stop of watchdog timer function enabled
SRST
0
0
0
0
0
0
0
0
0
1
0 0 1
1
1
System reset
RUPT
0
0
0
1
0
1
1
0
0
0
0 5 8
1
1
(UPTF) ← 0
SUPT
0
0
0
1
0
1
1
0
0
1
0 5 9
1
1
(UPTF) ← 1
SVDE
1
0
1
0
0
1
0
0
1
1
2 9 3
1
1
At power down mode, voltage drop detection
circuit valid
Parameter
Mnemonic
Other operation
Clock operation
LCD operation
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Note: SVDE instruction can be used only in H version.
Rev.1.01
Sep 17, 2003
page 116 of 130
Hexadecimal
notation
Function
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Skip condition
Carry flag CY
4556 Group
–
–
Transfers the contents of LCD control register L1 to register A.
–
–
Transfers the contents of register A to LCD control register L1.
–
–
Transfers the contents of register A to LCD control register L2.
–
–
Transfers the contents of register A to LCD control register L3.
–
–
Transfers the contents of register A to LCD control register C1.
–
–
Transfers the contents of register A to LCD control register C2.
–
–
Selects the RC oscillation circuit for main clock, stops the ring oscillator (internal oscillator).
–
–
Transfers the contents of clock control regiser MR to register A.
–
–
Transfers the contents of register A to clock control register MR.
–
–
Transfers the contents of register A to clock control register RG.
–
–
No operation; Adds 1 to program counter value, and others remain unchanged.
–
–
Puts the system in clock operating mode by executing the POF instruction after executing the EPOF instruction.
–
–
Puts the system in RAM back-up state by executing the POF2 instruction after executing the EPOF instruction.
–
–
Makes the immediate after POF or POF2 instruction valid by executing the EPOF instruction.
(P) = 1
–
Skips the next instruction when the P flag is “1”.
After skipping, the P flag remains unchanged.
(WDF1) = 1
–
Skips the next instruction when watchdog timer flag WDF1 is “1.” After skipping, clears (0) to the WDF1 flag.
Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT
instruction.
–
–
Stops the watchdog timer function by the WRST instruction.
–
–
System reset occurs.
–
–
Clears (0) to the high-order bit reference enable flag UPTF.
–
–
Sets (1) to the high-order bit reference enable flag UPTF.
–
–
Validates the voltage drop detection circuit at power down (clock operating mode and RAM back-up mode).
Rev.1.01
Sep 17, 2003
Datailed description
page 117 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
INSTRUCTION CODE TABLE
D9–D4 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001001010 001011001100 001101 001110 001111
010000 011000
010111 011111
Hex.
D3–D0 notation
00
01
BLA
02
03
04
05
06
07
SZB
BMLA
0
–
TASP
A
0
LA
0
SZB
1
–
–
TAD
A
1
SZB
2
–
–
TAX
SNZP INY
SZB
3
–
–
RT
08
09
0D
0E
0F
TABP TABP TABP TABP
BML
32* 48*
0
16
BML
BL
BL
BM
B
LA
1
TABP TABP TABP TABP
BML
33* 49*
1
17
BML
BL
BL
BM
B
A
2
LA
2
TABP TABP TABP TABP
BML
34* 50*
2
18
BML
BL
BL
BM
B
TAZ
A
3
LA
3
TABP TABP TABP TABP
BML
35* 51*
3
19
BML
BL
BL
BM
B
TAV1
A
4
LA
4
TABP TABP TABP TABP
BML
36* 52*
4
20
BML
BL
BL
BM
B
0A
0B
0C
10–17 18–1F
0000
0
NOP
0001
1
SRST CLD
0010
2
0011
3
0100
4
DI
RD
SZD
–
0101
5
EI
SD
SEAn
–
RTS TAV2
A
5
LA
5
TABP TABP TABP TABP
BML
37* 53*
5
21
BML
BL
BL
BM
B
0110
6
RC
–
SEAM
–
RTI
–
A
6
LA
6
TABP TABP TABP TABP
BML
38* 54*
6
22
BML
BL
BL
BM
B
0111
7
SC
DEY
–
–
–
–
A
7
LA
7
TABP TABP TABP TABP
BML
39* 55*
7
23
BML
BL
BL
BM
B
1000
8
POF2 AND
–
SNZ0
LZ
0
RUPT
A
8
LA
8
TABP TABP TABP TABP
BML
40* 56*
8
24
BML
BL
BL
BM
B
1001
9
–
TDA
–
LZ
1
SUPT
A
9
LA
9
TABP TABP TABP TABP
BML
41* 57*
9
25
BML
BL
BL
BM
B
1010
A
AM
TEAB TABE SNZI0
LZ
2
–
A
10
LA
10
TABP TABP TABP TABP
BML
42* 58*
10
26
BML
BL
BL
BM
B
1011
B
AMC
–
–
–
LZ
3
EPOF
A
11
LA
11
TABP TABP TABP TABP
BML
43* 59*
11
27
BML
BL
BL
BM
B
1100
C
TYA
CMA
–
–
RB
0
SB
0
A
12
LA
12
TABP TABP TABP TABP
BML
44* 60*
12
28
BML
BL
BL
BM
B
1101
D
–
RAR
–
–
RB
1
SB
1
A
13
LA
13
TABP TABP TABP TABP
BML
45* 61*
13
29
BML
BL
BL
BM
B
1110
E
TBA
TAB
–
TV2A
RB
2
SB
2
A
14
LA
14
TABP TABP TABP TABP
BML
46* 62*
14
30
BML
BL
BL
BM
B
1111
F
–
TAY
SZC TV1A
RB
3
SB
3
A
15
LA
15
TABP TABP TABP TABP
BML
47* 63*
15
31
BML
BL
BL
BM
B
POF
–
OR
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order
4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is
shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below.
BL
BML
BLA
BMLA
SEA
SZD
The second word
1p paaa aaaa
1p paaa aaaa
1p pp00 pppp
1p pp00 pppp
00 0111 nnnn
00 0010 1011
Rev.1.01
Sep 17, 2003
• * cannot be used in the M3455xM4/M4H.
page 118 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
INSTRUCTION CODE TABLE (continued)
D9–D4 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001101010 101011 101100 101101 101110 101111
110000
111111
Hex.
D3–D0 notation
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30–3F
0000
0
–
TW3A OP0A T1AB
–
–
IAP0 TAB1 SNZT1
–
WRST
TMA
0
TAM
0
XAM XAMI XAMD LXY
0
0
0
0001
1
–
TW4A OP1A T2AB
–
–
IAP1 TAB2 SNZT2
–
–
TMA
1
TAM
1
XAM XAMI XAMD LXY
1
1
1
0010
2
–
–
OP2A
–
–
0011
3
–
–
–
–
–
TAI1
0100
4
–
TK1A
–
–
–
0101
5
–
TK2A
–
TPSAB
0110
6
–
TMRA
–
0111
7
–
TI1A
1000
8
–
1001
9
1010
–
SNZT3
–
–
TMA
2
TAM
2
XAM XAMI XAMD LXY
2
2
2
–
–
–
SVDE**
–
TMA
3
TAM
3
XAM XAMI XAMD LXY
3
3
3
–
–
–
–
T2HAB
–
TMA
4
TAM
4
XAM XAMI XAMD LXY
4
4
4
–
–
–
TABPS
–
T2R2L
–
TMA
5
TAM
5
XAM XAMI XAMD LXY
5
5
5
–
–
TAK0
–
–
–
–
–
TMA
6
TAM
6
XAM XAMI XAMD LXY
6
6
6
–
–
–
TAPU0
–
–
–
–
–
TMA
7
TAM
7
XAM XAMI XAMD LXY
7
7
7
–
TFR0A
–
–
–
–
–
–
–
TC1A
TMA
8
TAM
8
XAM XAMI XAMD LXY
8
8
8
TRGA
–
TFR1A
–
–
TAK1
–
–
–
–
TC2A
TMA
9
TAM
9
XAM XAMI XAMD LXY
9
9
9
A
TL1A
–
TFR2A
–
TAL1 TAK2
–
–
–
–
TPAA
TMA
10
TAM
10
XAM XAMI XAMD LXY
10
10
10
1011
B
TL2A TK0A
–
–
TAW1
–
–
–
–
CRCK
–
TMA
11
TAM
11
XAM XAMI XAMD LXY
11
11
11
1100
C
TL3A
–
–
–
TAW2
–
–
–
RCP DWDT
–
TMA
12
TAM
12
XAM XAMI XAMD LXY
12
12
12
1101
D
TLCA
–
TPU0A
–
TAW3
–
–
–
SCP
–
–
TMA
13
TAM
13
XAM XAMI XAMD LXY
13
13
13
1110
E
TW1A
–
TPU1A
–
TAW4 TAPU1
–
–
–
–
–
TMA
14
TAM
14
XAM XAMI XAMD LXY
14
14
14
1111
F
TW2A
–
–
–
–
–
–
–
TMA
15
TAM
15
XAM XAMI XAMD
LXY
15
15
15
TR1AB
–
TAMR IAP2
–
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the loworder 4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal
representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of
each instruction is shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below.
BL
BML
BLA
BMLA
SEA
SZD
The second word
1p paaa aaaa
1p paaa aaaa
1p pp00 pppp
1p pp00 pppp
00 0111 nnnn
00 0010 1011
Rev.1.01
Sep 17, 2003
• ** can be used only in the M3455xM4H/M8H/G8H.
page 119 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
ABSOLUTE MAXIMUM RAINGS
Parameter
Symbol
VDD
Supply voltage
VI
Input voltage P0, P1, P2, D0–D5, RESET, INT, XIN, XCIN
VI
VO
Input voltage CNTR
Output voltage P0, P1, P2, D0–D7, RESET, CNTR
VO
Output voltage C, XOUT, XCOUT
VO
Output voltage SEG0–SEG28, COM0–COM3
Pd
Power dissipation
Topr
Operating temperature range
Tstg
Storage temperature range
Sep 17, 2003
Output transistors in cut-off state
Ta = 25 °C
Note: SEG11 to SEG16 pins are not equipped with the 4556 Group.
Rev.1.01
Conditions
page 120 of 130
Ratings
–0.3 to 6.5
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to VDD+0.3
300
–20 to 85
–40 to 125
Unit
V
V
V
V
V
V
mW
°C
°C
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
RECOMMENDED OPERATING CONDITIONS 1
(Mask ROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
(One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted)
Symbol
VDD
VDD
Parameter
Supply voltage
(when ceramic resonator is used)
Mask ROM version
f(STCK) ≤ 6 MHz
f(STCK) ≤ 4.4 MHz
Limits
Min.
Typ.
4
2.7
Max.
5.5
f(STCK) ≤ 2.2 MHz
2
5.5
f(STCK) ≤ 1.1 MHz
1.8
5.5
4
5.5
2.7
2.5
5.5
5.5
Mask ROM version
1.8
5.5
is used)
One Time PROM version
2.5
5.5
Supply voltage
f(STCK) ≤ 4.4 MHz
2.7
5.5
Supply voltage
Unit
V
5.5
One Time PROM version f(STCK) ≤ 6 MHz
f(STCK) ≤ 4.4 MHz
f(STCK) ≤ 2.2 MHz
(when quartz-crystal/ring oscillation
VDD
Conditions
V
V
(when RC oscillation is used)
VRAM
RAM back-up voltage
at RAM back-up mode
Mask ROM version
One Time PROM version
Supply voltage
VLC3
LCD power supply (Note 1)
1.8
VDD
2.5
VDD
P0, P1, P2, D0–D5
0.8VDD
XIN, XCIN
VDD
VDD
RESET
0.7VDD
0.85VDD
INT
0.85VDD
VDD
0.8VDD
VDD
P0, P1, P2, D0–D5
0
XIN, XCIN
RESET
0
0
0.2VDD
0.3VDD
INT
0
0.15VDD
0
0.15VDD
Mask ROM version
One Time PROM version
“H” level input voltage
CNTR
VIL
“L” level input voltage
CNTR
IOH(peak)
“H” level peak output current
“H” level average output current
–20
–10
–30
VDD = 3 V
–15
VDD = 5 V
–10
VDD = 3 V
–5
C
VDD = 5 V
–20
CNTR
VDD = 3 V
VDD = 5 V
–10
24
VDD = 3 V
12
VDD = 5 V
10
(Note 2)
IOL(peak)
“L” level peak output current
P0, P1, P2, D0–D7, C
CNTR
RESET
IOL(avg)
VDD = 3 V
4
“L” level average output current
P0, P1, P2, D0–D7, C
VDD = 5 V
15
(Note 2)
CNTR
VDD = 3 V
VDD = 5 V
7
5
RESET
VDD = 3 V
V
V
0.3VDD
VDD = 3 V
VDD = 5 V
P0, P1, P2, D0–D5
V
VDD
VDD = 5 V
P0, P1, P2, D0–D5
C
CNTR
IOH(avg)
V
0
VSS
VIH
V
1.6
2
mA
mA
mA
mA
2
ΣIOH(avg)
“H” level total average current
P0, P1, P2, D0–D5, C, CNTR
–40
mA
ΣIOL(avg)
“L” level total average current
P0, P1, P2, D0–D5, C, CNTR
60
mA
D6, D7, RESET
60
Notes 1: At 1/2 bias: VLC1 = VLC2 = (1/2)•VLC3
At 1/3 bias: VLC1 = (1/3)•VLC3, VLC2 = (2/3)•VLC3
2: The average output current is the average value during 100 ms.
Rev.1.01
Sep 17, 2003
page 121 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
RECOMMENDED OPERATING CONDITIONS 2
(Mask ROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
(One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted)
Symbol
f(XIN)
Parameter
Conditions
Oscillation frequency
Mask ROM
(with a ceramic resonator)
version
Through mode
Min.
Limits
Typ.
Max.
VDD = 4 to 5.5 V
6
VDD = 2.7 to 5.5 V
VDD = 2 to 5.5 V
4.4
2.2
VDD = 1.8 to 5.5 V
1.1
Frequency/2 mode VDD = 2.7 to 5.5 V
4.4
2.2
Frequency/4 mode VDD = 2 to 5.5 V
6
4.4
VDD = 1.8 to 5.5 V
Frequency/8 mode VDD = 1.8 to 5.5 V
6
One Time PROM Through mode
VDD = 4 to 5.5 V
version
VDD = 2.7 to 5.5 V
VDD = 2.5 to 5.5 V
4.4
Frequency/2 mode VDD = 2.7 to 5.5 V
6
4.4
6
2.2
VDD = 2.5 to 5.5 V
Frequency/4, 8 mode VDD = 2.5 to 5.5 V
Oscillation frequency
VDD = 2.7 to 5.5 V
f(XIN)
(at RC oscillation) (Note)
Oscillation frequency
Mask ROM
(with a ceramic resonator selected,
version
Through mode
external clock input)
6
4.4
MHz
VDD = 4 to 5.5 V
4.8
MHz
VDD = 2.7 to 5.5 V
VDD = 2 to 5.5 V
3.2
1.6
VDD = 1.8 to 5.5 V
0.8
Frequency/2 mode VDD = 2.7 to 5.5 V
4.8
VDD = 2 to 5.5 V
VDD = 1.8 to 5.5 V
3.2
1.6
4.8
Frequency/4 mode VDD = 2 to 5.5 V
f(XCIN)
Oscillation frequency (sub-clock)
f(CNTR) Timer external input frequency
tw(CNTR) Timer external input period
MHz
6
VDD = 2 to 5.5 V
VDD = 1.8 to 5.5 V
f(XIN)
Unit
VDD = 1.8 to 5.5 V
3.2
Frequency/8 mode VDD = 1.8 to 5.5 V
4.8
One Time PROM Through mode
VDD = 4 to 5.5 V
4.8
version
VDD = 2.7 to 5.5 V
VDD = 2.5 to 5.5 V
3.2
Frequency/2 mode VDD = 2.7 to 5.5 V
1.6
4.8
VDD = 2.5 to 5.5 V
3.2
Frequency/4, 8 mode VDD = 2.5 to 5.5 V
4.8
Quartz-crystal oscillator
CNTR
CNTR
3/f(STCK)
kHz
50
f(STCK)/6 Hz
s
(“H” and “L” pulse width)
TPON
Power-on reset circuit
valid supply voltage rising time
Mask ROM version
One Time PROM version
VDD = 0 → 1.8 V
100
VDD = 0 → 2.5 V
100
Note: The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits.
Rev.1.01
Sep 17, 2003
page 122 of 130
µs
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
at ceramic resonance (Mask ROM version)
at ceramic resonance (One Time PROM version)
f(STCK)
[MHz]
f(STCK)
[MHz]
6
6
4.4
4.4
2.2
2.2
Recommended
operating conditions
Recommended
operating conditions
1.1
1.8 2
2.7
4.5
5.5
VDD
[V]
at RC oscillation (Mask ROM version)
2.5
2.7
f(STCK)
[MHz]
4.4
4.4
Recommended
operating
conditions
5.5
VDD
[V]
2.7
f(STCK)
[MHz]
4.8
4.8
3.2
3.2
1.6
1.6
Recommended
operating
conditions
2.7
4.5
5.5
VDD
[V]
2.5
2.7
4.5
5.5
VDD
[V]
at quartz-crystal oscillation (One Time PROM version)
f(STCK)
[kHz]
f(STCK)
[kHz]
50
50
Recommended
operating
conditions
1.8
Sep 17, 2003
VDD
[V]
Recommended
operating
conditions
at quartz-crystal oscillation (Mask ROM version)
Rev.1.01
5.5
at external clock oscillation (One Time PROM version)
f(STCK)
[MHz]
1.8 2
VDD
[V]
Recommended
operating
conditions
at external clock oscillation (Mask ROM version)
0.8
5.5
at RC oscillation (One Time PROM version)
f(STCK)
[MHz]
2.7
4.5
page 123 of 130
Recommended
operating
conditions
5.5
VDD
[V]
2.5
5.5
VDD
[V]
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
ELECTRICAL CHARACTERISTICS 1
(Mask ROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
(One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted)
Symbol
VOH
Parameter
“H” level output voltage
Test conditions
IOH = –10 mA
IOH = –3 mA
4.1
VDD = 3 V
IOH = –5 mA
IOH = –1 mA
2.1
VDD = 5 V
IOH = –20 mA
3
IOH = –6 mA
IOH = –10 mA
4.1
2.1
IOH = –3 mA
2.4
VDD = 5 V
P0, P1, P2, D0–D5
VOH
“H” level output voltage
C, CNTR
VDD = 3 V
VOL
“L” level output voltage
“L” level output voltage
2.4
V
VDD = 3 V
IOL = 9 mA
1.4
IOL = 3 mA
0.9
VDD = 5 V
Unit
V
2
0.9
V
IOL = 5 mA
2
IOL = 1 mA
0.6
IOL = 2 mA
VI = VDD
0.9
2
µA
VI = 0 V P0, P1 No pull-up
–2
µA
kΩ
VDD = 3 V
“H” level input current
P0, P1, P2, D0–D5, XIN, XCIN, RESET
Max.
IOL = 15 mA
IOL = 5 mA
RESET
IIH
Typ.
VDD = 5 V
P0, P1, P2, D0–D7, C, CNTR
VOL
Limits
Min.
3
V
CNTR, INT
IIL
“L” level input current
P0, P1, P2, D0–D5, XIN, XCIN, RESET
RPU
CNTR, INT
Pull-up resistor value
VI = 0 V
P0, P1, RESET
VDD = 5 V
30
60
125
VDD = 3 V
50
120
250
VDD = 5 V
1
VDD = 3 V
0.4
VDD = 5 V
0.6
0.3
V
VDD = 3 V
VT+ – VT– Hysteresis CNTR
VDD = 5 V
0.2
V
0.2
f(RING)
VDD = 3 V
VDD = 5 V
VT+ – VT– Hysteresis RESET
VT+ – VT– Hysteresis INT
Ring oscillator clock frequency
VDD = 3 V
∆f(XIN)
V
200
500
700
100
250
400
Frequency error
VDD = 5 V ± 10 %, Ta = 25 °C
±17
(with RC oscillation,
error of external R, C not included )
VDD = 3 V ± 10 %, Ta = 25 °C
±17
kHz
%
(Note 1)
COM output impedance
VDD = 5 V
1.5
7.5
(Note 2)
VDD = 3 V
2
10
RSEG
SEG output impedance
VDD = 5 V
kΩ
VDD = 3 V
1.5
2
7.5
RVLC
(Note 2)
Internal resistor for LCD power supply
kΩ
RCOM
When dividing resistor 2r ✕ 3 selected
300
480
10
960
When dividing resistor 2r ✕ 2 selected
When dividing resistor r ✕ 3 selected
200
150
320
640
240
480
When dividing resistor r ✕ 2 selected
100
160
320
Notes 1: When RC oscillation is used, use the external 33 pF capacitor (C).
2: The impedance state is the resistor value of the output voltage.
at VLC3 level output: VO = 0.8 VLC3
at VLC2 level output: VO = 0.8 VLC2
at VLC1 level output: VO = 0.2 VLC2 + VLC1
at VSS level output: VO = 0.2 VSS
Rev.1.01
Sep 17, 2003
page 124 of 130
kΩ
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
ELECTRICAL CHARACTERISTICS 2
(Mask ROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
(One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted)
Symbol
IDD
Parameter
Supply current at active mode
Test conditions
VDD = 5 V
(with a ceramic resonator) f(XIN) = 6 MHz
f(RING) = stop
f(STCK) = f(XIN)/4
1.3
2.6
3.2
4.4
f(STCK) = f(XIN)/2
1.6
f(XCIN) = stop
f(STCK) = f(XIN)
VDD = 5 V
f(XIN) = 4 MHz
f(STCK) = f(XIN)/8
2.2
0.9
2.4
1.8
1
2
f(RING) = stop
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
1.2
2.4
f(XCIN) = stop
f(STCK) = f(XIN)
1.6
3.2
VDD = 3 V
f(STCK) = f(XIN)/8
0.3
f(XIN) = 4 MHz
f(STCK) = f(XIN)/4
0.6
0.8
f(RING) = stop
f(XCIN) = stop
f(STCK) = f(XIN)/2
0.4
0.5
1.4
50
100
60
120
160
240
VDD = 5 V
(with a ring oscillator)
f(XIN) = stop
f(STCK) = f(RING)/4
f(RING) = active
f(STCK) = f(RING)/2
80
f(XCIN) = stop
f(STCK) = f(RING)
VDD = 3 V
f(XIN) = stop
f(STCK) = f(RING)/8
120
10
20
13
26
f(RING) = active
f(STCK) = f(RING)/4
f(STCK) = f(RING)/2
19
38
f(XCIN) = stop
f(STCK) = f(RING)
31
62
at active mode
(with a quartz-crystal
VDD = 5 V
f(STCK) = f(XCIN)/8
7
f(XIN) = stop
f(STCK) = f(XCIN)/4
14
16
oscillator)
f(RING) = stop
f(XCIN) = 32 kHz
f(STCK) = f(XCIN)/2
f(STCK) = f(XCIN)
8
10
VDD = 3 V
28
f(STCK) = f(XCIN)/8
5
10
f(XIN) = stop
f(STCK) = f(XCIN)/4
6
12
f(RING) = stop
f(STCK) = f(XCIN)/2
7
f(XCIN) = 32 kHz
f(STCK) = f(XCIN)
14
16
f(XCIN) = 32 kHz
VDD = 5 V
VDD = 3 V
8
6
12
Ta = 25 °C
(POF2 instruction execution)
VDD = 5 V
10
VDD = 3 V
6
page 125 of 130
mA
mA
µA
µA
µA
µA
µA
10
at RAM back-up mode
0.1
mA
20
14
5
Unit
1.0
0.7
at active mode
(POF instruction execution)
Sep 17, 2003
Max.
f(STCK) = f(XIN)/8
Typ.
1.2
f(STCK) = f(XIN)
f(STCK) = f(RING)/8
at clock operation mode
Rev.1.01
Limits
Min.
2
µA
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
VOLTAGE DROP DETECTION CIRCUIT CHARACTERISTICS
(Ta = –20 °C to 85 °C, unless otherwise noted)
Symbol
VRST–
VRST+
Test conditions
Parameter
Detection voltage
Ta = 25 °C
(reset occurs) (Note 2)
Ta = -20 to 0 °C
Min.
1.6
1.7
1.8
Max.
2
2.3
Ta = 0 to 50 °C
Ta = 50 to 85 °C
1.4
Detection voltage
Ta = 25 °C
1.7
(reset release) (Note 3)
Ta = -20 to 0 °C
1.8
2.4
Ta = 0 to 50 °C
1.5
1.3
2.3
2
V
1.9
1.9
2.1
V
V
0.1
Detection voltage hysteresis
Unit
2.2
1.2
Ta = 50 to 85 °C
VRST+ –
Limits
Typ.
VRST–
IRST
TRST
Operation current (Note 4)
Detection time (Note 5)
VDD = 5 V
50
100
VDD = 3 V
30
60
VDD → (VRST– – 0.1 V)
0.2
1.2
Notes 1: The voltage drop detection circuit is equipped with only the H version.
2: The detected voltage (VRST–) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling.
3: The detected voltage (VRST+) is defined as the voltage when reset is released when the supply voltage (VDD) is rising from reset occurs.
4: In the H version, IRST is added to IDD (power current).
5: The detection time (TRST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST– – 0.1 V].
BASIC TIMING DIAGRAM
Parameter
Machine cycle
Pin (signal) name
System clock
STCK
Port D output
D0–D7
Port D input
D0–D5
Ports P0, P1, P2
output
P00–P03
P10–P13
P20–P23
Ports P0, P1, P2 input P00–P03
P10–P13
P20–P23
Interrupt input
Rev.1.01
Sep 17, 2003
INT
page 126 of 130
Mi
Mi+1
µA
ms
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
BUILT-IN PROM VERSION
In addition to the mask ROM versions, the 4556 Group has the
One Time PROM versions whose PROMs can only be written to
and not be erased.
The built-in PROM version has functions similar to those of the
mask ROM versions, but it has PROM mode that enables writing to
built-in PROM.
Table 19 Product of built-in PROM version
PROM size
Part number
(✕ 10 bits)
M34556G8FP
8192 words
M34556G8HFP
RAM size
(✕ 4 bits)
288 words
Table 19 shows the product of built-in PROM version. Figure 56
shows the pin configurations of built-in PROM versions.
The One Time PROM version has pin-compatibility with the mask
ROM version.
Package
42P2R-A
ROM type
One Time PROM [shipped in blank]
(1) PROM mode
The 4556 Group has a PROM mode in addition to a normal operation mode. It has a function to serially input/output the command
codes, addresses, and data required for operation (e.g., read and
program) on the built-in PROM using only a few pins. This mode
can be selected by muddog entry after powering on the VDD pin.
In the PROM mode, three types of software commands (read, program, and program verify) can be used. Clock-synchronous serial
I/O is used, beginning from the LSB (LSB first).
Writing with PROM programmer
Screening (Leave at 150 °C for 40 hours) (Note)
(2) Notes on handling
➀For the One Time PROM version shipped in blank, Mitsubishi
Electric corp. does not perform PROM writing test and screening
in the assembly process and following processes. In order to improve reliability after writing, performing writing and test
according to the flow shown in Figure 56 before using is recommended (Products shipped in blank: PROM contents is not
written in factory when shipped).
(3) Difference between Mask ROM version and
One Time PROM version
Mask ROM version and One Time PROM version have some difference of the following characteristics within the limits of an
electrical property by difference of a manufacture process, builtin ROM, and a layout pattern.
• a characteristic value
• a margin of operation
• the amount of noise-proof
• noise radiation, etc.,
Accordingly, be careful of them when swithcing.
Rev.1.01
Sep 17, 2003
page 127 of 130
Verify test with PROM programmer
Function test in target device
Note: Since the screening temperature is higher
than storage temperature, never expose the
microcomputer to 150 °C exceeding 100
hours.
Fig. 56 Flow of writing and test of the product shipped in blank
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
PIN CONFIGURATION (TOP VIEW)
RESET
XIN
1
42
VSS
VSS
XOUT
2
41
VDD
VDD
C/CNTR
CNVSS
3
40
XCIN/D6
4
39
D5/INT
XCOUT/D7
5
38
D4
RESET
6
37
D3
COM0
7
36
D2
COM1
8
35
D1
COM2
9
34
D0
COM3
10
33
P13/SEG28
SEG0/VLC3
11
32
P12/SEG27
SEG1/VLC2
12
31
P11/SEG26
SEG2/VLC1
13
30
P10/SEG25
SEG3
14
29
P03/SEG24
SEG4
15
28
P02/SEG23
SEG5
16
27
P01/SEG22
SEG6
17
26
P00/SEG21
SEG7
18
25
P23/SEG20
SEG8
19
24
P22/SEG19
SEG9
20
23
P21/SEG18
SEG10
21
22
P20/SEG17
Fig. 57 Pin configuration of built-in PROM version
Rev.1.01
Sep 17, 2003
page 128 of 130
M34556G8FP
M34556G8HFP
XIN
XOUT
VPP
VDD
VDD
PGM
SDA
SCLK
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
ROM CODE ACCESS PROTECTION
We would like to support a simple ROM code protection function
that prevents a party other than the ROM-code owner to read and
reprogram the built-in PROM code of the MCU.
First, Programmers must check the ID-code of the MCU.
If the ID-code is not blank, Programmer verifies it with the input IDcode. When the ID-codes do not match, Programmer will reject all
further operations.
The MCU has each 10 bits of dedicated ROM spaces in address
009016 to 009616, as an ID-code (referred to as “the ID-code”) enabling a Programmer to verify with the input ID-code and validate
further operations.
Address
009016
ID1
009116
ID2
009216
ID3
009316
ID4
009416
ID5
009516
ID6
009616
ID7
009716
Fig. 58 ROM-Code Protection ID Location
Rev.1.01
Sep 17, 2003
page 129 of 130
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4556 Group
PACKAGE OUTLINE
MMP
42P2R-A
EIAJ Package Code
SSOP42-P-450-0.80
Plastic 42pin 450mil SSOP
JEDEC Code
–
Weight(g)
0.63
e
b2
22
E
HE
e1
I2
42
Lead Material
Alloy 42/Cu Alloy
Recommended Mount Pad
F
Symbol
1
21
A
D
G
A2
e
b
L
L1
y
A1
A
A1
A2
b
c
D
E
e
HE
L
L1
z
Z1
y
c
z
Z1
Rev.1.01
Detail G
Sep 17, 2003
page 130 of 130
Detail F
b2
e1
I2
Dimension in Millimeters
Min
Nom
Max
2.4
–
–
–
–
0.05
–
–
2.0
0.5
0.35
0.4
0.2
0.15
0.13
17.7
17.5
17.3
8.6
8.4
8.2
–
0.8
–
12.23
11.93
11.63
0.7
0.5
0.3
–
1.765
–
–
0.75
–
–
–
0.9
0.15
–
–
0°
–
10°
–
0.5
–
–
11.43
–
–
1.27
–
REVISION HISTORY
Rev.
Date
4556 Group Data Sheet
Description
Summary
Page
1.00 Jul. 23, 2003
–
First edition issued
1.01 Sep. 17, 2003
50
51
61
128
Voltage drop detection circuit (only in H version) revised.
Table 15 revised. (Timer functions, Timer control registers, Port level, and Notes 6 and 7)
19 Voltage drop detection circuit (only in H version) revised.
Fig.57 revised.
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
nonflammable material or (iii) prevention against any malfunction or mishap.
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programs, algorithms, or circuit application examples contained in these materials.
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