NMOS linear image sensors / Technical information

TECHNICAL INFORMATION
SD-26
Characteristic and use of
NMOS linear image sensors
Contents
1. Introduction ....................................................................................................................... 4
2. Structure and basic operation ........................................................................................... 4
2-1. Structure ................................................................................................................................................. 4
2-2. Charge integration method .................................................................................................................... 4
2-3. Signal readout by shift register .............................................................................................................. 5
3. Sensor types and operation .............................................................................................. 5
3-1. Types of NMOS linear image sensors ................................................................................................... 5
3-2. Current output type NMOS linear image sensors ................................................................................. 6
3-2-1.
3-2-2.
3-2-3.
3-2-4.
3-2-5.
Configurations ....................................................................................................................................................... 6
Operating principle of current output type ........................................................................................................... 7
Readout method for the current output types ...................................................................................................... 8
Terminal voltage for current output types ............................................................................................................ 9
Input/output pulse timing for current output type ............................................................................................... 11
3-3. Voltage output type NMOS linear image sensors ................................................................................ 12
3-3-1.
3-3-2.
3-3-3.
3-3-4.
3-3-5.
Configurations of the voltage output types ........................................................................................................ 12
Operating principle of the voltage output types ................................................................................................. 13
Readout method for the voltage output types .................................................................................................... 13
Terminal voltage for the voltage output types .................................................................................................... 14
Input/output pulse timing for voltage output type ............................................................................................... 14
4. Characteristics ............................................................................................................... 16
4-1. Input/output characteristics .................................................................................................................. 16
4-1-1. Input/output characteristics (current output type) ............................................................................................. 16
4-1-2. Input/output characteristics (voltage output type) ............................................................................................. 16
4-2. Linearity error ........................................................................................................................................ 17
4-3. Spectral response characteristics ....................................................................................................... 17
4-4. Photoresponse non-uniformity ............................................................................................................ 18
4-5. Dark output ........................................................................................................................................... 18
4-6. Resolution ............................................................................................................................................ 20
4-7. Lag ........................................................................................................................................................ 21
4-8. Noise .................................................................................................................................................... 22
4-8-1. Random noise in current output type ................................................................................................................. 22
4-8-2. Random noise (voltage output type) .................................................................................................................. 23
4-9. Shift register frequency characteristics ................................................................................................ 24
4-10. Characteristic change by UV exposure .............................................................................................. 25
5. Precautions ..................................................................................................................... 26
5-1. Integration time setting ......................................................................................................................... 26
5-2. Output estimation ................................................................................................................................. 26
5-3. Light sources ........................................................................................................................................ 27
5-4. Positional accuracy of photosensitive area ......................................................................................... 27
5-5. Precautions during handling ................................................................................................................ 28
5-6. Precautions when configuring driver circuit boards ............................................................................ 29
6. Recommended driver circuits......................................................................................... 30
6-1. Driver circuit for current output type ...................................................................................................... 30
6-1-1. Current-to-voltage conversion method .............................................................................................................. 30
6-1-2. External current-integration method ................................................................................................................... 34
6-2. Driver circuit for voltage output type image sensor .............................................................................. 39
6-3. Pulse generator .................................................................................................................................... 44
7. Standard driver circuits ................................................................................................... 45
7-1. Driver circuit configurations .................................................................................................................. 45
7-2. Driver circuit functions .......................................................................................................................... 45
7-3. External current-integration circuit C7884 series for current-output image sensor ........................... 49
7-3-1. Product lineup ..................................................................................................................................................... 49
7-3-2. Specifications ...................................................................................................................................................... 49
7-3-3. How C7884 series differs from recommended circuit ....................................................................................... 50
7-4. Pulse generator circuit C8225 series .................................................................................................. 51
7-4-1. Product lineup ..................................................................................................................................................... 51
7-4-2. Specifications ...................................................................................................................................................... 51
7-4-3. Switch setting ...................................................................................................................................................... 52
7-5. Multichannel measurement units ........................................................................................................ 53
8. Reliability ......................................................................................................................... 54
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Characteristic and use of NMOS linear image sensors
Figure 2-2 Output timing diagram
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1. Introduction
START PULSE TO
SHIFT REGISTER
ADDRESS PULSE TO
SHIFT PHOTODIODE 1
ADDRESS PULSE TO
SHIFT PHOTODIODE 2
ADDRESS PULSE TO
SHIFT PHOTODIODE 3
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INTEGRATION TIME
The NMOS linear image sensor is a self-scanning photodiode
array designed specifically for detectors used in multichannel
spectroscopy. The NMOS linear image sensor offers a number
of features, for example, a large photosensitive area, high UV
sensitivity, stable performance against UV exposure, wide dynamic range due to low dark current and high saturation
charge, superior output linearity and uniformity, and also low
power consumption. In addition to standard types with a quartz
window, devices with a fiber optic plate are available allowing
efficient optical coupling to other imaging devices. Applications
include not only spectroscopy but also a diverse range of image
readout systems.
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OUTPUT SIGNAL
1
2
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n
1
2
3
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n
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This section explains the structure and operations of NMOS
linear image sensors.
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2. Structure and basic operation
ADDRESS PULSE TO
SHIFT PHOTODIODE n
TIME
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2-1. Structure
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START PULSE
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MOS SHIFT REGISTER
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CLOCK PULSE
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VIDEO LINE
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SWITCH
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PHOTODIODE
3
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n
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2
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1
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KMPDC0057EA
In contrast to the real-time signal readout method used for most
photodiodes, the NMOS linear image sensor uses a charge
integration method to read out the signal. In this method, an
electrical charge generated by photoelectric conversion at the
photodiode array is temporarily stored in the junction capacitance of each photodiode. The signal stored in each photodiode is read out through an output line (video line) by sequentially turning on the address switch connected to each photodiode at a delayed timing with respect to the preceding signal.
The MOS shift register is used to produce the address pulses
that turn on these switches. A typical output timing diagram is
shown in Figure 2-2.
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KMPDC0058EA
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Figure 2-1 NMOS linear image sensor equivalent circuit
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An NMOS linear image sensor, as shown in Figure 2-1, consists
of a photosensitive section constructed with a photodiode array,
a switch section that reads out the signal from the photodiode
array, and a shift register that addresses these switches.
2-2. Charge integration method
In the real-time readout method used for most photodiodes, the
signal output is proportional only to the incident light intensity. In
the charge integration method, however, the signal output is
obtained in proportion to the product of light intensity and integration time, that is, the signal output is proportional to the
amount of light exposure. This means that the signal output
level can be increased by making the integration time longer,
enabling low-light-level detection even with a photodiode with
small photosensitive area.
In NMOS linear image sensor operation, the integration time of
each photodiode is the time interval between when one switch
is turned on for signal readout, and the time at which the same
switch is turned on for the next readout. This is equal to the time
interval between each start pulse signal for the MOS shift register. If the incident light level changes within this integration time,
the change cannot be read out. Strictly speaking, the start time
for integration does shift slightly because the switch for each
photodiode is time-sequentially turned on as the signal is read
out. Therefore, if the light level varies with time, the signal output
from each photodiode does not become constant even though
the entire image sensor is uniformly illuminated.
There is an upper limit on the output charge since the junction
capacitance in which a signal charge is stored is finite. This is
called the saturation charge above which the signal output will
not increase with excessive light.
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Characteristic and use of NMOS linear image sensors
3. Sensor types and operation
3-1. Types of NMOS linear image sensors
Hamamatsu NMOS linear image sensors are available in the
following two readout methods.
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This section explains the types and configurations of
Hamamatsu NMOS linear image sensors as well as their operating principles.
The current output type offers superior linearity when used with
an external signal readout circuit operating in the current integration mode, making it ideally suited for use in applications
where high accuracy is particularly needed. The current output
type also gives a high-speed readout when used with the current-to-voltage conversion method.
The voltage output type NMOS linear image sensors use the
same output section as the current output type, but further in-
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1. Current output type S3901 to S3904 series, etc.
2. Voltage output type S3921 to S3924 series
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As stated above, NMOS linear image sensors use the charge
integration method in which the signal from each photodiode is
time-sequentially read out through one output line. It is not
therefore necessary to connect an individual readout circuit to
each photodiode. This means the external circuit configuration
is made simple.
When an external start pulse is applied to the shift register while
a two-phase clock pulse is being input, an address pulse is
sequentially sent to turn on the address switch of the 1st channel photodiode and thus the signal stored in each photodiode is
read out. If the next start pulse is introduced to the shift register
before the signals of all channels are read out, then two address
switches turn on at the same time, resulting in erroneous operation. Accordingly, the start pulse interval (integration time) must
be set longer than the readout time required for all channels.
NMOS linear image sensors use a different readout method
than for normal photodiodes. It is essential that the user understand these distinctions to make optimum settings to match operating conditions such as incident light level and integration
time length.
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2-3. Signal readout by shift register
Table 3-1 Quick reference for Hamamatsu NMOS linear image sensors
Current output type
Type No.
S3901-128Q, F
S3901-256Q, F
S3901-512Q, F
S3904-256Q, F
S3904-512Q, F
S3904-1024Q, F
S3902-128Q, F
S3902-256Q, F
S3902-512Q, F
S3903-256Q, F
S3903-512Q, F
S3903-1024Q, F
Number of pixels
128
256
512
256
512
1024
128
256
512
256
512
1024
Pixel size
(pixel pitch × height)
(μm)
50 × 2500
25 × 2500
50 × 500
25 × 500
Active area
[mm (H) × mm (V)]
6.4 × 2.5
12.8 × 2.5
25.6 × 2.5
6.4 × 2.5
12.8 × 2.5
25.6 × 2.5
6.4 × 0.5
12.8 × 0.5
25.6 × 0.5
6.4 × 0.5
12.8 × 0.5
25.6 × 0.5
Feature
• Low power consumption
• Superior output linearity
• Wide dynamic range
Voltage output type
Type No.
S3921-128Q, F
S3921-256Q, F
S3921-512Q, F
S3924-256Q, F
S3924-512Q, F
S3924-1024Q, F
S3922-128Q, F
S3922-256Q, F
S3922-512Q, F
S3923-256Q, F
S3923-512Q, F
S3923-1024Q, F
Number of pixels
128
256
512
256
512
1024
128
256
512
256
512
1024
Pixel size
(pixel pitch × height)
(μm)
50 × 2500
25 × 2500
50 × 500
25 × 500
Active area
[mm (H) × mm (V)]
6.4 × 2.5
12.8 × 2.5
25.6 × 2.5
6.4 × 2.5
12.8 × 2.5
25.6 × 2.5
6.4 × 0.5
12.8 × 0.5
25.6 × 0.5
6.4 × 0.5
12.8 × 0.5
25.6 × 0.5
Feature
• Boxcar output waveform
• Simple external readout
circuit
• Wide dynamic range
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Figure 3-2 Pinout (current output type)
NC
st
3
20
NC
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NC
21
4
19
NC
5
18
NC
NC
6
17
NC
Vscd
7
16
NC
Vss
8
15
NC
ACTIVE VIDEO
9
14
NC
DUMMY VIDEO
10
13
NC
Vsub
11
12
END OF SCAN
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Vss
Vscg
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Input
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Ground
Output
φ1
φ2
φst
Vscd
Vscg
Vss
Vsub
NC
Active video
Dummy video
EOS
Function
Clock pulse 1
Clock pulse 2
Start pulse
Saturation control drain
Saturation control gate
Ground (anode potential)
Substrate potential
No connection
Signal output
Switching noise output
End of scan
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The current output type NMOS linear image sensor consists of
a photosensitive section, readout switch section and shift register, integrated into a single chip. In addition, dummy photodiodes and anti-blooming switches are formed on the same
chip. Figure 3-1 shows the equivalent circuit for the current output type and Figure 3-2 shows the pinout configurations. The
pin designations and their functions are listed in Table 3-2.
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2
Terminal
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3-2-1. Configurations
1
1
Table 3-2 Pin description (current output type)
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3-2. Current output type NMOS linear image
sensors
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KMPDC0021EA
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clude a signal processing circuit that consists of a current integration circuit utilizing video line capacitance and an impedance conversion circuit. Although the linearity accuracy is
slightly lower than the current output type operated in the current integration mode, the voltage output type can internally
produce a low-impedance output signal with boxcar waveform.
This allows signal readout with a simple external circuit.
Table 3-1 gives the major product line of Hamamatsu NMOS
linear image sensors. Suffix “Q” of the type number means the
image sensors have a quartz window, while suffix “F” indicates
a fiber optic plate is used. The quartz window types ensure high
sensitivity in the UV range and also provide stable operation for
dark current and sensitivity performance even after extended
periods of UV exposure. Image sensors having a fiber optic
plate can be easily fiber-coupled to another optical element
such as an image intensifier. For detection of X-rays from 10
keV to 100 keV, semi-custom devices (“FX” type) having a
phosphor-coated fiber optic plate are also available in each
family of current output and voltage output type NMOS linear
image sensors. Furthermore, S8380/S8381 series devices with
enhanced near infrared sensitivity are provided.
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Characteristic and use of NMOS linear image sensors
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Figure 3-1 Equivalent circuit (current output type)
ADDRESS SWITCH
PHOTOSENSITIVE
SECTION
ACTIVE
PHOTODIODES
ANTIBLOOMING
SWITCHES
SATURATION
CONTROL GATE
SATURATION
CONTROL DRAIN
ADDRESS SWITCH
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SWITCH
SECTION
MOS SHIFT REGISTER
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2
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1
CLOCK
ACTIVE
VIDEO
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CLOCK
END OF
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DUMMY
VIDEO
DUMMY DIODES
1) Shift register
The shift register is comprised of N-channel MOS transistors.
Pins φ1, φ2 and φst in Figure 3-2 are input pulse terminals used
to operate the shift register. When an external start pulse φst is
supplied to the shift register with the two-phase clock pulse φ1
and φ2 being applied, the shift register begins operation and
generates a train of address pulses to sequentially turn on the
address switch beginning with the 1st channel. The shift register is designed for low power consumption to minimize temperature rise in the sensor elements. When one scan for all
pixels is completed, an end-of-scan (EOS) pulse is output at a
timing immediately after the last pixel is readout.
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DUMMY DIODE
SECTION
Vss
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SWITCH
SECTION
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SCANNING
CIRCUIT
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st
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START
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KMPDC0059EA
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(2) Photosensitive section
The photosensitive section is constructed with P-N junction
photodiodes consisting of an N-type diffusion layer formed on a
P-type silicon substrate. This section serves as a photoelectric
converter that transforms light signals into electrical signals,
and also temporarily stores the signal charge obtained. Pin Vss
is connected to the anode (P-type silicon) of each photodiode.
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todiode, the photodiode cannot store a signal charge in excess
of the saturation charge. Without saturation control, this causes
the excess signal charge to overflow and diffuse into the adjacent photodiodes and the video line, resulting in deterioration of
signal purity, so-called “blooming”.
An anti-blooming switch is provided in Hamamatsu NMOS linear image sensors for each photodiode separately from the
normal signal output line connected to the video line, in order to
allow the excess charge to bleed off.
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c
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Figure 3-3 Active area structure (current output type)
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The photodiode is designed and processed to provide high UV
sensitivity yet low dark current. The structure of the photosensitive section is shown in Figure 3-3, in which “a” is the photodiode pitch, “b” is the width of the photodiode diffusion layer and
“c” is the photodiode height.
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Characteristic and use of NMOS linear image sensors
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b
Figure 3-4 shows the structure of one pixel comprised of a photodiode and a readout switch, and Figure 3-5 shows its equivalent circuit. Specific operations are described below.
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Figure 3-4 Readout section structure
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SILICON OXIDE
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1.0 µm
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a
3-2-2. Operating principle of current output type
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VIDEO LINE
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1.0 µm
N TYPE SILICON
400 µm
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ADDRESS PULSE
FROM SHIFT REGISTER
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P TYPE SILICON
OUTPUT SIGNAL
hυ
PHOTODIODE
SWITCH
N
LOAD RESISTANCE RL
N
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c=2.5 mm
c=2.5 mm
c=0.5 mm
c=0.5 mm
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b=45 µm
b=20 µm
b=45 µm
b=20 µm
P
SUPPLY VOLTAGE V
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ADDRESS PULSE
FROM SHIFT REGISTER
VIDEO LINE
OUTPUT SIGNAL
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Figure 3-5 Equivalent circuit of current-to-voltage conversion method
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SWITCH
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LOAD RESISTANCE RL
KMPDC0062EA
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SUPPLY VOLTAGE V
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The photodiode is a P-N junction photodiode consisting of an
N-type diffusion area formed on a P-type silicon substrate. The
readout switch consists of an N-channel MOS transistor, with its
source connected to the cathode of a photodiode while the
drain and gate are respectively connected to the video line and
the address pulse input part from the shift register. The photodiode anode (silicon substrate) is connected to GND, and the
video line is biased at the positive potential Vb.
When an address pulse from the shift register is input to the gate
of the readout switch, the switch turns on. As a result, the photodiode cathode sets to the same potential as that of the video line
and the photodiode is initialized and reverse-biased. Thus the
photodiode junction capacitance Cj is fed with a charge, Qj=Cj
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(5) Anti-blooming switch
The anti-blooming switch section comprises a switch array constructed with N-channel MOS transistors, with the source of
each transistor connected to the cathode of a photodiode while
the drain and gate are connected respectively, to the saturation
control drain Vscd and saturation control gate Vscg.
When a light higher than the saturation exposure enters a pho-
KMPDC0061EA
PHOTODIODE
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(4) Readout switch
The readout switch section consists of an address switch array
made up of N-channel MOS transistors, with the source of each
transistor connected to the cathode of a photodiode or dummy
photodiode while the drain and gate are connected respectively, to the video line and address pulse input. Each photodiode in the photosensitive section is connected to the video
line via the individual address switch. When an address pulse is
applied from the shift register, the two address switches turn on
at the same time, and the output signal including spike noise is
derived from the active video line, while the spike noise signal is
output from the dummy video line. When the image sensor is
operated in the current-to-voltage conversion method, the output signal can be obtained with low spike noise, by performing
external differential amplification of each signal from the two
video lines. The spike noise appears via floating capacitance
between the gate and drain of each address switch at the time
that the address pulse is introduced.
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(3) Dummy photodiode
Dummy photodiodes generate a spike noise signal used for
external cancellation of spike noise in the current-to-voltage
conversion readout method. These photodiodes are shielded
with aluminum so that they are impervious to light.
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KMPDA0147EA
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S3901 SERIES: a=50 µm
S3904 SERIES: a=25 µm
S3902 SERIES: a=50 µm
S3903 SERIES: a=25 µm
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ADDRESS PULSE
FROM SHIFT REGISTER
3-2-3. Readout method for the current output types
(1) Current-to-voltage conversion method
The previous section described signal readout operating principle, using current-to-voltage conversion as one example of
light detection. In this method, the peak value of a differential
output waveform is read out as a signal output. However, the
output waveform taken at low output will not be identical pulse
shape to that taken at a high output. The lower the amplitude of
the output, the longer the time required to reach peak value. As
a result, the ratio of peak value to the area of the differential
waveform decreases. Since the amount of charge to be read out
corresponds to the differential waveform area, when measuring
the input/output characteristics by the current-to-voltage conversion method, its slope at low output is larger than that at high
output. For this reason, this signal readout method is not suited
for light detection where high accuracy at low output levels is
required. This method does however offer the advantages of
high-speed readout and simplified circuitry.
Figure 3-8 shows a recommended readout circuit. In order to
eliminate spike noise, after performing current-to-voltage conversion, this circuit extracts the differential output between signals from the video line and dummy video line.
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+V
In actual operation, the charge current gradually discharges
due to the re-combination current in the depletion layer and the
surface leakage current as well as the photocurrent described
above. These currents which are unrelated to the illumination of
light are referred to as the dark current and its output is called
the dark output. (See section 4-5.)
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Figure 3-6 Operation of current-to-voltage conversion method
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× Vb, from the power supply. When the readout switch is off
(open circuit) and the signal charge begins to accumulate, the
charge stored in the photodiode junction capacitance Cj is discharged when the charge generated by light (photocurrent) occurs. As shown in Figure 3-6, the slope of the potential across
the photodiode is a function of incident light. That is, the greater
the light intensity the more electron-hole pairs are created and
the faster the charge accumulates on Cj. Therefore photodiode
potential approaches GND potential. The amount of this discharge increases in proportion to the incident light level, but the
maximum amount is limited by the amount of charge initially
stored. This corresponds to the saturation charge.
When an address pulse from the shift register is then input and
the readout switch turns on, a charge equal to that discharged
during the integration time is fed from the power supply through
the load resistance RL, so that the photodiode is initialized
again. At this point, a potential difference resulting from the
charge current is developed across the load resistor RL, and is
detected as an output voltage. This output has a differential
waveform with a negative polarity with respect to the video line
bias voltage Vb. This signal readout method is known as the
current-to-voltage conversion and its simplified operating diagram is shown in Figure 3-6. In some cases, a feedback circuit
using an operational amplifier is used, as shown in Figure 3-7.
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Characteristic and use of NMOS linear image sensors
Figure 3-8 Recommended readout circuit for current-tovoltage conversion method
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PHOTODIODE
POTENTIAL
+5 V
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GND
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LOW OUTPUT
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10 kΩ
st
st
1
1
2
2
EOS
EOS
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HIGH OUTPUT
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5.1 kΩ
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OUTPUT VOLTAGE +V
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DUMMY
VIDEO
+
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TIME
KMPDC0063EA
5.1 kΩ
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Vss
Vsub
NC
ACTIVE
VIDEO
Vscd
+
+
+
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Figure 3-7 Equivalent circuit of current-to-voltage conversion method using op-amp
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Vscg
+2 V
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FEEDBACK RESISTANCE Rf
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KMPDC0065EA
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VIDEO LINE
SWITCH
+
○
○
○
OUTPUT SIGNAL
○
ADDRESS PULSE
FROM SHIFT REGISTER
○
SUPPLY VOLTAGE V
○
KMPDC0064EA
○
○
○
○
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PHOTODIODE
8
(2) Current integration method
There is another signal readout method in which the charged
current is integrated in an external circuit to measure the
amount of charge. This method enables high-precision signal
detection even at low output levels. Figure 3-9 shows a typical
current-integration circuit diagram using a charge amplifier. In
this circuit, the feedback capacitance Cf in the charge amplifier
is discharged by applying an external reset pulse immediately
before the readout switch turns on. When the readout switch
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Figure 3-9 Equivalent circuit of current-integration circuit
using a charge amplifier
○
○
has turned on, a charge which corresponds to the discharge
during the integration time is supplied to the photodiode junction capacitance from the power supply, so that the photodiode
is initialized. At the same time, the feedback capacitance Cf is
also charged by this current. This, allows an integration waveform with positive polarity to be derived from the output terminal
of the integration circuit. This output voltage Vout is proportional
to the amount of charge Q, and expressed as Vout=Q/Cf. The
output is a boxcar waveform, which facilitates signal processing. However, since this output waveform response is determined by the discharge time constant of the feedback capacitance Cf, the maximum readout frequency will be around 100
kHz.
Figure 3-10 shows a recommended readout circuit. For an
evaluation circuit using this method, Hamamatsu provides
C7884 series driver circuits. C7884 series includes a clamping
circuit connected to the latter stage in order to reduce random
noise components.
○
Characteristic and use of NMOS linear image sensors
○
○
○
RESET PULSE
○
OUTPUT SIGNAL
○
-
VIDEO LINE
SWITCH
○
+
○
○
○
ADDRESS PULSE
FROM SHIFT REGISTER
○
○
○
○
FEEDBACK
CAPACITANCE Cf
PHOTODIODE
○
○
○
○
○
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○
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SUPPLY VOLTAGE V
○
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Figure 3-10 Recommended readout circuit for current
integration method
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KMPDC0066EA
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○
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+5 V
1
1
DUMMY
VIDEO
○
○
2
RESET
OPEN
10 pF
○
+
○
○
OP-AMP (JFET INPUT)
○
○
Vscd
○
○
○
+
○
KMPDC0023EA
○
○
+2 V
○
NC
–
○
Vsub
ACTIVE
VIDEO
○
Vss
○
Vscg
The recommended terminal voltage for a current output type
NMOS linear image sensor is listed in Table 3-3.
The two-phase clock pulses φ1 and φ2 have positive polarity.
Their recommended amplitude voltage Vφ is 5 V, with a minimum of 4.5 V and a maximum of 10 V. The start pulse φst also
has positive polarity and its amplitude voltage Vφst should be
equal to the clock pulse voltage Vφ. No DC voltage is required
for driving the shift register. The Vss, Vsub and NC terminals
should be all grounded.
As explained in section 3-2-2, a positive bias voltage Vb should
be applied to the video line. This corresponds to the voltage
applied to the non-inverting input terminal of the operational
amplifier in the current-to-voltage conversion or current integration method. The recommended voltage for Vb is the clock
pulse voltage minus 3 V. For example, Vb should be 2 V when
Vφ is 5 V. The maximum voltage for Vb is Vφ-2.5 V and the
minimum voltage is 1.5 V.
The settable voltage range for Vb with respect to Vφ is shown in
Figure 3-11. Using a higher voltage for Vφ widens the settable
range for Vb. When Vb is set higher, the saturation charge will
increase accordingly. This is accompanied by an increase in
the dark current, which is however smaller than the increase in
saturation charge. Conversely, when Vb is set to a lower value,
the output waveform response is faster. These tendencies are
shown in Figures 3-12 and 3-13. Figure 3-12 shows the characteristic dependence of the saturation charge and dark output on
Vb, measured when Vφ is set to 10 V and normalized for the
value at Vb=2 V. Figure 3-13 shows how Vb affects the time
required for a differential waveform to reach the peak after input
of a clock pulse, which is measured when S3901-512Q is
driven with Vφ of 5 V and 10 V by the current-to-voltage conversion method. These facts indicate that the clock pulse voltage
Vφ and video bias voltage Vb should be set to their optimum
values depending on the ambient operating conditions.
It is recommended that the saturation control drain voltage
Vscd, be the same value as for the video bias line voltage Vb.
The saturation control gate Vscg should be grounded. When
incident light intensity is so high that blooming occurs even with
this setting, then setting Vcg at positive potential will enhance
the blooming suppression effect. But note that the saturation
charge lowers at the same time. This relation between the saturation control gate voltage Vscg and the saturation output
charge is shown in Figure 3-14.
The end-of-scan signal is available as a negative polarity signal
with respect to 5 V by connecting a 10 kΩ pull-up resistor to the
EOS terminal, at φ2 timing immediately after the last pixel output
is derived.
○
2
EOS
○
EOS
○
st
○
st
○
○
○
10 kΩ
3-2-4. Terminal voltage for current output types
9
Characteristic and use of NMOS linear image sensors
Table 3-3 Recommended terminal voltage (current output type)
Clock pulse voltage
Start pulse voltage
Video bias voltage
Saturation control drain voltage
Saturation control gate voltage
Typ.
5
Vφ
Vφ-3.0
Vb
0
Max.
10
0.4
10
0.4
Vφ-2.5
-
Unit
V
Figure 3-13 Output response time vs. video bias voltage
○
○
Figure 3-11 Video bias voltage margin (current output type)
Min.
4.5
0
4.5
0
1.5
-
○
Symbol
Vφ1, Vφ2 (H)
Vφ1, Vφ2 (L)
Vφst (H)
Vφst (L)
Vb
Vscd
Vscg
High
Low
High
Low
○
Input voltage
300
○
X.
S
ED
6
○
MA
BIA
○
ND
ME
○
M
CO
○
RE
○
○
4
○
○
VIDEO BIAS RANGE
2
200
V =5 V
V =10 V
100
○
OUTPUT RESPONSE TIME (ns)
○
○
8
○
VIDEO BIAS VOLTAGE (V)
○
○
○
10
S3901-512Q
Current-to-voltage conversion method
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MIN.
0
○
5
6
7
8
10
9
○
4
0
2
4
6
8
10
○
0
VIDEO BIAS VOLTAGE (V)
○
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CLOCK PULSE AMPLITUDE (V)
○
KMPDB0062EA
Figure 3-14 Saturated charge vs. saturation control gate
50
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4
○
3
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SATURATION CHARGE
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○
○
2
1
40
30
S3901
20
S3904
10
○
○
DARK OUTPUT
SATURATION CHARGE (pC)
○
○
○
○
S3901 to S3904 Series
V =10 V
Extemal current-integration method
○
V =5.0 V, Vb=Vscd=2.0 V
Extemal current-integration method measurred
○
0
○
DEPENDENCE OF THE SATURATION CHARGE
AND DARK OUTPUT AT Vb=2 V (Times)
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Figure 3-12 Saturated charge and dark output vs. video bias
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KMPDB0043EA
2
4
6
8
10
0
0
0.2
0.4
0.6
0.8
1.0
○
○
0
SATURATION CONTROL GATE VOLTAGE (V)
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KMPDB0061EA
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VIDEO BIAS VOLTAGE (V)
10
KMPDB0063EA
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shift register starts operating when the start pulse φst sets to
"High" level, so the φst pulse interval determines the signal integration time. As with two-phase clock pulses, the start pulse
also requires a pulse width of at least 200 ns, and must overlap
with φ2 for at least 200 ns. Furthermore, φ2 must be changed
only once from "High" to "Low" level during the "High" level of
φst, in order to initiate correct shift register operation.
The photodiode potential of a current output type NMOS linear
image sensor is reset within the readout period in which the
address switch is turned on. This means that if the pulse width
of φ2 synchronized with the address pulse is too short, a lag
phenomenon may occur. Because φ1 is used only for scanning
operation, it has advantageous characteristics in that the pulse
width of φ2 can be set longer than that of φ1. However, the duty
ratio of φ1 and φ2 should be set to 1:1 when the image sensor is
operated in the high-speed readout mode at 1 MHz or higher.
○
○
○
Figure 3-15 shows the input/output pulse timing diagram for a
current output type image sensor. The clock and waveform conditions are listed in Tables 3-4 and 3-5, respectively.
The two-phase clock pulses φ1 and φ2 can be either in a completely separate or complementary relation. However, do not
allow both pulses to turn "High" at the same time.
If the rise time and fall time of φ1 and φ2 are longer than 20 ns,
insert clock spaces X1 and X2 which are longer than "rise time/
fall time - 20" (ns). The pulse width of φ1 and φ2 requires at least
200 ns for stable operation of the shift register. Since the video
output signal is obtained at each rising edge of φ2, the clock
pulse frequency equals the signal readout frequency (data
rate).
The start pulse φst has the same amplitude as φ1 and φ2. The
○
3-2-5. Input/output pulse timing for current output type
○
Characteristic and use of NMOS linear image sensors
Table 3-4 Clock characteristics (current output type)
P aram eter
O perating frequency (V b=2 V , V φ=5 V )
C lock pulse line capacitance
(at 5 V bias)
S aturation control gate
capacitance
(at 5 V bias)
V ideo line capacitance
(at 2 V bias)
S 3901
S 3902
S 3903
S 3904
S 3901
S 3902
S 3903
S 3904
S 3901
S 3902
S 3903
S 3904
S ym bol
f
-128Q
-256Q
-512Q
-256Q
-512Q
-1024Q
-128Q
-256Q
-512Q
-256Q
-512Q
-1024Q
-128Q
-256Q
-512Q
-256Q
-512Q
-1024Q
Cφ
C scg
Cv
M in.
0.1
-
Typ.
21
36
67
27
50
100
12
20
35
14
24
45
7
11
20
10
16
30
M ax.
2000
-
U nit
kH z
M in.
200
Typ.
20
-
M ax.
-
U nit
-
20
-
200
-
-
200
trf - 20
-
80
120
160
70
110
140
80
120
160
100
150
200
-
pF
pF
pF
pF
pF
pF
Table 3-5 Pulse waveform conditions (current output type)
P aram eter
S tart pulse rise tim e / fall tim e
S tart pulse width
C lock pulse rise tim e / fall tim e
C lock pulse width
S tart pulse to clock pulse 2 overlap tim e
C lock pulse space
S 3901-128Q
S 3901-256Q
S 3901-512Q
S 3902-128Q
S 3902-256Q
V ideo delay tim e
S 3902-512Q
(50 % of saturation)
S 3903-256Q
Vb = 2 V, Vφ = 5 V
S 3903-512Q
S 3903-1024Q
S 3904-256Q
S 3904-512Q
S 3904-1024Q
S ym bol
trφs, tfφs
tpws
trφ1, trφ2
tfφ1, tfφ2
tpwφ1,
tpwφ2
tφov
X1, X2
tvd
ns
11
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structure of the photosensitive section and the pinout configurations. The pin designations and their functions are listed in
Table 3-6.
The structure and configurations are identical to the current output type except for the output signal processing section. The pin
designations for the input/output terminals such as φst, φ1, φ2,
Vscd, Vscg, Vss, Vsub, NC and EOS, and their functions are
exactly the same for the current output type. The Vdd and Reset
V terminals are for voltage input to the output signal circuit, and
Resetφ is a pulse input terminal. The output signal processing
section consists of a switching transistor array for reset connected to the video line and a source follower circuit for impedance conversion. Both are comprised of N-channel MOS transistors. The Vscd and Reset V terminals are common since they
are internally connected in the chip.
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Figure 3-15 Pulse timing diagram (current output type)
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○
When the signal from a current output type image sensor is read
out with an external current integration circuit, a reset pulse
φreset is required in addition to the above clock pulses in order
to reset the integration capacitance. However, it is possible to
share the φ1 and φreset by using a timing pulse as shown in
Figure 3-16, without impairing the above pulse conditions. To
maintain a constant photodiode reset potential, the rise of φreset
must be separated from the fall of φ2 for at least 50 ns. In this
case, it is also essential that the photodiode potential reset time
and readout time have the pulse width of φ2 set longer than that
of φ1. Note however, if the φreset pulse width is too short, the
integration capacitance does not completely reset and conversely, a lag resulting from the external circuit will occur.
○
Characteristic and use of NMOS linear image sensors
2
○
○
tpw 1
1 (H)
1 (L)
2 (H)
2 (L)
Figure 3-17 Equivalent circuit (voltage output type)
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V
V
V
V
tpw s
tpw 2
○
1
V s (H)
V s (L)
○
st
○
tvd
SCANNING
CIRCUIT
○
○
○
ACTIVE VIDEO OUTPUT
○
tf s
tf 1
○
○
tr 1
○
st
X1
X2
tf 2
1
2
PHOTOSENSITIVE
SECTION
ACTIVE
PHOTODIODES
ANTIBLOOMING
SWITCHES
SWITCH
SECTION
DUMMY DIODE
SECTION
END OF
SCAN
MOS SHIFT REGISTER
SOURCE
FOLLOWER
CIRCUIT
Vdd
ACTIVE
VIDEO
Vss
SATURATION
CONTROL GATE
SATURATION
CONTROL DRAIN
ADDRESS SWITCH
DUMMY
VIDEO
DUMMY DIODES
○
1
CLOCK
CLOCK
ADDRESS SWITCH
○
tr s
st
SWITCH
SECTION
○
○
END OF SCAN
START
RESET SWITCH
○
2
○
Reset
Reset V
t ov
○
KMPDC0067EA
○
○
tr 2
Figure 3-18 Active area structure (voltage output type)
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c
○
Figure 3-16 Pulse timing example for external currentintegration method
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KMPDC0022EA
○
50 ns MIN.
○
○
○
st
○
b
○
1, Reset
○
a
1.0 µm
SILICON OXIDE
N TYPE SILICON
○
○
○
P TYPE SILICON
○
○
○
b=45 µm
b=20 µm
b=45 µm
b=20 µm
c=2.5 mm
c=2.5 mm
c=0.5 mm
c=0.5 mm
○
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12
S3921 SERIES: a=50 µm
S3924 SERIES: a=25 µm
S3922 SERIES: a=50 µm
S3923 SERIES: a=25 µm
KMPDA0148EA
○
The voltage output type NMOS linear image sensor consists of
a photosensitive section, readout switch section, shift register
and output signal processing section, all integrated into a single
chip. This type of image sensor provides an output with boxcar
waveform. Figure 3-17 shows the equivalent circuit of the voltage output type. Figures 3-18 and 3-19 respectively show the
○
3-3-1. Configurations of the voltage output types
○
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3-3. Voltage output type NMOS linear image
sensors
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KMPDC0024EA
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1.0 µm
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VIDEO OUTPUT
400 µm
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○
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2
Characteristic and use of NMOS linear image sensors
22
NC
2
21
NC
st
3
20
NC
Vss
4
19
NC
Vscg
5
18
NC
6
17
NC
RESET V (Vscd)
7
16
NC
Vss
8
15
NC
ACTIVE VIDEO
9
14
NC
DUMMY VIDEO
10
13
END OF SCAN
Vsub
11
12
Vdd
○
1
1
○
rent flowing through the transistor used as a load. As a result, a
voltage signal is read out from the output terminal. After this, the
reset switch turns on while the address switch stays on, and the
video line and photodiode potentials are again initialized.
This readout method is referred to as video line integration
since it uses the video line capacitance. The dummy video line
operates in the same manner. A constant voltage is applied,
inside the chip, to the gate of the transistor used as a load. The
output is available in negative polarity with respect to a certain
constant voltage (approx. 1.5 V) which is determined by the
source follower circuit characteristics and the reset voltage.
Figure 3-20 Readout section structure
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○
○
RESET
○
○
○
○
○
○
2
○
○
○
○
○
Figure 3-19 Pinout (voltage output type)
Reset V
○
Reset
○
Vdd
○
Vss, Vsub and NC should be grounded.
○
RESET
SWITCH
○
KMPDC0025EA
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The voltage output type provides an output signal with boxcar
waveform of negative polarity with respect to the positive potential, so an external circuit is used to perform inverting amplification and offset cancellation.
A recommended readout circuit is shown in Figure 3-21. The
gain of this circuit is Rf/Rs. To prevent loading of the internal
source follower a resistor of 10 kΩ or more should be used.
Offset cancellation is performed by adjusting the variable resistor on the non-inverting input side of the operational amplifier.
Figure 3-21 Recommended readout circuit (voltage output type)
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○
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3-3-3. Readout method for the voltage output types
○
○
+5 V
+5 V
○
○
○
+
○
○
10 kΩ
st
EOS
Rf
EOS
1
1
2
2
○
○
○
○
○
st
Vdd
ACTIVE
VIDEO
OPEN
Rs 10 kΩ
–
Reset
+
+2.5 V
Reset V
(Vscd)
Vscg
+
○
○
○
○
Reset
DUMMY
VIDEO
Vsub
+15 V
NC
○
○
○
○
○
○
Vss
○
○
○
KMPDC0027EA
○
Figures 3-20 shows the structure of one pixel comprised of a
photodiode, a readout switch, and its equivalent circuit. This
section describes specific readout operations using these figures.
When the address and reset switches simultaneously turn on at
a certain time, the video line and photodiode potential are initialized. This reset switch consists of an MOS transistor, with its
source connected to the Reset V terminal, its gate to the Resetφ
terminal and the drain to the video line. Each time an output
signal from one pixel is read out, a reset pulse is input to the
Resetφ terminal so that the video line and photodiode potentials
are initialized to the reset voltage Vr which is applied to the
Reset V terminal. Both the address and reset switches then turn
off, and the stored charge in the photodiode is discharged from
the light output and dark output during the integration time.
Next, when only the address switch turns on, charge redistribution occurs by capacitive dividing between the video line and
photodiode. This supplies a charge into the photodiode from
the video line until the photodiode and video line potentials are
equalized. This change in the video line potential is input to the
gate of the source follower circuit, causing a change in the cur-
PHOTODIODE
○
3-3-2. Operating principle of the voltage output types
VIDEO LINE
ADDRESS
SWITCH
○
○
○
○
○
ADDRESS PULSE
FROM SHIFT REGISTER
KMPDC0069EA
○
Function
Clock pulse 1
Clock pulse 2
Start pulse
Saturation control drain
Saturation control gate
Reset voltage
Reset pulse
Source follower drain voltage
Ground (anode potential)
Substrate potential
No connection
Signal output
Switching noise output
End of scan
○
Terminal
φ1
φ2
φst
Vscd
Input
Vscg
Reset V
Reset φ
Vdd
Vss
Ground Vsub
NC
Active video
Output Dummy video
EOS
○
Table 3-6 Pin description (voltage output type)
13
Characteristic and use of NMOS linear image sensors
3-3-4. Terminal voltage for the voltage output types
The recommended terminal voltage for a voltage output type NMOS linear image sensor is listed in Table 3-7.
Table 3-7 Recommended terminal voltage (voltage output type)
Input voltage
Symbol
Vφ1, Vφ2(H)
Vφ1, Vφ2(L)
Vφst(H)
Vφst(L)
Vrφ (H)
Vrφ (L)
Vdd
Vr
Vscd
Vscg
Min.
4.5
0
4.5
0
4.5
0
4.5
2.0
-
Typ.
5
Vφ
Vφ
Vφ
Vφ-2.5
Vb
0
Max.
10
0.4
10
0.4
10
0.4
10
Vφ-2.0
-
Unit
V
○
○
○
○
○
○
○
○
○
○
○
Figure 3-23 shows the input/output pulse timing for a voltage
output type NMOS linear image sensor. The clock conditions
and waveform conditions are listed in Tables 3-8 and 3-9, respectively.
Figure 3-23 Pulse timing diagram (voltage output type)
st
tpw s
V s (H)
V s (L)
tpw 1
1
2
V
V
V
V
1 (H)
1 (L)
2 (H)
2 (L)
tpw 2
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
3-3-5. Input/output pulse timing for voltage output type
tvd
ACTIVE VIDEO OUTPUT
○
○
○
○
Vr (H)
Vr (L)
○
END OF SCAN
○
○
Figure 3-22 Reset voltage margin (voltage output type)
A constant voltage should be applied to the drain of the source
follower circuit in the output signal processing section, from the
Vdd terminal. The voltage Vdd should be equal to the clock
pulse voltage Vφ. The saturation control drain voltage Vscd
should be equal to the reset voltage Vr, and the saturation control gate voltage Vscg should be grounded.
Reset
○
As with the current output type, the recommended amplitude
voltage of φ1 and φ2, Vφ1 and Vφ2 is 5 V, with a maximum value
of 10 V and a minimum value of 4.5 V. The amplitude voltage of
φst and Vφst should be equal to the clock pulse voltage Vφ. The
Vss, Vsub and NC terminals should all be grounded.
Each photodiode of voltage output type image sensors is initialized via the reset switch connected to the Reset V terminal voltage Vr. This voltage corresponds to the video bias Vb for the
current output type. The recommended reset voltage Vr for voltage output type equals a value obtained by subtracting 2.5 V
from the clock pulse voltage Vφ. For example, Vr should be 2.5
V when Vφ is 5 V. The maximum voltage for Vr is Vφ-2.5 V and
the minimum voltage is 2 V. The settable voltage range for Vr
with respect to Vφ is shown in Figure 3-22. As with the current
output type, using a higher voltage for Vφ widens the settable
range for Vr. When Vr is set higher, the saturation charge will
increase accordingly. Conversely, when Vr is set to a lower
value, the output response is faster. These facts indicate that
the clock pulse voltage Vφ and reset voltage Vr should be set to
their optimum values depending upon the ambient operating
conditions. The reset pulse should be CMOS compatible with
positive polarity and its amplitude voltage Vrφ should be equal
to the clock pulse voltage Vφ.
○
○
High
Clock pulse voltage
Low
High
Start pulse voltage
Low
High
Reset pulse voltage
Low
Source follow drain voltage
Reset voltage
Saturation control drain voltage
Saturation control gate voltage
tr s
tf s
○
○
○
12
C
E
○
○
tf 1
○
X.
MA
X1
tf 2
X2
2
○
○
4
tr 1
1
○
ES
st
t ov
○
RE
DR
E
○
6
OM
ME
E
ND
AG
○
8
V
TV
T
OL
t ovr td r-2
ts r-2
○
RESET V VOLTAGE RANGE
RESET
○
RESET V VOLTAGE (V)
10
trr
○
tfr
2
○
○
MIN.
○
KMPDC0026EA
5
6
7
8
9
10
○
4
○
0
KMPDB0047EA
14
○
○
○
CLOCK PULSE AMPLITUDE (V)
○
○
○
○
○
○
○
○
○
○
○
○
The timing for clock pulses φ1 and φ2 and the start pulse φst are
exactly the same as those for the current output type. The signal
is obtained during the period from the rise of φ2 to the rise of φr.
Unlike the current output type, the reset operation of the voltage
output type is done during the period when the address and
reset switches are simultaneously turned on. For this reason,
the reset pulse must overlap with the clock pulse φ2. More specifically, the reset pulse should rise during the "High" level of φ2
and fall during the "Low" level of φ2.
○
Characteristic and use of NMOS linear image sensors
If this overlap time is too short, the photodiode reset is not complete, resulting in occurrence of lag. Because φ1 is used only for
scanning operation, it has advantageous characteristics in that
the pulse width of φ2 can be set longer than that of φ1 as shown
in the timing diagram of Figure 3-24, just as with the current
output type NMOS linear image sensors. However, the pulse
width of φ1 and φ2 should be set to at least 200 ns. In order to
maintain a constant photodiode reset potential, the rise of φ2
must be delayed at least 50 ns from the fall of the reset pulse.
Table 3-8 Clock characteristics (voltage output type)
Parameter
Operating Frequency (Vr=2.5 V, Vφ=Vdd=5 V)
S3921
S3922
Clock pulse line capacitance
(5 V bias)
S3923
S3924
Symbol
f
-128Q
-256Q
-512Q
-256Q
-512Q
-1024Q
Reset pulse line capacitance (5 V bias)
Saturation control gate capacitance
(5 V bias)
Min.
0.1
-
Cφ
Cr
S3921
S3922
S3923
S3924
-128Q
-256Q
-512Q
-256Q
-512Q
-1024Q
Cscg
Typ.
21
36
67
27
50
100
6
12
20
35
14
24
45
Max.
500
-
Unit
kHz
pF
pF
pF
-
pF
pF
Table 3-9 Pulse waveform conditions (voltage output type)
Parameter
Start pulse rise time / fall time
Start pulse width
Symbol
trφs, tfφs
tpws
trφ1, trφ2
tfφ1, tfφ2
tpwφ1, tpwφ2
trrφ, tfrφ
tφov
tφovr
tdφr-2
X1, X2
tsφr-2
Clock pulse rise time / fall time
Clock pulse width
Reset pulse rise time / fall time
Start pulse to clock pulse overlap time
Clock pulse 2 to reset pulse overlap time
Clock pulse 2 to reset pulse delay time
Clock pulse space
Clock pulse to reset pulse space
Video delay time
(50 % of Saturation)
Vr = 2.5 V, Vφ = Vdd = 5 V
S3921
S3922
S3923
S3924
-128Q
-256Q
-512Q
-256Q
-512Q
-1024Q
tvd
Min.
200
Typ.
20
-
Max.
-
-
20
-
200
200
660
50
trf -20
0
-
20
100
150
200
100
150
200
-
Unit
ns
Figure 3-24 Pulse timing example (recommended circuit for voltage output type)
st
1
2
Reset
50 ns MIN.
VIDEO OUTPUT
KMPDC0028EA
15
○
Characteristic and use of NMOS linear image sensors
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
Figure 4-2 Input/output characteristics [voltage output type
(50 µm pitch photodiode)]
(Typ.)
S3921-128Q
103
S3921-256Q
102
S3921-512Q
S3922-128Q
S3922-256Q
101
S3922-512Q
100
A Light (2856 K)
Reset V=2.5 V
Vdd=5.0 V
V =5.0 V
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
104
○
The output signal from a current output type NMOS linear image
sensor can be represented in units of charge (pC). Figure 4-1
shows a graph of input/output characteristics for S3901 to
S3904 series NMOS linear image sensors, plotted on a logarithmic scale. Since the upper limit of the output charge is determined by the amount of charge that can be stored in the photodiode junction capacitance, the input/output characteristics are
saturated as the output charge reaches the upper limit or break
point, even though the incident light level is excessively increased. The incident light level at that point is called the saturation exposure, and the output charge is called the saturation
charge. The light source used is a tungsten lamp operated at
2856 K (standard "A" light source). Note that sensitivity is wavelength-dependent and therefore differs depending on the light
source used. The output will not vary even if the number of
pixels or the video line capacitance is changed.
○
○
4-1-1. Input/output characteristics (current output type)
○
○
The relation between the light level incident to the image sensor and the signal output is referred to as the input/output characteristics. As stated in Section 2, NMOS linear image sensors
are operated by the charge integration readout method, so the
incident light level can be expressed as incident light exposure
(l x.s), which is a product of illuminance (l x) and integration time
(s).
○
○
○
4-1. Input/output characteristics
the case with the current output type, there is a saturation point
or break point in the input/output characteristics. The incident
light level at that point is called the saturation exposure, and the
output voltage is called the saturation output voltage. As explained in Section 3-3-2, the output voltage is determined by
charge redistribution between the photodiode and video line
when the address switch turns on. Therefore, the sensitivity and
saturation output voltage differ, depending on the video line
capacitance (the number of pixels), even though the photodiode size is identical. In addition, the source follower circuit
has an upper limit in the output voltage, which also affects the
final saturation output voltage. When an image sensor is operated under the recommended conditions (reset voltage=2.5 V,
Vdd=Vφ=5 V), the upper limit in the output of the source follower
circuit will be about 1.3 V.
Typical input/output characteristics of S3921/S3922 series and
S3924/S3923 series are shown in Figures 4-2 and 4-3. The
output voltage is measured at the output terminal of the image
sensor and the standard A light source is used.
OUTPUT VOLTAGE (mV)
This section explains the basic characteristics of NMOS linear
image sensors as well as typical data actually measured.
These measurements are made with driver circuits specifically
designed for NMOS linear image sensors, which are introduced in Section 6.
○
○
○
4. Characteristics
○
10-1
10-5
10-4
10-3
10-2
10-1
100
○
○
Figure 4-1 Input/output characteristics
(current output type)
○
EXPOSURE (lx · s)
○
(Typ.)
KMPDB0065EA
○
○
102
○
S3901 Series
○
Figure 4-3 Input/output characteristics [voltage output type
(25 µm pitch photodiode)]
○
○
S3904 Series
(Typ.)
○
104
○
S3902 Series
○
100
○
○
○
○
10-4
10-3
10-2
10-1
○
○
○
100
○
10-3
10-5
○
A Light (2856 K)
Vb=2.0 V
V =5.0 V
Extemal current-integration
method
10-2
S3924-256Q
103
S3924-512Q
S3924-1024Q
102
S3923-256Q
S3923-512Q
101
S3923-1024Q
100
A Light (2856 K)
Reset V=2.5 V
Vdd=5.0 V
V =5.0 V
○
○
○
The output signal from a voltage output type NMOS linear image sensor can be represented in units of voltage (mV). As is
16
10-4
10-3
10-2
10-1
100
EXPOSURE (lx · s)
○
○
4-1-2. Input/output characteristics (voltage output type)
10-1
10-5
○
○
○
KMPDB0064EA
○
○
○
EXPOSURE (lx · s)
OUTPUT VOLTAGE (mV)
○
S3903 Series
10-1
○
OUTPUT CHARGE (pC)
101
KMPDB0066EA
Characteristic and use of NMOS linear image sensors
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
The slope of the input/output characteristics, the γ value, plotted
on the logarithmic graph in the preceding section is approximately 1. But in actual measurement, the input/output characteristics slightly deviate from the linearity (γ=1). This deviation is
known as the linearity error. The deviation from γ=1, ΔX, at a
certain point, is expressed as a percentage with the deviation
divided by the output X.
In the case of the current output type image sensors, as long as
the output is within 95 % of the saturation charge, the linearity
error can be held to a small value by using an external circuit in
the current-integration readout mode, making it well suited in
applications requiring high accuracy. At an output larger than
95 % of the saturation charge, part of the output begins to flow
into the anti-blooming switch. The resultant output becomes
smaller than γ=1 and the resulting linearity error is more than -1
%.
The output from a voltage output type image sensor is determined by the video line capacitance and photodiode junction
capacitance. However, the junction capacitance is voltage-dependent and therefore increases as the output reaches saturation. As a result, the output drops below γ=1, causing a larger
linearity error. Figure 4-4 shows typical linearity error in the voltage output type NMOS linear image sensor. This reveals that
the linearity error is -2 % at a light exposure which is 10 % of the
saturation level, and that above this, the linearity error increases ranging from -2 % to more than -50 %. The voltage
output type offers ease of use yet has the disadvantage that
linearity error becomes larger as the output reaches saturation.
○
○
○
4-2. Linearity error
○
○
Figure 4-4 Linearity error (voltage output type)
○
○
○
○
(Typ.)
10
○
○
○
○
○
-10
○
S3923 Series
○
-20
○
S3924 Series
S3922 Series
○
○
○
SATURATION
EXPOSURE
10-2
10-1
100
○
○
-30 A Light (2856 K)
Reset V=2.5 V
Vdd=5.0 V
V =5.0 V
-40
10-4
10-3
○
○
○
○
S3921 Series
○
LINEARITY ERROR (%)
0
○
○
○
○
○
○
○
○
○
○
○
When light strikes a photosensitive section having with P-N
junctions, the electrons within the valence band are stimulated.
If the light energy is greater than the band gap Eg of silicon, the
electrons are pulled into the conduction band, generating electron/hole pairs or carriers. These generated carriers diffuse toward the depletion layer of the photodiode. In the depletion
layer the electric field accelerates the carriers to pass through
○
○
4-3. Spectral response characteristics
○
○
○
KMPDB0067EA
○
○
EXPOSURE (lx . s)
the P-N junction, resulting in an accumulated signal to be read
out. If the light energy is smaller than the band gap energy Eg, it
cannot be detected. This limiting wavelength λ (nm) can be
given by: λ=1239.5/Eg (eV)
The band gap energy Eg for silicon is 1.12 eV at room temperatures, so that the limiting wavelength will be approximately
1100 nm. This means that the silicon photodiode cannot detect
light wavelengths longer than 1100 nm.
The light absorption coefficient for silicon differs depending on
light wavelength. The longer the light wavelength, the smaller
the absorption coefficient. In other words, incident light at longer
wavelengths penetrates deeper into the silicon substrate, generating carriers in deep positions within it. Since these carriers
have a limited life, they can only diffuse a certain distance after
being generated. This means that, even when the same amount
of light enters the image sensor, the probability that the generated carriers will reach the depletion layer and eventually be
detected as an output signal varies with the depth of the carrier
generation or with the incident light wavelength. In addition,
how the incident light undergoes interference, reflection and
absorption on the surface protective coating of the photodiode
such as the silicon oxide layer, also depends on the wavelength
and affects the sensitivity.
The relation between the incident light wavelength and the sensitivity is known as the spectral response characteristic. Even
among silicon sensors, the spectral characteristics differ depending on the silicon substrate used and the depth of the P-N
junction formed. Figure 4-5 shows typical spectral response
characteristics of S3904-1024Q and S3904-1024F NMOS image sensors. The peak and valley positions in the spectral response are slightly different from process lot to lot. Hamamatsu
NMOS image sensors are uniquely processed to form a junction capacitance that enhances UV sensitivity. Types with suffix
“Q” have a quartz window for high sensitivity in the UV range.
Furthermore, in order to reduce the adverse effect of infrared
light on spatial resolution and to minimize the sensitivity ratio
between short wavelength and long wavelength, Hamamatsu
NMOS image sensors use a well structure capable of suppressing sensitivity on the long wavelength side. This type of NMOS
image sensor provides peak response at a wavelength of near
600 nm.
The spectral response varies with the sensor element temperature. This is mainly because light absorption coefficient increases with a rise in temperature, so sensitivity varies linearly
with respect to the temperature. Figure 4-6 shows the rate of
change in sensitivity per °C (temperature coefficient) in NMOS
image sensors, as a function of wavelength. If we let the temperature coefficient at a certain wavelength be Cλ (%/°C), then
the sensitivity drops by Cλ ΔT each time temperature lowers by
ΔT (°C). The longer the wavelength, the larger the change of
sensitivity. This tendency is more noticeable at wavelengths
longer than the peak response wavelength.
17
Characteristic and use of NMOS linear image sensors
○
○
Figure 4-5 Spectral response
○
(Typ.)
○
○
○
○
○
○
0.20
○
Vb=2.0 V
V =5.0 V
Extemal currentintegration
method
○
○
○
0.15
○
○
○
0.10
○
○
800
1000
1200
○
600
○
400
○
○
KMPDB0068EA
○
○
WAVELENGTH (nm)
○
○
Figure 4-6 Temperature dependence of spectral response
○
(Typ.)
○
○
S3901-512Q
S3904-1024Q
1
S3901-512Q
0
-1
50 % of saturation
"A" light source (2856 K)
Vb=2.0 V
V =5.0 V
External current-integration
method
-2
○
○
2
-3
0
100
200
300
400
500
○
○
○
0.5
○
PIXELS (ch)
○
○
KMPDB0070EA
4-5. Dark output
○
○
○
0
○
○
○
○
400
600
800
1000
1200
○
-0.5
200
Vb=2.0 V
V =5.0 V
Extermal current-integration
method
○
TEMP. COEFFICIENT (%/ C)
○
1
PHOTORESPONSE NON-UNIFORMITY (%)
S3904-1024F
(Typ.)
3
○
0.05
0
200
100 (%)
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
Like other types of light sensors, NMOS image sensors exhibit a
small output even when no incident light is present. This is
known as the dark output (dark current), and is chiefly caused
by discharge of the stored charge in each photodiode due to the
recombination current within the photodiode depletion layer
and/or the surface leakage current. Because the upper limit of
the output is determined by the saturation charge, a large dark
output narrows the output range of light detection. As with sensitivity, the dark output is non-uniform and is derived together
with the light output. This means it is important to reduce the
dark output to a minimal level compared to the light output unless performing signal processing that subtracts the dark output
from each pixel.
The dark output charge is expressed as the product of dark
current and integration time, and thereby increases in proportion to the integration time. The integration time must be determined by taking the magnitude of the dark output into account.
When the signal of a current output type NMOS linear image
sensor is read out with an external current-integration circuit, if
we let the dark output be Vd (V) and the integration capacitance
be Cf (pF), then the dark output charge Qd (pC) is given by
Cf.Vd. While, if we let the integration time be Ts (s), the dark
current Id (pA) is given as follows:
ID = Cf . Vd/Ts
○
○
○
○
○
○
Where X is the average output of all pixels, ΔX is the absolute
value of the difference between the average output and the
maximum (or minimum) output. The average output in this measurement is adjusted to 50 % of the saturation output, and a
standard "A" light source is used. The outputs from the first and
the last pixels are excluded from this PRNU measurement because their pixel arrangement and input pulse continuity differ
from other intermediate pixels. Figure 4-7 is an example of
○
○
PRNU = (ΔX/X)
○
○
Each of the photodiodes arrayed in an image sensor is carefully
fabricated to provide uniform performance, but each also exhibits some small non-uniformity in terms of sensitivity. This may be
due to crystal flaws in the silicon substrate, variations in the
wafer process and diffusion in the manufacturing process. This
non-uniformity is often called the photoresponse non-uniformity
(PRNU) and, for Hamamatsu NMOS image sensors, it is defined in the equation below by measuring the outputs of all pixels when the entire photosensitive area of each photodiode is
uniformly illuminated.
○
○
4-4. Photoresponse non-uniformity
○
○
○
KMPDB0069EA
○
○
WAVELENGTH (nm)
18
Figure 4-7 Non-uniformity
○
S3904-1024Q
○
PHOTO SENSITIVITY (A/W)
0.25
PRNU in all pixels of S3901-512Q which has a photodiode
height of 2.5 mm. It shows that the PRNU with respect to the
normal average output is within ±1 %, achieving good output
uniformity. The maximum non-uniformity for Hamamatsu NMOS
image sensors is specified as being within ±3 %.
In addition to the element properties, scratches and dust on the
faceplate may reduce the light transmission to certain pixels,
causing output uniformity to deteriorate. So sufficient care concerning these points is needed when handling image sensors.
As the temperature rises, the number of carriers thermally excited into the valence band from the conduction band increase,
causing dark current to increase exponentially with the element
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
40 ˚C
30 ˚C
100
20 ˚C
10-1
0 ˚C
10 ˚C
-10 ˚C
10-2
-20 ˚C
○
○
S3904 Series
100
101
ID=0.1 pA (25 ˚C)
Vb=2.0 V
V =5.0 V
External currentintegration method
10-3
10-2
○
10-1
-30 ˚C
10-1
100
101
102
103
104
○
○
S3902 Series
10-2
INTEGRATION TIME (s)
○
○
S3903 Series
○
KMPDB0073EA
○
10-3
○
DARK CURRENT (pA)
○
○
○
S3901 Series
101
(Typ.)
102
DARK OUTPUT CHARGE (pC)
(Typ.)
102
Figure 4-10 Dark output charge vs. integration time
(S3904 Series)
○
○
○
○
○
Figure 4-8 Dark current vs. temperature
(current output type)
shows an example of dark current uniformity in S3904-1024Q.
Hamamatsu NMOS image sensors are designed to minimize
the dark output as well as its non-uniformity. But dark output
uniformity is usually not as good as photoresponse uniformity,
and some slight erratic data may appear in some cases.
○
○
○
○
temperature. In Hamamatsu NMOS image sensors for example, the dark current doubles for every 5 °C increase in
temperature. This equals a temperature dependence of 1.15
times per °C, in other words if the temperature varies by ΔT
(°C), then the dark current will be (1.15)ΔT times. Accordingly,
the upper limit of the image sensor operating temperature is
restricted by the magnitude of the dark output. In applications
requiring high measurement accuracy, temperature control of
the image sensor is necessary. For instance, cooling the image sensor with a thermoelectirc cooling element will effectively reduce the dark current and allow longer integration
time, thus allowing measurements at even lower light levels.
○
Characteristic and use of NMOS linear image sensors
0
20
40
○
○
60
(Typ.)
0.15
○
○
-20
Figure 4-11 Dark current uniformity (S3904-1024Q)
○
10-5
-40
○
Vb=2.0 V
V =5.0 V
External current-integration
method
10-4
○
○
KMPDB0071EA
○
○
○
Figure 4-9 Dark output charge vs. integration time
(S3901 Series)
○
0.10
0.05
○
○
○
40 ˚C
○
○
Vb=2.0 V
V =5.0 V
External current-integration
method
○
○
30 ˚C
100
0
0
200
400
600
800
1000
○
○
20 ˚C
PIXELS (ch)
○
10-1
KMPDB0074EA
○
10 ˚C
○
0 ˚C
○
-10 ˚C
10-2
○
-20 ˚C
○
DARK OUTPUT CHARGE (pC)
101
ID=0.2 pA (25 ˚C)
Vb=2.0 V
V =5.0 V
External currentintegration method
○
(Typ.)
102
DARK CURRENT (pA)
○
○
TEMPERATURE (˚C)
○
100
101
102
103
104
○
10-1
○
10-3
10-2
Table 4-1 Dark current (current output type)
○
-30 ˚C
Type No.
○
○
○
○
○
○
○
○
Max.
0.6
0.15
0.08
0.3
○
Typ.
S3901 Series
0.2
S3902 Series
0.08
S3903 Series
0.04
S3904 Series
0.1
External current-integration method
Measured with C7884 at Vb=2 V and Vφ=5 V
○
Figure 4-8 shows typical dark current temperature characteristics of S3901 to S3904 series. Their specified dark current values (typical and maximum values) at 25 °C are listed in Table
4-1. Figure 4-9 and Figure 4-10 show the dependence of dark
charge as a function of integration time for various temperatures for S3901 and S3904 series respectively. Figure 4-11
○
○
KMPDB0072EA
○
○
○
INTEGRATION TIME (s)
Dark current
Ta=25 °C
(pA)
19
Characteristic and use of NMOS linear image sensors
Figure 4-12 CTF characteristics
○
○
○
○
○
substrate. Figures 4-13 and 4-14 prove that the half-width of the
output response is 80 % of the photodiode pitch when the photosensitive area is scanned with a slit of light at 600 nm.
○
○
1 LINE PAIR
BLACK LEVEL
○
○
○
WHITE LEVEL
INCIDENT
LIGHT
(b)
(c)
(d)
○
(a)
VBO
VB
○
○
○
○
Vw
Vwo
OUTPUT
○
○
PIXEL PITCH
CTF= Vwo-VBO ×100 [%]
Vw-VB
○
○
Resolution is the ability of an image sensor to discern and reproduce the details of an incident pattern. Since the photosensitive area of NMOS image sensors is not continuous but consists
of many discrete pixels regularly arranged, the output of an incident image is derived as separate pixels. Therefore, when a test
pattern having a series of black-and-white square wave stripes
at progressively smaller spacing is viewed with an NMOS image sensor, the difference between the black and white signal
levels in the output gets smaller as the stripe spacing decreases. The extent of this output modulation versus the incident pattern is called the contrast transfer function (CTF) and is
defined as follows:
○
○
○
4-6. Resolution
○
○
○
(Typ.)
Vb=2.0 V
V =5.0 V
Extemal currentintegration method
5 µm Slit light
○
○
○
1
RELATIVE OUTPUT
0.6
0.4
White light
○
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○
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○
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○
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0.8
800 nm
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0.2
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600 nm
-50
0
50
100
○
○
0
-100
○
○
DISTANCE (µm)
○
○
○
○
○
Figure 4-14 Output response to slitted incident light
(S3904-1024Q)
○
(Typ.)
Vb=2.0 V
V =5.0 V
Extemal currentintegration method
5 µm Slit light
○
○
○
○
1
White light
0.6
800 nm
0.4
600 nm
0.2
0
-50
-25
0
25
50
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0.8
DISTANCE (µm)
○
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○
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20
Figure 4-13 Output response to slitted incident light
(S3901-512Q)
KMPDB0075EA
○
where VW and VB are the black and white image outputs, and
VWO and VBO are respectively the actual outputs of the white
level and black level. As stated, the CTF is measured with a
square wave pattern. On the other hand, the ratio of the output
modulation versus the input from a sine wave pattern is defined
as the modulation transfer function (MTF).
The fineness or detail existing between black-and-white stripes
of the incident pattern is expressed in spatial frequency of the
incident image. The spatial frequency is the number of stripes
per unit length and is equivalent to the reciprocal of the length
from one white pattern to another white pattern in Figure 4-12.
Usually, the spatial frequency is expressed in units of “line pairs
per millimeters (lp/mm)”. As seen in the figure, the finer the incident pattern or the higher the spatial frequency, the lower the
CTF (or contrast transfer function) will be.
Resolution of Hamamatsu NMOS image sensors is defined by
the MTF (or modulation transfer function). In our actual MTF
measurements, the output of a certain pixel is measured while
light is passed through a slit to scan the photosensitive area,
and this is then converted to obtain the relation between the
spatial frequency and MTF by means of Fourier transform. Figures 4-13 and 4-14 respectively show the output response of
S3901-512Q and S3904-1024Q, measured when the photosensitive area is scanned with a slitted light. The abscissa indicates the distance of movement of the slitted light with respect to
the center of the photodiode under measurement, so “0” means
that the slitted light is striking the center of the photodiode. Figures 4-15 and 4-16 show the MTF characteristics of the output
response obtained in Figures 4-13 and 4-14 respectively.
It can be seen from the figures that the resolution is wavelengthdependent. The longer the wavelength, the poorer the resolution or MTF. This is because photoelectric conversion at longer
wavelengths occurs in deeper positions inside the substrate
and thus the distance of diffusion in the horizontal direction is
made longer, so that the generated charge may leak into the
adjacent pixels until it reaches the depletion layer of the P-N
junction. To suppress these effects and minimize deterioration
in the resolution at longer wavelengths, Hamamatsu NMOS
image sensors use a well structure in which the carriers generated in deep positions inside the substrate are captured by the
KMPDC0070EA
RELATIVE OUTPUT
100 (%)
○
✕
○
VWO - VBO
VW - VB
○
CTF =
KMPDB0076EA
○
Characteristic and use of NMOS linear image sensors
○
Figure 4-15 MTF (S3901-512Q)
○
○
○
1
○
(Typ.)
○
○
0.8
○
○
White light
0.6
○
MTF
○
800 nm
○
○
600 nm
ing constant is determined by the photodiode capacitance Cp
and the ON resistance Ron of the address switch, the charge
cannot be completely injected if the address time is too short, so
that the photodiode is set to a voltage lower than its correct reset
potential. A charge is then fed to reach the actual reset potential
from this low potential even if no incident light is present. Consequently, a signal is derived due to the stored charge at the
next readout.
Figure 4-17 Lag
0.2
2
4
6
○
○
8
10
○
0
INCIDENT LIGHT
○
Vb=2.0 V
V =5.0 V
Extemal currentintegration method
LIGHT OUTPUT
○
0
○
○
○
○
0.4
○
○
SPATIAL FREQUENCY (Line pair/mm)
OUTPUT
LAG
DARK OUTPUT
○
○
KMPDB0077EA
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Figure 4-16 MTF (S3904-1024Q)
○
TIME
T
KMPDC0071EA
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(Typ.)
1
○
○
○
0.8
0.6
○
○
MTF
White light
○
○
800 nm
0.4
○
○
○
600 nm
0.2
4
8
12
16
○
○
○
○
20
○
0
○
○
0
Vb=2.0 V
V =5.0 V
Extemal currentintegration method
○
○
SPATIAL FREQUENCY (Line pair/mm)
○
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○
Lag is a phenomenon in which part of the signal persists in the
next scan after an output signal has been read out by one scan.
This is also called the time lag. A specific example is shown in
Figure 4-17. When the incident light is switched from “on” to “off”
at time T, the output signal is read out by the first scan after time
T as the image sensor has been illuminated during the integration time. At the second scan ideally, no output signal should be
read out, since the image sensor has not been illuminated during the preceding integration time. But, unless all the output
signals are completely read out at the first scan, the unread
signal will be read out at the next scan. In this way, lag occurs
since the signal readout cannot follow a steep change in incident light, thus degrading the signal accuracy with respect to
time.
Lag is caused by incomplete initialization of photodiodes. As
stated in Section 2, the reset of a photodiode is performed by
charging the photodiode capacitance from the power supply
while the address switch is turned on and by setting the photodiode potential to a certain positive potential. Since the charg-
○
4-7. Lag
○
○
○
KMPDB0078EA
Due to this, the lag is closely related to the reset time, so the
higher the readout speed, the larger the amount of lag. Figure 418 shows examples of the relation between lag and reset time,
measured when the outputs of S3901/S3904 series are read
out in the current-to-voltage conversion method. In this measurement, incident light is switched from “on” to “off” and the
output of a certain channel is readout, then the subsequent output of the same channel at the next scan is measured. The
amount of lag is defined as the rate of the output at the second
scan divided by the output that should be ideally obtained with
the first scan, and is usually expressed as a percentage. The
amount of lag decreases exponentially as the reset time is set
longer. Figure 4-18 proves that, even for S3901 series with its
large photodiode area, the amount of lag decreases below 0.1
% when the reset time is set to 2.5 µs or longer.
As stated above, the reset time for the current output type image
sensors corresponds to the time that the address switch is
turned on (or the time that clock pulse φ2 is being fed in). To the
contrary, the reset operation for the voltage output type image
sensors is performed while the address switch is turned on and
also an external reset pulse is applied to the reset switch. Thus
reset time corresponds to the overlap time of the clock pulse φ2
and reset pulse. Figure 4-19 shows an example of how the
amount of lag relates to the overlap time of φ2 and reset pulse for
S3921/S3924 series. The figure shows that the amount of lag
decreases exponentially as the overlap time lengthens, for example the amount of lag for S3921-512Q decreases to below
0.1 % when the reset time is set to 2 µs or longer.
The discussion above refers to a situation that the incident light
level steeply has decreased. When the incident light conversely
increases, a similar phenomenon occurs producing a signal
output which is smaller than the ideal output. If the amount of
unread signal is too large, a lag may appear in not only the first
scan but also the subsequent scans, so that several scans may
be required before reaching a normal output state. At this point,
21
○
○
○
○
○
○
○
○
when there is sufficient time for signal processing with respect
to a change in the incident light, a dummy scan is effective in
eliminating lag effects. In this method, after the signal has
changed, dummy scans are repeated until the output reaches
the normal steady state, and data is then read out.
○
Characteristic and use of NMOS linear image sensors
○
○
Figure 4-18 Lag (current output type)
(Typ.)
○
100
○
○
○
○
Vb=2.0 V
V =5.0 V
Extemal currentintegration method
○
10
○
○
○
○
○
1
○
○
LAG (%)
S3901 Series
○
0.1
0
1
2
3
○
○
0.01
○
KMPDB0079EA
○
○
RESET TIME (µs)
○
○
Figure 4-19 Lag (voltage output type)
○
(Typ.)
○
100
○
○
○
○
○
○
1
○
S3924-1024Q
○
○
LAG (%)
○
○
S3921-512Q
○
○
○
○
0.1
○
0.01
2
3
○
1
○
0
When a current output type NMOS linear image sensor is read
out by the external current-integration method, the following 5
types of random noise components may be included in the output.
(1) Dark current shot noise
(2) Photodiode reset noise
(3) Reset noise due to readout circuit integration
capacitance
(4) Readout circuit current noise
(5) Readout circuit voltage noise
○
Reset V=2.5 V
Vdd=5.0 V
V =5.0 V
10
4-8-1. Random noise in current output type
○
○
○
○
○
S3904 Series
○
○
RESET PULSE AND CLOCK PULSE 2 OVERLAP TIME (µs)
○
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○
NMOS image sensor noise is largely divided into fixed pattern
noise and random noise.
Fixed pattern noise includes spike noise and dark current.
Spike noise is a switching noise occurring on the video line via
the drain to gate capacitance of the MOS switch when an address pulse is input. The magnitude of these noises is constant
when the readout conditions are specified, so they can be subtracted from each pixel on signal processing software.
In contrast, random noise is traceable to erroneous fluctuations
of voltage, current or electrical charge which are caused in the
signal output process. This random noise may occur inside the
image sensor and also in the readout circuit. When the fixed
pattern noise is subtracted by an external circuit, random noise
○
○
4-8. Noise
○
○
○
KMPDB0080EA
22
determines the lower limit of light detection of the image sensor,
or the lower limit of dynamic range. Taking performance during
actual operation into account, Hamamatsu NMOS image sensors are tested and evaluated by measuring the total random
noise derived from the readout circuit, not from the image sensor only. The following sections discuss random noise of the
current output type and voltage output type NMOS image sensors, evaluated with the recommended driver/amplifier circuits
available from Hamamatsu. The noise level is expressed in
equivalent input noise or ENI, which is a value converted into
input charge units to the image sensor. These units are the rootmean-square value for the number of electrons (electrons
r.m.s.).
Figure 4-20 shows a typical noise level when the signal of a
current output type NMOS image sensor is read out by an external current-integration circuit. Here the abscissa indicates the
sum of the photodiode capacitance and video line capacitance.
This noise measurement is made at a readout speed of 64 µs
per pixel, an integration time of 100 ms and a sensor element
temperature of 15 °C. The noise level is 2000 to 3500 (electrons r.m.s.) depending on the pixel size and the number of
pixels.
In general, reset noise (3) occurring when the integration capacitance is reset, is predominant in current-integration circuits. However, this component can be greatly reduced by introduction of a clamping circuit that holds the signal at a constant potential immediately after reset has been performed.
Consequently, the readout circuit voltage noise (5) and photodiode reset noise (2) become significant sources of random
noise. The readout circuit voltage noise increases in proportion
to the sum of the video line capacitance and photodiode capacitance, while the photodiode reset noise increases in proportion to the square root of the photodiode capacitance. The
reset noise component makes up a large portion of the total
noise, especially for S3901/S3904 series NMOS image sensors which have a large photodiode area.
The dark current shot noise (1) results from fluctuations due to
erratic generation of the dark output charge. This noise level is
small under the above conditions, but increases with increasing dark output charge. Therefore, it differs depending on operating conditions such as integration time and temperature (dark
current value). Figure 4-22 shows the noise level (theoretical
value) of S3904-1024Q as a function of the dark output charge.
Type No.
S3901-128
-256
-512
S3902-128
-256
-512
S3903-256
-512
-1024
S3904-256
-512
-1024
DR
4
9.5 × 10
4
9.1 × 10
4
8.7 × 10
4
2.5 × 10
4
2.4 × 10
4
2.3 × 10
4
1.2 × 10
4
1.0 × 10
4
0.9 × 10
4
4.4 × 10
4
4.2 × 10
4
4.0 × 10
ADC
16
15
14
15
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○
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○
○
○
○
○
○
○
Table 4-2 Dynamic range of current output types
○
The dark current shot noise component makes up a larger portion of the noise, and as the dark output charge increases, resulting in more total noise. In addition to the above noise
sources, there is shot noise due to photon-excited charges produced when light strikes the image sensor. This is caused by
fluctuations due to the random arrival of photons. Consequently, the noise level as shown in Figure 4-20 may not be
attained depending on the actual operating environment.
Since the upper limit of the dynamic range is determined by the
saturation output charge while the lower limit depends on the
charge equal to the noise level shown in Figure 4-20, the dynamic range can be figured out from these values. Table 4-2
shows the dynamic range for the current output type image sensors.
○
Characteristic and use of NMOS linear image sensors
○
○
○
Figure 4-20 Noise level (Current output types)
○
○
4000
○
256
○
128
512
1024
○
256
1024
512
○
128
○
○
○
○
256
2000
○
1000
10
20
30
40
50
○
0
○
○
KMPDB0081EA
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SUM OF PHOTODIODE CAPACITANCE
AND VIDEO LINE CAPACITANCE (pF)
○
○
○
Figure 4-21 Noise level vs. dark output charge
(Theoretical value for S3904-1024Q)
○
○
○
○
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○
15000
Dark current shot noise
Photodiode reset noise
Video line reset noise
Readout circuit current noise
Readout circuit voltage noise
Johnson noise of resistors used in inverting amplifier of
readout circuit
○
○
○
○
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○
10000
1
10
100
○
0.1
○
0.01
○
○
DARK OUTPUT CHARGE (pC)
○
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KMPDB0082EA
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0
0.001
○
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5000
Figure 4-22 shows a typical noise level when the signal of a
voltage output type NMOS linear image sensor is read out by an
external inverting amplification circuit. Here the abscissa indicates the sum of the photodiode capacitance and video line
capacitance. This noise measurement is made at a readout
speed of 64 µs per pixel, an integration time of 100 ms and a
sensor element temperature of 15 °C. The noise level is proportional to the sum of the photodiode capacitance and video line
capacitance, and ranges from 2000 to 5500 (electrons r.m.s.).
The dominate noise sources are, readout circuit current noise
(4), Johnson noise (6), and video line reset noise (3). The readout circuit voltage noise and Johnson noise are proportional to
the sum of the photodiode capacitance and video line capacitance. The video line reset noise is proportional to the square
root of the video line capacitance. Just as with current output
type image sensors, dark current shot noise of (1) and photoninduced shot noise will vary depending on the operating conditions.
Since the upper limit of the dynamic range is determined by the
saturation output charge while the lower limit depends on the
charge equal to the noise level shown in Figure 4-22, the dynamic range can be figured out from these values. Table 4-3
shows the dynamic range for the voltage output type image
sensors.
○
NOISE (e- r.m.s.)
(1)
(2)
(3)
(4)
(5)
(6)
○
○
○
○
Vb=2.0 V
V =5.0 V
External current-integration
method
○
0
When the signal of a voltage output type NMOS linear image
sensor is read out by the external inverting amplification
method, the following 6 types of random noise components may
be included in the output.
○
○
512
256 512
○
NOISE (e- r.m.s.)
3000
4-8-2. Random noise (voltage output type)
23
Characteristic and use of NMOS linear image sensors
○
○
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1024
1024
○
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512
512
○
256
○
128
○
512
4000
○
256
128
○
256
2000
○
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○
NOISE (e- r.m.s.)
256
10
○
○
20
30
40
50
○
0
○
0
○
Reset V=2.5 V
Vdd=5.0 V
V =5.0 V
15
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14
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15
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1: 2=1:1
6
-40 ˚C
0 ˚C
5
20 ˚C
50 ˚C
4
3
2
0.01
0.1
1
10
○
○
○
7
○
READOUT FREQUENCY (MHz)
Figure 4-24 Minimum operating clock pulse voltage
vs. readout frequency (S3904-1024Q)
7
1: 2=1:1
-40 ˚C
6
0 ˚C
20 ˚C
5
50 ˚C
4
3
2
0.01
0.1
1
10
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KMPDB0084EA
READOUT FREQUENCY (MHz)
○
The shift register of NMOS linear image sensors consists of Nchannel MOS transistors and operates when an external start
pulse and two-phase clock pulses are applied. The clock pulse
must have an amplitude higher than a certain voltage. This is
because a voltage higher than the threshold voltage Vth must
be applied to the gate of MOS transistors which constitute the
shift register, in order to turn on the MOS transistors. This minimum clock pulse voltage required for shift register operation
varies with the operating frequency, so the maximum operating
frequency exists according to the clock pulse voltage. This limitation of the operating frequency occurs because, as the operating frequency increases, the pulse response in the scanning
circuit required for shift register operation does not end within
the clock time and disables normal operation of the shift register. At this point, increasing the clock pulse voltage lowers the
ON resistance of MOS transistors and makes the pulse response faster, thus enabling proper operation. In this way, the
higher the clock pulse voltage, the higher the maximum operating frequency will be. The maximum operating frequency for
Hamamatsu current output type NMOS image sensors is specified as a 2 MHz data rate (readout frequency) at a clock pulse
voltage of 5 V.
The frequency characteristics of the minimum operating clock
○
○
4-9. Shift register frequency characteristics
Figure 4-23 Minimum operating clock pulse voltage vs.
readout frequency (S3901-512Q)
○
○
○
○
15
○
○
○
ADC
○
DR
4
4.7 × 10
4
4.5 × 10
4
4.1 × 10
4
2.4 × 10
4
2.1 × 10
4
1.7 × 10
4
1.4 × 10
4
1.1 × 10
4
0.7 × 10
4
3.9 × 10
4
3.0 × 10
4
2.7 × 10
○
Type No.
S3921-128
-256
-512
S3922-128
-256
-512
S3923-256
-512
-1024
S3924-256
-512
-1024
○
○
Table 4-3 Dynamic range (voltage output type)
○
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KMPDB0083EA
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○
SUM OF PHOTODIODE CAPACITANCE
AND VIDEO LINE CAPACITANCE (pF)
MINIMUM OPERATING CLOCK PULSE VOLTAGE (V)
512
pulse voltage also vary with the sensor element temperature.
The threshold voltage Vth and pulse response that determine
the lower limit of the operating clock voltage vary with temperature, but in different manners. The threshold voltage Vth for
MOS transistors drops with increasing temperature and the
minimum clock pulse voltage required to turn on MOS transistors drops. In contrast, the pulse response become slower as
temperature increases because the ON resistance of MOS transistors and the diffusion resistance inside the scanning circuit
increase, and the maximum operating frequency decreases but
the minimum operating clock voltage increases.
Figures 4-23 and 4-24 show minimum operating clock pulse
voltage vs. readout frequency at different temperatures from -40
°C to +50 °C while the duty ratio of two-phase clock pulses is set
to 1:1. When the readout frequency is low, the threshold voltage
Vth is predominant in determining the minimum operating clock
pulse voltage, and the lower the temperature, the higher the
minimum operating clock pulse voltage becomes. On the other
hand, in high-speed operation the pulse response is the dominant factor, and the higher the temperature, the higher the minimum operating clock pulse voltage becomes.
MINIMUM OPERATING CLOCK PULSE VOLTAGE (V)
6000
○
○
○
Figure 4-22 Noise level (voltage output type)
○
KMPDB0085EA
24
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○
VARIATION IN CURRENT (%)
250
200
150
100
UV source:
254 nm mercury lamp
Initial value: 100 %
Vb=2.0 V
V =5.0 V
External currentintegration method
50
0
0
200
400
600
800
1000
1200
UV EXPOSURE (Joule/cm2)
○
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300
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KMPDB0188EA
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Figure 4-25 UV sensitivity after UV exposure (S3901-512Q)
○
○
Silicon photodiodes characteristics tend to deteriorate after
continuous exposure to UV (ultraviolet) radiation, for example
dark current may increase or sensitivity may drop. This deterioration is attributed to an increase in the interface state, which
occurs when binding of Si and H, O or OH at the Si-SiO2 interface is broken by input of high-energy UV radiation. This then
causes the surface leakage current to rise, leading to an increased dark current. At the same time, the photon-generated
charge is trapped by this state, so the photon-generated current
reduces, resulting in lowered sensitivity. This is particularly noticeable for light at shorter wavelengths because it is absorbed
near the surface of the substrate.
Figures 4-25 and 4-26 respectively show spectral response
and dark current characteristics of S3901-512Q, measured after exposure to UV radiation from a mercury lamp (1100 Joules/
cm2 at 254 nm).
Spectral response measured before UV exposure is also plotted in Figure 4-25 indicating there is no sensitivity drop even
after UV exposure. Figure 4-26 shows dark current variations in
percentage, with 100 % being equal to the initial value measured before UV exposure. It is clear that the dark current increase is suppressed to 2.5 times the initial value even after a
UV exposure of 1100 Joules/cm2.
Hamamatsu NMOS linear image sensors are designed to provide stable characteristics even after a long-term UV exposure
making them ideally suited for use in spectrophotometry where
sensors are likely to be used for the detection of UV radiation.
Figure 4-26 Dark current change under UV exposure
(S3901-512Q)
○
4-10. Characteristic change by UV exposure
○
Characteristic and use of NMOS linear image sensors
○
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○
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○
○
○
○
○
0.2
○
UV source:
254 nm mercury lamp
Vb=2.0 V
V =5.0 V
External currentintegration method
○
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0.1
○
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1000
1200
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800
1400
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600
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KMPDB0187EA
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WAVELENGTH (nm)
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400
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0
200
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0
100
UV exposure (Joule/cm2)
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PHOTO SENSITIVITY (A/W)
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(Typ.)
0.3
25
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(3) Readout time
When a start pulse is input, the shift register starts operation.
The next start pulse cannot be input until the last pixel is
scanned for output (readout time). If a start pulse is input during
the readout time again, the output signals from the first scan and
the second scan are mixed. In view of the these facts, it is obvious that integration time cannot be set shorter than the readout
time required to scan all pixels, so the minimum integration time
is limited by the readout time. Therefore, the minimum integration time is determined by the readout frequency and number of
pixels.
For example, when an NMOS linear image sensor with 1024
pixels is operated at a readout frequency of 50 kHz, the readout
time required for all pixels is
26
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20 µs # 1024 = 20.48 ms
5-2. Output estimation
If the illuminance of light falling on the photosensitive surface is
known, the output charge can be estimated from the spectral
response characteristics.
Taking as an example a situation in which S3904 series (pixel
pitch 25 µm, pixel height 2.5 mm) is illuminated with light at a
wavelength of 500 nm and a faceplate illuminance of 1 µW/cm2.
If the integration time is set, for example, to 100 ms, then the
incident exposure is given by
Input light exposure = illuminance [W/cm2] # integration time [s]
= 1 # 10-6 # 0.1 [W . s/cm2]
= 0.1 [µJ/cm2]
Next, let us figure out the sensitivity of S3904 series in response
to incident light at 500 nm. Spectral response in Figure 4-5 is
represented in sensitivity per unit area, which is 0.2 A/W at 500
nm. If the entire photodiode is illuminated, the sensitivity of
S3904 series is given as follows:
Sensitivity = 0.2 [A/W] # 0.25 # 25 # 10-4 [cm2]
= 1.25 # 10-4 [cm2 . A/W]
= 125 [cm2 . µC/J]
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The integration time cannot be set shorter than this value.
The readout frequency for Hamamatsu NMOS linear image
sensors is matched with the clock pulse frequency. The maximum readout frequency is determined by the maximum operating frequency of the shift register. But it should be noted that
image sensor characteristics such as the amount of lag may
vary depending the reset time for each pixel as explained previously, even when the image sensor is operated at a frequency
lower than the maximum readout frequency. Accordingly, readout time must be selected by taking into account operating and
readout conditions as well as the characteristics necessary for
the device application.
Thus the output charge is given by the product of input light
exposure and sensitivity, as follows:
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T = (Qsat # allowable value) / ID
= (20 # 0.01) / 0.1 = 2 (s)
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(2) Dark current level
The dark output is proportional to the product of the dark current
and the integration time. Since the saturation output charge is
constant, an increase in dark output narrows the range of light
detection. The dark output also exhibits non-uniformity, so the
dark output component of each pixel must be subtracted, otherwise light detection accuracy degrades with increasing dark
output.
The allowable level of the dark output depends on the characteristics to be required. The allowable level of the dark output
should first be determined and then the integration time set so
that dark output does not exceed the required value. Because
the dark output is also temperature-dependent, the integration
time should be adjusted according to changes in the ambient
temperature.
For example, let us consider the integration time settings
needed to make measurements using S3904 series NMOS linear image sensor under conditions where the allowable dark
output is 1 % of the saturation charge. Since the dark current at
a saturation charge of 20 pC and operating temperature of 25
°C is typically 0.1 pA, the maximum integration time T becomes
2 seconds as calculated from the equation below. If the sensor
element temperature rises to 35 °C, the dark current increases
to 0.4 pA. The maximum integration time for the same allowable
dark output (1 % of the saturation charge) will be 500 ms.
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(1) Incident light intensity
The output of an NMOS linear image sensor is proportional to
the quantity of incident light, in other words, the product of the
light intensity and the integration time. Since the maximum
charge that can be stored in each photodiode is finite, it is not
possible to read out a signal change exceeding the saturation
output charge. In addition, such an over-saturation charge may
cause blooming phenomenon, resulting in adverse effects on
image sensor characteristics.
For the above reasons, the maximum integration time must be
set in consideration of the incident light intensity, so that no
saturation occurs in the signal output.
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The integration time corresponds to the time interval between
start pulses φst. This means that the integration time does not
vary even if the operating frequency of the shift register is
changed. The integration time can only be changed by varying
the interval between the input of one start pulse and the input of
the next start pulse.
When setting the integration time, its maximum and minimum
times are limited by incident light intensity, dark current level,
and readout time. Therefore, an optimum integration time must
be selected by taking these factors into account.
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5-1. Integration time setting
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5. Precautions
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Characteristic and use of NMOS linear image sensors
Output charge = input light exposure # sensitivity
= 0.1 # 125 = 12.5 [pC]
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5-4. Positional accuracy of photosensitive area
Photodiodes are arrayed in geometrical precision on the silicon
chip of an NMOS linear image sensor, providing a high degree
of position detection accuracy. However, due to factors such as
mounting precision of the chip onto the package or dimensional
precision of the ceramic package itself, the distance from the
package to the photosensitive position is specified within a certain tolerance with respect to a reference position.
Figure 5-1 shows outline drawings of an NMOS linear image
sensor together with the positional accuracy of the photosensitive area. Drawing (1) of Figure 5-1 shows a top view of the
image sensor, and (2) is a side view in the scanning direction,
while (3) is another side view along the plane perpendicular to
the scanning direction. In Hamamatsu NMOS linear image sensors, the positional accuracy in the scanning direction is specified as the distance between the first pixel position and the
package center, as shown in (1). The height of the photosensitive surface is specified as the distance from the surface of the
quartz window to the chip surface. The package size and the
position of the photosensitive area differ according to the pixel
size and number of pixels.
As stated, the position of the photosensitive area is within a
certain tolerance. This means that the positional accuracy may
differ slightly from image sensor to image sensor. In critical applications requiring high measurement accuracy, the image
sensor should be installed in equipment having an alignment
mechanism for making fine-adjustments to the positions in the
X, Y and Z directions and also to the chip surface angle θ with
respect to the package, so that the tolerance of each image
sensor can be compensated.
The photosensitive position tolerance with respect to the leads
becomes even larger when involving package lead brazing
precision which is about ±0.2 mm. Also note the direction of
height, since the leads are not always brazed perfectly parallel
to the package. For this reason, the photosensitive area might
become tilted with respect to the board if the image sensor is
installed using the leads as a reference. To avoid this, fit in
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Since NMOS linear image sensors have spectral response
characteristics, their sensitivity differs depending on light wavelength of the light source to be used. This means that light intensity and integration time must be adjusted according to the light
source. Input/output characteristics of Hamamatsu NMOS linear image sensors are measured using a standard "A" light
source (tungsten lamp at 2856 K color temperature).
When a tungsten lamp or deuterium lamp is used as the light
source, attention should be paid to the output stability after the
lamp turns on and to the output variations resulting from the
lamp service life. In some cases, the sensor element temperature may rise due to the lamp heating up, causing the dark output and apparent sensitivity to increase. In addition, the sensor
element temperature may rise due to repeated opening and
closing of the shutter located between the lamp and the sensor,
thus increasing the dark output and apparent sensitivity as well.
Therefore, in applications requiring high accuracy, some
means to minimize temperature change in the sensor element
is essential. Such means would include, for example, radiating
heat from the light source, widening the distance between light
source and sensor element, and temperature control of the sensor element.
In the measurement of light from an AC-operated light source
such as a fluorescent lamp, if the frequency is too low, lighting
fluctuation may appear in the output as flicker effects. Therefore,
such a lamp must be operated at a high frequency of about 50
kHz or more, and not at the normal frequency used in commercial power lines. In high frequency lighting, the lighting duration
is sufficiently short compared to the integration time, so flicker
effects on the output are reduced.
In measurement of pulsed light from an LED and other light
sources, if changes in light intensity occur within the integration
time, the NMOS linear image sensor operating in the chargeintegration mode cannot detect these changes separately. The
changes within the integration time are output as one signal.
When the light source is positioned too close to the image sensor, non-uniformity in the incident light level, which results from
the light source output characteristics and/or the installation
method, may appear in the image sensor output. In such cases,
the light source must be positioned farther away from the sensor
or a diffuser plate should be interposed between them so that
the incident light becomes uniform. When focusing on an image
with a lens system, the quantity of light near the image sensor
might sometimes be reduced. This problem (so-called shading)
can be corrected by placing a slit with an aperture pattern which
is inverse to the output pattern, in the optical path.
When the incident light includes long wavelength components,
resolution and output uniformity may be degraded because
long wavelength light is absorbed at deeper positions within the
sensor substrate. To minimize these effects, Hamamatsu
NMOS linear image sensor are designed to suppress sensitivity
to long wavelengths. In addition, use of an infrared-cut filter
further reduces these effects. On the other hand, light of short
wavelengths has higher incident energy and may cause damage inside the sensor substrate, leading to an increased dark
current and lowered sensitivity. Due to the improved manufacturing process, Hamamatsu NMOS linear image sensors are
engineered to resist UV radiations. However, the NMOS linear
image sensor should not be exposed to UV radiations unnecessarily except during measurement, because the longer the UV
exposure time, the larger the deterioration of characteristics becomes.
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5-3. Light sources
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Since the saturation charge of S3904 series is 20 pC, an output
charge equal to about 60 % of the saturation charge can be
obtained under the above conditions. The output charge is proportional to the integration time and as described previously,
the integration time is limited by the output saturation time, so
that the maximum integration time in this case will be 20/12.5 ×
100 = 160 ms.
The output charge can also be estimated for image sensors with
different photosensitive areas or different light wavelengths, by
substituting the numerical values in the above equations.
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Characteristic and use of NMOS linear image sensors
27
D
31.75
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3.0
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(2) Package side view
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spacers between the board and package to make it level so that
the package surface can be used as a reference for installing
the image sensor. The table below and Figure 5-1 show the
dimensional and positional tolerance of Hamamatsu NMOS linear image sensors.
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Characteristic and use of NMOS linear image sensors
2.5
5.0 ± 0.2
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3.0
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0.51
2.54
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5.2 ± 0.2
40.6
25.4
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0.5
5.2 ± 0.2
E
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0.5
5.0 ± 0.2
2.54
25.4
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2.5
b
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0.51
(3) Chip height (all types)
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Figure 5-1 Dimensional outlines (Unit: mm)
1.3 ± 0.2*
ACTIVE AREA
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S3901/S3921-128
-256
-512
S3902/S3922-128
-256
-512
S3903/S3923-256
-512
-1024
S3904/S3924-256
-512
-1024
a
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Type No.
Side
view
D
D
E
D
D
E
D
D
E
D
D
E
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Top
view
A
B
C
A
B
C
A
B
C
A
B
C
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* Optical distance from
outer surface of quartz window
to chip surface
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(1) Package top view
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0.25
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10.16
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KMPDA0077EA
5-5. Precautions during handling
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b
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10.4
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ACTIVE LENGTH
a
3.2 ± 0.3
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5.4 ± 0.2
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ACTIVE LENGTH
6.4
A
Pay special attention to the following points to ensure correct
use of NMOS linear image sensors.
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b
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10.4
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ACTIVE LENGTH
a
6.4 ± 0.3
5.4 ± 0.2
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ACTIVE LENGTH
12.8
B
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31.75
C
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(2) Installation
When installing an image sensor into the socket on the circuit
board, note the correct pin positions. If the image sensor is mistakenly mounted in a reversed or incorrect position, it may be
damaged when power is applied. After making sure the image
sensor has been installed correctly, turn on the power supply.
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b
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10.4
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ACTIVE LENGTH
a
12.8 ± 0.3
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5.4 ± 0.2
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ACTIVE LENGTH
25.6
(1) Absolute maximum ratings
As with other electronic devices, NMOS linear image sensors
have maximum ratings specified for the supply voltage, storage
temperature and operating temperature that must not be exceeded even momentarily. Always use a NMOS linear image
sensor within the maximum ratings. For example, the maximum
ratings for Hamamatsu NMOS linear image sensors with a
quartz window are specified as 15 V for the supply voltage, -40
to +85 °C for storage temperature, and -30 to +65 °C for the
operating temperature.
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40.6
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KMPDA0076EA
28
(3) Electrostatic countermeasures
Although NMOS linear image sensors are provided with safety
measures to guard against static electricity, careful handling is
required. For example, always wear cotton gloves and antistatic clothing to prevent electrostatic damage due to electrical
charges from friction etc. Furthermore, electrostatic measures
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(5) Digital signal
An NMOS linear image sensor can be operated with a CMOS
level input clock pulses. The input clock pulse line should be
separated from the video signal line and power supply line as
much as possible, because constant voltage variations occur
within it. The input pulses should be fed to the sensor element at
the specified timing. In high-speed operation, the clock voltage
hold time particularly affects shift register operation. So care is
required so that rise and fall times are not delayed.
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(6) Analog signal
The wiring width and length from the video output terminal to the
amplifier should be kept as short as possible. Further, use the
same wiring width and length of signal line for the active video
side and for the dummy video side, so that their capacitance
matches. To avoid noise intrusion into the output signal, the
video signal line should be located away from the digital signal
lines subject to constant voltage variations, such as the clock
line. Also, the lines should not cross each other at the front or
rear of the circuit board.
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(7) Supply voltage
The video bias voltage and reset voltage determine the photodiode reset potential, and the clock pulse amplitude determines
the ON resistance of the address switch. Therefore, if these supply voltages for the image sensor fluctuate, the output characteristics become unstable. The power supplies used must provide good voltage regulation and also the image sensor supply
voltage should be insensitive to variations in the external voltage supply. The supply voltage for the image sensor should be
stable even if voltage fluctuations accompanying the operation
of the circuit components occur in the power supply line. The
power supply line for the sensor element should be separated
as much as possible from digital signal lines such as clock line
on which constant voltage variations occur.
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(8) Others
Make sure circuitry is reliably shielded because noise can be
generated by factors such as mechanical action in the equipment in which the image sensor and driver circuit board are
installed, and this noise then mixes with the output signal.
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(4) Grounding
To prevent the digital circuit noise from intruding into the analog
circuit via ground, isolate the digital circuit from the analog circuit, and use a thick ground line having lower resistance. The
NC (no connection) terminals should all be grounded.
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(3) Circuit components
As stated earlier, the dark current and sensitivity of an image
sensor vary greatly with sensor element temperature. To minimize the temperature rise or variations in the sensor, use circuit
components which generate as little heat as possible. If components which generate heat must be used, locate these components away from the image sensor and also provide effective
heat dissipation measures.
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(2) Circuit board
The mounting holes of the circuit board should be slightly larger
than the screw diameter to allow fine-adjustment of the sensitive area position when mounting the circuit board. The circuit
board material used should be warp-resistant so that the focal
point will not shift. Moreover, the board should be resistant to
heat radiation from the light source.
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(1) Image sensor mounting side
The image sensor should be installed on the rear side opposite
to the component-mounted side. This is to facilitate adjustment
of mounted components even after the image sensor has been
installed in an optical system. For example, the variable resistors can be easily accessed from the rear side during image
sensor operation.
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The following points require particular attention when configuring driver circuit boards because the driver and readout circuits
are influenced by image sensor light input section and these
circuits are also characterized by a mix of digital and analog
circuitry.
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5-6. Precautions when configuring driver circuit boards
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(4) Faceplate (window)
Grime or scratches on the faceplate may degrade uniform sensitivity. If fingerprints or oil from hands adhere to the faceplate,
the window transmittance may be lowered, causing performance deterioration. Never touch the faceplate window with
bare hands. Before using the image sensor, the faceplate
should be cleaned. Use a soft cloth or cotton swab moistened
with ethyl alcohol to wipe off the faceplate. Do not use dry cloth
or cotton swabs as these may generate static electricity. When
packaging or transporting the equipment in which the image
sensor is installed, take sufficient care to keep the faceplate
protected from dust, grime and scratch.
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should be implemented to protect the image sensor, for example, grounding of items in the work environment and tools.
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Characteristic and use of NMOS linear image sensors
29
Characteristic and use of NMOS linear image sensors
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6. Recommended driver circuits
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6-1. Driver circuit for current output type
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(a) Current-to-voltage conversion amplifier
As a current-to-voltage conversion amplifier, choose a
high-speed dual operational amplifier (having two circuits) that exhibits low noise and less leaks.
(b) Differential amplifier
Choose an amplifier that is resistant to load capacitance.
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Note the following points when selecting amplifiers.
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(1) Recommended circuit configuration
This type of driver circuit basically consists of a control signal
generator and a video signal processor. Figures 6-1 and 6-2
show the block diagram and circuit diagram of a typical driver
circuit using the current-to-voltage conversion method. The
control signal generator produces various control pulses required for the image sensor and external signal processor. The
video signal processor performs current-to-voltage conversion,
differential amplification and then outputs the processed signal.
By applying external supply voltages for digital and analog circuitry, and also master clock and master start pulses, this driver
circuit provides a data video output, trigger pulse and end-ofscan (EOS) pulse. Table 6-1 gives a description of the input/
output terminals.
The control signal generator consists of a PLD (programmable
logic device), and generates a start pulse and two-phase clock
pulses to operate the shift register. The control signal generator
also provides a trigger signal for external sample-and-hold and
outputs it via a buffer. These signals are synchronized with an
external master clock pulse, and are initialized by an external
master start pulse. The master clock and master start pulses are
input to the PLD via a buffer.
The video signal processor is made up of three sections. The
active video output current from the image sensor is first fed to
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6-1-1. Current-to-voltage conversion method
the inverting input terminal of the first-stage amplifier and converted into a voltage. The non-inverting input terminal is applied
at a video bias voltage of 2 V. Similarly, another first stage amplifier performs current-to-voltage conversion of the dummy
video output from the image sensor. The output of this first stage
is a positive going signal with respect to the 2 V video bias
voltage, with a differential waveform. The active video output
includes the signal and switching noise components, while the
dummy video output only consists of a switching noise component. In the differential amplifier of the next stage, the switching
noise component, which is fixed pattern noise, can be eliminated by differential amplification of these two outputs. Thus a
signal output without switching noise is derived from the data
video terminal as the final output. This final output has a differential waveform of positive polarity with respect to ground level.
The end-of-scan (EOS) terminal is pulled up at 5 V, with a resistor of 10 kΩ. The end-of-scan signal appears synchronized with
the φ2 timing immediately after the last pixel is scanned, and is
available to an external device from the EOS terminal via a
buffer.
Figure 6-1 Block diagram of recommended current-to-voltage conversion circuit
CONTROL SIGNAL GENERATOR
st
1, 2
EOS
VIDEO
BUFFER
PLD
VIDEO SIGNAL PROCESSOR
BUFFER
Start, CLK
EOS, trigger
D. GND
I-V
SENSOR
AMP
DUMMY
I-V
Data Video
VCC
D. GND
VOLTAGE REGULATOR
+15 V
+2 V
A. GND
-15 V
KACC0145EA
30
Characteristic and use of NMOS linear image sensors
Figure 6-2 Recommended current-to-voltage conversion circuit
P2
TRIG
1
8
6
4
2
33
32
31
30
29
28
27
26
25
24
23
19
PST 34
35
P1
36
MCLK
37
38
39
40
41
MSTART VCC
42
43
44
EOS
G
A4
A3
A2
A1
Y4
Y3
Y2
Y1
12
14
16
18
74VHCT244AF
PLD
22
21
20
19
18
17
16
15
14
13
12
IO
IO
IO
IO
IO
VCC
GND
IO
IO
IO
IO
IO
IO
GND
IN3/CLK3
IN2/CLK2
IN1/CLK1
IN0/CLK0
VCC
IO
IO
IO
TDI
IO
IO
GND
IO
IO
TMS
IO
VCC
IO
IO
0.1 µF
CLK
START
VCC
IO
TDO
IO
IO
VCC
IO
IO
TCK
IO
GND
IO
VCC
Y4
Y3
Y2
Y1
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
3
5
7
9
74VHCT244AF
VCC
CLK2
NC
CLK1
NC
ST
NC
VSS
NC
VSCG
NC
NC
NC
VSCD
NC
VSS
NC
ACTIVE VIDEO
NC
DUMMY VIDEO
NC
EOS
VSUB
22
21
20
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S390X SERIES 10 k
VCC
1k
1k
1k
1k
VCC
1
2
3
4
5
6
7
8
9
10
11
TRIGGER
N_EOS
G
17
15
13
11
VCC
VCC
0.22 µ 0.22 µ 0.22 µ 0.22 µF
-15
1000 pF
10 µF/25 V
1000 pF
3 pF
5 pF
10 µF/25 V
1000 pF
7
10 k
10 k
DATA VIDEO
15
24 k
- 6
+ 5
100
-15
0.1 µF
2
6
+ 3
3 pF
8
7
4
VCC
10 µF/25 V
-15
0.1 µF
2
1
+ 3
24 k
4
+15
+15
0.1 µF
10 k
13 k
8
10 k
100
+15
0.1 µF
+15
2k
0.1 µF
KACC0146EA
Table 6-1 Input/output terminal description of recommended current-to-voltage conversion circuit
Terminal name
Symbol
on board
Polarity
Supply voltage Vd
(for digital circuitry)
+5
-
+5 V, 70 mA
+15
-
+15 V, 30 mA
-15
-
-15 V, 30 mA
Master start pulse φms
START
Positive
Initializes internally generated pulse; C-MOS logic
compatible.
Master clock pulse φmc
CLK
Positive
Synchronizes internally generated pulse; CMOS logic
compatible.
Supply voltage Va
(for analog circuitry)
Input
Ground
Ground.
G
-
Video
Positive
Video output.
Trigger pulse
Trig.
Positive
A/D conversion timing signal; CMOS logic compatible.
End-of-scan pulse
EOS
Negative
End-of-scan signal for shift register; CMOS logic
compatible.
Video
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
tive going output. Their amplitude voltages Vtrig and Veos are
also 5 V. The final data video output obtained has positive
polarity with respect to the ground.
Voltages actually applied to the image sensor are as follows:
The amplitude of the clock pulses Vφ1 and Vφ2, and start pulse
Vφst are 5 V; the video bias voltage Vb that determines the
photodiode reset voltage is 2 V; the saturation control gate
voltage Vscg is 0 V; the saturation control drain voltage Vscd is
2 V which is equal to the video line bias voltage Vb. The Vss,
Vsub and NC terminals are all grounded.
○
(2) Supply voltage
Table 6-2 shows typical input supply voltage, input pulse amplitude voltage, output voltage and output pulse amplitude
voltage for this recommended driver circuit.
The input supply voltage Vcc for digital circuitry is +5 V, and Vs
for analog circuitry is ±15 V. The input pulses consist of a master clock pulse φmc and a master start pulse φms. These are
positive going pulses and their amplitude voltages Vmc and
Vms are both 5 V. The trigger pulse for external output is a
positive going output, while the end-of-scan pulse is a nega-
○
○
Output
Function
31
Characteristic and use of NMOS linear image sensors
Table 6-2 Typical input/outupt voltages for recommended current-to-voltage conversion circuit
Input or output voltage
Supply voltage for digital circuitry
Supply voltage for analog circuitry
Input
Mater start pulse φms
Master clock pulse φmc
Trigger pulse
Output
End-of-scan pulse
Start pulse φst
Output for
Clock pulse φ1, φ2
image
sensor
Video bias voltage
Saturation control drain voltage
Saturation control gate voltage
Symbol
Vd
Va
Vms (H)
Vms (L)
Vmc (H)
Vmc (L)
Vtrig (H)
Vtrig (L)
Veos (H)
Veos (L)
Vs (H)
Vs (L)
Vφ1, Vφ2 (H)
Vφ1, Vφ2 (L)
Vb
Vscd
Vscg
Min.
4.85
±14.5
2
0
2
0
4.75
4.75
4.75
4.75
-
Typ.
5
±15
5
5
5
5
5
5
2
2
0
Max.
5.5
±15.5
5.4
0.8
5.4
0.8
5.4
0.4
5.4
0.4
5.4
0.4
5.4
0.4
-
Unit
V
(3) Pulse timing
The input pulse timing diagram for a recommended current-tovoltage conversion circuit is shown in Figure 6-3, along with
output pulse timing for the image sensor. The input/output pulse
timing conditions are also shown in Table 6-3.
Figure 6-3 Timing diagram for recommended current-to-voltage conversion circuit
MASTER CLOCK CLK
MASTER START Start
START
st
CLOCK
1
CLOCK
2
TRIG. Trigger
VIDEO OUTPUT Data Video
END OF SCAN EOS
KACCC0147EA
Table 6-3 Pulse timing conditions for recommended current-to-voltage conversion circuit
Input
Output
Output
for
image
sensor
32
Parameter
Mater start pulse φms width
Mater start pulse φms rise time / fall time
Master clock pulse φmc width
Master clock pulse φmc rise time / fall time
Master clock frequency
End of scan pulse width
End of scan pulse rise time / fall time
Trigger pulse width
Trigger pulse rise time / fall time
Start pulse φst width
Start pulse φst rise time / fall time
Clock pulse φ1, φ2 width
Clock pulse φ1, φ2 rise time / fall time
Symbol
tpwφms
tfφms, tfφms
tpwφmc
tfφmc, tfφmc
fφmc
tpweos
treos, tfeos
tpwtrig
trtrig, tftrig
tpwφs
trφs, tfφs
tpwφ1, tpwφ2
trφ1, tfφ1, trφ2, tfφ2
Min.
1/fφmc
30
-
Typ.
2/fφmc
3/fφmc
2/fφmc
2/fφmc
-
Max.
500
500
8
100
100
100
100
Unit
s
ns
MHz
s
ns
s
ns
s
ns
s
ns
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
The clock pulses φ1 and φ2 for the sensor have a duty ratio of 50
%, so are complementary to each other. Both pulses are set to
high level with a pulse width equal to two cycles of the master
clock pulse. The 1:1 pulse ratio is most suitable when operating
an image sensor at the maximum operating frequency because
the upper limit of shift register operation is determined by the
clock pulse width.
The signal output is obtained in synchronization with the φ2
timing. The timings of the start pulse φst and clock pulses φ1 and
φ2 are also shown in Figure 6-3.
The data acquisition timing for A/D conversion in this driver circuit is set at a point one master clock pulse cycle after the signal
output, and is also used for peak-hold processing of the differential waveform by using an external circuit. This timing diagram is also shown in Figure 6-3.
The end-of-scan signal is output in synchronization with the φ2
timing immediately after the last pixel is read out.
A saturated output is shown in Figure 6-4.
○
The input pulses to the image sensor are supplied from the PLD
at regular cycles, in minimum units of one cycle of the master
clock pulse φmc.
The start pulse φst for the image sensor is produced in synchronization with the fall of the master start pulse φms, with a duration equal to two cycles of the master clock pulse φmc. Thus the
master start pulse interval corresponds to the signal integration
time, which is the reciprocal of the master start pulse frequency
fφms, that is, 1/fφms (s). To ensure stable start operation, the
master start pulse width tpwφms should be longer than the master clock pulse width tpwφmc of one cycle, and also they should
be synchronized.
This driver circuit reads out one pixel in a duration equal to 4
cycles of the master clock pulse φmc. (One pixel may also be
read out in a duration equal to one cycle or two cycles if the duty
ratio of the clock pulses φ1 and φ2 is 50 %.) Therefore, all pulses
other than the start pulse are generated at this cycle to produce
the time-series output signal of each pixel. This means that the
output signal readout frequency is 1/4th of the master clock
pulse frequency fφmc.
○
Characteristic and use of NMOS linear image sensors
Figure 6-4 Output of recommended current-to-voltage conversion circuit (saturated output)
(b) Enlarged view near EOS pulse
○
○
○
○
○
Figure 6-5 Wiring example (recommended current-tovoltage conversion circuit)
DC POWER
SUPPLY
OSCILLOSCOPE
○
○
○
○
○
○
GND
EXT. TRIGGER
INPUT
-15 V
GND
+15 V
GND
+5 V
PULSE
GENERATOR
St.
GND
CLK
GND
Trig.
GND
CH1
GND
GND
Video
ANALOG INPUT
GND
S/H, A/D
CONVERSION
S/H INPUT
GND
KACCC0148EA
○
○
○
○
○
○
○
○
○
○
○
○
○
○
NMOS
LINEAR
IMAGE
SENSOR
○
(4) Connection
Figure 6-5 shows a wiring example for this driver circuit and
peripheral devices. The power supplies (+5 V, ±15 V) should
be connected to their respective power input terminals of the
circuit, and the master start and master clock pulses from the
pulse generator should be input to the St and CLK input terminals. The St terminal is also connected to the external trigger
input terminal of the oscilloscope and the data video output
(Video) is input to the oscilloscope. The trigger output terminal
(Trig) and data video output terminal (Video) of this circuit
should be connected respectively to the timing input terminal
and analog input terminal of the S/H and A/D conversion circuit.
○
○
○
(a) Saturated output
33
Characteristic and use of NMOS linear image sensors
○
nals. The control signal generator also provides a trigger signal
for external sample-and-hold and outputs it via a buffer. These
signals are synchronized with an external master clock pulse,
and are initialized by an external master start pulse. The master
clock and master start pulses are input to the PLD via a buffer.
The video signal processor can be divided into four sections.
The first stage integrates the video output signal from the image
sensor. The non-inverting input terminal of this first stage is applied at a video bias voltage of 2 V. A reset switch is added in
○
○
○
(5) Caution points
If operation is abnormal, check the following points.
○
○
○
○
○
○
○
○
○
○
○
○
(a) Are correct voltages (+5 V, ±15 V) being supplied to the
circuit board?
(b) Are the specified master clock and master start pulses
input to the circuit board?
(c) Are the clock pulses φ1, φ2 and start pulse φst being
supplied to the image sensor socket pins?
(d) Is the end-of-scan (EOS) signal being output?
Figure 6-6 Block diagram of recommended external
current-integration circuit
○
○
6-1-2. External current-integration method
○
○
○
○
(1) Recommended circuit configuration
This circuit basically consists of a control signal generator and a
video signal processor. Figures 6-6 and 6-7 show the block
diagram and circuit diagram of a recommended circuit. The
control signal generator produces control pulses needed for the
image sensor and signal processor. The video signal processor
performs current integration, amplification and DC restoration,
then outputs the processed signal. By applying external supply
voltages for digital and analog circuitry, and also master clock
and master start pulses, this driver circuit provides a data video
output, monitor video output, trigger pulse and end-of-scan
(EOS) pulse. Table 6-4 gives a description of the input/output
terminals.
The control signal generator consists of a PLD (programmable
logic device), and generates a start pulse and two-phase clock
pulses to operate the shift register as well as signals to reset the
current-integration circuit for output signal processing, clamp
signals for DC restoration, and switching noise cancellation sig-
D. GND
CONTROL SIGNAL GENERATOR
BUFFER
PLD
BUFFER
Start, CLK
EOS, Trigger
○
○
○
○
st
1, 2
VCC
VIDEO SIGNAL PROCESSOR
○
○
EOS
○
RESET
○
○
VIDEO
SENSOR
Buf
Data Video
○
○
Amp
CLAMP
○
○
○
○
○
C-V
A. GND
○
○
+2 V
○
+15 V
○
○
-15 V
○
○
VOLTAGE REGULATOR
○
KACCC0149EA
Figure 6-7 Recommended external current-integration circuit
VCC
1k
0.1 µF
2
4
6
8
Y1
Y2
Y3
Y4
A1
A2
A3
A4
1
VCC
G
74VHCT244AFT
IO
IO
IO
IO
IO
VCC
GND
IO
IO
IO
IO
IO
IO
GND
IN/GCLK
IN/OE1
IN/GCLRn
IN/OE2/GCLK2
VCC
IO
IO
IO
1000 pF
10 µF/25 V
1000 pF
1
RESET
TRIG
P2
VCC
1k
11
13
15
17
A1
A2
A3
A4
19
G
10 k
+15
OUT
3.9 k
6
0.01 µF 100
5
7
- 2
+ 3
+15
0.1 µF
2
10 pF
0.1 µF
0.1 µF
- 2
+ 3
VR1
10 k
5 pF
U102B
11
13
15
17
A1
A2
A3
A4
19
G
Y1
Y2
Y3
Y4
9
7
5
3
74VHCT244AFT
5
4
0.1 µF
8
1k
-15
1
6
7
SWITCH
910
1
4
IN
1
4
- 2
+ 3
5
7
6
-15
CONT
3
3 pF
3
1.6 k
OUT
-15
VCC
VR2
10 k
5.1 k
330 pF
DATA VIDEO
0.1 µF
IN
0.1 µF
100
22
21
20
19
18
17
16
15
14
13
12
NC
CLK2
NC
CLK1
NC
ST
NC
VSS
NC
VSCG
NC
NC
NC
VSCD
NC
VSS
NC
ACTIVE VIDEO
NC
DUMMY VIDEO
EOS
VSUB
1k
SWITCH
330 pF
1
2
3
4
5
6
7
8
9
10
11
S390X SERIES
100 k
8
9
7
5
3
VCC
1k
1000 pF
15
Y1
Y2
Y3
Y4
74VHCT244AFT
100
10 µF/25 V
0.22 µ 0.22 µ 0.22 µ 0.22 µF
G
74VHCT244AFT
P1
PST
VCC
VCC
VCC
18
16
14
12
1
-15
VCC
10 µF/25 V
CLAMP
CONT
+15
22
21
20
19
18
17
16
15
14
13
12
PLD
1
2
3
4
5
6
7
8
9
10
11
TRIGGER
N_EOS
34
35
36
37
38
39
40
41
42
43
44
Y1
Y2
Y3
Y4
2
START
CLK
18
16
14
12
IO
TDO
IO
IO
VCC
IO
IO
TCK
IO
GND
IO
PST
P1
0.1 µF
2
4
6
8
TDI
IO
IO
GND
IO
IO
TMS
IO
VCC
IO
IO
VCC
A1
A2
A3
A4
1
VCC
1k
33
32
31
30
29
28
27
26
25
24
23
VCC
+15 Monitor Video
+15
R11
100
0.1 µF
C13
2 k 13 k
+15
0.1 µF
KACCC0150EA
34
Characteristic and use of NMOS linear image sensors
Table 6-4 Input/output terminal description of recommended external current-integration circuit
Terminal name
Function
+5
-
+5 V, 70 mA
+15
-15
-
Master start pulse φms
START
Positive
CLK
Positive
G
M.V
D.V
Trig.
Positive
Positive
Positive
EOS
Negative
+15 V, 30 mA
-15 V, 30 mA
Initializes internally generated pulse; C-MOS logic
compatible.
Synchronizes internally generated pulse; CMOS logic
compatible.
Ground
Output for noise cancel and adjustment
Low noise, final video output
A/D conversion timing signal; CMOS logic compatible.
End-of-scan signal for shirt register; CMOS logic
compatible.
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
Note the following points when selecting circuit components.
(a) First-stage amplifier
As a first-stage amplifier, choose an amplifier having low
noise and less leaks while taking the switching speed
into account.
(b) Second-stage, third-stage amplifiers
Choose an amplifier that is resistant to load capacitance.
(c) Reset switch and clamp switch
Use an FET or analog switch with low ON resistance and
reset noise. Also take the signal voltage range into consideration.
○
○
○
○
○
○
○
○
○
○
(2) Supply voltage
Table 6-5 gives the recommended values for input supply voltage, input pulse amplitude voltage, output voltage and output
pulse amplitude voltage.
The input supply voltage Vcc for digital circuitry is +5 V, and ±Vs
for analog circuitry is ±15 V. The input pulses consist of a master clock pulse φmc and a master start pulse φms. These are
positive going pulses and their amplitude voltages Vmc and
Vms are both 5 V. The trigger pulse for external output is also a
positive going output while the end-of-scan pulse is a negative
going output. Their amplitude voltages Vtrig and Veos are also
5 V. The data video output from the last stage is obtained with
positive polarity with respect to ground, while the monitor video
output used for adjustment of switching noise cancellation is
available as a positive going signal with respect to approximately 2 V.
Voltages actually applied to the image sensor are as follows:
The amplitude of the clock pulses Vφ1 and Vφ2, and start pulse
Vφst are 5 V; the video bias voltage Vb that determines the
photodiode reset voltage is 2 V; the saturation control gate
voltage Vscg is 0 V; the saturation control drain voltage Vscd is
2 V which is equal to the video line bias voltage Vb. The Vss,
Vsub and NC terminals are all grounded. The dummy video
output is not used with this circuit, so the dummy video output
terminal is left open.
○
The end-of-scan (EOS) terminal is pulled up at 5 V, with a resistor of 10 kΩ. The end-of-scan signal appears synchronized with
the φ2 timing immediately after the last pixel is scanned, and is
available to an external device from the EOS terminal via a
buffer.
○
○
Vout [V] = 3 # Q [pC] / 10 [pF]
○
where Q is the output charge from the image sensor.
The second stage is a non-inverting amplifier with a gain of 3,
which also serves as a low-pass filter to eliminate high frequency noise. This output is a positive going signal with respect
to approximately 1 V, and is used as the monitor video output
when adjusting the switching noise cancellation. Next is a
clamping circuit consisting of a capacitor and a switching element for DC restoration of video signals. The clamping circuit
holds the output potential at ground level by turning on the
clamp switch for a certain period of time (clamp period) immediately after the integration capacitance is reset, so that the integration capacitance reset noise is eliminated. The clamping circuit eliminates random reset noise, while the first stage removes only fixed pattern switching noise. The output signal
from this stage then changes from the ground level to positive
polarity and enters the last stage. The last stage is a non-inverting amplifier with a gain of 1, also serving as a low-pass filter.
The output signal is then finally derived from the data video
terminal. If the output charge is Q (pC), then the output voltage
Vout (V) is given by
○
○
V [V] = Q [pC] / 10 [pF]
○
○
parallel to the integration capacitor of 10 pF, so that the capacitance is reset by a signal input to the reset switch each time a
pixel is read out. The first stage also cancels the switching noise
generating in synchronization with the clock pulses. The first
stage output V, which is a positive going, boxcar waveform output with respect to the 2 volt video bias, is given by
○
End-of-scan pulse
○
Master clock pulse
φmc
Ground
Monitor video
Data video
Trigger pulse
○
Supply voltage Vd (for
digital circuitry)
Supply voltage Va (for
analog circuitry)
○
Output
Polarity
○
Input
Symbol on
board
35
Characteristic and use of NMOS linear image sensors
Table 6-5 Input/outupt voltages for recommended current-to-voltage conversion circuit
Input or output voltage
Supply voltage for digital circuitry
Supply voltage for analog circuitry
Input
Symbol
Vd
Va
Vms (H)
Vms (L)
Vmc (H)
Vmc (L)
Vtrig (H)
Vtrig (L)
Veos (H)
Veos (L)
Vφs (H)
Vφs (L)
Vφ1, Vφ2 (H)
Vφ1, Vφ2 (L)
Vb
Vscd
Vscg
Mater start pulse φms
Master clock pulse φmc
Trigger pulse
Output
End-of-scan pulse
Start pulse φst
36
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
Typ.
5
±15
5
5
5
5
5
5
2
2
0
Max.
5.5
±15.5
5.4
0.8
5.4
0.8
5.4
0.4
5.4
0.4
5.4
0.4
5.4
0.4
-
Unit
V
in the output signal synchronized with the reset pulse φreset
and clock pulse φ2. Since this noise is fixed pattern noise, it can
be canceled out by injecting a charge equal to this noise component but in opposite phase, into the output signal component. More specifically, the inverted pulses of the reset pulse
φreset and clock pulse φ2 are fed to the inverting input terminal
of the integration amplifier via a CR coupled circuit. The amount
of charge injection is adjusted with a variable resistor.
The clamping circuit eliminates noise generated by the reset
switch in the integration amplifier as well as performing DC
restoration of the output signal. This random reset noise is
eliminated during the period between the end of reset operation for the integration capacitance and the signal output, in
other words, while φreset is low but φ2 is high. If this period is too
short, noise reduction may be insufficient. In this driver circuit,
this period corresponds to one cycle of the master clock pulse.
Data acquisition timing for A/D conversion is set at a point one
master clock pulse cycle after signal output. As Figure 6-6
shows, the trigger pulse for external output is set at this point, in
other words, set to rise at a point 1/2 of the φ2 high level. Therefore, the data is acquired in synchronization with the rise of the
trigger pulse.
The end-of-scan signal is output in synchronization with the φ2
timing immediately after the last pixel is read out.
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
(3) Pulse timing
The input/output pulse timing diagram for a recommended circuit is shown in Figure 6-8, along with output pulse timing for the
image sensor. Pulse timing conditions are also shown in Table
6-6.
The input pulses to the image sensor are supplied from the PLD
at regular cycles, with minimum units of one cycle of the master
clock pulse φmc.
The start pulse φst for the image sensor is produced in synchronization with the rise of the master start pulse φms, with a duration equal to two cycles of the master clock pulse φmc. Thus the
master start pulse interval corresponds to the signal integration
time, which is the reciprocal of the master start pulse frequency
fφms, that is, 1/fφms (s). To ensure stable start operation, the
master start pulse width tpwφms should be longer than the master clock pulse width tpwφmc of one cycle, and they also should
be synchronized.
This driver circuit is designed to read out one pixel in a duration
equal to 4 cycles of the master clock pulse φmc. Within this duration, the output signal readout, integration capacitance reset
and output potential clamping are performed. Therefore, all
pulses other than the start pulse are generated at this cycle to
produce the time-series output signal from each pixel. This
means that the output signal readout frequency is 1/4th of the
master clock pulse frequency fφmc. Taking account of the relation between the integration reset time, clamp period and other
characteristics, the maximum readout frequency for this driver
circuit is specified as 62.5 kHz.
The clock pulses φ1 and φ2 for the sensor are set to a high level
with pulse widths equal to two cycles of the master clock pulse.
The signal output is obtained in synchronization with the φ2
timing. The timings of the start pulse φst and clock pulses φ1 and
φ2 are shown in Figure 6-8.
Accompanying the on/off operations of address switches or integration capacitance reset switches, switching noise appears
○
Output for
Clock pulse φ1, φ2
image
sensor
Video bias voltage
Saturation control drain voltage
Saturation control gate voltage
Min.
4.85
±14.5
2
0
2
0
4.75
4.75
4.75
4.75
-
(4) Connection
Figure 6-9 shows a wiring example of this driver circuit and
peripheral devices. The power supplies (+5 V, ±15 V) should
be connected to the respective power input terminals of the
circuit, and the master start and master clock pulses from the
pulse generator should be input to the St and CLK input terminals. The St terminal should also be connected to the external
trigger input terminal of the oscilloscope. The data video output
terminal (D.V.) and monitor video output terminal (M.V.) of this
circuit should be connected to the input terminals (CH1, CH2)
Characteristic and use of NMOS linear image sensors
Figure 6-8 Timing diagram for recommended external current-integration conversion circuit
MASTER CLOCK CLK
MASTER START Start
START
st
CLOCK
1
CLOCK
2
RESET
CLAMP
TRIG. Trigger
VIDEO OUTPUT Data Video
END OF SCAN EOS
KACCC0151EA
Table 6-6 Pulse timing conditions for recommended external-current integration circuit
Symbol
tpwφms
trφms, tfφms
tpwφmc
trφmc, tfφmc
fφmc
tpweos
treos, tfeos
tpwtrig
trtrig, tftrig
tpwφs
trφs, tfφs
tpwφ1
tpwφ2
trφ1, tfφ1, trφ2, tfφ2
Min.
1/fφmc
30
-
Typ.
2/fφmc
1/fφmc
2/fφmc
2/fφmc
2/fφmc
-
Max.
500
500
375
100
100
100
100
Unit
s
ns
kHz
s
ns
s
ns
s
ns
s
ns
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DC POWER
SUPPLY
-15 V
GND
+15 V
GND
+5 V
○
GND
○
M. V.
PULSE
GENERATOR
St.
GND
CLK
GND
Trig.
GND
GND
D. V.
ANALOG INPUT
GND
S/H, A/D
CONVERSION
S/H INPUT
GND
KACCC0152EA
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NMOS
LINEAR
IMAGE
SENSOR
GND
EXT. TRIGGER
INPUT
CH2
GND
OSCILLOSCOPE
CH1
GND
○
(5) Adjusting switching noise cancellation
As explained in the previous section “(3) Pulse timing” the
switching noise appearing in the output can be canceled out by
introducing φreset and φ2 at the inverting input terminal of the
integration amplifier via a CR coupled circuit.
To make adjustment, first operate the image sensor under dark
conditions and then observe the monitor video output on the
oscilloscope. The monitor video output is a positive going signal with respect to 2 V, so switch the oscilloscope input selector
to AC. In this state, adjust the variable resistors VR1 and VR2
shown in the circuit diagram of Figure 6-7 until switching noise
synchronized with φreset and φ2 is minimized. The photographs
in Figure 6-10 show the switching noise adjustment and saturated output state as displayed on the oscilloscope.
Figure 6-9 Wiring example (recommended external current
integration circuit)
○
○
of the oscilloscope. The trigger output terminal (Trig) and data
video output terminal (D.V.) of this circuit should be connected
to the timing input terminal and analog input terminal of the S/H
and A/D conversion circuit, respectively.
After all connections are complete, turn on the power to each
device.
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○
○
Parameter
Mater start pulse φms width
Mater start pulse φms rise time / fall time
Input
Master clock pulse φmc width
Master clock pulse φmc rise time / fall time
Master clock frequency
End of scan pulse width
End of scan pulse rise time / fall time
Output
Trigger pulse width
Trigger pulse rise time / fall time
Start pulse φst width
Start pulse φst rise time / fall time
Output
for image Clock pulse φ1 width
sensor
Clock pulse φ2 width
Clock pulse φ1, φ2 rise time / fall time
37
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(d) After VR2 adjustment
(e) Saturated output
(f) Enlarged view near EOS pulse
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(c) Before VR2 adjustment
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(b) After VR1 adjustment
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(a) Before VR1 adjustment
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Figure 6-10 Adjustment and saturated output of
external current-integration circuit
○
Characteristic and use of NMOS linear image sensors
38
(6) Caution items
If operation is abnormal, check the following points.
(a) Are correct voltages (+5 V, ±15 V) supplied to the circuit
board?
(b) Are the specified master clock and master start pulses
input to the circuit board?
(c) Are the clock pulses φ1, φ2 and start pulse φst being supplied to the image sensor socket pins?
(d) Is the end-of-scan (EOS) signal being output?
○
Characteristic and use of NMOS linear image sensors
to the non-inverting terminal of the first-stage amplifier. However, the image sensor provides a negative going, boxcar
waveform output with respect to a certain positive potential. The
output signal must therefore be transformed into a signal with
positive polarity with respect to ground, in order to make signal
processing easy by an external circuit. In this driver circuit, the
video signal is next fed to the inverting input terminal of the
second-stage amplifier while the non-inverting input terminal is
biased at a positive potential. The offset can be compensated
by adjusting this bias voltage, and the output will be a positive
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6-2. Driver circuit for voltage output type image
sensor
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(1) Circuit configuration
This type of driver circuit basically consists of a control signal
generator and a video signal processor. Figures 6-11 and 6-12
show the block diagram and circuit diagram of a recommended
driver circuit. The control signal generator produces various
control pulses required for the image sensor and external signal processor. The video signal processor performs inverting
amplification and DC restoration of the image sensor video signal and then outputs the processed signal. By applying external
supply voltages for digital and analog circuitry, and also master
clock and master start pulses, this driver circuit provides a data
video output, trigger pulse and end-of-scan (EOS) pulse. Table
6-7 gives a description of the input/output terminals.
The control signal generator consists of a PLD (programmable
logic device), and generates a start pulse and two-phase clock
pulses to operate the shift register and also a reset signal for
internal signal processing. The control signal generator also
provides a trigger signal for external sample-and-hold and outputs it via a buffer. These signals are synchronized with an external master clock pulse, and are initialized by an external
master start pulse. The master clock and master start pulses are
input to the PLD via a buffer.
The video signal processor consists of a non-inverting amplifier
and an inverting amplifier. Image sensors to be used with this
driver circuit incorporate a signal processing circuit comprised
of a current integration circuit utilizing video line capacitance
and an impedance conversion circuit. If a load (resistance or
capacitance) is added to the sensor video line, stable sensor
operation cannot be maintained, so this signal should be input
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Figure 6-11 Block diagram of driver circuit for voltage
output type image sensor
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TIMING SIGNAL GENERATOR
BUFFER
D. GND
PLD
BUFFER
Start, CLK
EOS, Trigger
○
○
○
○
st, rst
1, 2
VCC
VIDEO SIGNAL PROCESSOR
○
○
○
○
○
EOS
○
VIDEO
AMP
AMP
Data Video
○
○
○
○
○
○
○
SENSOR
A. GND
○
+2.5 V
○
○
+15 V
-15 V
○
○
○
VOLTAGE REGULATOR
○
○
○
KACCC0153EA
Figure 6-12 Recommended driver circuit for voltage output type image sensor
VCC
VCC
1k
TRIG
1k
10 k
33 P1
32
31
30
29
28
27
26
25
24
23
VCC
G
A4
A3
A2
A1
Y4
Y3
Y2
Y1
12
14
16
18
74VHCT244AF
RESET 34
PST
35
36
37
38
39
40
41
VCC
42
43
44
IO
IO
GND
IN3/CLK3
IN2/CLK2
IN1/CLK1
IN0/CLK0
VCC
IO
IO
IO
PST
P1
P2
RESET
22
21
20
19
18
17
16
15
14
13
12
IO
IO
IO
IO
IO
VCC
GND
IO
IO
IO
IO
1
2
3
4
5
6
7
8
9
10
11
TRIGGER
N_EOS
8
6
4
2
TDI
IO
IO
GND
IO
IO
TMS
IO
VCC
IO
IO
0.1 µF
1
CLK
START
19
IO
TDO
IO
IO
VCC
IO
IO
TCK
IO
GND
IO
VCC
VCC
17
15
13
11
A4
A3
A2
A1
Y4
Y3
Y2
Y1
3
5
7
9
74VHCT244AF
0.1 µF
PLD
0.22 µF 0.22 µF
VCC
VCC
VCC
+15
-15
VCC
10 µF/25 V
1000 pF
10 µF/25 V
1000 pF
1k
2k
10 k
CLK2
NC
CLK1
NC
ST
NC
VSS
NC
VSCG
NC
RESET
NC
VSCD
NC
VSS
NC
ACTIVE VIDEO
NC
DUMMY VIDEO EOS
VDD
VSUB
22
21
20
19
18
17
16
15
14
13
12
VCC
S392X SERIES
0.1 µF
+15
VCC
1k
0.22 µF 0.22 µF
1000 pF
2k
2 pF
2 pF
10 µF/25 V
1
2
3
4
5
6
7
8
9
10
11
G
10 k
10 k
-15
4
0.1 µF
3
15
1
6
+ 5
+15
1
2
+ 3
10 k
8
7
DATA VIDEO
0.1 µF
2
0.1 µF
+15
5.1 k
KACCC0154EA
39
Characteristic and use of NMOS linear image sensors
Table 6-7 Input/output terminal description of driver circuit for voltage output type image sensors
Terminal name
Input
Polarity
+5
-
Supply voltage Vd
(for digital circuitry)
Supply voltage Va
(for analog circuitry)
Master start pulse φms
+15
-15
START
Master clock pulse φmc
CLK
Ground
Video
Trigger pulse
End-of-scan pulse
G
Video
Trig.
EOS
Function
+5 V, 70 mA
+15 V, 30 mA
-15 V, 30 mA
Positive Initializes internally generated pulse; C-MOS logic compatible.
Synchronies internally generated pulse; CMOS logic
Positive
compatible.
Ground.
Positive Video output.
Positive A/D conversion timing signal; CMOS logic compatible.
Negative End-of-scan signal for shirt register; CMOS logic compatible.
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(2) Supply voltage
Table 6-8 shows the recommended values of input supply voltage, input pulse amplitude voltage, output voltage and output
pulse amplitude voltage.
The input supply voltage Vd for digital circuitry is +5 V, and Va
for analog circuitry is ±15 V. The input pulses consist of a master
clock pulse φmc and a master start pulse φms. These are positive going outputs and their amplitude voltages Vmc and Vms
are both 5 V. The trigger pulse for external output is a positive
going output while the end-of-scan pulse is a negative going
output. Their amplitude voltages Vtrig and Veos are also 5 V.
The final data video output obtained has a positive polarity with
respect to the ground.
○
signal with respect to ground. The output signal is amplified 6
times by these two amplifiers and derived from the video output
terminal.
The end-of-scan (EOS) terminal is pulled up at 5 V, with a resistor of 10 kΩ. The end-of-scan signal appears synchronized
with the φ2 timing immediately after the last pixel is scanned,
and is available for an external device from the EOS terminal
via the buffer.
Note the following points when selecting amplifiers.
(a) Non-inverting amplifier
Choose a high-speed operational amplifier with low
noise.
(b) Inverting amplifier
Choose a high-speed operational amplifier that is resistant to load capacitance.
○
○
Output
Symbol on
board
Table 6-8 Input/output voltages for recommended driver circuit designed for voltage output type image sensors
Input or output voltage
Supply voltage for digital circuitry
Supply voltage for analog circuitry
Input
Mater start pulse φms
Master clock pulse φmc
Trigger pulse
Output
End-of-scan pulse
Start pulse φst
Clock pulse φ1, φ2
Output for
Reset pulse φr
image
sensor
Reset voltage
Saturation control drain voltage
Saturation control gate voltage
Internal output processing circuit drain
voltage
40
Symbol
Vd
Va
Vms (H)
Vms (L)
Vmc (H)
Vmc (L)
Vtrig (H)
Vtrig (L)
Veos (H)
Veos (L)
Vs (H)
Vs (L)
Vφ1, Vφ2 (H)
Vφ1, Vφ2 (L)
Vr (H)
Vr (L)
Vr
Vscd
Vscg
Min.
4.85
±14.5
2
0
2
0
4.75
4.75
4.75
4.75
4.75
-
Typ.
5
±15
5
5
5
5
5
5
5
2.5
2.5
0
Max.
5.5
±15.5
5.4
0.8
5.4
0.8
5.4
0.4
5.4
0.4
5.4
0.4
5.4
0.4
5.4
0.4
-
Vdd
-
5
-
Unit
V
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(3) Pulse timing
The input/output pulse timing diagram for this driver circuit is
shown in Figure 6-13, along with its output pulse timing for the
image sensor. The pulse timing conditions are listed in Table 69.
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Voltages actually applied to the image sensor are as follows:
The amplitude of the clock pulses Vφ1 and Vφ2, start pulse Vφst,
and reset pulse Vφr are 5 V; the reset voltage Vr that determines
the photodiode reset potential is 2.5 V; the saturation control
gate voltage Vscg is 0 V; the saturation control drain voltage
Vscd is 2.5 V which is equal to the reset voltage Vr; the supply
voltage Vdd for the drain of the internal signal processor is 5 V.
The Vss, Vsub and NC terminals are all grounded. The dummy
video output is not used with this circuit, so the dummy video
output terminal is left open.
○
Characteristic and use of NMOS linear image sensors
The input pulses to the image sensor are supplied from the PLD
at regular cycles, with minimum units of one cycle of the master
clock pulse φmc. The start pulse φst for the image sensor is
produced in synchronization with the fall of the master start
pulse φms, with a duration equal to two cycles of the master
clock pulse φmc. Thus the master start pulse interval corresponds to the signal integration time, which is the reciprocal of
the master start pulse frequency fφms, that is 1/fφms (s). To ensure stable start operation, the master start pulse width tpwφms
should be longer than the master clock pulse width tpwφmc of
one cycle.
This driver circuit is designed to read out one pixel in a period
equal to 6 cycles of the master clock pulse φmc. Both the readout for one pixel and the reset for the photodiode and video line
are performed in this period. For this reason, all pulses other
Figure 6-13 Timing diagram of recommended driver circuit for voltage output type image sensor
MASTER CLOCK CLK
MASTER START Start
START
st
CLOCK
1
CLOCK
2
RESET
CLAMP
TRIG. Trigger
VIDEO OUTPUT Data Video
END OF SCAN EOS
KACCC0155EA
Table 6-9 Pulse timing conditions for recommended driver circuit for voltage output type image sensor
Parameter
Mater start pulse φms width
Mater start pulse φms rise time / fall time
Input
Master clock pulse φmc width
Master clock pulse φmc rise time / fall time
Master clock frequency
End of scan pulse width
End of scan pulse rise time / fall time
Output
Trigger pulse width
Trigger pulse rise time / fall time
Start pulse φst width
Start pulse φst rise time / fall time
Clock pulse φ1 width
Clock pulse φ2 width
Output
Clock pulse φ1, φ2 rise time / fall time
for image
Reset pulse φr width
sensor
Reset pulse φr rise time / fall time
Reset pulse φ2 overlap times
Reset pulse rise time to φ2 fall time
difference
Symbol
tpwφms
trφms, tfφms
tpwφmc
trφmc, tfφmc
fφmc
tpweos
treos, tfeos
tpwtrig
trtrig, tftrig
tpwφs
trφs, tfφs
tpwφ1
tpwφ2
trφ1, tfφ1, trφ2, tfφ2
tpwφr
trφr, tfφr
tφovr
Min.
1/fφmc
30
-
Typ.
4/fφmc
3/fφmc
2/fφmc
2/fφmc
4/fφmc
3/fφmc
2/fφmc
Max.
500
500
3
100
100
100
100
100
-
tdφ-2
-
1/fφmc
-
Unit
s
ns
MHz
s
ns
s
ns
s
ns
s
ns
s
ns
41
(4) Connections
Figure 6-14 shows a wiring example for this driver circuit and
peripheral devices. The power supplies (+5 V, ±15 V) should be
connected to their respective power input terminals of the circuit, and the master start and master clock pulses from the pulse
generator should be input to the St and CLK input terminals.
The St terminal is also connected to the external trigger input
terminal of the oscilloscope and the data video output (Video) is
input to the oscilloscope. The trigger output terminal (Trig) and
data video output terminal (Video) of this circuit should be connected respectively to the timing input terminal and analog input terminal of the S/H and A/D conversion circuit.
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put is set to rise at a point 1/4th of the φ2 high level. Data is
therefore acquired in synchronization with the rise of the trigger
pulse.
The end-of-scan signal is output in synchronization with the φ2
timing immediately after the last pixel is read out.
(5) Adjusting the output offset level
As explained in the previous section “(1) Circuit configuration”,
the video output offset level can be adjusted by varying the
voltage applied to the non-inverting input terminal of the inverting amplifier. This adjustment is made by using a variable resistor shown in the recommended driver circuit diagram.
To make this adjustment, first operate the image sensor under
dark conditions and then observe the video output on the oscilloscope. Adjust the variable resistor so that the output level
during the φ2 high and φr low levels are set to ground level as
shown in oscilloscope photographs of Figure 6-15.
○
than the start pulse are generated at this cycle to produce the
time-series output signal of each pixel. This means that the
output signal readout frequency is 1/6th of the master clock
pulse frequency fφmc. Taking account of the relation between
the photodiode reset time and other characteristics, the maximum readout frequency for this driver circuit is specified as 500
kHz.
The clock pulses φ1 and φ2 are in a complementary relation.
Both pulses are set to a high level with a pulse width respectively equal to two and four cycles of the master clock pulse. The
signal output is obtained in synchronization with the φ2 timing.
The timing of the start pulse φst and clock pulses φ1 and φ2 are
also shown in Figure 6-13.
The photodiode potential is reset by simultaneously turning on
the address switch and the reset switch for internal signal processing circuit so that the photodiode potential is set equal to
the reset voltage Vr. Since the address switch operates synchronized with the clock pulse φ2, the reset pulse φr must overlap with φ2. In this driver circuit operation, the reset pulse φr sets
to high level for a period equal to three cycles of the master
clock pulse and the two cycles of them are overlapped with φ2.
To maintain the photodiode reset potential at a constant value,
the reset pulse φr falls one master clock cycle earlier than the
rise of φ2. The timing diagram of reset pulse φr is also shown in
Figure 6-13. The video output signal is obtained between the
rise of φ2 and the rise of φr.
Data acquisition timing for A/D conversion in this driver circuit is
set at a point one master clock pulse cycle after the signal output. As shown in Figure 6-13, the trigger pulse for external out-
○
Characteristic and use of NMOS linear image sensors
Figure 6-14 Wiring example (recommended driver circuit for voltage output type)
DC POWER
SUPPLY
-15 V
GND
+15 V
GND
+5 V
Video
GND
NMOS
LINEAR
IMAGE
SENSOR
PULSE
GENERATOR
St.
GND
CLK
GND
Trig.
GND
GND
EXT. TRIGGER
INPUT
OSCILLOSCOPE
CH1
GND
ANALOG INPUT
GND
S/H, A/D
CONVERSION
S/H INPUT
GND
KACCC0156EA
42
○
○
(d) Enlarged view near EOS pulse
(6) Caution points
If operation is abnormal, check the following points.
(1) Are correct voltages (+5 V, ±15 V) being supplied to the
circuit board?
(2) Are the specified master clock and master start pulses
input to the circuit board?
(3) Are the clock pulses φ1, φ2 and start pulse φst being supplied to the image sensor socket pins?
(4) Is the end-of-scan (EOS) signal being output?
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(c) Saturated output
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(b) After offset adjustment
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(a) Before offset adjustment
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Figure 6-15 Offset adjustment and saturated output of
driver circuit for voltage output type sensor
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Characteristic and use of NMOS linear image sensors
43
Characteristic and use of NMOS linear image sensors
PLD and also determines the image sensor operating time
(data rate).
Figure 6-17 shows timing diagrams for the master clock and
master start pulses. The master start pulse width is set twice as
long as the master clock pulse width.
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(2) Master clock pulse setting
To set the master clock pulse, use the rotary switch SW-CLK.
The original clock frequency is divided by the PLD.
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(3) Master start pulse interval setting
To set the master clock pulse interval, use the rotary switch SWSTART and slide switch SW-125.
This master start pulse interval corresponds to the integration
time. Since integration time = X 510Y (s), the PLD should be
programmed so that X can be set with SW-125 and Y with SWSTART.
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(1) Circuit configuration
Figure 6-16 shows the circuit diagram of a recommended pulse
generator. By applying an external supply voltage of 5 V (30
mA), this pulse generator provides a master clock pulse and
master start pulse outputs. Since a crystal oscillator is used as
master clock, highly accurate pulse signals can be obtained.
The master start pulse initializes the driver circuit and determines the integration time of the image sensor. The master
clock pulse becomes a minimum pulse unit originated in the
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○
Hamamatsu provides C8225 pulse generator that can be used
with either the current output type or voltage output type driver
circuit. C8225 generates a master clock pulse and master start
pulse by applying an external 5 V. The pulse frequency can be
preset within an optimum range.
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○
○
6-3. Pulse generator
Figure 6-16 Recommended pulse generator circuit
CLK
VCC
OPEN (32 MHz)
VCC
R1
10 k
R2
10 k
R3
10 k
4
COM
COM
8
4
2
1
START2
START4
TMS
START8
R4
10 k
CLK8
CLK4
CLK2
CLK1
2
1
6
5
1k
R6
10 k
R7
10 k
R8
10 k
VCC
4
COM
COM
8
4
2
1
1
2
3
4
5
6
7
8
9
10
11
TDI
IO
IO
GND
IO
IO
TMS
IO
VCC
IO
IO
IO
TDO
IO
IO
VCC
IO
IO
TCK
IO
GND
IO
33
32
31
30
29
28
27
26
25
24
23
VCC
TCK
1k
1
2
PLD
1
2
10 µF
4
MSTART
TC7SET32F
4
MCLK
OUT
VCC
TC7SET32F
START8
START4
START2
START1
2
1
6
5
R9
10 k
VCC
1000 pF
X5
SW-START
3
VCC
X1
X2
VCC
R5
10 k
VCC
1k
TD1
CLK8
START1
SW-CLK
3
CLK
CLK1
CLK2
CLK4
VCC
44
43
42
41
40
39
38
37
36
35
34
3
1
VCC JP3
32 MHz (24 MHz)
0 -01
4 VCC
3 OUT
OUT
2 GND
1 VCC
OE
OE
IO
IO
IO
VCC
IN0/CLK0
IN1/CLK1
IN2/CLK2
IN3/CLK3
GND
IO
IO
OUT
GND
IO
IO
IO
IO
GND
VCC
IO
IO
IO
IO
IO
VCC
12
13
14
15
16
17
18
19
20
21
22
4
2
VCC
R10
10 k
VCC
R11
10 k
X1
X2
X5
VCC
0.1 µF 0.1 µF 0.1 µF 0.1 µF 0.22 µF 0.22 µF 0.22 µF 0.22 µF
KACCC0157EA
Figure 6-17 Timing diagram for recommended pulse generator circuit
MASTER CLOCK MCLK
MASTER START MStart
KACCC0126EA
44
Characteristic and use of NMOS linear image sensors
7. Standard driver circuits
Hamamatsu offers various types of driver circuits specifically
designed to operate NMOS linear image sensors as shown in
Table 7-1. Hamamatsu also provides C8225 pulse generator
for use with these driver circuits, as well as A8226 cable for
connection to C7884 driver circuits.
Table 7-1 Driver circuits for NMOS linear image sensors
Type
Circuit configuration
External current
integration method
C7884/-01,
C7884G/-01
Multichannel detector head
Non-cooled
Non-cooled
type with
Cooled type
type
square housing
C8892
C7884-20/-21
C5964 series
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
(1) Board type
This board type driver circuit is designed so that an image sensor can be mounted in the center of the board. Since the board
is compact and easy to use, it can be used not only in image
sensor evaluation but also in actual applications when installed into equipment.
○
○
○
○
○
(2) Non-cooled multichannel detector head
This is a driver circuit assembled into a compact detector head
with a square or circular configuration. The square type uses
C7884 or C7884-01 driver circuit board. The circular type has a
circular flange (approximately φ8 cm diameter bolt circle) for
connection to a monochromator and the depth is as short as
less than 40 mm. Both the square and circular types have the
same connector pin arrangement. (Note: This pin arrangement
differs from C7884 and C7884-01.)
The case of each detector head has shielding effects against
external noise and an optical axis alignment function for image
sensor. The signal input from, or output to external devices can
be handled through the single connector located on the rear of
the case, allowing easy handling.
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
(3) Cooled multichannel detector head
This multichannel detector head has a temperature control circuit and heat radiating fins to maintain sensor temperature at 0
°C. Cooling the image senor reduces its dark current and allows an extended time for integrating signal charge.
○
Hamamatsu provides three types of driver circuits with different
functions: board type, cooled multichannel detector head and
non-cooled multichannel detector head. Their outline drawings
are shown in Figure 7-1.
○
○
7-2. Driver circuit functions
○
○
○
C8892, C5964 series)
These circuits perform integration of video output current, offset
cancellation, signal amplification and noise elimination with a
clamping circuit.
○
(1) Current output/current integration type (C7884 series,
○
○
Hamamatsu provides two types of driver circuits for current output type NMOS image sensors (S3901 to S3904, S8380, S8381
series): a current-to-voltage conversion type and a current integration type. Hamamatsu also provides one type of driver circuit
for voltage output type NMOS image sensors.
The driver circuit basically consists of a pulse generator and a
signal processor. The pulse generator produces start pulses
and two-phase clock pulses necessary to drive the image sensor by input of external master clock and master start pulses. It
also outputs trigger pulses for data acquisition. The signal processor performs the signal processing necessary for video output of the image sensor, as described below.
○
○
7-1. Driver circuit configurations
○
○
Current output type
Driver circuit
board type No.
45
Characteristic and use of NMOS linear image sensors
Figure 7-1 Dimensional outlines (Unit: mm)
(a) C7884/-05
(4 ×) C3
63.5
2
1
16
15
50.8
7.62
(2 ×) 3.6
7.62
7.62
55.88
KACCA0086EA
(b) C7884G/-01
(4 ×) C3
1.6
10.0
1.6
25.4
63.5
25.4
7.62
(2 ×) 3.6
7.62
7.62
55.88
KACCA0106EA
46
Characteristic and use of NMOS linear image sensors
(c) C8892
NMOS LINEAR IMAGE SENSOR
(OPTION)
33.0
45˚
2.0
86.0
72.0
78PCD
(4 ×) 3.3
DRIVER CIRCUIT
BOARD
SIGNAL
CONNECTOR
FLANGE
OFFSET
ADJUSTER
TRIMMER
FOCUS ADJUSTER DIAL
HOUSING CASE
(INCLUDING FLANGE)
FRONT VIEW
SIDE VIEW
REAR VIEW
The focal position can be adjusted backward within the range
from 0 to 4.5 mm (circuit stroke length) with a focal adjustment dial.
WEIGHT: approx. 0.16 kg
KACCA0113EA
(d) C7884-20, C7884-21
75.0
(4 ×) C7
25.0
(8 ×) R3
0
65.0
14.0
75.0
45.
D-SUB 15 PIN
SOCKET TYPE
90PCD
(4 ×) 3.5 THROUGH-HOLE
46.0
(2 ×) M3
EFFECTIVE LENGTH 10
KACCA0112EA
47
Characteristic and use of NMOS linear image sensors
(g) C5964 series
49.0
(4 ×) M3
DEPTH 9
80.0
115
94.0
40.0
FOCAL LENGTH 7.0 ± 0.5
KACCA0053EA
(h) C8225 series
(4 ×) C3
25.4
29.21
3.6
MOUNT FOR
C7883/C7884/C7885 SERIES
7.62
7.62
63.5
3.81
7.62
(4 ×)
55.88
MOUNT FOR
C7883/C7884/C7885 SERIES
KACCA0087EA
48
Characteristic and use of NMOS linear image sensors
7-3. External current-integration circuit C7884 series for current-output image sensor
7-3-1. Product lineup
Product name
Type No.
C7884
C7884G
Driver circuit
C7884-01
C7884G-01
Detector head
C7884-20
C7884-21
Pulse generator
C8225-01
Cable
A8226
7-3-2. Specifications
■ Absolute maximum ratings
Parameter
Positive supply voltage
Negative supply voltage
Operating temperature
Storage temperature
Features
Low noise
Superior output linearity
Boxcar waveform output
C7884 + C8225-01
Assembled with pulse generator
Low noise
Superior output linearity
Boxcar waveform output
C7884-01 + C8225-01
Assembled with pulse generator
C7884 is incorporated.
C7884-01 is incorporated.
Integration time: 1 μs to 50 s
CLK frequency: 32 MHz to 62.5 kHz
BNC, length 1 m
Supplied with male connector
(Ta=25 °C)
Symbol
+Vs Max
-Vs Max
Topr
Tstg
Condition
No condensation
No condensation
Value
+20
-20
0 to +50
-10 to +60
Unit
V
V
°C
°C
Min.
Typ.
Max.
Current-to-voltage conversion
0.3
500
1
62.5
62.5
Unit
V/pC
kHz
MHz
kHz
kHz
■ Characteristics (Unless otherwise noted Ta=25 °C, +Vs=+12 V)
(1) Analog circuitry
Parameter
Circuit operation mode
Circuit gain
Symbol
G
C7884
Data rate
fvo
C7884-01
Condition
All series
S3901/S3904 series
S3902/S3903 series
S3901/S3904 series
S3902/S3903 series
49
Characteristic and use of NMOS linear image sensors
(2) Digital circuitry
Parameter
Symbol
Vms (H)
Vms (L)
tpwφms
trφms
tfφms
Vmc (H)
Vmc (L)
tpwφmc
trφmc
tfφmc
Min.
2.0
Input voltage
0
Master start pulse
φms
Pulse width
1/fφmc
(Positive logic)
Rise time
Fall time
2.0
Input
Input voltage
0
Pulse width
30
Master clock pulse
φmc
Rise time
(Positive logic)
Fall time
C7884
Frequency
fφmc
C7884-01
Vtrig (H)
2.0
Output voltage
Vtrig (L)
0
Trigger pulse
Trig
Pulse width
tpwtrig
(Positive logic)
Rise time
trtrig
Fall time
tftrig
Output
Veos (H)
2.0
Output voltage
Veos (L)
0
End of scan pulse
EOS
Pulse width
tpweos
(Negative logic)
Rise time
treos
Fall time
tfeos
NOTE: Maximum clock frequency: Value in parentheses is for S3902/S3903 series.
Parameter
Positive supply voltage
Negative supply voltage
Positive supply voltage
C7884
Negative supply voltage
Positive supply voltage
C7884-01
Negative supply voltage
Symbol
+Vs
-Vs
+Is
-Is
+Is
-Is
Typ.
5.0
5.0
5.0
1/fφmc
5.0
2/fφmc
-
Max.
5.4
0.8
50
50
5.4
0.8
20
20
2 (4)
250
5.4
0.8
100
100
5.4
0.8
100
100
Unit
V
V
ns
ns
ns
V
V
ns
ns
ns
MHz
kHz
V
V
ns
ns
ns
V
V
ns
ns
ns
■ General ratings
Supply voltage
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
l External noise measures
Filters and capacitors are placed on the power supply line to
prevent external noise pickup.
○
○
l Temperature stability
To improve temperature stability, reference and filter circuits
are incorporated in various points and a regulator is installed
in the power supply.
○
○
l Power supply
C7884 internally generates supply voltage Vcc for digital circuitry and operates from two power supplies (±12 V Typ.).
○
○
7-3-3. How C7884 series differs from recommended
circuit
○
○
○
Current consumption
50
Condition
+15 V
-15 V
+15 V
-15 V
Min.
+11.5
-11.5
-
Typ.
+12.0
-12.0
35
10
25
15
Max.
+15.5
-15.5
-
Unit
V
V
mA
mA
mA
mA
Characteristic and use of NMOS linear image sensors
7-4. Pulse generator circuit C8225 series
7-4-1. Product lineup
Product name
Type No.
Pulse generator
C8225-01
Features
C7884 series
Integration time: 1 μs to 50 s
CLK frequency: 32 MHz to 62.5 kHz
7-4-2. Specifications
■ Absolute maximum ratings (Ta=25 °C)
Parameter
Supply voltage
Operating temperature
Storage temperature
Symbol
+Vs V Max
Topr
Tstg
Condition
Value
+7
0 to +50
-10 to +60
No condensation
No condensation
Unit
V
°C
°C
■ Characteristics (Unless otherwise noted, Ta=25 °C, +5 V)
Parameter
Master start pulse
MStart
(Positive logic)
Output
Output voltage
Pulse width
Rise time
Fall time
Output voltage
Master clock pulse
MCLK
(Positive logic)
Pulse width
Rise time
Fall time
Frequency
Symbol
Vms (H)
Vms (L)
tpwφms
trφms
tfφms
Vmc (H)
Vmc (L)
tpwφmc
trφmc
tfφmc
fφmc
Min.
2.0
0
1/fφmc
2.0
0
30
-
Typ.
4.8
4.8
-
Max.
5.0
0.8
50
50
5.0
0.8
10
10
32 (24)
Unit
V
V
ns
ns
ns
V
V
ns
ns
ns
MHz
Min.
+4.5
Typ.
+5.0
Max.
+5.5
30
Unit
V
mA
* Maximum clock frequency
■ General ratings
Parameter
Symbol
Condition
Supply voltage
+Vs
Current consumption
+Is
+5 V
* Current consumption varies depending on clock frequency.
51
Characteristic and use of NMOS linear image sensors
7-4-3. Switch setting
■ MCLK
Use the CLK switch to set MCLK (readout frequency).
CLK switch
C8225-01
No.
Frequency
0
32 MHz
1
16 MHz
2
8 MHz
3
4 MHz
4
2 MHz
5
1 MHz
6
500 kHz
7
250 kHz
8
125 kHz
9
62.5 kHz
■ MStart
C7884
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz
15.625 kHz
C7884-01
62.5 kHz
31.25 kHz
15.625 kHz
Use the ST switch and 1-2-5 switch to set the integration time of the driver circuit.
ST switch and 1-2-5 switch (same for all series)
ST switch
1-2-5 switch
Integration time
1
1 μs
0
2
2 μs
5
5 μs
1
10 μs
1
2
20 μs
5
50 μs
1
100 μs
2
2
200 μs
5
500 μs
1
1 ms
3
2
2 ms
5
5 ms
1
10 ms
4
2
2 ms
5
5 ms
1
100 ms
5
2
200 ms
5
500 ms
1
1s
6
2
2s
5
5s
1
10 s
7
2
20 s
5
50 s
NOTE: When the ST switch is set to 8 or 9, MStart is always “Low” and no pulse is output.
52
Characteristic and use of NMOS linear image sensors
○
○
○
○
○
○
(2) Cables
Hamamatsu also provides cables designed for connecting the
NMOS multichannel detector head with peripheral devices.
○
○
○
○
○
○
○
○
○
(1) Data processing unit C8799
C8799 is a data processing unit that converts video signals
from an NMOS image sensor driver circuit into digital signals
and transfers them to a PC.
The USB interface allows easy connection to a PC for highspeed data communications at 12 Mbps.
○
○
To operate NMOS multichannel detector heads easier,
Hamamatsu provides peripheral devices such as data processing units. Figure 7-2 shows a setup example when an
NMOS multichannel detector head is used with an IBM PC/AT
compatible personal computer.
○
○
○
7-5. Multichannel measurement units
Figure 7-2 Typical setup for multichannel detector head and peripheral devices
OSCILLOSCOPE
SIGNAL CABLE
A3020 (1.5 m, 2 CABLES)
(CONNECTORIZED
AT BOTH ENDS)
CABLE FOR IMAGE SENSOR
(CONNECTORIZED
AT BOTH ENDS)
(0.5 m)
A3017
A3017-01 (1 m)
A3017-02 (1.5 m)
POWER SUPPLY
POWER SUPPLY CABLE
(CONNECTORIZED
AT BOTH ENDS)
A3018-02 (1.5 m)
HAMAMATSU
DATA PROCESSING UNIT
C8799
C8892
USB CABLE (1.5 m)
C8799 ACCESSORIES
PC/AT COMPATIBLE
MACHINE
KACCC0184EE
53
Characteristic and use of NMOS linear image sensors
8. Reliability
Hamamatsu NMOS linear image sensors are subjected to reliability testing based on Japanese Industrial Standard (JIS), with EIAJ
(Japan Electronic Machinery Association) and MIL (U.S. military) standards also being taken into account as well. Reliability testing
of items listed in Table 8-1 is periodically performed.
Table 8-1 Reliability testing for NMOS linear image sensors
Tested item
Conditions
High temperature storage
85 °C (Tstg Max.) for 1000 hours
High temperature operation
65 °C (Topr Max.) at Vφ = 10 V for 1000 hours
High temperature and High
60 °C, 90 %, Vφ = 10 V (Clock voltage Max.) 1000 hours
humidity operation
Temperature Cycling (storage)
-40 °C for 30 minutes to 85 °C for 30 minutes, 100 cycles (Tstg Min. to Tstg Max.)
Shock
100 G for 6 ms, XYZ directions, 3 times each
Vibration
100 to 2000 Hz, 20 G, XYZ directions, 48 minutes
Terminal strength
Puling 0.5 kg for 30 seconds, bending 90 ° two times
Static electricity damage
C = 200 pF, R = 0 Ω, ±200 V, between all adjacent terminals
NOTE: Criteria for reliability testing are based on the maximum or minimum performance values listed in our catalog.
Information furnished by HAMAMATSU is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions.
Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. ©2014 Hamamatsu Photonics K.K.
HAMAMATSU PHOTONICS K.K., Solid State Division
1126-1 Ichino-cho, Hamamatsu City, 435-8558 Japan, Telephone: (81) 053-434-3311, Fax: (81) 053-434-5184, http://www.hamamatsu.com
U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218
Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 08152-3750, Fax: (49) 08152-2658
France: Hamamatsu Photonics France S.A.R.L.: 8, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10
United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777
North Europe: Hamamatsu Photonics Norden AB: Smidesvägen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01
Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1/E, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741
Cat. No. KMPD9001E06
Feb. 2014 DN
54