Technical information Current output type CMOS linear image sensors with variable integration time function S10121 to S10124 series 1 [Figure 1] Block diagram Features (a) NMOS linear image sensor (S3901 to S3904 series) Start pulse In previous current output type NMOS linear image sensors, once a readout starts, the internal shift register scans the readout switches from the first pixel to the last pixel to read out all the pixels, and therefore the integration times of all pixels are the same. With current output type CMOS linear image sensors with variable integration time function, a readout control circuit is used to control the shift register output making it possible to read out only specific pixels and set an appropriate integration time for each pixel. When a CMOS linear image sensor is used in a spectrometer and the like, light dispersed according to wavelength enters each pixel. The level of light entering each pixel is different. The variable integration time function can be used to set a long integration time for pixels with low incident light levels and short integration time for those with high incident light levels to enable measurements with high S/N over a wide spectral range. MOS shift register Clock pulse Video line Switch Photodiode 1 2 3 ..... n KMPDC0057EA (b) CMOS linear image sensor (S10121 to S10124 series) Start pulse MOS shift register Clock pulse Readout control circuit Control pulse Video line Switch Photodiode 1 2 3 ..... n KMPDC0487EA [Table 1] Comparison of NMOS linear image sensors and CMOS linear image sensors NMOS linear image sensor (S3901 to S3904 series) Product name Features Type no. Spectrophotometry S3901 S3902 Spectrophotometry S3903 128, 256, 512 Pixel pitch [µm] S3904 256, 512, 1024 50 S10121 S10122 S10123 128, 256, 512 25 S10124 256, 512, 1024 50 25 Pixel height [mm] 2.5 0.5 0.5 2.5 2.5 0.5 0.5 2.5 Saturation charge [pC] 50 10 5 25 140 28 14 70 3.25 7.25 18.25 1.75 3.75 8.25 Peak sensitivity wavelength [nm] Power consumption across Vdd and Vss [mW]*1 1 •High UV sensitivity •Low power consumption •Smoothly varying spectral •Variable integration time for response characteristics each pixel in UV region •Large saturation charge •Excellent output linearity •High UV sensitivity •Excellent output linearity •Low power consumption Application Number of pixels CMOS linear image sensor (S10121 to S10124 series) 600 - - 750 - *1: f(CLK)=250 kHz (S10121/S10124 series), 500 kHz (S10122/S10123 series) - 0.75 1.75 4.25 1.5 3.5 8.25 [Figure 2] Spectral response (typical example) (b) Equivalent circuit (a) 200 to 1200 nm ϕst 1 0.4 CMOS linear image sensor S10121 to S10124 series Photosensitivity (A/W) D Q D Q D Q D Q C Q C Q C Q C Q (Ta=25 °C) ϕclk 22 CMOS linear image sensor S10111 to S10114 series 0.3 ϕint 2 9 Active Video NMOS linear image sensor S3901 to S3904 series 0.2 Readout switch Vdd 4,7 GND 5,6,11 Photodiode 1 ch 2 ch Last channel Anti-blooming switch 0.1 Vofg 3 10 Dummy Video Vofd 8 0 200 12 EOS Shift register with readout control circuit 400 600 800 1000 1200 KMPDC0489EA Wavelength (nm) KMPDB0401EB 2 (b) Ultraviolet region (Ta=25 °C) 0.1 Photosensitivity (A/W) 0.08 (1) Photodiode (photosensitive area) The photosensitive area is made up of PN junction photodiodes, which are composed an N-type diffusion layer formed on a P-type silicon substrate. It serves as a photoelectric converter that converts light signals into electrical signals and also temporarily stores the obtained signal charges. Vss is connected to the anode of each photodiode. The photodiode is designed to provide high UV sensitivity but low dark current. Figure 4 shows a structure diagram of the photosensitive area. “A” indicates the photodiode pixel pitch; “B” indicates the width of the photodiode diffusion layer; “C” indicates the photodiode height. S10121 to S10124 series 0.06 Conventional type S10111 to S10114 series 0.04 0.02 0 200 220 240 260 280 Description of each section 300 Wavelength (nm) KMPDB0411EB [Figure 4] Structure of photosensitive area [Figure 3] Device structure Dummy Video 9 Active Video 10 Vofg 3 Video line 8 Vofd Vdd 4 Readout switch 7 Vdd B A 1.0 μm Shift register with readout control circuit ϕint 2 11 GND Oxidation silicon GND 5 Dummy photodiode Photodiode array Dummy photodiode 6 GND Anti-blooming switch N-type silicon KMPDC0488EA 1.0 μm ϕst 1 EOS 12 400 μm ϕclk 22 C (a) Block diagram P-type silicon S10121 S10122 S10123 S10124 A B C 2.5 mm series 50 μm 45 μm 0.5 mm series 0.5 mm series 25 μm 20 μm 2.5 mm series KMPDA0124EC 2 The readout switch is made up of an address switch array, which is composed of N-channel MOS transistors whose source is the photodiode cathode, drain is the video line, and gate is the address pulse input. Each photodiode is connected to the active video line via an address switch. The address pulse from the shift register turns on the address switch and causes the output signal to appear in the video line. The readout switch ON resistance is approximately 500 Ω. (3) Anti-blooming switches The anti-blooming switch is made up of switches, which are composed of N-channel MOS transistors whose source is the photodiode cathode, gate is the overflow gate, and drain is the overflow drain. When a light level higher than the saturation exposure enters a photodiode, the photodiode cannot store a signal charge in excess of the saturation charge. The excess signal charge overflows and diffuses into the adjacent photodiodes and the video lines, resulting in deterioration of signal purity, so-called “blooming.” An anti-blooming switch is provided in the S10121 to S10124 series for each photodiode separately from the normal signal output line connected to the video line, in order to allow the excess charge to bleed off. (4) Shift register with readout control function The shift register with readout control function is composed of a D type flip-flop for every channel plus one extra D type flip-flop and NOR gates [Figure 5]. The CLK signal is input to pin C of each D type flip-flop of every channel that makes up the shift register (), and the ST signal connected to pin D of the ch 1 D type flipflop (). The D type flip-flop retains the input to pin D as output of pin Q on the falling edge of the CLK signal. Pin Q of ch 1 is connected to pin D type of ch 2 (), and this pattern is repeated to the last channel. Applying ST and CLK signals externally causes the D type flip-flop circuit to operate, and the signal is output from each channel in order from ch 1. Furthermore, to allow readout control, the inverted signal from pin Q and the INT signal are input to the two input terminals of each NOR gate (). The on and off of the address switch of each channel can be controlled using the INT signal. When the readout of all pixels is complete, an EOS (endof-scan) pulse is output at the next timing after the last pixel. [Figure 5] Circuit of shift register with readout control function 1 ch Q1 D Q ST C Q 2 ch Q2 D Q Q1 C Q Last channel Qn D Q Q2 C Q D Q D type flip-flop Qn C Q Qn + 1 EOS CLK INT NOR gate S1 S2 Sn To address switch KMPDC0490EA The INT signal and the output from the D type flip-flops enter the NOR gates. When consecutive pixels are read out, a high-level period must be provided in the INT signal to prevent the shift register output of adjacent pixels from turning on simultaneously in the gray area of Figure 6, in order to ensure only a single pixel is turned on. The INT signal must be set to high level for at least 30 ns before and after the CLK falling signal. However, this is not necessary during the period between an EOS and the next rising edge of the ST signal. Timing chart 3 Figure 6 shows a timing chart of the shift register section. The CLK signal is changed from high level to low level once during the high-level period of ST. This starts the operation of the D flip-flops making up the shift register. [Figure 6] Shift register operation T1 T2 NOR output signals DFF output signals Input signals (2) Readout switches T3 T4 CLK ST INT Q1 Q2 Q3 Q4 S1 S2 S3 S4 Address switch ON Address switch ON Active Video 1 ch Address switch ON Address switch OFF 2 ch 3 ch 4 ch Read Not read QX: Pin Q output of X ch SX: NOR gate output of X ch KMPDC0491EA · T1 CLK changes to low level, and Q1 changes to low level. Since the INT signal is at high level, S1 remains at low level. · T2 When the INT signal changes to low level while Q1 is at low level, S1 changes to high level, and the readout switch of the ch 1 shift register turns on. 3 · T3 Q1 is at low level. When the INT signal changes to high level, S1 changes to low level, and the readout switch the integration time (one cycle of the start pulse) of the first pixel. The integration time can be varied for each pixel by applying INT pulse as shown in figure 8. [Figure 8] Timing chart (variable integration time function) of the ch 1 shift register turns off. CLK · T4 Q4 is at low level. When the INT signal is at high level, S4 remains at low level, and the readout switch of the 1 cycle ST Readout timing 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 INT ch 4 shift register remains off. 1 ch integration time [Figure 7] Timing chart 2 ch integration time 3 ch integration time 4 ch integration time CLK tpi(ST), integration time Output ST Invalid data INT KMPDC0233ED Active Video (available period) Last pixel 1st 2nd 3rd 4th EOS Enlarged view Valid data tf(CLK) 1st 2nd 3rd 4th 5 tr(CLK) Operating principle CLK 1/f(CLK) tr(ST) ST t(ST-CLK) tf(ST) t(CLK-ST) t(INT-CLK) t(CLK-INT) INT should be high when not reading pixels. INT tr(INT) Active Video (available period) Parameter S1012*-128 S1012*-256 Start pulse (ST) cycle S1012*-512 S1012*-1024 INT pulse rise and fall times INT pulse - clock pulse timing Clock pulse - INT pulse timing Start pulse rise and fall times Clock pulse duty ratio Clock pulse rise and fall times Clock pulse - start pulse timing Start pulse - clock pulse timing 1st 2nd Symbol tpi(ST) tr(INT), tf(INT) t(INT-CLK) t(CLK-INT) tf(ST), tr(ST) tf(CLK), tr(CLK) t(CLK-ST) T(ST-CLK) tf(INT) 3rd Min. 130/f(CLK) 258/f(CLK) 514/f(CLK) 1026/f(CLK) 0 30 30 0 40 0 20 20 4th Typ. 20 20 50 20 - 5th Max. Unit s 30 ns 1 / [2 × f(CLK)] ns 1 / [2 × f(CLK)] ns ns 30 % 60 ns 30 ns ns KMPDC0249EE 4 Variable integration time function Controlling CLK of pin INT makes it possible to change the integration time of each pixel to “an integer multiple of the readout cycle.” If CLK of pin INT is set to high level at the readout timing of a specific pixel, the signal for that pixel is not output [Figure 8]. If the signal from the specified pixel is not output, integration continues for that pixel. For example, if the integration time of a readout cycle is 100 ms and this function is used to output a signal every three cycles for a specific pixel, the integration time for that pixel is 300 ms. Increasing the integration time of a specific pixel makes it possible to efficiently detect low-level wavelength component signals of dispersed light. The timing chart of the variable integration time function is shown in Figure 8. Here, an example is provided for a case where the integration times of the second, third, and fourth pixels are set to twice, three times, and four times Figure 9 shows the setup of a photodiode and readout switch for a single pixel. Figure 10 shows the equivalent circuit of the setup. The details of the readout operation are explained below. The photodiode is a PN junction photodiode consisting of an N-type diffusion region formed on a P-type silicon substrate. The readout switch is made up of N-channel MOS transistors whose source is the photodiode cathode, drain is the the video line side, and gate is the address pulse input from the shift register. The photodiode anode (silicon substrate) is connected to GND, and the video line is biased at the positive potential Vb. When an address pulse from the shift register enters the gate of the readout switch, the switch turns on. As a result, the photodiode cathode is set to the same potential as the video line, and the photodiode is initialized to a reverse-bias state. At this point, the photodiode junction capacitance Cj is supplied with a charge, Qj = Cj × Vb, from the power supply. When the switch turns off and integration starts, the stored charge is discharged by the charge generated by the incident light, and the cathode potential approaches GND potential. The amount of discharge increases in proportion to the incident light level, but the maximum amount is limited by the amount of charge initially stored. This corresponds to the saturation charge. When an address pulse is received again and the readout switch turns on, a charge equal to the that discharged during the integration time is supplied from the power supply through the load resistance RL, so that the photodiode is initialized again. At this point, a potential difference due to the charge current appears across the load resistance R L, and is detected as an output voltage. This output has a differential waveform with a negative polarity with respect to the video line bias voltage Vb. This signal readout method is called current-to-voltage conversion, and its simplified operating diagram is shown in Figure 11. 4 [Figure 9] Structure of readout section Address pulse from shift register Video line Output signal hυ Photodiode Switch N Load resistance RL N P Supply voltage V KMPDC0061EA [Figure 10] Equivalent circuit of current-to-voltage conversion method Address pulse from shift register Video line Output signal Switch Load resistance RL Photodiode Supply voltage V KMPDC0062EA [Figure 11] Operation of current-to-voltage conversion method Address pulse from shift register +V current integration, amplification, and DC restoration on the video signals received from the sensor. The voltage regulator generates Vofd (=Vb) and Vofg. Digital supply voltage, analog supply voltage, master clock pulse, and master start pulse are applied to the driver circuit from external sources. On the other hand, the driver circuit outputs data video signal, trigger pulse, and EOS pulse. The timing signal generator consists of a PLD (programmable logic device) and transmits (1) clock pulse and start pulse to operate the sensor shift register, (2) reset signals to the current integrating circuit to process output signals, and (3) clamp signal to the DC restoration circuit. The generator also provides a trigger output signal for external sample-and-hold and transmits it via a buffer. These signals are synchronized with an external master clock pulse and are initialized by an external master start pulse. The video signal processor comprises four sections: firststage amplifier, second-stage amplifier, clamp circuit, and last-stage amplifier. The first stage amplifier integrates the video output current from the sensor. Video bias voltage Vb (=Vofd) is applied to the non-inverting input terminal of the first stage amplifier. A reset switch is connected in parallel with the integration capacitor, so that the capacitance is reset by a reset signal input to the switch each time a pixel is read out. The first stage amplifier also cancels the switching noise that is synchronized to the clock pulse. The first stage amplifier output, which is a positive boxcar waveform with respect to the 2 V video bias, is given by equation (1). Denoting the output voltage (unit: V) as V and the output charge (unit: pC) as Q, V = Q/Cf ······(1) Photodiode potential [Figure 12] External driver circuit example GND Timing signal generator Video signal processor Low output High output MCLK Reset CLK MST PLD ST Sensor INT Output voltage +V Cf Active Video Amp + - Buffer Data Video C-V Time Clamp KMPDC0063EA EOS Trigger In actual operation, the stored charge gradually discharges due to the re-combination current and the surface leakage current in the depletion layer in addition to the photocurrent described above. These currents that are unrelated to the illumination of light are referred to as dark current and its output is called dark output. 6 External current integrating driver circuit example As shown in Figure 12, a driver circuit consisting of a timing signal generator, video signal processor, voltage regulator, and so on must be prepared. The timing signal generator generates pulses required by the sensor, signal processor, and so on. The video signal processor performs 5 Vofg 0.2 V Vofd Vb 2V Voltage regulator KMPDC0492EA The second-stage amplifier performs non-inverting amplification. Then, a clamp circuit composed of a capacitor and switch performs CDS (correlated double sampling). The clamp switch is turned on for a given period (clamp period) immediately after the integration capacitance is reset in order to fix the clamp circuit output potential to ground. This eliminates the reset noise that occurs in the integration capacitance reset switch. The last-stage non-inverting amplifier transmits data video signals. The voltage regulator generates two voltages: Vofg and Vofd. Vofg is applied to the MOS transistor gate, and therefore hardly any current flows to pin OFG. The current that flows through pin OFD depends on the oversaturated state. Up to several tens of mA may flow. To use in a over-saturated state, the drive capability must be increased to allow current to flow through pin Vofd. [Figure 13] Timing chart example of external driver circuit MST MCLK ST CLK INT Reset Clamp Trigger Data Video EOS 7 Q&A What is the difference between the CMOS linear image sensor S10121 to S10124 series and the NMOS linear image sensor S3901 to S3904 series? See the comparison table of Table 1. The S10121 to S10124 series feature large saturation charge and variable integration time function. In addition, a smooth spectral response is achieved in the ultraviolet region [Figure 2 (b)]. How should the dummy video terminal be used? KMPDC0386EB Precautions when configuring the driver circuit · Separate the analog circuit ground and the digital circuit The dummy video terminal outputs only the switching noise component. The dummy video terminal is used in the current-to-voltage conversion method, but this method is not recommended because obtaining highly accurate readout is difficult. Note that the dummy video terminal is not used when the current integrating readout circuit is used. ground. · Connect the video output terminal to the amplifier input What is the voltage Vb that is listed in the condition terminal in the shortest possible distance. · When wiring, avoid crossing of analog and digital signals or running them in parallel as much as possible. · Use a series power supply having only small voltage fluctuations. Vb is a video bias voltage for using the current integrating readout method; there is no terminal on the image sensor for Vb. See Figure 12, which provides an connection example of the integrating circuit and Vb. Vb is a voltage for the non-inverting input terminal of the integration amplifier. It is a reset voltage for the photodiode. Hamamatsu provides the C10808 series as a driver circuit for the CMOS linear image sensor S10121 to S10124 series. For details on the C10808 series, refer to the datasheet. [Figure 14] Block diagram (C10808 series) C10808 series ST CLK INT Timing signal generator EOS Video signal processor Buffer Buffer PLD MStart, MCLK EOS, Trigger D.GND RESET Video Amp Sensor C-V +2 V +12 V -12 V Buf Is it necessary to operate Vb and Vofd at the same voltage? Normally, operate Vb and Vofd at the same voltage. Vofd is connected to the drain of the overflow-drain MOS transistor. An equivalent circuit is shown in Figure 3 (b). In the over-saturated state, current flows from Vofd to the photodiode. For example, if 100000 lx, an extremely intense light, is incident, several tens of milliamperes of current flows. Therefore, we recommend a circuit in which an op amp is connected as a buffer. Data Video What is the optimum voltage for video bias voltage Vb? CLAMP +3.3 V, +5 V column of electrical characteristics? A measurement example of a video bias voltage and saturation charge is shown in Figure 15. The video bias voltage ranges from 0.5 V to 2.5 V and is typically 2 V. A.GND +15 V -15 V Voltage regulator KACCC0558EA 6 [Figure 15] Video bias voltage vs. saturation charge (typical example) (a) S10121-512Q sensor at such wavelengths? The image sensor has some sensitivity for light whose wavelength is 200 nm and less, but it is outside the guaranteed range. Please use it at your own risk. 200 Saturation charge (pC) whose wavelength is 200 nm and less? If so, are there any points to consider when using the image (Ta=25 °C, driver circuit C10808-01) 250 Does the image sensor have sensitivity for light 150 How is the EOS pulse used? 100 The EOS pulse can be used to determine whether all the shift register stages are operating normally. 50 How should the Cf value be set when using the current integrating readout circuit? 0 0 1 2 3 Video bias voltage (V) KMPDB0402EA (b) S10124-1024Q (Ta=25 °C, driver circuit C10808-01) 120 What are the points to consider when constructing a 100 Saturation charge (pC) Set the value by considering the saturation output charge Qsat, the output voltage of the amplifier to be used, and so forth. For example, in the case of the S10121 series, if the saturation output charge Qsat is 140 pC and 5 V of amplitude relative to the video bias voltage can be provided for the output voltage of the op amp, Cf=Qsat/V=140 pC/5 V=28 pF. current integrating readout circuit? 80 60 40 20 0 0 1 2 3 Video bias voltage (V) KMPDB0403EA Is it necessary to set the overflow gate voltage Vofg Consider the following points if you are selecting ICs for the current integrating readout circuit. First-stage amplifier: For the first-stage amplifier, select an IC with low noise and low input bias current while considering the switching speed. Second- and third-stage amplifiers: Select amplifiers that can handle high load capacitance. Reset switch and clamp switch: Use FET or analog switches. Select switches with minimal ON resistance and low reset noise and charge injection. Also, consider the signal voltage range. Are window materials other than the quartz window or to 0.2 V? Is there a problem with using 0 V? Also, is it windowless types supported? okay to apply the voltage through a resistor divider? Windowless types can be provided. Consult with your nearest Hamamatsu sales office. Please also consult us about window materials other than the quartz window. The saturation charge is influenced by variance in Vofg. The larger the Vofg, the smaller the saturation charge. Since Vofg is connected to the anti-blooming MOS transistor gate in the sensor, it is at high input impedance and hardly any current flows. Therefore, there is no problem in applying Vofg through a resistor divider. Using Vofg at 0 V will cause problems such as increased time lag (unread signals) and deterioration in the sensitivity uniformity between pixels at near saturation output. To prevent these problems, use Vofg at 0.2 V. To what light levels does the overflow prevention function (anti-blooming function) work? Under standard conditions, it has been confirmed that blooming does not occur up to 100 times the saturation exposure. If all pixels are read out without using the variable integration time function, is it okay to leave the INT pulse at the low-level voltage? The rising and falling edges of the internal pulse Q generated from the shift register overlap with the falling edges of the CLK signal [gray area in Figure 6]. If the INT pulse is kept at the low-level voltage at all times, there is a possibility that the readout switches of two pixels turn on simultaneously. Therefore, the INT pulse must be applied so that it is at high level for 30 ns before and after the CLK falling edges. Which section of the video signal should I refer to for the dark output reference? Refer to the video output of each pixel during the dark states. This product does not have a dark output reference like the optical black of the CCD. 7 What are the soldering conditions? Use a soldering temperature of 260 °C or less, and perform the soldering within 5 seconds. This condition applies to a single pin. There is no problem in soldering multiple pins consecutively. We recommend that you grip the root of the lead you are soldering with tweezers or a similar tool to dissipate heat and prevent heat from conducting to the product package. As long as these conditions are met, there is no problem in using lead-free solder. This product does not support flow soldering. Information described in this material is current as of September, 2014. Product specifications are subject to change without prior notice due to improvements or other reasons. This document has been carefully prepared and the information contained is believed to be accurate. In rare cases, however, there may be inaccuracies such as text errors. Before using these products, always contact us for the delivery specification sheet to check the latest specifications. Type numbers of products listed in the delivery specification sheets or supplied as samples may have a suffix "(X)" which means preliminary specifications or a suffix "(Z)" which means developmental specifications. The product warranty is valid for one year after delivery and is limited to product repair or replacement for defects discovered and reported to us within that one year period. However, even if within the warranty period we accept absolutely no liability for any loss caused by natural disasters or improper product use. Copying or reprinting the contents described in this material in whole or in part is prohibited without our prior permission. www.hamamatsu.com HAMAMATSU PHOTONICS K.K., Solid State Division 1126-1 Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (81) 53-434-3311, Fax: (81) 53-434-5184 U.S.A.: Hamamatsu Corporation: 360 Foothill Road, Bridgewater, N.J. 08807, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218 Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 8152-375-0, Fax: (49) 8152-265-8 France: Hamamatsu Photonics France S.A.R.L.: 19, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10 United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777 North Europe: Hamamatsu Photonics Norden AB: Torshamnsgatan 35 16440 Kista, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01 Italy: Hamamatsu Photonics Italia S.r.l.: Strada della Moia, 1 int. 6, 20020 Arese (Milano), Italy, Telephone: (39) 02-93581733, Fax: (39) 02-93581741 China: Hamamatsu Photonics (China) Co., Ltd.: B1201, Jiaming Center, No.27 Dongsanhuan Beilu, Chaoyang District, Beijing 100020, China, Telephone: (86) 10-6586-6006, Fax: (86) 10-6586-2866 Cat. No. KMPD9008E01 Sep. 2014 DN 8