MIL-PRF-38534 AND 38535 CERTIFIED FACILITY RAD HARD HIGH VOLTAGE SYNCHRONOUS SWITCHING REGULATOR CONTROLLER 5055RH SERIES FEATURES: Manufactured using Space Qualified RH3845 Dice Radiation Hardened to 300 Krad(Si) (Method 1019.7 Condition A) Neutron Tested to 5E11 n/cm² (Method 1017.2) High Voltage Operation: Up to 60V Input, and 36V Output Programmable Frequency 100-500KHz, or Synchronizable to 600KHz 70µA Shutdown Supply Current Antislope Compensation – Current Limit Unaffected by Duty Cycle Reverse Inductor Current Inhibit – Improves Efficiency with Light Loads External Compensation Capable of Driving Standard Power MOSFETs Available to DLA SMD 5962F14223 DESCRIPTION: The MSK5055RH is a radiation hardened wide input voltage range step-down synchronous switching regulator controller. The wide input range, programmable output voltage and switching frequency, make these regulators suitable for a wide variety of medium to high power applications. The adjustable operating frequency provides the flexibility to keep the switching noise out of sensitive frequency bands, and when synchronized, can be ganged out of phase with other controllers for reduced noise and component size. The MSK5055RH is hermetically sealed in a 16 pin flatpack, and is available with straight or gull wing leads. EQUIVALENT SCHEMATIC PIN-OUT INFORMATION TYPICAL APPLICATIONS 1 2 3 4 5 6 7 8 POL Applications Intermediate Bus Converter Satellite System Power Supply Step Down Synchronous Regulator High Efficiency Subsystem Supply VIN SHDN CSS SGND VFB VC SYNC FSET 16 15 14 13 12 11 10 9 BOOST TG SW VCC BG PGND SENSE+ SENSE- CASE=ISOLATED 1 8548-102 Rev. G 8/15 ABSOLUTE MAXIMUM RATINGS 10 VIN 65V Input Voltage VBOOST BOOST Voltage (BOOST) 80V SW 65V to -2V Switch Voltage 9 24V Differential Boost Voltage (BOOST TO SW) VCC 24V Bias Supply Voltage VSENSE SENSE+ and SENSE- Voltages 40V +/-1V Differential Sense Voltage TLD TST TJ TC ELECTRICAL SPECIFICATIONS SYNC, VC, VFB, CSS and SHDN SHDN Pin Currents Lead Temperature Range (10 Seconds) Storage Temperature 13 Junction Temperature Operating Case Temperature ESD Rating 5V 1mA 300°C -65°C to 150°C 150°C -55°C to +125°C 1C NOTES: 1 2 3 4 5 6 7 8 9 10 11 12 13 Unless otherwise specified VIN=20V, VCC=BOOST=10V, SHDN≥2V, RSET=49.9KΩ, SENSE-=SENSE+=10V, SGND=PGND= SW=SYNC=0V. Guaranteed by design but not tested. Typical parameters are representative of device performance but are for reference only. Supply current specification does not include switch drive currents. Actual supply currents will be higher. DC measurement of gate drive output "ON" voltage is typically 8.6V. Internal dynamic bootstrap operations yields typical gate "ON" voltages of 9.8V during standard switching operation. Standard operation gate "ON" voltage is not tested but guaranteed by design. Industrial grade devices shall be tested to subgroup 1 unless otherwise specified. Military grade devices (“H” and “K” suffix) shall be 100% tested to subgroups 1,2,3,4 and 7. Subgroup 3,6 and 8 available upon request. Subgroup 1,4,7 TC = +25°C Subgroup 2,5,8a TC = +125°C Subgroup 3,6,8b TC = -55°C The -2V absolute maximum on the SW pin is a transient condition. It is guaranteed by design, but not tested. Continuous operation at or above absolute maximum ratings may adversely affect the device performance and/or life cycle. Pre and post irradiation limits at 25°C, up to 300 Krad(Si) TID, are identical unless otherwise specified. Reference DLA SMD 5962F14223 for electrical specifications for devices purchased as such. Internal solder reflow temperature is 180°C, do not exceed. 2 8548-102 Rev. G 8/15 APPLICATION NOTES DEVICE TYPES (-1, -2) BG – The BG pin is the gate drive for the synchronous rectifier or bottom N-Channel MOSFET. Be aware of the high speed and large currents here during circuit layout. Keep traces short and as wide as possible to minimize parasitic impedances. The MSK5055RH can be ordered to operate in one of two different ways at light load. The different modes are internally configured at the factory and are identified by the “dash number.” DASH NUMBER -1 -2 PGND – The PGND pin is the high-current ground reference. Connect it directly to the negative side of the VCC decoupling capacitor. Care should be taken to make sure that these currents are not referenced by the SGND pin to avoid injecting noise into the ground reference. MODE Reverse Current Internal Connection Mode VFB Disabled (DCM VCC Enabled (CCM) SGND – the SGND pin should be connected to the negative side of the output capacitor. Use a common ground plane to minimize impedance, but locate the high current fast switching devices together so their returns remain local and do not corrupt the SGND reference. Device type “-1” disables the reverse current capability at light configuration “-2.” It loads. This configuration is more efficient than allows the inductor current to go discontinuous and the PWM will skip pulses to maintain regulation at light loads. This configuration will have a minimum load current requirement, typically 1mA. SW – The SW pin is the switch node for the device. The source of the top MOSFET (forward switch), the drain for the bottom MOSFET (synchronous rectifier), the inductor, and the BOOST capacitor are all connected to this node. Use short wide trace to minimize the impedance of this node. Device type “-2” allows reverse current in the synchronous switch at light loads. This configuration is less efficient at light loads but operations in continuous conduction mode at light loads. SHDN – The SHDN pin provides a method to disable the device. Pull this pin below 1.35V (nominal) to disable switching. Pull below one VBE (0.7V nominal) to enter low power shutdown. A resistor divider to VIN can be used to set UVLO using the 1.35V threshold. When not in use, pull the pin up to VIN with a large value resistor. When exceeding the absolute maximum rating of 5V the pin voltage will be clamped at 6V nominal. Limit the current into the pin to less than 1mA to prevent overstress. PIN FUNCTIONS VIN – The VIN pin is the input supply pin for the device, and should be decoupled to SGND with a low ESR capacitor located close to the pin — ( See application circuit for typical values). VCC – The VCC pin provides access to the internal 8V bias supply for decoupling and optional external sourcing. It is the power supply for most of the internal functions and the MOSFET gate drive. VCC can only source current and may be tied to an external source to improve efficiency and allow for lower voltage operation. If VCC is tied to an external source greater than 6.5V the device will operate with Vin as low as 4V. This configuration reduces power dissipation in the device by bypassing the internal regulator. The VCC pin charges the bootstrapped capacitor through a diode connected to the BOOST pin. In shutdown mode the VCC pin sinks 20µA until the pin voltage is discharged to zero volts. Note: When connecting VCC to an external source. The source must be greater than or equal to VIN +1V. BOOST – The BOOST pin provides the supply for the bootstrapped gate drive, and is externally connected to a low ESR ceramic BOOST capacitor. The value of the BOOST capacitor should be at least 50 times greater than the gate capacitance of the top MOSFET. Smaller values may be used, but analysis of the voltage drop is recommended. An external diode connected from VCC to the BOOST pin charges the bootstrap capacitor during the off-time of the main power switch. Locate the VCC and BOOST decoupling capacitors in close proximity to the device. CSS – The CSS pin is used for soft start. It allows the user to program the rate of change of the output at start-up. The capacitance required for a given output slew rate can be calculated using the following formula: TG – The TG pin is the gate drive for the forward switch, or top N-Channel MOSFET. Be aware of the high speed and large currents here during circuit layout. Keep traces short and as wide as possible to minimize parasitic impedances. CSS = 11µA(TSS/1.231V) The pin should be left open if not in use. 3 8548-102 Rev. G 8/15 TYPICAL APPLICATION CIRCUIT APPLICATION NOTES CONT'D SENSE-- The SENSE- pin is the negative input to the current sense amplifier. The sensed inductor current limit is set to 100mV across both SENSE inputs. RSENSE=70mV/IOUT(MAX) Given: IP-P < 0.30 x IOUT(MAX) SENSE+ - The SENSE+ pin is the positive input to the current sense amplifier. The sensed inductor current limit is set to 100mV across both SENSE inputs. RSENSE=70mV/IOUT(MAX) Given: IP-P < 0.30 x IOUT(MAX) SELECTING THE SWITCHING FREQUENCY VFB – The VFB (Feedback) pin is used to set the output voltage. Use a resistive divider to set the voltage at the VFB pin to 1.231V The MSK5055RH can be set to operate over a frequency range of 100KHz to 500KHz, and is synchronizeable up to 600KHz. There are several factors to consider when selecting the operating frequency including: efficiency, component size, output ripple, application sensitive frequency bands, and the minimum on time of the controller. The output ripple voltage and efficiency will vary with frequency and input voltage. Higher frequencies increase switching losses, but use smaller inductors and/or bulk capacitors saving board space. Lower frequencies reduce switching losses, but increase ripple current and require larger inductors and/or bulk capacitance to achieve the same output ripple voltage. when the output is at the desired level. VO=VFB 1+ R1 R2 VC – The VC pin provides a means to externally compensate the loop response of the controller. VC is the output of the transconductance error amplifier. A capacitor to ground creates a pole in the control loop. A series RC creates a pole zero combination in the control loop. If the VC pin is externally manipulated, use a source impedance of 1KΩ. SELECTING THE INPUT CAPACITOR The input capacitance provides a low impedance source to the input of the regulator. A low impedance is necessary for high speed, high efficiency switching and tight regulation. The input bus sources an average DC current while the input capacitance sources the AC component of the input current. Select the input capacitor based on voltage ripple requirements, RMS current rating and bulk capacitance. Assuming the capacitor ESR is lower than the bus impedance at the switching frequency and above, the ESR will dominate the voltage ripple. FSET – The FSET pin programs the oscillator frequency via a single resistor to ground. The RSET resistor must be present even when synchronization mode is used—Use the formula or the table below to select the resistance value for a desired frequency. RSET(KΩ) ≈ 9.55 x 104 x fSW(KHZ) (-1.31) RSET (KΩ) FSW (KHz) 229 100 135 150 92.0 200 67.3 250 54.2 300 44.2 350 37.4 400 32.0 450 27.7 500 VP-P ≅ IP-P x ESR Given: IP-P = IOUT The RMS current capability is related to power dissipation capability of the capacitor. Replace the capacitor with one that has a higher rating, or place more capacitors in parallel if more capability is needed. Sharing of ripple current between capacitors will be approximately equal if all of the capacitors are the same type, and preferably from the same lot. The RMS current seen by the input capacitors can be approximated by the following equation: IRMS ≅ IOUT x SQRT (3D^2 - 3D +1) Given: D ≅ VOUT/VIN Parallel ceramic capacitors are required to filter the high frequency components of the switching waveform. Locate the bias supply capacitors close to the VIN and SGND pins on the MSK5055RH. Locate the power input capacitors close to the drain of the forward switch (VIN) and the source of the synchronous rectifier (Power Ground). Use short, wide PCB lands to minimize parasitic impedances. SYNC – The SYNC pin is the input for synchronization of the internal oscillator to an external clock. Program the internal oscillator to be between 10% and 25% below the external clock. The recommended signal is a square wave of at least 2V in amplitude, a pulse width greater than 1µS, and a rise time of less than 500nS. If the SYNC pin is not used in the application, tie it to SGND. 4 8548-102 Rev. G 8/15 APPLICATION NOTES CONT'D SELECTING THE OUTPUT CAPACITOR The output capacitor filters the ripple current from the inductor to The volt-seconds product can be calculated as follows: an acceptable ripple voltage seen by the load. The primary factor in determining voltage ripple is the ESR of the output capacitor. The V*S = VI x dt voltage ripple can be approximated as follows: Given: VP-P = IP-P x ESR VI = the inductor voltage (VIN – VO) dt = VO/(VIN x fSW) The capacitive term of the output voltage ripple lags the ESR term Allow sufficient derating to prevent saturation and/or overstress when by 90° and can be calculated as follows: selecting the inductor. VP-P(CAP) = IP-P/ (8 x f x c) SELECTING THE MOSFETS Where: C = output capacitance in Farads A compromise between conduction loss and transition loss is recommended for the top MOSFET (forward switch). The bottom Select a capacitor or combination of capacitors that can tolerate MOSFET’s (synchronous rectifier) power dissipation is dominated the worst-case ripple current with sufficient de-rating. When using by the conduction loss. For highest efficiency, keep the total power multiple capacitors in parallel to achieve lower ESR or more bulk dissipation in each switch as low as possible. Conduction loss is a capacitance, sharing of ripple current between capacitors will be function of RDS(ON), and transition loss is a function of CRSS. The tranapproximately equal if all of the capacitors are the same type, and sition losses become more significant as input voltages and switching preferably from the same lot. Low ESR tantalum capacitors are frequency rise. recommended over aluminum electrolytic capacitors. Use ceramic decoupling capacitors to minimize high frequency noise. Gate charge losses are dissipated in the MSK5055RH and gate resistors if used. Gate charge is related to RDS(ON) and transition time. The power dissipated in the MSK5055RH and gate resistors due to gate charge by each MOSFET can be approximated by the following equation: COMPENSATING THE LOOP The feedback loop response can be optimized for the application PD(GATE DRIVE)= QG x VG x FSW by adjusting the values of the RC network from the VC pin to ground. Analysis is recommended to determine the phase margin and gain Given: QG = Gate Charge margin at the specific input voltage and load conditions of the appliVG = Gate Drive Voltage cation. Typically, a single RC network from VC to ground works well. FSW = Switching Frequency An additional ceramic capacitor from VC to ground may be needed to cancel the zero and prevent high frequency ringing or instability. Parasitic FET capacitances can couple the negative switch node transients onto the bottom MOSFET gate drive pin of the device, which could exceed the absolute maximum rating for the pin. A Schottky catch SELECTING THE INDUCTOR diode rated for 1A is recommended connected to ground to protect The important parameters for inductor selection are: its value, the pin from these transients. volt-second product, saturation and RMS current. To determine the peak current in the inductor add ½ of the p-p ripple current to the desired IOUT(MAX). A typical starting point for peak to peak current ripple is 20% of IOUT(MAX). Use the following equation to determine the RMS current: TOTAL DOSE RADIATION TEST PERFORMANCE Radiation performance curves have been generated for all testing performed by MSK. These curves show performance trends throughout each test process, and are located in the MSK5055RH radiation test report. The complete test report as available in the RAD HARD PRODUCTS section of the MSK website. IRMS = IDC * SQRT ( 1+ (1/3) * (∆I/IDC)2 ) Given: IDC = The DC output current ∆I = ½ of the peak to peak ripple current The minimum inductance value can be calculated as follows: LMIN > VOUT x 2DCMAX-1 DCMAX x ADDITIONAL APPLICATION INFORMATION RSENSE x 8.33 fSW For additional applications information, please reference Linear Technology’s® LT3845 data sheet. Given: DC = Duty Cycle = VOUT/VIN fSW = Switching Frequency This calculation also accommodates the max ripple/DC requirements for the slope compensation circuit. 5 8548-102 Rev. G 8/15 TYPICAL PERFORMANCE CURVES 6 8548-102 Rev. G 8/15 TYPICAL PERFORMANCE CURVES CONT'D 7 8548-102 Rev. G 8/15 MECHANICAL SPECIFICATIONS ESD TRIANGLE INDICATES PIN 1 WEIGHT=1.5 GRAMS TYPICAL MSK5055- 1 K RH ALL DIMENSIONS ARE SPECIFIED IN INCHES ORDERING INFORMATION LEAD CONFIGURATIONS BLANK= STRAIGHT RADIATION HARDENED SCREENING BLANK= INDUSTRIAL; H=MIL-PRF-38534 CLASS H; K=MIL-PRF-38534 CLASS K VERSION -1=DCM; -2=CCM GENERAL PART NUMBER The above example is a DCM, Class K regulator controller with straight leads. NOTE: See DLA SMD 5962F14223 for DLA part number options. 8 8548-102 Rev. G 8/15 MECHANICAL SPECIFICATIONS ESD TRIANGLE INDICATES PIN 1 WEIGHT=1.5 GRAMS TYPICAL MSK5055-1 K RH G ALL DIMENSIONS ARE SPECIFIED IN INCHES ORDERING INFORMATION LEAD CONFIGURATIONS G=GULL WING RADIATION HARDENED SCREENING BLANK= INDUSTRIAL; H=MIL-PRF-38534 CLASS H; K=MIL-PRF-38534 CLASS K VERSION -1=DCM; -2=CCM GENERAL PART NUMBER The above example is a DCM, Class K regulator controller with gull wing formed leads. NOTE: See DLA SMD 5962F14223 for DLA part number options. 9 8548-102 Rev. G 8/15 REVISION HISTORY MSK www.anaren.com/msk The information contained herein is believed to be accurate at the time of printing. MSK reserves the right to make changes to its products or specifications without notice, however, and assumes no liability for the use of its products. Please visit our website for the most recent revision of this datasheet. 10 8548-102 Rev. G 8/15