How to Design an Isolated, High Frequency, Push-Pull DC/DC Converter

design ideas
How to Design an Isolated, High Frequency, Push-Pull
DC/DC Converter
Dawson Huang
A simple push-pull DC/DC converter with a fixed 50% duty cycle is often used as a low
noise transformer driver in communication systems, medical instruments and distributed
power supplies. This simple scheme provides no voltage regulation—requiring a low
dropout (LDO) post regulator—a combination that presents potentially serious problems.
First, any significant variation in the driver’s input voltage, along with the fixed 50% duty
cycle, can increase the differential voltage across the LDO, resulting in significant power
losses and high temperature rise in the LDO. Second, low switching frequency requires
relatively bulky transformers, sometimes occupying 30% to 50% of the converter space.
The LT3999 monolithic DC/DC push-pull
driver avoids these issues with two important features: duty cycle control and high
frequency operation:
•Duty cycle control allows compensation
for wide VIN variation—something standard fixed duty cycle transformer drivers cannot do—greatly reducing LDO
loss when facing a wide input range.
•High switching frequency, up to
1MHz , leads to smaller transformers and lower output ripple.
wide input range, the other for a
compact high frequency transformer
driver with fixed input voltage.
The LT3999 combines these two
features with high 36V input voltage
and 1A input current capabilities,
making it a high power and flexible
low noise push-pull converter IC.
PUSH-PULL DC/DC CONVERTER
DESIGN FOR WIDE RANGING INPUT
This article presents two step-bystep design procedures: One for a
push-pull DC/DC converter with a
The flowchart in Figure 1b shows
how a push-pull converter can be
designed in eight simple steps. These
steps produce the LT3999 10V–15V
input, ±12V output, 200m A 1MHz pushpull converter shown in Figure 1a.
Figure 1. (a) LT3999 push-pull DC/DC converter with wide input range
and duty cycle control (b) Easy 8-step push-pull converter design
(a)
APPLICATION SPECIFICATIONS
fSW, VIN(MIN), VIN(MAX), VOUT1, IOUT1, IOUT2
(b)
1
RT
UVLO & OVLO/DC
2
VIN(MIN) TO VIN(MAX)
R1
CIN
SYNC
R3
2
R2
RDC
R4
ILIM/SS
1
RT
RBIAS
CSS
RBIAS
7
6
L1
•
C1
D2
•
•
D3
GND
U1
POSITIVE
LDO
3
N = NP:NS
4
RECTIFIER
5
INDUCTOR
6
LDO
7
SNUBBER
8
VOUT
COUT1
L2
D4
RDC
RD
SWB
RT
RDC
•
C3
LT3999
OVLO/DC
3
5
D1
T1
SWA
UVLO
R4
4
8
VIN
C2
U2
NEGATIVE
LDO
–VOUT
COUT2
April 2015 : LT Journal of Analog Innovation | 25
The LT3999 is a monolithic DC/DC transformer driver, which features duty cycle
control, high frequency and high power. It allows a wide input voltage range and low
loss at the LDO, while using small passive components due to the high frequency
operation. It also features input voltage up to 36V and input current up to 1A.
VIN
RA
RB
UVLO
OR
OVLO/DC
RA2
UVLO
RA1
OVLO/DC
1
RB
R A1 = R A2
(a)
RB = 143k. Calculations 5 and 6 give
DCMAX = 0.43, and RDC = 13.3k.
calculated by equations 3 and 4 for
UVLO and OVLO/DC, respectively.
RA2 can be chosen around 1MΩ.
VIN
VIN(MAX )
VIN(MIN)
(b)
1.25
Figure 2. Setting the precision UVLO and OVLO/
DC via resistor divider using either (a) a 2-resistor
method or (b) a 3-resistor method.
(3)
1
RB = R A2
=
VIN(MAX )
VIN(MIN)
(4)
VIN(MIN) = 10V, RA = 1M, RB = 143k.
RT = 12.1k sets fSW = 1MHz.
VIN(MAX) = 15.5V, RA = 1M, RB = 86.6k.
Step 2: Set the Input Voltage Range
(UVLO, OVLO/DC)
Step 3: Set the Maximum Duty Cycle
(R DC(MAX))
The UVLO (undervoltage lockout)
and OVLO/DC (overvoltage lockout/
duty cycle) pins are used to set input
voltage range. Either a 2- or 3-resistor
method can be used. For the 2-resistor
method shown in Figure 2a, RB is
calculated using equations 1 and 2 for
UVLO and OVLO/DC, respectively. For
low loss, we can assume R A = 1MΩ.
The maximum duty cycle (DCMAX) is
determined by the switching period
(TS = 1/fSW) and non-overlap time (TD(MIN))
between the two power switches, as
shown in equation 5. For the 2-resistor
method, RDC is calculated by equation
6. For the 3-resistor method, substitute R A = R A1 + R A2 in equation 6.
For UVLO:
For OVLO:
RB(UVLO) =
RA
VIN(MIN)
1.25
RB(OVLO) =
RA
VIN(MAX)
1.25
DCMAX = (1)
(2)
1
For the 3-resistor method shown
in Figure 2b, R A1 and RB are
26 | April 2015 : LT Journal of Analog Innovation
TS − 2TD(MIN)
2TS
(5)
RB
• R T • DCMAX • 4
R A + RB
1.25
(6)
RDC
1
=
VIN(MIN) •
In the Figure 1(a) example, TS = 1µs,
TD(MIN) = 70ns (typical value in the
data sheet), VIN(MIN) = 10V, R A = 1M,
Ns
Np
VOUT1 + VOUT2 + VLDO1 + VLDO2 + 2VF
(7)
2 ( VIN(MIN) − VSW ) • 2DCmax
VSW is the switch saturation voltage
for internal switches. VF is the forward
voltage of the rectifier diodes. VLDO1 and
VLDO2 are the dropout voltages of the
positive and negative LDOs. VSW = 0.4V,
VF = 0.7V, VLDO1 = VLDO2 = 0.8V are good
1
For the 2-resistor method used in
Figure 1a:
First, set the switching frequency
with RT; the value chosen from
Table 1 in the LT3999 data sheet.
The transformer turns ratio is
represented in equation 7.
N=
VIN(MIN)
1.25
Step 1: Set the Switching Frequency
(R T)
Step 4: Select the Transformer (T1)
VIN(MIN)
rules of thumb. If a commercial transformer with an exact calculated turns
ratio cannot be found, select one that
is close and calculate DCMAX in equation 7 accordingly. Then, recalculate RDC
in equation 6 based on new DCMAX .
In the Figure 1(a) example, VOUT1 =
−VOUT2 = 12V and VIN(MIN) = 10V, so choose
Wurth 750314781(N = 2) for DCMAX = 0.43.
Step 5: Design the Rectifier (D1, D2, D3
and D4)
The peak voltage across the rectifier bridge
is composed of the transformer secondary
side voltage (VSEC) plus any ringing voltage
spikes. VSEC is calculated using equation
8. The ringing voltage spike, however, is
difficult to predict, as it depends on the
loop resistance, the leakage inductance of
the transformer, and the junction capacitance of the rectifiers. As general rule, the
rectifier voltage rating (VREC) should be at
design ideas
7
3.5
7
3.5
6
3
6
3
VDIFF (V)
5
2.5
POWER LOSS
4
2
3
1.5
2
VDIFF
1
0
10
11
12
13
VIN (V)
14
15
16
0
Step 6: Select the Inductors (L1, L2)
The minimum inductor value (LMIN) is
set by the peak current limit of internal
switcher (ILIM) as shown by equation 9.
L MIN
=
2
ILIM
IOUT1
2N
TS
2
1.5
0
When VIN(MAX) = 15.5V, N = 2, VREC ≥ 93V,
IREC ≥ 200m A: a Central CMSH1-200HE
(200V, 1A) satisfies these requirements.
2N • VIN(MAX) • (1 2DCMIN ) • DCMIN
3
1
The current rating of the rectifier (IREC)
should be greater than the load current.
(9)
Higher inductance produces better regulation and lower voltage ripple, but requires
a correspondingly greater volume part.
The optimum inductor value is determined by taking into account both output
noise and solution volume requirements.
When VIN(MAX) = 15.5V,
DCMIN = 0.28, TS = 1µs, N = 2, ILIM = 1A,
IOUT1 = IOUT2 = 200m A, LMIN = 38.3µ H:
A Coilcraft XFL3012-393MEC (39.3µ H)
2.5
2
0.5
(8)
POWER LOSS
4
2
least 1.5 times the transformer turns ratio
multiplied by the maximum input voltage.
Because the two secondary windings are
connected across the rectifier bridge, a
factor of two is required, producing the
formula for the rectifier voltage rating:
VREC ≥ 1.5 • 2N • VIN(MAX)
5
1
Figure 3. LDO (U2) VIN − VOUT differential and power
loss vs input voltage
4
VIN = 10V
VDIFF
POWER LOSS (W)
8
VDIFF (V)
4
IOUT1 = IOUT2 = 200mA
POWER LOSS (W)
8
1
0.5
0
25
50
0
100 125 150 175 200
IOUT1 = IOUT2 (mA)
75
Figure 4. LDO (U2) VIN − VOUT differential and power
loss vs load
satisfies these requirements without
adding unnecessary size.
Step 7: Select the Low Dropout Linear
Regulator (U2, U3)
The maximum voltage of LDO occurs
at maximum input voltage under no
load, when VSEC equals VIN(MAX) • N.
The current rating of the LDO should
be greater than the load current.
When VIN(MAX) = 15.5V, N = 2, the voltage
rating for the LDOs should be 31V and
−31V, satisfied by the LT3065 (45V, 500m A)
and LT3090 (−36V, 400m A), respectively.
Step 8: Add a Snubber (C S and R S)
The recommended approach for designing an RC snubber (CS and RS in Figure 1)
is to measure the period of the ringing at
the LT3999’s SWA and SWB pins when its
switchers turn off without the snubber,
and then add capacitance—starting with
something in the range of 100pF—until
the ringing period lengthens by 1.5x to 2x.
The change in period determines the value
of the parasitic capacitance (CPAR), from
which the parasitic inductance (LPAR) can
be determined from the initial period.
Similarly, initial values can be estimated
using data sheet values for switch capacitance and transformer leakage inductance.
Once the value of the drain node capacitance and inductance are known, a
series resistor can be added to the snubber capacitance to dissipate power
and critically dampen the ringing. The
equation for deriving the optimal series
resistance using the observed periods
(tPERIOD , and tPERIOD(SNUBBED)) and snubber capacitance (CS) is below. Refer to
the LT3748 data sheet for more details.
CPAR =
L PAR =
CS
2
 tPERIOD(SNUBBED) 

 −1
tPERIOD


( tPERIOD ) 2
CPAR • 4π
RSNUBBER =
2
L PAR
CPAR
(10)
(11)
(12)
RESULTS
The measured results in Figures 3, 4
and 5 show that duty cycle control in
the push-pull converter of Figure 1
maintains a low VIN − VOUT differential
across the LDOs, resulting in minimized
power loss and temperature rise. Figure 3
shows that at 200m A per LDO, VDIFF ,
remains under 2.5V over the entire input
voltage range of 10V–15V. Figure 4
shows power loss remains low across
the load current range. Figure 5 and
Figure 6 show the thermal results.
For comparison, Figure 7 shows the
efficiency comparison of the design with
duty cycle control disabled and duty
April 2015 : LT Journal of Analog Innovation | 27
U1
U2
T1
U2
T1
U1
U3
U3
VIN = 10V
VOUT1 = 12V, VOUT2 = −12V
IOUT1 = IOUT2 = 200mA
NO FORCED AIR
VIN = 15V
VOUT1 = 12V, VOUT2 = −12V
IOUT1 = IOUT2 = 200mA
NO FORCED AIR
Figure 5. Thermal image of the design in Figure 1 in action, VIN = 10V
Figure 6. Thermal image, VIN = 15V
cycle control enabled. The efficiency
drops dramatically when input voltage
increases. Figure 8 shows the differential voltage across the positive LDO with
duty cycle control disabled and duty
cycle control enabled. Figures 9 and 10
show the thermal results. It is evident
that the duty cycle control reduces the
differential voltage and improves the
efficiency and thermal performance
Step 1: Set the Switching Frequency
(R T)
COMPACT TRANSFORMER DRIVER
FOR A FIXED INPUT VOLTAGE
The transformer turns ratio is
determined by:
Normally, the output voltage of the
basic unregulated transformer driver
converter changes significantly with
changes in load current. To produce a
regulated voltage, an LDO on the output
is strongly recommended. Figure 6a
shows the schematic of low part count
transformer driver using the LT3999.
Figure 6b shows the design flowchart.
VOUT + VLDO(OPTIONAL) + VF
N
N= S =
NP
VIN − VSW
In the design example, for high
frequency fSW = 1MHz , RT = 12.1k.
transformer driver output to the post
regulated low noise output. VLDO is the
drop at highest current, so it should be
minimized. 0.8V provides enough drop to
avoid dropout without the LDO getting
hot. A good rule of thumb assumption
is VSW = 0.4V, VF = 0.7V, VLDO = 0.8V.
The current rating of the transformer
should be 20%~50% larger than the
output current to leave some room.
Step 2: Select the Transformer (T1)
(13)
where VSW is the switch saturation voltage for internal switchers, and VF is the
forward voltage of a rectifier diode.
The sum of the peak magnetizing current
(IM(PEAK)) and the full load current
reflected to the primary side (N • IOUT)
should less than the peak current limit
of the internal switcher (ILIM). Based on
this, minimal LM (LM(MIN)) is required.
70
8
DUTY CYCLE CONTROL
ENABLED
60
7
6
50
40
VDIFF (V)
EFFICIENCY (%)
The four simple steps in the flowchart
can be used to design a 1MHz , low parts
count, 5V input, 5V output 400m A output transformer driver as an example.
The switching frequency of the LT3999 is
set by a single RT resistor selected based
on the table in the LT3999 data sheet
(frequency range is from 50kHz to 1MHz).
VLDO is the drop from the unregulated
DUTY CYCLE CONTROL
DISABLED
DUTY CYCLE CONTROL
DISABLED
5
4
3
2
30
1
20
10
11
12
13
VIN (V)
14
15
16
Figure 7. Efficiency comparison of the design with
duty cycle control disabled and duty cycle control
enabled, IOUT1 = IOUT2 = 200mA
28 | April 2015 : LT Journal of Analog Innovation
0
DUTY CYCLE CONTROL
ENABLED
10
11
12
13
VIN (V)
14
15
16
Figure 8. LDO (U2) VIN − VOUT differential vs VIN at
full load with duty cycle control disabled and with
duty cycle control enabled, IOUT1 = IOUT2 = 200mA
design ideas
U1
U2
T1
U2
T1
U1
U3
U3
VIN = 10V
VOUT1 = 12V, VOUT2 = −12V
IOUT1 = IOUT2 = 200mA
NO FORCED AIR
VIN = 15V
VOUT1 = 12V, VOUT2 = −12V
IOUT1 = IOUT2 = 200mA
NO FORCED AIR
Figure 9. Thermal image of the design with duty cycle control
disabled in circuit of Figure 1, VIN = 10V
The CMSH1-20M (20V, 1A)
satisfies these requirements.
IM(PEAK ) + N •IOUT
V −V
T 
=  IN SW • S  + N •IOUT
L
4

M
< ILIM
LM >
Figure 10. Thermal image of the design with duty cycle control
disabled in circuit of Figure 1, VIN = 15V
(14)
VIN − VSW
T
• S = L M(MIN)
ILIM − N •IOUT 4
CONCLUSION
Step 4: Low Dropout Linear Regulator
(U2, Optional)
The maximum input voltage of
the optional post-regulating LDO
(VLDO_IN(MAX)) occurs at no load,
where it equals VIN • N = 7.5V. The
current rating of the LDO should be
larger than the load current (>400m A
in the case of the design example).
(15)
For VOUT = VIN = 5V, the Coilcraft
PA6383-AL (N = 1.5) is a good fit.
Step 3: Rectifier (D1, D2)
Choose the rectifier diodes based on
voltage and current. The voltage across
the diodes is more than twice that of the
transformer secondary voltage because
of its center tap structure. The voltage
rating of the rectifier should be larger
than 2N • VIN = 15V, maybe by 20%.
A good LDO for the 5V, 400m A
output is the LT1763 (20V, 500m A).
4
VIN
CIN
3
D1
2
VIN
UVLO
SWA
SYNC
T1
•
IN
•
COUT
•
RDC
ILIM/SS
RBIAS
VOUT
COUT1
GND
RT
1
N = NP:NS
2
RECTIFIER
3
LDO
4
•
D2
RT
RBIAS
OUT
LDO
IN
LT3999
RT
APPLICATION SPECIFICATIONS
fSW, VIN, VOUT, IOUT
OPTIONAL
OVLO/DC
1
The LT3999 is a monolithic DC/DC transformer driver, which features duty cycle
control, high frequency and high power. It
allows a wide input voltage range and low
loss at the LDO, while using small passive components due to its high frequency
operation. It also features input voltage
up to 36V and input current up to 1A. n
SWB
(a)
(b)
Figure 11. (a) Low parts count, fixed input voltage transformer driver. (b) Design flowchart for the transformer driver
April 2015 : LT Journal of Analog Innovation | 29