R ™ DiePlus Advantage iCE65L08F-TCS110I SiliconBlue November 24, 2010 (1.0) Preliminary Data Sheet Supplement New package Supplement for CS110 4.35mm x 4.77 mm WLCSP (see iCE65 L-Series Data Sheet for Electrical and Architecture Characteristics) Figure 1: iCE65L08 WLCSP DiePlus™ Advantage is SiliconBlue’s focused program to provide designers with an optimal device mounting solution for mobile handheld applications. This data sheet provides detailed information regarding the DiePlus Advantage iCE65L08 CS110 device. Smallest possible board footprint Mechanical package structures such as lead frames and heat slugs are eliminated, as well plastic encapsulation Lowest cost solution, eliminating costs associated with encapsulated packages Up to 90% less weight than equivalent pin-count packaged devices WLCSP redistribution layer technology exhibits excellent electrical characteristics No signal integrity issues often associated with mounting substrates Robust electrical connections minimize resistance and inductance Laser etched custom marking available for WLCSP devices Full wafer custom programming of Non-Volatile Configuration Memory (NVCM) available WLCSP technology eliminates need for KGD manufacturing flow Devices use standard PCB reflow mounting methods Eliminates need for wire bonding and lead frames Available in 0.4mm pitch (CS) Table 1: iCE65 Ultra Low-Power Programmable Logic DiePlus Family Summary iCE65L08 Logic Cells (LUT + Flip-Flop) RAM4K Memory Blocks RAM4K Memory bits Configuration bits Size Weight Wafer Level Chip Scale Package, WLCSP 7,680 32 128K 1.057 Kb 4.77mm x 4.35mm 34 mg Package I/O Pins © 2007-2010 by SiliconBlue Technologies Corporation. All rights reserved. www.SiliconBlueTech.com CS110 92(12) (1.0, 24-NOV-2010) 1 iCE65 Ultra Low-Power DiePlus™ iCE65L08F-TCS110I Industry’s most advanced packages The iCE65 mobileFPGA family uses the most advanced packaging technology available, DiePlus™ Wafer Level Chip Scale Devices CS110 L08 (92) .4* pitch 4.8*x4.3 CC72 CS63 CS36 L08 (55) L04 (48) L01(25) .5 pitch 4.8x4.3 .4 pitch 3.8x3.2 .4 pitch 2.5x2.5 These devices can then be mounted to printed circuit boards just like standard ball grid array devices. By using WLCSP, iCE65 mobileFPGAs offer very small footprints and eliminate standard plastic package costs. * Dimensions in mm including Wafer Level Chip Scale Packaging (WLCSP). WLCSP technology adds a redistribution layer to a bare die, allowing standard mounting balls to be added. s by Prevail ing Technol ogy, Inc. ( www.pre vai li ng-technol ogy.com ) (1.0, 24-NOV-2010) 2 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Ordering Information: WLCSP Figure 2 describes the iCE65 ordering codes for all packaged components. See the separate iCE DiCE data sheets when ordering die-based products. Figure 2: iCE65 Ordering Codes (WLCSP) iCE65 L08 F -T CS 110 I Logic Cells (x1,000) Temperature Range L08 I = Industrial (TA = –40° to 85° Celsius) Configuration Memory F = NVCM + reprogrammable Package Leads Power Consumption/ Speed Package Style -T = High speed CS = wafer level chip-scale package (0.4 mm pitch) iCE65 Footprint Diagram Conventions Figure 3 illustrates the naming conventions used in the following footprint diagrams. Each PIO pin is associated with an I/O Bank. PIO pins in I/O Bank 3 that support differential inputs are also numbered by differential input pair. Figure 3: CS and CC Package Footprint Diagram Conventions 1 Ball row number Ball column number Single-ended PIO Numbering A PIO0 PIO0 Ball number A1 I/O bank number B PIO3/ DP07A C PIO3/ DP07B Differential Input Pair Indicators SiliconBlue Technologies Corporation www.SiliconBlueTech.com Differential Input Pair Numbering PIO0/ DP07A Pair pin polarity Pair number Differential Pair Dot indicates unconnected pin for iCE65L04 in CB284 package (1.0, 24-AUG-2010) 3 iCE65 Ultra Low-Power DiePlus™ iCE65L08F-TCS110I CS110 Wafer-Level Chip-Scale Ball Grid Array The CS110 package is wafer-level chip-scale ball grid array with 0.4 mm ball pitch. The iCE65L08 is the only device available in this package. Footprint Diagram Figure 4 shows the footprint diagram for the 110-ball wafer-level chip-scale package (CS110). Figure 3 shows the conventions used in the diagram. Compared to other packages, the footprint may appear left-right flipped because the balls on the CS110 package are mounted on the same side as the active circuitry. In other packages, the balls are mounted on the opposite side from the active circuitry. See Table 2 for a complete, detailed pinout for the 110-ball wafer-level chip-scale BGA packages. The signal pins are also grouped into the four I/O Banks and the SPI interface. Figure 4: iCE65L08 CS110 Wafer-Level Chip-Scale BGA Footprint (Top View) 1 2 3 I/O Bank 0 5 6 7 4 VPP_ VPP_ PIO0 GND FAST A 2V5 VCCIO_0 B PIO1 PIO1 PIO0 PIO0 PIO0 GBIN1/ PIO0 GBIN0/ PIO0 8 9 10 11 PIO3/ PIO3/ VCC PIO0 PIO0 DP00B DP00A A PIO3/ PIO3/ PIO0 PIO0 PIO0 DP01B DP01A B PIO3/ PIO3/ C PIO1 PIO1 PIO1 PIO1 PIO0 PIO0 PIO0 PIO0 DP02A DP02B GND C I/O Bank 1 E GBIN3/ GBIN2/ PIO1 PIO1 F GND VCCIO_1 VCCIO_3 D PIO3/ PIO3/ PIO3/ PIO1 PIO1 PIO0 PIO0 PIO0 DP04B DP05A DP05B GND E PIO3/ PIO3/ GBIN7/ PIO3/ PIO3/ F DP07B DP07A PIO1 PIO1 PIO2 PIO2 PIO2 DP06A DP06B G VCC PIO1 PIO1 PIO1 PIO2 PIO2 PIO2 PIO2 GBIN6/ PIO3/ DP08A I/O Bank 3 PIO3/ PIO3/ PIO3/ D PIO1 PIO1 PIO1 PIO1 PIO0 PIO0 PIO0 DP04A DP03A DP03B PIO3/ GND G DP08B PIO3/ PIO3/ H PIO1 PIO1 PIO1 PIO1 PIO2 PIO2 PIO2 PIO2 DP09A DP09B VCC H PIOS/ PIOS/ CRESET_B PIO2/ GBIN5/ PIO2 PIO2 PIO2 PIO3/ PIO3/ J J PIO1 SPI_SCK DP10A DP10B CBSEL1 PIO2 SPI_SI K SPI_VCC 1 PIOS/ PIOS/ SPI_SS_B SPI_SO 2 3 SPI Bank CDONE 4 PIO2/ GBIN4/ VCCIO_2 GND PIO2 PIO3/ PIO3/ K DP11A DP11B CBSEL0 PIO2 8 9 10 11 5 6 7 I/O Bank 2 Pinout Table Table 2 provides a detailed pinout table for the CS110 package. The iCE65L08 is the only device available in the CS110 package. Pins are generally arranged by I/O bank, then by ball function. The table also highlights the differential input pairs in I/O Bank 3. The CS110 package has no JTAG pins. Table 2: iCE65L08 CS110 Wafer-level Chip-scale BGA Pinout Table Ball Function GBIN0/PIO0 GBIN1/PIO0 PIO0 PIO0 PIO0 PIO0 (1.0, 24-NOV-2010) 4 Ball Number B6 A6 A3 A8 A9 B3 Type GBIN GBIN PIO PIO PIO PIO Bank 0 0 0 0 0 0 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Ball Function PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 VCCIO_0 Ball Number B4 B5 B7 B8 B9 C5 C6 C7 C8 D5 D6 D7 E5 E6 E7 A5 Type PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO VCCIO Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GBIN2/PIO1 GBIN3/PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 VCCIO_1 E2 E1 B1 B2 C1 C2 C3 C4 D1 D2 D3 D4 E3 E4 F3 F4 G2 G3 G4 H1 H2 H3 H4 J1 F2 GBIN GBIN PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO VCCIO 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CDONE CRESET_B GBIN4/PIO2 GBIN5/PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 K4 J4 K6 J6 F5 F6 F7 G5 G6 G7 CONFIG CONFIG GBIN GBIN PIO PIO PIO PIO PIO PIO 2 2 2 2 2 2 2 2 2 2 SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.0, 24-AUG-2010) 5 iCE65 Ultra Low-Power DiePlus™ iCE65L08F-TCS110I Ball Function PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2/CBSEL0 PIO2/CBSEL1 VCCIO_2 Ball Number G8 H5 H6 H7 H8 J7 J8 J9 K9 K5 J5 K7 Type PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO VCCIO Bank 2 2 2 2 2 2 2 2 2 2 2 2 PIO3/DP00A PIO3/DP00B A11 A10 DPIO DPIO 3 3 PIO3/DP01A PIO3/DP01B B11 B10 DPIO DPIO 3 3 PIO3/DP02A PIO3/DP02B C9 C10 DPIO DPIO 3 3 PIO3/DP03A PIO3/DP03B D9 D10 DPIO DPIO 3 3 PIO3/DP04A PIO3/DP04B D8 E8 DPIO DPIO 3 3 PIO3/DP05A PIO3/DP05B E9 E10 DPIO DPIO 3 3 PIO3/DP06A PIO3/DP06B F8 F9 DPIO DPIO 3 3 PIO3/DP07A GBIN7/PIO3/DP07B F11 F10 DPIO DPIO/GBIN 3 3 GBIN6/PIO3/DP08A PIO3/DP08B G9 G10 DPIO/GBIN DPIO 3 3 PIO3/DP09A PIO3/DP09B H9 H10 DPIO DPIO 3 3 PIO3/DP10A PIO3/DP10B J10 J11 DPIO DPIO 3 3 PIO3/DP11A PIO3/DP11B K10 K11 DPIO DPIO 3 3 VCCIO_3 D11 VCCIO 3 PIOS/SPI_SO PIOS/SPI_SI PIOS/SPI_SCK PIOS/SPI_SS_B SPI_VCC K3 J3 J2 K2 K1 SPI SPI SPI SPI SPI_VCC SPI SPI SPI SPI SPI GND GND GND GND GND GND A4 C11 E11 F1 G11 K8 GND GND GND GND GND GND GND GND GND GND GND GND VCC A7 VCC VCC (1.0, 24-NOV-2010) 6 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Ball Function VCC VCC Ball Number G1 H11 Type VCC VCC Bank VCC VCC VPP_2V5 VPP_FAST A1 A2 VPP VPP VPP VPP Package Mechanical Drawing Figure 5: CS110 Package Mechanical Drawing 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 e CS110: 4.354 x 4.770 mm, 110-ball, 0.4 mm ball-pitch, wafer-level chipscale ball grid array Top View Bottom View A A SiliconBlue iCE65L08F-T CS110I NXXXXXXX YYWW C D E F G H J B C D E D1 Mark pin A1 dot D B F G H J K K b e A A1 Top Side Coating E1 Side View E Description Symbol Number of Ball Columns X Number of Ball Rows Y Number of Signal Balls X Body Size Y Ball Pitch Ball Diameter Edge Ball Center to Center X Y Package Height Stand Off Top Marking Format Line Content 1 Logo iCE65L08F 2 -T CS110 3 ENG 4 NXXXXXXX 5 YYWW SiliconBlue Technologies Corporation www.SiliconBlueTech.com Description Logo Part number Power/Speed Package type Engineering Lot Number Date Code Min. Nominal Max. n E D e b — — — — 11 10 110 4.770 4.354 0.40 0.25 4.790 4.374 — — E1 D1 A A1 — — 0.761 0.17 4.00 3.60 0.800 0.20 — — 0.839 0.23 Units Columns Rows Balls mm Thermal Resistance Junction-to-Ambient θ (⁰C/W) 0 LFM 200 LFM 37 30 (1.0, 24-AUG-2010) 7 iCE65 Ultra Low-Power DiePlus™ iCE65L08F-TCS110I Revision History Version Date 1.0 24-NOV-2010 Description Initial Preliminary Data Sheet Supplement Release Copyright © 2007–2010 by SiliconBlue Technologies LTD. All rights reserved. SiliconBlue is a registered trademark of SiliconBlue Technologies LTD in the United States. Specific device designations, and all other words and logos that are identified as trademarks are, unless noted otherwise, the trademarks of SiliconBlue Technologies LTD. All other product or service names are the property of their respective holders. SiliconBlue products are protected under numerous United States and foreign patents and pending applications, maskwork rights, and copyrights. SiliconBlue warrants performance of its semiconductor products to current specifications in accordance with SiliconBlue's standard warranty, but reserves the right to make changes to any products and services at any time without notice. SiliconBlue assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by SiliconBlue Technologies LTD. SiliconBlue customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. R SiliconBlue SiliconBlue Technologies Corporation cumentati on s ervi ces by Prevail ing Techn ol ogy, Inc. ( www.pre vai ling-technol ogy.com ) (1.0, 24-NOV-2010) 8 3255 Scott Blvd. Building 7, Suite 101 Santa Clara, California 95054 United States of America Tel: +1 408-727-6101 Fax: +1 408-727-6085 www.SiliconBlueTech.com SiliconBlue Technologies Corporation www.SiliconBlueTech.com