USE GAL DEVICES FOR NEW DESIGNS FINAL COM’L: H-15/25 Lattice Semiconductor PALCE24V10H-15/25 EE CMOS 28-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS ■ Electrically erasable CMOS technology provides reconfigurable logic and full testability ■ High speed CMOS technology — 15-ns propagation delay for “-15” version — 25-ns propagation delay for “-25” version ■ Outputs individually programmable as registered or combinatorial ■ Programmable output polarity ■ ■ ■ ■ Programmable enable/disable control Preloadable output registers for testability Automatic register reset on power-up Cost-effective 28-pin plastic SKINNYDIP and PLCC packages ■ Extensive third-party support through FusionPLD partners ■ Fully tested for 100% programming and functional yields and high reliability GENERAL DESCRIPTION active-high or active-low output. The output configuration is determined by two global bits and one local bit controlling four multiplexers in each macrocell. The PALCE24V10 is an advanced PAL device built with low-power, electrically-erasable CMOS technology. Its macrocells provide a universal device architecture. The PALCE24V10 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the very wide input gates available in PAL devices. The equations are programmed into the device through floatinggate cells in the AND logic array that can be erased electrically. The fixed OR array allows up to eight product terms per output for logic functions. The sum of these products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial with an I1–I12, I14, I15 BLOCK DIAGRAM CLK/I0 14 Programmable AND Array (48 x 80) MACRO MACRO MACRO MACRO MACRO MACRO MACRO MACRO MACRO MACRO MC0 MC1 MC2 MC3 MC4 MC5 MC6 MC7 MC8 MC9 Input MUX Input MUX OE/I13 I/O0 I/O1 Publication# 12222 Rev. F Issue Date: February 1996 I/O2 Amendment /0 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 12222F-1 2-291 CONNECTION DIAGRAMS Top View SKINNYDIP PLCC 3 26 I/O9 I3 4 25 I/O8 I4 5 25 I/O8 I4 5 24 I/O7 I5 6 7 24 23 I/O7 I/O6 I/O5 GND 4 3 2 1 28 27 26 6 23 I/O6 VCC 7 22 I/O5 I6 8 22 I7 9 10 21 20 11 19 GND I7 9 20 I/O4 I8 10 19 I/O3 12 13 14 15 16 17 18 I9 11 18 I/O2 I10 12 17 I/O1 I11 13 16 I/O0 I12 14 15 OE/I13 I8 I9 12222F-3 Note: Pin 1 is marked for orientation. PIN DESIGNATIONS = Clock GND = Ground I = Input I/O = Input/Output OE = Output Enable VCC = Supply Voltage 2-292 I/O4 I/O3 I/O2 21 I/O0 I/O1 8 I12 OE/I13 I6 I10 I11 I5 VCC 12222F-2 CLK I14 I14 I2 I/O9 I1 27 CLK/I0 I15 I15 2 I1 28 I2 1 I3 CLK/I0 PALCE24V10H-15/25 ORDERING INFORMATION Commercial Products Programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: PAL CE 24 V 10 H -15 P C FAMILY TYPE PAL = Programmable Array Logic OPERATING CONDITIONS C = Commercial (0°C to +75°C) TECHNOLOGY CE = CMOS Electrically Erasable PACKAGE TYPE P = 28-Pin 300 mil Plastic SKINNYDIP (PD3028) J = 28-Pin Plastic Leaded Chip Carrier (PL 028) NUMBER OF ARRAY INPUTS OUTPUT TYPE V = Versatile NUMBER OUTPUTS POWER H = Half Power (115 mA ICC) SPEED -15 = 15 ns tPD -25 = 25 ns tPD Valid Combinations PALCE24V10H-15 PC, JC PALCE24V10H-25 Valid Combinations Valid Combinations lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. PALCE24V10H-15/25 (Com’l) 2-293 FUNCTIONAL DESCRIPTION The PALCE24V10 is a universal PAL device. It has ten independently configurable macrocells (MC0..MC9). Each macrocell can be configured as a registered output, combinatorial output, combinatorial I/O, or dedicated input. The programming matrix implements a programmable AND logic array, which drives a fixed OR logic array. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. Pins 1 and 15 serve either as array inputs or as clock (CLK) and output enable (OE) for all flip-flops. Unused input pins should be tied directly to VCC or GND. Product terms with all bits unprogrammed (disconnected) assume the logical HIGH state and product terms with both true and complement of any input signal connected assume a logical LOW state. The programmable functions on the PALCE24V10 are automatically configured from the user’s design specification, which can be in a number of formats. The design specification is processed by development software to verify the design and create a programming file. This file, once downloaded to a programmer, configures the device according to the user’s desired function. OE 11 VCC 0X 10 11 10 00 01 SL0X SG1 11 0X D SL1X CLK I/OX 10 Q Q 0 1 Macrocells MC1 – MC8 SL0X OE 11 VCC 0X 10 11 10 00 01 SL0X SG1 11 0X D SL1X CLK I/OX 10 Q Q 10 11 0X Macrocells MC0 and MC9 SG0 SL0X From Adjacent Pin 12222F-4 PALCE24V10 Macrocell 2-294 PALCE24V10H-15/25 Configuration Options Each macrocell can be configured as one of the following: registered output, combinatorial output, combinatorial I/O or dedicated input. In the registered output configuration, the output buffer is enabled by the OE pin. In the combinatorial configuration, the buffer is either controlled by a product term or always enabled. In the dedicated input configuration, the buffer is always disabled. The macrocell configurations are controlled by the configuration control word. It contains 2 global bits (SG0 and SG1) and 20 local bits (SL00 through SL09 and SL10 through SL19). SG0 determines whether registers will be allowed. SG1 determines whether the output buffer is user-controlled or in a fixed state. Within each macrocell, SL0x, in conjunction with SG1, selects the configuration of the macrocell and SL1x sets the output as either active low or active high. The configuration bits work by acting as control inputs for the multiplexers in the macrocell. There are four multiplexers: a product term input, an enable select, an output select, and a feedback select multiplexer. SG1 and SL0x are the control signals for all four multiplexers. In MC0 and MC9, SG0 is added on the feedback multiplexer. These configurations are summarized in table 1 and illustrated in figure 2. If the PALCE24V10 is configured as a combinatorial device, the CLK and OE pins are available as inputs to the array. If the device is configured with registers, the CLK and OE pins cannot be used as data inputs. Registered Output Configuration The control bit settings are SG0 = 0, SG1 = 1 and SL0x = 0. There is only one registered configuration. All eight product terms are available as inputs to the OR gate. Data polarity is determined by SL1x. SL1x is an input to the exclusive-OR gate which is the D input to the flipflop. SL1x is programmed as 1 for inverted output or 0 for non-inverted output. The flip-flop is loaded on the LOWto-HIGH transition of CLK. The feedback path is from Q on the register. The output buffer is enabled by OE. Combinatorial Configurations The PALCE24V10 has three combinatorial output configurations: dedicated output in a non-registered device, I/O in a non-registered device and I/O in a registered device. Dedicated Output in a Non-Registered Device Dedicated Input in a Non-Registered Device The control bit settings are SG0 = 1, SG1 = 0 and SL0x = 1. The output buffer is disabled. The feedback signal is the I/O pin. Combinatorial I/O in a Non-Registered Device The control settings are SG0 = 1, SG1 = 1, and SL0x = 1. Only seven product terms are available to the OR gate. The eighth product term is used to enable the output buffer. The signal at the I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to be used as an input. Combinatorial I/O in a Registered Device The control bit settings are SG0=0,SG1=1 and SL0x =1. Only seven product terms are available to the OR gate. The eighth product term is used as the output enable. The feedback signal is the corresponding I/O signal. Table 1. Macrocell Configurations SG0 SG1 SL0x Cell Configuration Device has registers 0 1 0 0 1 1 Registered Output Combinatorial I/O Device has no registers 1 0 0 1 0 1 Combinatorial Output Dedicated Input 1 1 1 Combinatorial I/O Programmable Output Polarity The polarity of each macrocell output can be active high or active low, either to match output signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. It can also save “DeMorganizing” efforts. Selection is made through a programmable bit SL1x which controls an exclusive-OR gate at the output of the AND/OR logic. The output is active high if SL1x is a 0 and active low if SL1x is a 1. The control settings are SG0 = 1, SG1 = 0, and SL0x = 0. All eight product terms are available to the OR gate. Because the macrocell is a dedicated output, the feedback is not used. PALCE24V10H-15/25 2-295 OE OE D CLK Q D Q CLK Q Q Registered Active High Registered Active Low Combinatorial I/O Active Low Combinatorial I/O Active High VCC VCC Combinatorial Output Active Low Combinatorial Output Active High Dedicated Input 12222F-5 Figure 2. Macrocell Configurations Figure 2: Macrocell Configurations 2-296 PALCE24V10H-15/25 Power-Up Reset Programming and Erasing All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the PALCE24V10 depend on whether they are selected as registered or combinatorial. If registered is selected, the output will be HIGH. If combinatorial is selected, the output will be a function of the logic. The PALCE24V10 can be programmed on standard logic programmers. It also may be erased to reset a previously configured device back to its virgin state. Erasure is automatically performed by the programming hardware. No special erase operation is required. Quality and Testability Register Preload The register on the PALCE24V10 Series can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. Security Bit A security bit is provided on the PALCE24V10 as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. However, programming and verification are also defeated by the security bit. The bit can only be erased in conjunction with the array during an erase cycle. The PALCE24V10 offers a very high level of built-in quality. The erasability if the device provides a direct means of verifying performance of all the AC and DC parameters. In addition, is verifies complete programmability and functionality of this device to yield the highest programming yields and post-programming function yields in the industry. Technology The PALCE24V10 is fabricated with our advanced electrically-erasable (EE) CMOS process. The array connections are formed with proven EE cells. Inputs and outputs are designed to be compatible with TTL devices. This technology provides strong input-clamp diodes, output slew-rate control, and a grounded substrate for clean switching. Electronic Signature Word An electronic signature word is provided in the PALCE24V10. It consists of 64 bits of programmable memory that can contain any user-defined data. The signature data is always available to the user independent of the security bit. PALCE24V10H-15/25 2-297 LOGIC DIAGRAM 0 CLK/I 0 1 I1 2 I2 3 4 8 12 16 20 24 28 32 36 40 44 11 10 01 00 D I3 27 I 14 26 I/O 25 I/O 8 24 I/O 7 23 I/O 6 22 I/O 5 SL0 9 SG1 11 01 00 10 Q SL1 9 7 I 15 11 10 01 00 VCC 0 28 9 Q 10 11 0x 4 SG0 11 10 01 00 11 10 01 00 VCC SL0 8 SG1 8 D I4 Q SL1 8 15 0 1 5 11 10 01 00 11 10 01 00 VCC SL0 7 SG1 16 D Q 0 1 6 11 10 01 00 11 10 01 00 VCC SL0 6 SG1 24 Q SL1 6 31 0 1 8 11 10 01 00 11 10 01 00 VCC SL0 5 SG1 32 Q D SL1 39 I7 9 VCC 7 11 01 00 10 Q D I6 11 01 00 10 Q SL1 7 23 I5 11 01 00 10 Q 11 01 00 10 Q 5 0 1 21 0 4 8 12 16 20 24 28 32 36 40 GND 44 CLK OE 12222F-6 2-298 PALCE24V10H-15/25 LOGIC DIAGRAM (continued) 0 4 8 12 16 20 24 28 32 36 40 CLK OE 44 11 10 01 00 11 10 01 00 VCC SL0 4 SG1 40 D SL1 47 11 01 00 10 Q 20 I/O 4 19 I/O 3 18 I/0 2 17 I/O 1 16 I/O 0 15 OE/I13 Q 4 0 1 I 8 10 11 10 01 00 11 10 01 00 VCC SL0 3 SG1 48 D SL1 55 11 01 00 10 Q Q 3 0 1 I 9 11 11 10 01 00 11 10 01 00 VCC SL0 2 SG1 56 D SL1 2 63 11 01 00 10 Q Q 0 1 I 10 12 11 10 01 00 11 10 01 00 VCC SL0 1 SG1 64 D Q SL1 1 71 11 01 00 10 Q 0 1 I 11 13 11 10 01 00 11 10 01 00 VCC SL0 0 SG1 72 D SL1 79 Q 11 01 00 10 Q 0 10 11 0x I 12 14 SG0 0 4 8 12 16 20 24 28 32 36 40 44 12222F-6 (concluded) PALCE24V10H-15/25 2-299 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . –55°C to +125°C Commercial (C) Devices Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage with Respect to Ground . . . . . . . . . . . . –0.5 V to + 7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . –0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. DC Output or I/O Pin Voltage . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0°C to +75°C) . . . . . . . . . . . . . . . . . . . . 100 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Max Unit VOH Output HIGH Voltage IOH = –3.2 mA VCC = Min VOL Output LOW Voltage IOL = 24 mA VCC = Min VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –10 µA IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) 10 µA IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) –10 µA ISC Output Short-Circuit Current VCC = Max VOUT = 0.5 V (Note 3) –150 mA ICC Supply Current Outputs Open (IOUT = 0 mA) VCC = Max, f = 15 MHz 115 mA VIN = VIH or VIL 2.4 VIN = VIH or VIL V 0.5 2.0 –30 V V Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-300 PALCE24V10H-15/25 (Com’l) CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Descriptions Test Conditions Typ Unit Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25°C, 5 pF Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol -15 Max Unit Input or Feedback to Combinatorial Output 15 25 ns tS Setup Time from Input or Feedback to Clock 10 12 ns tH Hold Time fMAX Clock Width Maximum Frequency (Notes 3 and 4) Max 0 Clock to Output tWL tWH Min -25 tPD tCO Parameter Description Min 0 10 ns 12 ns LOW 6 8 ns HIGH 6 8 ns External Feedback 1/(tS + tCO) 50 41.6 MHz Internal Feedback (fCNT) 1/(tS + tCF) 66 50 MHz No Feedback 1/(tWH + tWL) 83.3 62.5 MHz tPZX OE to Output Enable (Note 3) 15 20 ns tPXZ OE to Output Disable (Note 3) 15 20 ns tEA Input to Output Enable Using Product Term Control (Note 3) 15 25 ns tER Input to Output Disable Using Product Term Control (Note 3) 15 25 ns Notes: 2. See Switching Test Circuit for test conditions. 3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) – tS. PALCE24V10H-15/25 (Com’l) 2-301 SWITCHING WAVEFORMS Input or Feedback VT tS Input or Feedback VT tH VT Clock tCO tPD Combinatorial Output Registered Output VT VT 12222F-7 12222F-8 Combinatorial Output Registered Output VT VT Input OE tER Output tEA VOH - 0.5V VOL + 0.5V tPXZ VT Output VT VOL + 0.5V 12222F-9 12222F-10 OE to Output Disable/Enable Input to Output Disable/Enable tWH VT Clock tWL 12222F-11 Clock Width Notes: 1. VT = 1.5 V 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–5 ns typical. 2-302 tPZX VOH - 0.5V PALCE24V10H-15/25 KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State KS000010-PAL SWITCHING TEST CIRCUIT 5V S1 R1 Output CL R2 12222F-12 Specification S1 tPD, tCO Closed tPZX, tEA Z → H: Open Z → L: Closed tPXZ, tER H → Z: Open CL R1 R2 Measured Output Value 1.5 V 50 pF 200 Ω 5 pF L → Z: Closed 390 Ω 1.5 V H → Z: VOH – 0.5 V L → Z: VOL + 0.5 V PALCE24V10H-15/25 2-303 parts. As a result, the device can be erased and reprogrammed—a feature which allows 100% testing at the factory. ENDURANCE CHARACTERISTICS The PALCE24V10 is manufactured using our advanced electrically erasable process. This technology uses an EE cell to replace the fuse link used in bipolar Endurance Characteristics Symbol Parameter Test Conditions tDR Min Pattern Data Retention Time N Min Reprogramming Cycles Max Storage Temperature Min Unit 10 Years Max Operating Temperature 20 Years Normal Programming Conditions 100 Cycles INPUT/OUTPUT EQUIVALENT SCHEMATICS VCC ESD Program/Verify Protection Circuitry Typical Input VCC Preload Circuitry Feedback Input Typical Output 12222F-14 2-304 PALCE24V10H-15/25 POWER-UP RESET The PALCE24V10 has been designed with the capability to reset during system power-up. Following powerup, all flip-flops will be reset to LOW. The output state will be HIGH independent of the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Parameter Symbol Due to the synchronous operation of the power-up reset and the wide range of ways VCC can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are: ■ The VCC rise must be monotonic. ■ Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Description Min tPR Power-Up Reset Time tS Input or Feedback Setup Time Unit 1000 ns See Switching Characteristics Clock Width LOW tWL Max VCC 4V Power tPR Registered Output tS Clock tWL 12222F-15 Power-Up Reset Waveform PALCE24V10H-15/25 2-305