FINAL COM’L: -5/7/10/12/15 IND: -7/10/12/14/18 MACH®111-5/7/10/12/15 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ◆ 44 Pins in PLCC and TQFP ◆ 32 Macrocells ◆ 5 ns tPD Commercial, 7.5 ns tPD Industrial ◆ 182 MHz fCNT ◆ 32 I/Os; 4 dedicated inputs/clocks; 2 dedicated inputs ◆ 32 Flip-flops; 4 clock choices ◆ 2 “PALCE26V16” blocks ◆ SpeedLocking™ for guaranteed fixed timing ◆ Bus-Friendly™ Inputs and I/Os ◆ Peripheral Component Interconnect (PCI) compliant (-5/-7/-10/-12) ◆ Programmable power-down mode ◆ Safe for mixed supply voltage system designs ◆ Pin-compatible with the MACH211 GENERAL DESCRIPTION The MACH111 is a member of Vantis’ high-performance EE CMOS MACH 1 & 2 families. This device has approximately three times the logic macrocell capability of the popular PALCE22V10 without loss of speed. The MACH111 consists of two PAL® blocks interconnected by a programmable switch matrix. The two PAL blocks are essentially “PALCE26V16” structures complete with product-term arrays and programmable macrocells, which can be programmed as high speed or low power. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH111 macrocell provides either registered or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type or Ttype to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All macrocells can be connected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input. Vantis offers software design support for MACH devices through its own development system and device fitters integrated into third-party CAE tools. Platform support extends across PCs, Sun and HP workstations under advanced operating systems such as Windows 3.1, Windows 95 and NT, SunOS and Solaris, and HPUX. Publication# 20420 Amendment/+1 Rev: B Issue Date: June 1998 MACHXL® software is a complete development system for the PC, supporting Vantis' MACH devices. It supports design entry with Boolean and behavioral syntax, state machine syntax and truth tables. Functional simulation and static timing analysis are also included in this easy-touse system. This development system includes high-performance device fitters for all MACH devices. The same fitter technology included in MACHXL software is seamlessly incorporated into third-party tools from leading CAE vendors such as Synario, Viewlogic, Mentor Graphics, Cadence and MINC. Interface kits and MACHXL configurations are also available to support design entry and verification with other leading vendors such as Synopsys, Exemplar, OrCAD, Synplicity and Model Technology. These MACHXL configurations and interfaces accept EDIF 2.0.0 netlists, generate JEDEC files for MACH devices, and create industry-standard SDF, VITAL-compliant VHDL and Verilog output files for design simulation. Vantis offers in-system programming support for MACH devices through its MACHPRO® software enabling MACH device programmability through JTAG compliant ports and easy-to-use PC interface. Additionally, MACHPRO generated vectors work seamlessly with HP3070, GenRad and Teradyne testers to program MACH devices or test them for connectivity. All MACH devices are supported by industry standard programmers available from a number of vendors. These programmer vendors include Advin Systems, BP Microsystems, Data I/O Corporation, Hi-Lo Systems, SMS GmbH, Stag House, and System General. 2 MACH111-5/7/10/12/15 BLOCK DIAGRAM Block A I0-I1/CLK0 I3-I4/CLK2 I/O0 – I/O15 16 16 I/O Cells 16 16 4 4 Macrocells 2 OE 52 x 70 AND Logic Array and Logic Allocator 4 26 Switch Matrix 26 52 x 70 AND Logic Array and Logic Allocator 2 OE 4 4 Macrocells 16 16 2 I/O Cells 16 16 I/O16 – I/O31 Block B CLK3/I5 CLK1/I2 20420B-1 MACH111-5/7/10/12/15 3 CONNECTION DIAGRAM Top View 3 2 I/O28 I/O29 I/O30 I/O31 VCC GND I/O0 5 4 I/O1 I/O2 I/O3 6 1 44 43 42 41 40 39 I/O27 I/O6 8 38 I/O26 I/O7 9 37 I/O25 I0 10 36 I/O24 CLK0/I1 11 35 CLK3/I5 GND 12 34 GND CLK1/I2 13 33 CLK2/I4 I/O8 14 32 I3 I/O9 15 31 I/O23 I/O10 16 30 I/O22 I/O11 17 29 I/O21 Block B 7 I/O5 Block A I/O4 44-Pin PLCC I/O20 I/O19 I/O18 I/O17 I/O16 VCC GND I/O15 I/O14 I/O13 I/O12 18 19 20 21 22 23 24 25 26 27 28 20420B-2 Note: Pin-compatible with the MACH211SP and MACH211. PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output VCC = Supply Voltage 4 MACH111-5/7/10/12/15 CONNECTION DIAGRAM Top View 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 I/O27 I/O26 I/O25 I/O24 CLK3/I5 GND CLK2/I4 I3 I/O23 I/O22 I/O21 I/O12 I/O13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O19 I/O20 12 13 14 15 16 17 18 19 20 21 22 I/O5 I/O6 I/O7 I0 CLK0/I1 GND CLK1/I2 I/O8 I/O9 I/O10 I/O11 Block B Block A 44 43 42 41 40 39 38 37 36 35 34 I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O31 I/O30 I/O29 I/O28 44-Pin TQFP 20420B-3 Note: Pin-compatible with the MACH211SP. PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output VCC = Supply Voltage MACH111-5/7/10/12/15 5 ORDERING INFORMATION Commercial Products Vantis programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: MACH 111 -5 J C FAMILY TYPE MACH = Macro Array CMOS High-Speed OPERATING CONDITIONS C = Commercial (0°C to +70°C) DEVICE NUMBER 111 = 32 Macrocells, 44 Pins, Power-Down option, Bus-Friendly Inputs PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) V = 44-Pin Thin Quad Flat Pack (PQT044) SPEED -5 = 5 ns tPD -7 = 7.5 ns tPD -10 = 10 ns tPD -12 = 12 ns tPD -15 = 15 ns tPD Valid Combinations Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local Vantis sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACH111-5 MACH111-7 MACH111-10 JC, VC MACH111-12 MACH111-15 6 MACH111-5/7/10/12/15 (Com’l) ORDERING INFORMATION Industrial Products Vantis programmable logic products for industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: MACH 111 -7 J I FAMILY TYPE MACH = Macro Array CMOS High-Speed OPERATING CONDITIONS I = Industrial (–40°C to +85°C) DEVICE NUMBER 111 = 32 Macrocells, 44 Pins, Power-Down option, Bus-Friendly Inputs PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) SPEED -7 = 7.5 ns tPD -10 = 10 ns tPD -12 = 12 ns tPD -14 = 14 ns tPD -18 = 18 ns tPD Valid Combinations Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local Vantis sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACH111-7 MACH111-10 MACH111-12 JI MACH111-14 MACH111-18 MACH111-7/10/12/14/18 (Ind) 7 FUNCTIONAL DESCRIPTION The MACH111 consists of two PAL blocks connected by a switch matrix. There are 32 I/O pins and 2 dedicated input pins feeding the switch matrix. These signals are distributed to the two PAL blocks for efficient design implementation. There are four clock pins that can also be used as dedicated inputs. The PAL Blocks Each PAL block in the MACH111 (Figure 1) contains a 64-product-term logic array, a logic allocator, 16 macrocells, and 16 I/O cells. The switch matrix feeds each PAL block with 26 inputs. This makes the PAL block look effectively like an independent “PALCE26V16.” There are four additional output enable product terms in each PAL block. For purposes of output enable, the 16 I/O cells are divided into 2 banks of 8 macrocells. Each bank is allocated two of the output enable product terms. An asynchronous reset product term and an asynchronous preset product term are provided for flip-flop initialization. All flip-flops within the PAL block are initialized together. The Switch Matrix The MACH111 switch matrix is fed by the inputs and feedback signals from the PAL blocks. Each PAL block provides 16 internal feedback signals and 16 I/O feedback signals. The switch matrix distributes these signals back to the PAL blocks in an efficient manner that also provides for high performance. The design software automatically configures the switch matrix when fitting a design into the device. The Product-term Array The MACH111 product-term array consists of 64 product terms for logic use, and 6 special-purpose product terms. Four of the special-purpose product terms provide programmable output enable; one provides asynchronous reset, and one provides asynchronous preset. Two of the output enable product terms are used for the first eight I/O cells; the other two control the last eight macrocells. The Logic Allocator The logic allocator in the MACH111 takes the 64 logic product terms and allocates them to the 16 macrocells as needed. Each macrocell can be driven by up to 12 product terms. The design software automatically configures the logic allocator when fitting the design into the device. Table 1 illustrates which product term clusters are available to each macrocell within a PAL block. Refer to Figure 1 for cluster and macrocell numbers. Table 1. 8 Logic Allocation Output Macrocell Available Clusters Output Macrocell Available Clusters M0 C0, C1 M8 C8, C9 M1 C0, C1, C2 M9 C8, C9, C10 M2 C1, C2, C3 M10 C9, C10, C11 M3 C2, C3, C4 M11 C10, C11, C12 M4 C3, C4, C5 M12 C11, C12, C13 M5 C4, C5, C6 M13 C12, C13, C14 M6 C5, C6, C7 M14 C13, C14, C15 M7 C6, C7 M15 C14, C15 MACH111-5/7/10/12/15 The Macrocell The MACH111 macrocells can be configured as either registered or combinatorial, with programmable polarity. The macrocell provides internal feedback whether configured as registered or combinatorial. The flip-flops can be configured as D-type or T-type, allowing for product-term optimization. The flip-flops can individually select one of four clock pins, which are also available as data inputs. The registers are clocked on the LOW-to-HIGH transition of the clock signal. The flip-flops can also be asynchronously initialized with the common asynchronous reset and preset product terms. The I/O Cell The I/O cell in the MACH111 consists of a three-state output buffer. The three-state buffer can be configured in one of three ways: always enabled, always disabled, or controlled by a product term. If product term control is chosen, one of two product terms may be used to provide the control. The two product terms that are available are common to eight I/O cells. Within each PAL block, two product terms are available for selection by the first eight three-state outputs; two other product terms are available for selection by the last eight three-state outputs. SpeedLocking for Guaranteed Fixed Timing The unique MACH 1 & 2 architecture is designed for high performance—a metric that is met in both raw speed, but even more importantly, guaranteed fixed speed. Using the design of the central switch matrix, the MACH111 product offers the SpeedLocking feature, which allows a stable fixed pin-to-pin delay, independent of logic paths, routing resources and design refits for up to 12 product terms per output. Other non-Vantis CPLDs incur serious timing delays as product terms expand beyond their typical 4 or 5 product-term limits. Speed and SpeedLocking combine for continuous, high performance required in today's demanding designs. Bus-Friendly Inputs and I/Os The MACH111 inputs and I/Os include two inverters in series which loop back to the input. This double inversion reinforces the state of the input and pulls the voltage away from the input threshold voltage. Unlike a pull-up, this configuration cannot cause contention on a bus. For an illustration of this configuration, please turn to the Input/Output Equivalent Schematics section. PCI Compliant The MACH111-5/7/10/12 is fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The MACH111-5/7/10/12’s predictable timing ensures compliance with the PCI AC specifications independent of the design. Power-Down Mode The MACH111 features a programmable low-power mode in which individual signal paths can be programmed as low power. These low-power speed paths will be slightly slower than the non-low-power paths. This feature allows speed critical paths to run at maximum frequency while the rest of the paths operate in the low-power mode, resulting in power savings of up to 50%. Safe for Mixed Supply Voltage System Designs The MACH111 is safe for mixed supply voltage system designs. The 5-V device will not overdrive 3.3-V devices above the output voltage of 3.3 V, while it accepts inputs from other 3.3-V devices. Thus, the MACH111 provides easy-to-use mixed-voltage design compatibility. MACH111-5/7/10/12/15 9 0 4 8 12 16 20 24 28 32 36 40 43 47 51 Output Enable Output Enable Asynchronous Reset Asynchronous Preset M0 Output Macro Cell M1 Output Macro Cell M2 Output Macro Cell M3 Output Macro Cell M4 Output Macro Cell M5 Output Macro Cell 0 C0 I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O C1 C2 C3 C5 C6 Switch Matrix C7 C8 Logic Allocator C4 C9 Output Macro Cell M6 Output Macro Cell M7 Output Macro Cell M8 C10 C11 Output Macro Cell M9 C12 C13 Output Macro Cell M10 C14 C15 63 Output Macro Cell M11 Output Macro Cell M12 Output Macro Cell M13 Output Macro Cell M14 Output Macro Cell CLK M15 2 Output Enable Output Enable 0 4 8 12 16 20 24 28 32 36 40 43 47 51 16 16 20420B-4 Figure 1. 10 MACH111 PAL Block MACH111-5/7/10/12/15 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0°C to +70°C Device Junction Temperature . . . . . . . . . . . . . +150°C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V Supply Voltage with Respect to Ground . . . . . . . . . . . . . . –0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . .–0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. DC Output or I/O Pin Voltage . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0°C to 70°C) . . . . . . . . . 200 mA Str esses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. DC CHARACTERISTICS over COMMERCIAL operating ranges Parameter Symbol Parameter Description Test Conditions Min 2.4 Typ Max Unit VOH Output HIGH Voltage IOH = –3.2 mA, VCC = Min, VIN = VIH or VIL VOL Output LOW Voltage IOL = 16 mA, VCC = Min, VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA IIL Input LOW Current VIN = 0 V, VCC = Max (Note 2) –10 µA V 0.5 V 2.0 V IOZH Off-State Output Leakage Current VOUT = 5.25 V, VCC = Max HIGH VIN = VIH or VIL (Note 2) 10 µA IOZL Off-State Output Leakage Current VOUT = 0 V, VCC = Max LOW VIN = VIH or VIL (Note 2) –10 µA –160 mA ISC ICC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 Supply Current (Static) VCC = 5 V, TA = 25°C, f = 0 MHz (Note 4) 40 mA Supply Current (Active) VCC = 5 V, TA = 25°C, f = 1 MHz (Note 4) 45 mA Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter program in low-power mode. This pattern is programmed in each PAL block and is capable of being enabled and reset. MACH111-5/7/10/12/15 (Com’l) 11 CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Input Capacitance VIN = VCC –0.5 V Output Capacitance VOUT = 2.0 V VCC = 5.0 V, TA = 25°C f = 1 MHz Typ Unit 6 pF 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Paramete r Symbol tPD -5 Parameter Description tS Setup Time from Input, I/O, or Feedback to Clock tH Register Data Hold Time tCO Clock to Output tWL tWH tAR 1/(tS + tCO) -10 -12 Min Max Min Max 5 7.5 Min 10 -15 Max Min Max Unit 12 15 ns D-type 3.5 5.5 6.5 7 10 ns T-type 4 6.5 7.5 8 11 ns 0 3.5 Maximum Frequency Internal Feedback (fCNT) (Note 1) No Feedback Max 0 Clock Width External Feedback fMAX Min Input, I/O, or Feedback to Combinatorial Output -7 0 5 0 6 0 8 ns 10 ns LOW 2.5 3 5 6 6 ns HIGH 2.5 3 5 6 6 ns D-type 143 95 80 66.7 50 MHz T-type 133 87 74 62.5 47.6 MHz D-type 182 133 100 76.9 66.6 MHz T-type 167 125 91 71.4 55.5 MHz 200 166.7 100 83.3 83.3 MHz 1/(tWL + tWH) Asynchronous Reset to Registered Output 7.5 tARW Asynchronous Reset Width (Note 1) 4.5 tARR Asynchronous Reset Recovery Time 4.5 tAP Asynchronous Preset to Registered Output 9.5 5 5 7.5 11 7.5 7.5 9.5 16 12 8 11 20 15 ns 10 16 ns ns 20 ns tAPW Asynchronous Preset Width (Note 1) 4.5 5 7.5 12 15 ns tAPR Asynchronous Preset Recovery Time (Note 1) 4.5 5 7.5 8 10 ns tEA Input, I/O, or Feedback to Output Enable 7.5 9.5 10 12 15 ns tER Input, I/O, or Feedback to Output Disable 7.5 9.5 10 12 15 ns tLP tPD Increase for Powered-down Macrocell (Note 3) 10 10 10 10 10 ns tLPS tS Increase for Powered-down Macrocell (Note 3) 7 7 7 7 7 ns tLPCO tCO Increase for Powered-down Macrocell (Note 3) 3 3 3 3 3 ns tLPEA tEA Increase for Powered-down Macrocell (Note 3) 10 10 10 10 10 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 2. See Switching Test Circuit for test conditions. 3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter. 12 MACH111-5/7/10/12/15 (Com’l) ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . . –65°C to +150°C Industrial (I) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . –55°C to +125°C Device Junction Temperature . . . . . . . . . . . . . +150°C Supply Voltage with Respect to Ground . . . . . . . . . . –0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . .–0.5 V to VCC + 0.5 V Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . –40°C to +85°C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. DC Output or I/O Pin Voltage. . . . . . . . . . . –0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = –40°C to +85°C) . . . . . . 200 mA Str esses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. DC CHARACTERISTICS over INDUSTRIAL operating ranges Parameter Symbol Parameter Description Test Conditions VOH Output HIGH Voltage IOH = –3.2 mA, VCC = Min, VIN = VIH or VIL VOL Output LOW Voltage VIH Input HIGH Voltage IOL = 16 mA, VCC = Min, VIN = VIH or VIL Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage IIH Input HIGH Current IIL Input LOW Current VIN = 5.25 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) ISC ICC Min Typ Max Unit 2.4 V 0.5 2.0 V V Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) –30 0.8 V 10 µA –10 µA 10 µA –10 µA –160 mA Supply Current (Static) VCC = 5 V, TA = 25°C, f = 0 MHz (Note 4) 40 mA Supply Current (Active) VCC = 5 V, TA = 25°C, f = 1 MHz (Note 4) 45 mA Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter program in low-power mode. This pattern is programmed in each PAL block and is capable of being enabled and reset. MACH111-7/10/12/14/18 (Ind) 13 CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Input Capacitance VIN = VCC –0.5 V Output Capacitance VOUT = 2.0 V VCC = 5.0 V, TA = 25°C f = 1 MHz Typ Unit 6 pF 8 pF SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) Parameter Symbol tPD -7 Parameter Description tS Setup Time from Input, I/O, or Feedback to Clock tH Register Data Hold Time tCO Clock to Output tWL tWH tAR 7.5 1/(tS + tCO) -12 -14 -18 Max Min Max Min Max Min Max Unit 10 12 14 18 ns D-type 5.5 6.5 7 8.5 12 ns T-type 6.5 7.5 8 10 13.5 ns 0 5 Maximum Frequency Internal Feedback (fCNT) (Note 1) No Feedback Max Min 0 Clock Width External Feedback fMAX Min Input, I/O, or Feedback to Combinatorial Output -10 0 6 0 8 0 10 ns 12 ns LOW 3 5 6 6 7.5 ns HIGH 3 5 6 6 7.5 ns D-type 95 80 66.7 54 40 MHz T-type 87 74 62.5 50 38 MHz D-type 133 100 76.9 61.5 53 MHz T-type 125 91 71.4 57 44 MHz 166.7 100 83.3 83.3 61.5 MHz 1/(tWL + tWH) Asynchronous Reset to Registered Output 9.5 tARW Asynchronous Reset Width (Note 1) 5 tARR Asynchronous Reset Recovery Time 5 tAP Asynchronous Preset to Registered Output 11 7.5 7.5 9.5 16 12 19.5 14.5 8 11 10 16 24 18 ns 12 19.5 ns ns 24 ns tAPW Asynchronous Preset Width (Note 1) 5 7.5 12 14.5 18 ns tAPR Asynchronous Preset Recovery Time 5 7.5 8 10 12 ns tEA Input, I/O, or Feedback to Output Enable (Note 1) 9.5 10 12 14.5 18 ns tER Input, I/O, or Feedback to Output Disable (Note 1) 9.5 10 12 14.5 18 ns tLP tPD Increase for Powered-down Macrocell (Note 3) 10 10 10 10 10 ns tLPS tS Increase for Powered-down Macrocell (Note 3) 7 7 7 7 7 ns tLPCO tCO Increase for Powered-down Macrocell (Note 3) 3 3 3 3 3 ns tLPEA tEA Increase for Powered-down Macrocell (Note 3) 10 10 10 10 10 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 2. See Switching Test Circuit for test conditions. 3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter. 14 MACH111-7/10/12/14/18 (Ind) TYPICAL CURRENT vs. VOLTAGE (I-V) CHARACTERISTICS VCC = 5.0 V, TA = 25°C IOL (mA) 80 60 40 20 VOL (V) -1.0 -0.8 -0.6 -0.4 -0.2 -20 .2 .4 .6 .8 1.0 -40 -60 -80 Output, LOW 20420B-5 IOH (mA) 25 1 2 3 4 5 VOH (V) -3 -2 -1 -25 -50 -75 -100 -125 -150 Output, HIGH 20420B-6 II (mA) 20 VI (V) -2 -1 -20 1 2 3 4 5 -40 -60 -80 -100 Input MACH111-5/7/10/12/15 20420B-7 15 TYPICAL ICC CHARACTERISTICS VCC = 5 V, TA = 25°C High Speed 150 125 Low Power ICC (mA) 100 75 50 25 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Frequency (MHz) 20420B-6 The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register. 16 MACH111-5/7/10/12/15 TYPICAL THERMAL CHARACTERISTICS Measured at 25°C ambient. These parameters are not tested. Typ Parameter Symbol Parameter Description θjc Thermal impedance, junction to case θja Thermal impedance, junction to ambient θjma TQFP PLCC 11 Thermal impedance, junction to ambient with air flow Unit 15 °C/W 40 24 °C/W 200 lfpm air 35 18 °C/W 400 lfpm air 33 17 °C/W 600 lfpm air 32 16 °C/W 800 lfpm air 31 15 °C/W Plastic θjc Considerations The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the θjc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, θjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. The thermal measurements are taken with components on a six-layer printed circuit board. SWITCHING WAVEFORMS Input, I/O, or Feedback VT tPD Combinatorial Output VT 20420B-7 Combinatorial Output Input, I/O, or Feedback VT tS tWH tH VT Clock Clock tCO Registered Output tWL VT 20420B-8 Registered Output 20420B-9 Clock Width Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. MACH111-5/7/10/12/15 17 SWITCHING WAVEFORMS tARW Input, I/O, or Feedback VT tAR Registered Output VT tARR VT Clock 20420B-10 Asynchronous Reset tAPW Input, I/O, or Feedback VT tAP Registered Output VT tAPR VT Clock 20420B-11 Asynchronous Preset Input, I/O, or Feedback VT tER Outputs tEA VOH – 0.5 V VOL + 0.5 V VT 20420B-12 Output Disable/Enable Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. 18 MACH111-5/7/10/12/15 KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State KS000010-PAL SWITCHING TEST CIRCUIT* 5V S1 R1 Output Test Point R2 CL 20420B-13 Commercial Specification tPD, tCO tEA tER S1 CL R1 R2 300 Ω 390 Ω Measured Output Value Closed Z → H: Open 35 pF Z → L: Closed H → Z: Open L → Z: Closed 1.5 V 5 pF H → Z: VOH – 0.5 V L → Z: VOL + 0.5 V * Switching several outputs simultaneously should be avoided for accurate measurement. MACH111-5/7/10/12/15 19 fMAX PARAMETERS The parameter fMAX is the maximum clock rate at which the device is guaranteed to operate. Because the flexibility inherent in programmable logic devices offers a choice of clocked flip-flop designs, fMAX is specified for three types of synchronous designs. The first type of design is a state machine with feedback signals sent off-chip. This external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest path defining the period is the sum of the clock-to-output time and the input setup time for the external signals (tS + tCO). The reciprocal, fMAX, is the maximum frequency with external feedback or in conjunction with an equivalent speed device. This fMAX is designated “fMAX external.” The second type of design is a single-chip state machine with internal feedback only. In this case, flip-flop inputs are defined by the device inputs and flip-flop outputs. Under these conditions, the period is limited by the internal delay from the flip-flop outputs through the internal feedback and logic to the flip-flop inputs. This fMAX is designated “fMAX internal”. A simple internal counter is a good example of this type of design; therefore, this parameter is sometimes called “fCNT.” The third type of design is a simple data path application. In this case, input data is presented to the flip-flop and clocked through; no feedback is employed. Under these conditions, the period is limited by the sum of the data setup time and the data hold time (tS + tH). However, a lower limit for the period of each fMAX type is the minimum clock period (tWH + tWL). Usually, this minimum clock period determines the period for the third fMAX, designated “fMAX no feedback.” All frequencies except fMAX internal are calculated from other measured AC parameters. fMAX internal is measured directly. CLK CLK (SECOND CHIP) LOGIC tS REGISTER LOGIC tCO tS REGISTER fMAX Internal (fCNT) fMAX External 1/(ts + tCO) CLK LOGIC REGISTER tS fMAX No Feedback; 1/(ts + tH) or 1/(tWH + tWL) 20420B-14 20 MACH111-5/7/10/12/15 ENDURANCE CHARACTERISTICS The MACH families are manufactured using Vantis’ advanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Endurance Characteristics Parameter Symbol tDR N Parameter Description Units 10 Min Pattern Data Retention Time Max Reprogramming Cycles Test Conditions Years Max Storage Temperature 20 Years Max Operating Temperature 100 Cycles Normal Programming Conditions INPUT/OUTPUT EQUIVALENT SCHEMATICS VCC 100 kΩ VCC 1 kΩ ESD Protection Input VCC VCC 100 kΩ 1 kΩ Preload Circuitry Feedback Input I/O MACH111-5/7/10/12/15 20420B-15 21 POWER-UP RESET The MACH devices have been designed with the capability to reset during system power-up. Following power-up, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways VCC can rise to its steady state, two conditions are required to insure a valid power-up reset. These conditions are: 1. The VCC rise must be monotonic. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Symbol Parameter Descriptions tPR Power-Up Reset Time tS Input or Feedback Setup Time tWL Max Unit 10 µs See Switching Characteristics Clock Width LOW VCC Power 4V tPR Registered Output tS Clock tWL 20420B-16 Power-Up Reset Waveform 22 MACH111-5/7/10/12/15 DEVELOPMENT SYSTEMS (subject to change) For more information on the products listed below, please consult the local Vantis sales office. MANUFACTURER SOFTWARE DEVELOPMENT SYSTEMS Vantis Corporation P.O. Box 3755 920 DeGuigne Drive Sunnyvale, CA 94088 (408) 732-0555 or 1(888) 826-8472 (VANTIS2) http://www.vantis.com MACHXL Software Vantis-ABEL Software Vantis-Synario Software Aldec, Inc. 3 Sunset Way, Suite F Henderson, NV 89014 (702) 456-1222 or (800) 487-8743 ACTIVE-CAD Cadence Design Systems 555 River Oaks Pkwy San Jose, CA 95134 (408) 943-1234 or (800) 746-6223 PIC Designer Concept/Composer Synergy Leapfrog/Verilog-XL Exemplar Logic, Inc. 815 Atlantic Avenue, Suite 105 Alameda, CA 94501 (510) 337-3700 Leonardo™ Galileo™ Logic Modeling 19500 NW Gibbs Dr. P.O. Box 310 Beaverton, OR 97075 (800) 346-6335 Mentor Graphics Corp. 8005 S.W. Boeckman Rd. Wilsonville, OR 97070-7777 (800) 547-3000 or (503) 685-7000 SmartModel® Library Design Architect, PLDSynthesis™ II Autologic II Synthesizer, QuickSim Simulator, QuickHDL Simulator MicroSim Corp. 20 Fairbanks Irvine, CA 92718 (714) 770-3022 MicroSim Design Lab PLogic, PLSyn MINC Inc. 6755 Earl Drive, Suite 200 Colorado Springs, CO 80918 (800) 755-FPGA or (719) 590-1155 PLDesigner-XL™ Software Model Technology 8905 S.W. Nimbus Avenue, Suite 150 Beaverton, OR 97008 (503) 641-1340 V-System/VHDL OrCAD, Inc. 9300 S.W. Nimbus Avenue Beaverton, OR 97008 (503) 671-9500 or (800) 671-9505 OrCAD Express Synario® Design Automation 10525 Willows Road N.E. P.O. Box 97046 Redmond, WA 98073-9746 (800) 332-8246 or (206) 881-6444 ABEL™ Synario™ Software MACH111-5/7/10/12/15 23 MANUFACTURER Synopsys 700 E. Middlefield Rd. Mountain View, CA 94040 (415) 962-5000 or (800) 388-9125 SOFTWARE DEVELOPMENT SYSTEMS FPGA or Design Compiler (Requires MINC PLDesigner-XL™) VSS Simulator Synplicity, Inc. 624 East Evelyn Ave. Sunnyvale, CA 94086 (408) 617-6000 Teradyne EDA 321 Harrison Ave. Boston, MA 02118 (800) 777-2432 or (617) 422-2793 Synplify MultiSIM Interactive Simulator LASAR VeriBest, Inc. 6101 Lookout Road, Suite A Boulder, CO 80301 (800) 837-4237 Viewlogic Systems, Inc. 293 Boston Post Road West Marlboro, MA 01752 (800) 873-8439 or (508) 480-0881 MANUFACTURER Acugen Software, Inc. 427-3 Amherst St., Suite 391 Nashua, NH 03063 (603) 881-8821 VeriBest PLD Viewdraw, ViewPLD, Viewsynthesis Speedwave Simulator, ViewSim Simulator, VCS Simulator TEST GENERATION SYSTEM ATGEN™ Test Generation Software iNt GmbH Busenstrasse 6 D-8033 Martinsried, Munich, Germany (87) 857-6667 PLDCheck 90 Vantis is not responsible for any information relating to the products of third parties. The inclusion of such information is not a representation nor an endorsement by Vantis of these products. 24 MACH111-5/7/10/12/15 APPROVED PROGRAMMERS (SUBJECT TO CHANGE) For more information on the products listed below, please consult the local Vantis sales office. MANUFACTURER PROGRAMMER CONFIGURATION Advin Systems, Inc. 1050-L East Duane Ave. Sunnyvale, CA 940 86 (408) 243-7000 or (800) 627-2456 BBS (408) 737-9200 Fax (408) 736-2503 BP Microsystems 1000 N. Post Oak Rd., Suite 225 Houston, TX 77055-7237 (800) 225-2102 or (713) 688-4600 BBS (713) 688-9283 Fax (713) 688-0920 Data I/O Corporation 10525 Willows Road N.E. P.O. Box 97046 Redmond, WA 98073-9746 (800) 426-1045 or (206) 881-6444 BBS (206) 882-3211 Fax (206) 882-1043 Pilot-U40 BP1200 UniSite™ Hi-Lo Systems 4F, No. 2, Sec. 5, Ming Shoh E. Road Taipei, Taiwan (886) 2-764-0215 Fax (886) 2-756-6403 or Tribal Microsystems / Hi-Lo Systems 44388 South Grimmer Blvd. Fremont, CA 94538 (510) 623-8859 BBS (510) 623-0430 Fax (510) 623-9925 SMS GmbH Im Grund 15 88239 Wangen Germany (49) 7522-97280 Fax (49) 7522-972850 or SMS USA 544 Weddell Dr. Suite 12 Sunnyvale, CA 94089 (408) 542-0388 Pilot-U84 BP1400 Model 2900 ALL-07 Sprint Expert Stag House Silver Court Watchmead, Welwyn Garden City Herfordshire UK AL7 1LT 44-1-707-332148 Fax 44-1-707-371503 MVP BP2100 BP2200 Model 3900 AutoSite FLEX-700 Sprint Optima Multisite Stag Quazar MACH111-5/7/10/12/15 25 MANUFACTURER PROGRAMMER CONFIGURATION System General 1603A South Main Street Milpitas, CA 95035 (408) 263-6667 BBS (408) 262-6438 Fax (408) 262-9220 or 3F, No. 1, Alley 8, Lane 45 Bao Shing Road, Shin Diau Taipei, Taiwan (886) 2-917-3005 Fax (886) 2-911-1283 Turpro-1 Turpro-1/FX Turpro-1/TX APPROVED ADAPTER MANUFACTURERS MANUFACTURER California Integration Coordinators, Inc. 656 Main Street Placerville, CA 95667 (916) 626-6168 Fax (916) 626-7740 PROGRAMMER CONFIGURATION MACH/PAL Programming Adapters Emulation Technology, Inc. 2344 Walsh Ave., Bldg. F Santa Clara, CA 95051 (408) 982-0660 Fax (408) 982-0664 Adapt-A-Socket® Programming Adapters APPROVED ON-BOARD ISP PROGRAMMING TOOLS MANUFACTURER PROGRAMMER CONFIGURATION Corelis, Inc. 12607 Hidden Creek Way, Suite H Cerritos, California 70703 (310) 926-6727 JTAGPROG™ Vantis Corporation P.O. Box 3755 920 DeGuigne Drive Sunnyvale, CA 94088 (408) 732-0555 or 1(888) 826-8472 (VANTIS2) http://www.vantis.com MACHPRO® 26 MACH111-5/7/10/12/15 PHYSICAL DIMENSIONS PL 044 44-Pin Plastic Leaded Chip Carrier (measured in inches) .685 .695 .650 .656 .062 .083 .042 .056 Pin 1 I.D. .685 .695 .650 .656 .500 .590 REF .630 .013 .021 .026 .032 .050 REF .009 .015 .090 .120 .165 .180 TOP VIEW SEATING PLANE SIDE VIEW MACH111-5/7/10/12/15 16-038-SQ PL 044 DA78 6-28-94 ae 27 PHYSICAL DIMENSIONS PQT044 44-Pin Thin Quad Flat Pack (measured in millimeters) 44 1 11.80 12.20 9.80 10.20 9.80 10.20 11.80 12.20 11° – 13° 0.95 1.05 1.20 MAX 1.00 REF. 0.30 0.45 0.80 BSC 11° – 13° 16-038-PQT-2 PQT 44 7-11-95 ae Trademarks Copyright 1998 Vantis Corporation. All rights reserved. AMD is a registered trademark of Advanced Micro Devices, Inc. Vantis, the Vantis logo and combinations thereof, SpeedLocking and Bus-Friendly are trademarks, and MACH, MACHXL, MACHPRO and PAL are registered trademarks of Vantis Corporation. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 28 MACH111-5/7/10/12/15