LATTICE MACH110-12JC

FINAL
COM’L: -12/15/20
IND: -14/18/24
MACH110-12/15/20
Lattice Semiconductor
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
■ 44 Pins
■ 32 Outputs
■ 32 Macrocells
■ 32 Flip-flops; 2 clock choices
■ 12 ns tPD Commercial
14 ns tPD Industrial
■ 2 “PAL22V16” Blocks
■ 77 MHz fCNT
■ Pin-compatible with MACH111, MACH210,
MACH211, MACH215
■ 38 Inputs
GENERAL DESCRIPTION
The MACH110 is a member of our high-performance
EE CMOS MACH 1 family. This device has approximately three times the logic macrocell capability of the
popular PAL22V10 without loss of speed.
The MACH110 consists of two PAL blocks interconnected by a programmable switch matrix. The two PAL
blocks are essentially “PAL22V16” structures complete
with product-term arrays and programmable macrocells. The switch matrix connects the PAL blocks to
each other and to all input pins, providing a high degree
of connectivity between the fully-connected PAL blocks.
This allows designs to be placed and routed efficiently.
The MACH110 macrocell provides either registered or
combinatorial outputs with programmable polarity. If a
registered configuration is chosen, the register can be
configured as D-type or T-type to help reduce the
number of product terms. The register type decision can
be made by the designer or by the software. All
macrocells can be connected to an I/O cell. If a buried
macrocell is desired, the internal feedback path from the
macrocell can be used, which frees up the I/O pin for use
as an input.
Publication# 14127 Rev. I
Issue Date: May 1995
Amendment /0
BLOCK DIAGRAM
I0 – I1,
I3 – I4
I/O0 – I/O15
16
16
I/O
Cells
16
16
2
Macrocells
OE
4
44 x 70
AND Logic Array
and
Logic Allocator
22
Switch Matrix
22
44 x 70
AND Logic Array
and
Logic Allocator
2
OE
2
Macrocells
16
16
I/O
Cells
2
16
16
I/O16 – I/O31
2
MACH110-12/15/20
CLK1/I5,
CLK0/I2
14127I-1
CONNECTION DIAGRAM
Top View
I/O0
GND
4
2
3
I/O29
I/O28
I/O2
I/O1
5
I/O31
I/O30
I/O3
6
VCC
I/O4
PLCC
1 44 43 42 41 40
I/O5
I/O6
7
39
I/O27
8
38
I/O7
I0
9
37
I/O26
I/O25
10
I/O24
CLK1/I5
I1
11
36
35
GND
12
34
GND
CLK0/I2
13
33
I4
I/O8
I/O9
14
32
I3
15
31
I/O10
I/O11
16
30
I/O23
I/O22
29
I/O21
17
I/O20
I/O18
I/O19
I/O16
I/O17
GND
VCC
I/O14
I/O15
I/O12
I/O13
18 19 20 21 22 23 24 25 26 27 28
14127I-2
Note:
Pin-compatible with MACH111, MACH210, MACH211, and MACH215.
PIN DESIGNATIONS
CLK/I =
GND =
I
=
I/O =
VCC
Clock or Input
Ground
Input
Input/Output
= Supply Voltage
MACH110-12/15/20
3
ORDERING INFORMATION
Commercial Products
Programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
MACH
110 -12
J
FAMILY TYPE
MACH = Macro Array CMOS High-Speed
OPTIONAL PROCESSING
Blank = Standard Processing
OPERATING CONDITIONS
C = Commercial (0°C to +70°C)
DEVICE NUMBER
110 = 32 Macrocells, 44 Pins
SPEED
-12 = 12 ns tPD
-15 = 15 ns tPD
-20 = 20 ns tPD
PACKAGE TYPE
J = 44-Pin Plastic Leaded
Chip Carrier (PL 044)
Valid Combinations
MACH110-12
MACH110-15
MACH110-20
4
C
JC
Valid Combinations
The Valid Combinations table lists configurations
planned to be supported in volume for this device.
Consult your local sales office to confirm availability
of specific valid combinations and to check on newly
released combinations.
MACH110-12/15/20 (Com’l)
ORDERING INFORMATION
Industrial Products
Programmable logic products for Industrial applications are available with several ordering options. The order number (Valid
Combination) is formed by a combination of:
MACH
110
-14
J
FAMILY TYPE
MACH = Macro Array CMOS High-Speed
OPTIONAL PROCESSING
Blank = Standard Processing
DEVICE NUMBER
110 = 32 Macrocells, 44 Pins
OPERATING CONDITIONS
I = Industrial (–40°C to +85°C)
SPEED
-14 = 14 ns tPD
-18 = 18 ns tPD
-24 = 24 ns tPD
PACKAGE TYPE
J = 44-Pin Plastic Leaded Chip
Carrier (PL 044)
Valid Combinations
MACH110-14
MACH110-18
MACH110-24
I
JI
Valid Combinations
The Valid Combinations table lists configurations
planned to be supported in volume for this device.
Consult your local sales office to confirm availability
of specific valid combinations and to check on newly
released combinations.
MACH110-14/18/25 (Ind)
5
FUNCTIONAL DESCRIPTION
The MACH110 consists of two PAL blocks connected by
a switch matrix. There are 32 I/O pins and 6 dedicated
input pins feeding the switch matrix. These signals are
distributed to the two PAL blocks for efficient design
implementation. There are two clock pins that can also
be used as dedicated inputs.
Table 1. Logic Allocation
Output Macrocell
Available
Clusters
M0
C0, C1
M1
C0, C1, C2
M2
C1, C2, C3
M3
C2, C3, C4
The PAL Blocks
M4
C3, C4, C5
Each PAL block in the MACH110 (Figure 1) contains a
64-product-term logic array, a logic allocator, 16 macrocells and 16 I/O cells. The switch matrix feeds each PAL
block with 22 inputs. This makes the PAL block look
effectively like an independent “PAL22V16”.
M5
C4, C5, C6
M6
C5, C6, C7
M7
C6, C7
M8
C8, C9
M9
C8, C9, C10
There are four additional output enable product terms in
each PAL block. For purposes of output enable, the 16
I/O cells are divided into 2 banks of 8 macrocells. Each
bank is allocated two of the output enable product terms.
M10
C9, C10, C11
M11
C10, C11, C12
M12
C11, C12, C13
M13
C12, C13, C14
An asynchronous reset product term and an asynchronous preset product term are provided for flip-flop
initialization. All flip-flops within the PAL block are
initialized together.
M14
C13, C14, C15
M15
C14, C15
The Switch Matrix
The MACH110 switch matrix is fed by the inputs and
feedback signals from the PAL blocks. Each PAL block
provides 16 internal feedback signals and 16 I/O
feedback signals. The switch matrix distributes these
signals back to the PAL blocks in an efficient manner
that also provides for high performance. The design
software automatically configures the switch matrix
when fitting a design into the device.
The Product-Term Array
The MACH110 product-term array consists of 64
product terms for logic use, and 6 special-purpose
product terms. Four of the special-purpose product
terms provide programmable output enable, one
provides asynchronous reset, and one provides a
synchronous preset. Two of the output enable product
terms are used for the first eight I/O cells; the other two
control the last eight macrocells.
The Logic Allocator
The logic allocator in the MACH110 takes the 64 logic
product terms and allocates them to the 16 macrocells
as needed. Each macrocell can be driven by up to
12 product terms. The design software automatically
configures the logic allocator when fitting the design into
the device.
The Macrocell
The MACH110 macrocells can be configured as either
registered or combinatorial, with programmable polarity. The macrocell provides internal feedback whether
configured as registered or combinatorial. The flip-flops
can be configured as D-type or T-type, allowing for
product-term optimization.
The flip-flops can individually select one of two clock
pins, which are also available as data inputs. The registers are clocked on the LOW-to-HIGH transition of the
clock signal. The flip-flops can also be asynchronously
initialized with the common asynchronous reset and
preset product terms.
The I/O Cell
The I/O cell in the MACH110 consists of a three-state
output buffer. The three-state buffer can be configured
in one of three ways: always enabled, always disabled,
or controlled by a product term. If product term control is
chosen, one of two product terms may be used to
provide the control. The two product terms that are
available are common to eight I/O cells. Within each
PAL block, two product terms are available for selection
by the first eight three-state outputs; two other product
terms are available for selection by the last eight
three-state outputs.
These choices make it possible to use the macrocell as
an output, an input, a bidirectional pin, or a three-state
output for use in driving a bus.
Table 1 illustrates which product term clusters are
available to each macrocell within a PAL block. Refer to
Figure 1 for cluster and macrocell numbers.
6
MACH110-12/15/20
0
4
8
12
16
20
24
28
32
36
40
43
Output Enable
Output Enable
Asynchronous Reset
Asynchronous Preset
M0
Output
Macro
Cell
M1
Output
Macro
Cell
M2
Output
Macro
Cell
M3
Output
Macro
Cell
M4
Output
Macro
Cell
M5
Output
Macro
Cell
0
C0
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
C1
C2
C3
C5
C6
Switch
Matrix
C7
C8
Logic Allocator
C4
C9
Output
Macro
Cell
M6
Output
Macro
Cell
M7
Output
Macro
Cell
M8
C10
C11
Output
Macro
Cell
M9
C12
C13
Output
Macro
Cell
M10
C14
C15
63
Output
Macro
Cell
M11
Output
Macro
Cell
M12
Output
Macro
Cell
M13
Output
Macro
Cell
M14
Output
Macro
Cell
CLK
M15
4
Output Enable
Output Enable
0
4
8
12
16
20
24
28
32
36
40
43
16
16
14127I-3
Figure 1. MACH110 PAL Block
MACH110-12/15/20
7
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature
With Power Applied . . . . . . . . . . . . . –55°C to +125°C
Ambient Temperature (TA)
Operating in Free Air . . . . . . . . . . . . 0°C to +70°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V
Supply Voltage (VCC)
with Respect to Ground . . . . . +4.75 V to +5.25 V
DC Input Voltage . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
Static Discharge Voltage . . . . . . . . . . . . . . . . 2001 V
Latchup Current
(TA = 0°C to 70°C) . . . . . . . . . . . . . . . . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA, VCC = Min
VIN = VIH or VIL
2.4
VOL
Output LOW Voltage
IOL = 16 mA, VCC = Min
VIN = VIH or VIL
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
V
IIH
Input HIGH Current
VIN = 5.25 V, VCC = Max (Note 2)
10
µA
IIL
Input LOW Current
VIN = 0 V, VCC = Max (Note 2)
–10
µA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2)
10
µA
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2)
–10
µA
ISC
Output Short-Circuit Current
VOUT = 0.5 V, VCC = Max (Note 3)
–160
mA
ICC
Supply Current (Typical)
VCC = 5 V, TA=25°C,
f = 25 MHz (Note 4)
V
0.5
2.0
V
V
–30
95
mA
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. Measured with a 16-bit up/down counter program. This pattern is programmed in each PAL block and is capable of being
loaded, enabled, and reset.
8
MACH110-12/15/20 (Com’l)
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Conditions
Typ
Unit
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25°C
6
pF
Output Capacitance
VOUT = 2.0 V
f = 1 MHz
8
pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
Parameter Description
tPD
tS
Min
Input, I/O, or Feedback to Combinatorial
Output (Note 3)
Setup Time from Input, I/O, or Feedback
to Clock
tH
Hold Time
tCO
Clock to Output (Note 3)
tWL
Clock Width
External Feedback 1/(tS + tCO)
Maximum
Frequency
(Note 1)
Internal Feedback (fCNT)
1/(tWL + tWH)
No Feedback
tAR
-15
Min Max
12
-20
Min Max
15
20
Unit
ns
D-type
7
10
13
ns
T-type
8
11
14
ns
0
0
0
ns
8
tWH
fMAX
-12
Max
10
12
ns
LOW
6
6
8
ns
HIGH
6
6
8
ns
D-type
66.7
50
40
MHz
T-type
62.5
47.6
38.5
MHz
D-type
76.9
66.6
47.6
MHz
T-type
71.4
55.5
43.5
MHz
83.3
83.3
62.5
MHz
Asynchronous Reset to Registered Output
16
20
25
ns
tARW
Asynchronous Reset Width (Note 1)
12
15
20
ns
tARR
Asynchronous Reset Recovery Time (Note 1)
8
10
15
ns
tAP
Asynchronous Preset to Registered Output
16
20
25
ns
tAPW
Asynchronous Preset Width (Note 1)
12
15
20
ns
tAPR
Asynchronous Preset Recovery Time (Note 1)
8
10
15
ns
tEA
Input, I/O, or Feedback to Output Enable (Note 3)
12
15
20
ns
tER
Input, I/O, or Feedback to Output Disable (Note 3)
12
15
20
ns
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
2. See Switching Test Circuit, for test conditions.
3. Parameters measured with 16 outputs switching.
MACH110-12/15/20 (Com’l)
9
ABSOLUTE MAXIMUM RATINGS
INDUSTRIAL OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Ambient Temperature (TA)
Operating in Free Air . . . . . . . . . . . . –40°C to +85°C
Ambient Temperature
With Power Applied . . . . . . . . . . . . . –55°C to +125°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . 2001 V
Latchup Current
(TA = –40°C to +85°C) . . . . . . . . . . . . . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.
DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
VOH
Output HIGH Voltage
IOH = –3.2 mA, VCC = Min
VIN = VIH or VIL
2.4
VOL
Output LOW Voltage
IOL = 16 mA, VCC = Min
VIN = VIH or VIL
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
V
IIH
Input HIGH Current
VIN = 5.25 V, VCC = Max (Note 2)
10
µA
IIL
–10
µA
10
µA
–10
µA
–160
mA
Input LOW Current
VIN = 0 V, VCC = Max (Note 2)
IOZH
Off-State Output Leakage
Current HIGH
VOUT= 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2)
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2)
ISC
Output Short-Circuit Current
VOUT = 0.5 V, VCC = Max (Note 3)
ICC
Supply Current (Typical)
VCC = 5 V, TA = 25°C, f = 25 MHz (Note 4)
Typ
Max
Unit
V
0.5
2.0
V
V
–30
95
mA
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of
being loaded, enabled, and reset.
10
MACH110-14/18/20 (Ind)
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Conditions
Input Capacitance
VIN = 2.0 V
Output Capacitance
VOUT = 2.0 V
Typ
Unit
6
pF
8
pF
VCC = 5.0 V, TA = 25°C
f = 1 MHz
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
Parameter
Symbol
Parameter Description
tPD
tS
Min
Input, I/O, or Feedback to Combinatorial
Output (Note 3)
Setup Time from Input, I/O, or Feedback
to Clock
tH
Hold Time
tCO
Clock to Output (Note 3)
tWL
Clock Width
External Feedback 1/(tS + tCO)
Maximum
Frequency
(Note 1)
Internal Feedback (fCNT)
1/(tWL + tWH)
No Feedback
tAR
-18
Min Max
14.5
Asynchronous Reset Width (Note 1)
tARR
Asynchronous Reset Recovery Time (Note 1)
tAP
Asynchronous Preset to Registered Output
24
Unit
ns
D-type
8.5
12
16
ns
T-type
10
13.5
17
ns
0
0
0
ns
12
14.5
ns
LOW
7.5
7.5
10
ns
HIGH
7.5
7.5
10
ns
D-type
53.5
40
32
MHz
T-type
50
38
30
MHz
D-type
61.5
53
38
MHz
T-type
57
44
34.5
MHz
66.5
66.5
50
MHz
Asynchronous Reset to Registered Output
tARW
-24
Min Max
18
10
tWH
fMAX
-14
Max
19.5
24
30
ns
14.5
18
24
ns
10
12
18
ns
19.5
24
30
ns
tAPW
Asynchronous Preset Width (Note 1)
14.5
18
24
ns
tAPR
Asynchronous Preset Recovery Time (Note 1)
10
12
18
ns
tEA
Input, I/O, or Feedback to Output Enable (Note 3)
14.5
18
24
ns
tER
Input, I/O, or Feedback to Output Disable (Note 3)
14.5
18
24
ns
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
2. See Switching Test Circuit, for test conditions.
3. Parameters measured with 16 outputs switching.
MACH110-14/18/20 (Ind)
11
TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS
VCC = 5.0 V, TA = 25°C
IOL (mA)
80
60
40
20
VOL (V)
–1.0 –0.8 –0.6 –0.4 –0.2
–20
.2
.4
.6
.8
1.0
–40
–60
–80
14127I-4
Output, LOW
IOH (mA)
25
1
2
3
4
5
VOH (V)
–3
–2
–1
–25
–50
–75
–100
–125
–150
14127I-5
Output, HIGH
II (mA)
20
VI (V)
–2
–1
–20
1
2
3
4
5
–40
–60
–80
–100
14127I-6
Input
12
MACH110-12/15/20
TYPICAL ICC CHARACTERISTICS
VCC = 5 V, TA = 25°C
150
125
MACH110
100
ICC (mA)
75
50
25
0
0
10
20
30
40
50
60
70
80
90
Frequency (MHz)
14127I-7
The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of
being loaded, enabled, and reset.
Maximum frequency shown uses internal feedback and a D-type register.
MACH110-12/15/20
13
TYPICAL THERMAL CHARACTERISTICS
Measured at 25°C ambient. These parameters are not tested.
Parameter
Symbol
Parameter Description
Typ
PLCC
Unit
θjc
Thermal impedance, junction to case
14
°C/W
θja
Thermal impedance, junction to ambient
39
°C/W
200 lfpm air
33
°C/W
400 lfpm air
30
°C/W
600 lfpm air
27
°C/W
800 lfpm air
25
°C/W
θjma
Thermal impedance, junction to
ambient with air flow
Plastic θjc Considerations
The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The
heat-flow paths in plastic-encapsulated devices are complex, making the θjc measurement relative to a specific location on the
package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the
package. Furthermore, θjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a
constant temperature. Therefore, the measurements can only be used in a similar environment.
14
MACH110-12/15/20
SWITCHING WAVEFORMS
Input, I/O, or
Feedback
VT
tPD
Combinatorial
Output
VT
14127I-8
Combinatorial Output
Input, I/O,
or Feedback
Input, I/O, or
Feedback
VT
tS
VT
tH
tSL
Gate
VT
Clock
tHL
tCO
Registered
Output
VT
tPDL
tGO
Latched
Out
VT
VT
14127I-10
14127I-9
Registered Output
Latched Output (MACH 2, 3, and 4)
tWH
Clock
Gate
VT
tGWS
tWL
14127I-12
14127I-11
Clock Width
Gate Width (MACH 2, 3, and 4)
Registered
Input
VT
tSIR
Input
Register
Clock
Registered
Input
VT
tHIR
Input
Register
Clock
VT
tICO
Combinatorial
Output
VT
14127I-13
Output
Register
Clock
Registered Input (MACH 2 and 4)
VT
tICS
VT
14127I-14
Input Register to Output Register Setup
(MACH 2 and 4)
Notes:
1. VT = 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–4 ns typical.
MACH110-12/15/20
15
SWITCHING WAVEFORMS
Latched
In
VT
tSIL
tHIL
Gate
VT
tIGO
Combinatorial
Output
VT
14127I-15
Latched Input (MACH 2 and 4)
tPDLL
Latched
In
VT
Latched
Out
Input
Latch Gate
VT
tIGOL
tSLL
tIGS
VT
Output
Latch Gate
14127I-16
Latched Input and Output
(MACH 2, 3, and 4)
Notes:
1. VT = 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–4 ns typical.
16
MACH110-12/15/20
SWITCHING WAVEFORMS
tWICH
Clock
Input
Latch
Gate
VT
VT
tWICL
tWIGL
14127I-18
14127I-17
Input Register Clock Width
(MACH 2 and 4)
Input Latch Gate Width
(MACH 2 and 4)
tARW
tAPW
Input, I/O, or
Feedback
Input, I/O,
or Feedback
VT
VT
tAR
Registered
Output
tAP
Registered
Output
VT
VT
tARR
Clock
tAPR
Clock
VT
VT
14127I-19
14127I-20
Asynchronous Reset
Asynchronous Preset
Input, I/O, or
Feedback
VT
tER
Outputs
tEA
VOH - 0.5V
VOL + 0.5V
VT
14127I-21
Output Disable/Enable
Notes:
1. VT = 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–4 ns typical.
MACH110-12/15/20
17
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
“Off” State
KS000010-PAL
SWITCHING TEST CIRCUIT
5V
S1
R1
Output
Test Point
R2
CL
14127I-22
Commercial
Specification
tPD, tCO
tEA
tER
S1
CL
R1
R2
Closed
Measured
Output Value
1.5 V
Z → H: Open
Z → L: Closed
35 pF
H → Z: Open
L → Z: Closed
5 pF
1.5 V
300 Ω
390 Ω
H → Z: VOH – 0.5 V
L → Z: VOL + 0.5 V
*Switching several outputs simultaneously should be avoided for accurate measurement.
18
MACH110-12/15/20
fMAX PARAMETERS
The parameter fMAX is the maximum clock rate at which
the device is guaranteed to operate. Because the flexibility inherent in programmable logic devices offers a
choice of clocked flip-flop designs, fMAX is specified for
three types of synchronous designs.
The first type of design is a state machine with feedback
signals sent off-chip. This external feedback could go
back to the device inputs, or to a second device in a
multi-chip state machine. The slowest path defining the
period is the sum of the clock-to-output time and the input setup time for the external signals (tS + tCO). The reciprocal, fMAX, is the maximum frequency with external
feedback or in conjunction with an equivalent speed device. This fMAX is designated “fMAX external.”
The second type of design is a single-chip state machine with internal feedback only. In this case, flip-flop
inputs are defined by the device inputs and flip-flop outputs. Under these conditions, the period is limited by the
internal delay from the flip-flop outputs through the internal feedback and logic to the flip-flop inputs. This fMAX is
designated “fMAX internal”. A simple internal counter is a
good example of this type of design; therefore, this parameter is sometimes called “fCNT.”
The third type of design is a simple data path application. In this case, input data is presented to the flip-flop
and clocked through; no feedback is employed. Under
these conditions, the period is limited by the sum of the
data setup time and the data hold time (tS + tH). However,
a lower limit for the period of each fMAX type is the minimum clock period (tWH + tWL). Usually, this minimum
clock period determines the period for the third fMAX, designated “fMAX no feedback.”
For devices with input registers, one additional fMAX parameter is specified: fMAXIR. Because this involves no
feedback, it is calculated the same way as fMAX no feedback. The minimum period will be limited either by the
sum of the setup and hold times (tSIR + tHIR) or the sum of
the clock widths (tWICL + tWICH). The clock widths are normally the limiting parameters, so that fMAXIR is specified
as 1/(tWICL + tWICH). Note that if both input and output registers are use in the same path, the overall frequency will
be limited by tICS.
All frequencies except fMAX internal are calculated from
other measured AC parameters. fMAX internal is measured directly.
CLK
CLK
(SECOND
CHIP)
LOGIC
LOGIC
REGISTER
tS
t CO
tS
fMAX Internal (fCNT)
fMAX External; 1/(tS + tCO)
LOGIC
REGISTER
CLK
CLK
REGISTER
REGISTER
tS
tSIR
fMAX No Feedback; 1/(tS + tH) or 1/(tWH + tWL)
LOGIC
tHIR
fMAXIR ; 1/(tSIR + tHIR) or 1/(tWICL + tWICH)
14127I-23
MACH110-12/15/20
19
ENDURANCE CHARACTERISTICS
The MACH families are manufactured using our
advanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in
bipolar parts. As a result, the device can be erased and
reprogrammed, a feature which allows 100% testing at
the factory.
Endurance Characteristics
Parameter
Symbol
tDR
N
20
Parameter Description
Min
Units
Test Conditions
10
Years
Max Storage
Temperature
Min Pattern Data Retention Time
20
Years
Max Operating
Temperature
Max Reprogramming Cycles
100
Cycles
Normal Programming
Conditions
MACH110-12/15/20
INPUT/OUTPUT EQUIVALENT SCHEMATICS
VCC
100 kΩ
1 kΩ
VCC
ESD
Protection
Input
VCC
VCC
100 kΩ
1 kΩ
Preload
Circuitry
Feedback
Input
14127I-24
I/O
MACH110-12/15/20
21
POWER-UP RESET
The MACH devices have been designed with the capability to reset during system power-up. Following powerup, all flip-flops will be reset to LOW. The output state
will depend on the logic polarity. This feature provides
extra flexibility to the designer and is especially valuable
in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the
synchronous operation of the power-up reset and the
Parameter
Symbol
wide range of ways VCC can rise to its steady state, two
conditions are required to insure a valid power-up reset.
These conditions are:
1. The VCC rise must be monotonic.
2. Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Parameter Descriptions
Max
Unit
tPR
Power-Up Reset Time
10
µs
tS
Input or Feedback Setup Time
tWL
Clock Width LOW
See
Switching
Characteristics
VCC
Power
4V
tPR
Registered
Output
tS
Clock
tWL
14127I-25
Power-Up Reset Waveform
22
MACH110-12/15/20
USING PRELOAD AND OBSERVABILITY
In order to be testable, a circuit must be both controllable
and observable. To achieve this, the MACH devices
incorporate register preload and observability.
Preloaded
HIGH
D
In preload mode, each flip-flop in the MACH device can
be loaded from the I/O pins, in order to perform
functional testing of complex state machines. Register
preload makes it possible to run a series of tests from a
known starting state, or to load illegal states and test for
proper recovery. This ability to control the MACH
device’s internal state can shorten test sequences,
since it is easier to reach the state of interest.
Q1
Q
AR
Preloaded
HIGH
The observability function makes it possible to see the
internal state of the buried registers during test by
overriding each register’s output enable and activating
the output buffer. The values stored in output and buried
registers can then be observed on the I/O pins. Without
this feature, a thorough functional test would be
impossible for any designs with buried registers.
D Q2
Q
AR
While the implementation of the testability features is
fairly straightforward, care must be taken in certain
instances to insure valid testing.
One case involves asynchronous reset and preset. If the
MACH registers drive asynchronous reset or preset
lines and are preloaded in such a way that reset or
preset are asserted, the reset or preset may remove the
preloaded data. This is illustrated in Figure 2. Care
should be taken when planning functional tests, so that
states that will cause unexpected resets and presets are
not preloaded.
Another case to be aware of arises in testing combinatorial logic. When an output is configured as combinatorial, the observability feature forces the output into
registered mode. When this happens, all product terms
are forced to zero, which eliminates all combinatorial
data. For a straight combinatorial output, the correct
value will be restored after the preload or observe
function, and there will be no problem. If the function
implements a combinatorial latch, however, it relies on
feedback to hold the correct value, as shown in Figure 3.
As this value may change during the preload or observe
operation, you cannot count on the data being correct
after the operation. To insure valid testing in these
cases, outputs that are combinatorial latches should not
be tested immediately following a preload or observe
sequence, but should first be restored to a known state.
On
Preload
Mode
Off
Q1
AR
Q2
Figure 2. Preload/Reset Conflict
14127I-26
Set
All MACH 2 devices support both preload and
observability.
Contact individual programming vendors in order to
verify programmer support.
Reset
Figure 3. Combinatorial Latch
14127I-27
MACH110-12/15/20
23
PHYSICAL DIMENSIONS*
PL 044
44-Pin Plastic Leaded Chip Carrier (measured in inches)
.685
.695
.650
.656
.042
.056
.062
.083
Pin 1 I.D.
.685
.695
.650
.656
.500 .590
REF .630
.013
.021
.026
.032
.050 REF
.009
.015
TOP VIEW
SEATING PLANE
SIDE VIEW
*For reference only. BSC is an ANSI standard for Basic Space Centering.
28
.090
.120
.165
.180
MACH110-12/15/20
16-038-SQ
PL 044
DA78
6-28-94 ae