GAL26CLV12 Low Voltage E2CMOS PLD Generic Array Logic™ FEATURES Features Functional Block Diagram • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 5 ns Maximum Propagation Delay — Fmax = 200 MHz — 3.5 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology I/CLK INPUT RESET 8 I OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q 8 • 3.3V LOW VOLTAGE 26CV12 ARCHITECTURE — JEDEC-Compatible 3.3V Interface Standard — Inputs and I/O Interface with Standard 5V TTL Devices I • ACTIVE PULL-UPS ON ALL PINS I 8 PROGRAMMABLE AND-ARRAY (122X52) 8 • E2 CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention I I I • TWELVE OUTPUT LOGIC MACROCELLS — Maximum Flexibility for Complex Logic Designs — Programmable Output Polarity I • PRELOAD AND POWER-ON RESET OF ALL REGISTERS — 100% Functional Testability 10 12 12 10 I 8 • APPLICATIONS INCLUDE: — Glue Logic for 3.3V Systems — DMA Control — State Machine Control — High Speed Graphics Processing — Standard Logic Speed Upgrade I 8 I 8 I • ELECTRONIC SIGNATURE FOR IDENTIFICATION 8 I PRESET Description Pin Configuration The GAL26CLV12D, at 5 ns maximum propagation delay time, provides higher performance than its 5V counterpart. The GAL26CLV12D can interface with both 3.3V and 5V signal levels. The GAL26CLV12D is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. 4 I The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. 2 I/O/Q I/O/Q I I/CLK I I I PLCC 28 26 25 5 I VCC I/O/Q 7 GAL26CLV12D I Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. I 23 I/O/Q I/O/Q Top View 9 21 11 19 18 I GND I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q 16 I/O/Q I 14 I 12 I I I/O/Q Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 26clv12_02 1 July 1997 Specifications GAL26CLV12 GAL26CLV12D Ordering Information Commercial Grade Specifications Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package 5 3.5 3.5 130 GAL26CLV12D-5LJ 28-Lead PLCC 7.5 5.5 4.5 130 GAL26CLV12D-7LJ 28-Lead PLCC Part Number Description XXXXXXXX _ XX X X X GAL26CLV12D Device Name Grade Speed (ns) L = Low Power Power Blank = Commercial Package J = PLCC 2 Specifications GAL26CLV12 Output Logic Macrocell (OLMC) The GAL26CLV12D has a variable number of product terms per OLMC. Of the twelve available OLMCs, two OLMCs have access to twelve product terms (pins 20 and 22), two have access to ten product terms (pins 19 and 23), and the other eight OLMCs have eight product terms each. In addition to the product terms available for logic, each OLMC has an additional product term dedicated to output enable control. The GAL26CLV12D has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset (SP). These two product terms are common to all registered OLMCs. The Asynchronous Reset sets all registered outputs to zero any time this dedicated product term is asserted. The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted. The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or registered mode. This allows each output to be individually configured as either active high or active low. NOTE: The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen. A R D 4 TO 1 MUX Q CLK Q SP 2 TO 1 MUX GAL26CLV12D OUTPUT LOGIC MACROCELL (OLMC) Output Logic Macrocell Configurations NOTE: In registered mode, the feedback is from the /Q output of the register, and not from the pin; therefore, a pin defined as registered is an output only, and cannot be used for dynamic I/O, as can the combinatorial pins. Each of the Macrocells of the GAL26CLV12D has two primary functional modes: registered, and combinatorial I/O. The modes and the output polarity are set by two bits (S0 and S1), which are normally controlled by the logic compiler. Each of these two primary modes, and the bit settings required to enable them, are described below and on the following page. COMBINATORIAL I/O In combinatorial mode the pin associated with an individual OLMC is driven by the output of the sum term gate. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either “on” (dedicated output), “off” (dedicated input), or “product-term driven” (dynamic I/O). Feedback into the AND array is from the pin side of the output enable buffer. Both polarities (true and inverted) of the pin are fed back into the AND array. REGISTERED In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMC’s D-type flip-flop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for each OLMC, and can therefore be defined by a logic equation. The D flip-flop’s /Q output is fed back into the AND array, with both the true and complement of the feedback available as inputs to the AND array. 3 Specifications GAL26CLV12 Registered Mode AR AR Q D CLK Q D Q CLK SP Q SP ACTIVE LOW ACTIVE HIGH S0 = 0 S1 = 0 S0 = 1 S1 = 0 Combinatorial Mode ACTIVE LOW ACTIVE HIGH S0 = 1 S1 = 1 S0 = 0 S1 = 1 4 Specifications GAL26CLV12 GAL26CLV12D Logic Diagram/JEDEC Fuse Map PLCC Package Pinout 1 0 4 8 12 16 20 24 28 32 36 40 44 48 ASYNCHRONOUS RESET (TO ALL REGISTERS) 0000 0052 . . . 0468 8 0520 . . . 0936 8 0988 . . . 1404 8 1456 . . . 1872 8 1924 . . . . 2444 10 2496 . . . . . 3120 12 OLMC 3172 . . . . . 3796 12 OLMC 3848 . . . . 4368 10 OLMC 4420 . . . 4836 8 4888 . . . 5304 8 5356 . . . 5772 8 OLMC S0 6344 S1 6345 2 OLMC S0 6346 S1 6347 3 OLMC S0 6348 S1 6349 4 OLMC S0 6350 S1 6351 5 OLMC S0 6352 S1 6353 6 S0 6354 S1 6355 28 27 26 25 24 23 22 8 S0 6356 S1 6357 20 9 S0 6358 S1 6359 10 OLMC S0 6360 S1 6361 11 OLMC S0 6362 S1 6363 12 OLMC S0 6364 S1 6365 13 5824 . . . 6240 8 OLMC S0 6366 S1 6367 14 6292 19 18 17 16 15 SYNCHRONOUS PRESET (TO ALL REGISTERS) 6368, 6369 ... Electronic Signature ... 6430, 6431 Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 M S B L S B 5 Specifications GAL26CLV12 Absolute Maximum Ratings(1) Recommended Operating Conditions Supply voltage VCC .................................... -0.5 to +4.6V Input or I/O voltage applied ....................... -0.5 to +5.6V Off-state output voltage applied ................ -0.5 to +4.6V Storage Temperature ................................. -65 to 150°C Ambient Temperature with Power Applied ......................................... -55 to 125°C Commercial Devices: Ambient Temperature (TA) ............................. 0 to +75°C Supply voltage (VCC) with Respect to Ground ......................... +3.0 to +3.6V 1.Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL VIL VIH IIL1 IIH VOL VOH MIN. TYP.3 MAX. UNITS Input Low Voltage Vss - 0.3 — 0.8 V Input High Voltage 2.0 — 5.25 V I/O High Voltage 2.0 — Vcc+0.5 V PARAMETER CONDITION Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — -100 µA Input or I/O High Leakage Current (Vcc-0.2)V ≤ VIN ≤ VCC — — 10 µA Input Leakage Current Vcc ≤ VIN ≤ 5.25V — — 10 µA I/O Leakage Current Vcc ≤ VIN ≤ 5.25V — — 2 mA Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.4 V IOL = 500µA Vin = VIL or VIH — — 0.2 V IOH = MAX. Vin = VIL or VIH 2.4 — — V Vcc-0.2V — — V Low Level Output Current — — 8 mA High Level Output Current — — -8 mA -15 — -80 mA — 90 130 mA Output High Voltage IOH = -100µA Vin = VIL or VIH IOL IOH IOS2 Output Short Circuit Current COMMERCIAL ICC Operating Power Supply Current VCC = 3.3V VOUT = 0.5V TA= 25°C VIL = 0V VIH = 3.0V Unused Inputs at GND ftoggle = 15MHz Outputs Open 1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 3.3V and TA = 25 °C 6 Specifications GAL26CLV12 AC Switching Characteristics Over Recommended Operating Conditions PARAMETER tpd2 tco2 tcf3 tsu th fmax4 twh4 twl4 ten tdis tar tarw tarr tspr 1) 2) 3) 4) TEST COND1. COM COM -5 -7 DESCRIPTION UNITS MIN. MAX. MIN. MAX. A Input or I/O to Combinational Output 1 5 1 7.5 ns A Clock to Output Delay 1 3.5 1 4.5 ns — Clock to Feedback Delay — 3 — 3 ns — Setup Time, Input or Feedback before Clock↑ 3.5 — 5.5 — ns — Hold Time, Input or Feedback after Clock↑ 0 — 0 — ns A Maximum Clock Frequency with External Feedback, 1/(tsu + tco) 143 — 100 — MHz A Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) 154 — 117 — MHz A Maximum Clock Frequency with No Feedback 200 — 142 — MHz — Clock Pulse Duration, High 2.5 — 3.5 — ns — Clock Pulse Duration, Low 2.5 — 3.5 — ns B Input or I/O to Output Enabled 1 6 1 7.5 ns C Input or I/O to Output Disabled 1 6 1 7.5 ns A Input or I/O to Asynchronous Reset of Register 1 6 1 9 ns — Asynchronous Reset Pulse Duration 5.5 — 7 — ns — Asynchronous Reset to Clock↑ Recovery Time 4 — 5 — ns — Synchronous Preset to Clock↑ Recovery Time 4 — 5 — ns Refer to Switching Test Conditions section. Minimum values for tpd and tco are not 100% tested but established by characterization. Calculated from fmax with internal feedback. Refer to fmax Descriptions section. Refer to fmax Descriptions section. Characterized but not 100% tested. Capacitance (TA = 25°C, f = 1.0 MHz) SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS CI Input Capacitance 8 pF VCC = 3.3V, VI = 0V CI/O I/O Capacitance 8 pF VCC = 3.3V, VI/O = 0V 7 Specifications GAL26CLV12 Switching Waveforms INPUT or I/O FEEDBACK INPUT or I/O FEEDBACK VALID INPUT VALID INPUT ts u t pd th CLK COMBINATORIAL OUTPUT tc o REGISTERED OUTPUT Combinatorial Output 1 / fm a x (external fdbk) Registered Output INPUT or I/O FEEDBACK t dis t en OUTPUT CLK 1 / fm ax (int ern al fd bk ) Input or I/O to Output Enable/Disable t su tc f REGISTERED FEEDBACK fmax with Feedback tw l tw h CLK 1 / fm a x (w/o fdbk) Clock Width INPUT or I/O FEEDBACK DRIVING SP INPUT or I/O FEEDB ACK DRIVI NG AR tsu th tspr CLK tarw CLK tarr tco R E G I S T ER E D OUTPUT REGISTERED OUTPUT tar Synchronous Preset Asynchronous Reset 8 Specifications GAL26CLV12 fmax Descriptions CLK LOGIC ARRAY CLK REGISTER LOGIC ARRAY tsu tco REGISTER fmax with External Feedback 1/(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco. CLK LOGIC ARRAY t cf t pd fmax with Internal Feedback 1/(tsu+tcf) REGISTER Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd. tsu + th fmax with No Feedback Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Switching Test Conditions Input Pulse Levels Input Rise and Fall Times 1.5ns 10% – 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load +1.45V GND to 3.0V TEST POINT FROM OUTPUT (O/Q) UNDER TEST See Figure Output Load Conditions (see figure) Test Condition A B C High Z to Active High at 1.9V High Z to Active Low at 1.0V Active High to High Z at 1.9V Active Low to High Z at 1.0V Z0 = 50Ω, CL = 35pF* *CL includes test fixture and probe capacitance. R1 CL 50Ω 50Ω 50Ω 50Ω 50Ω 35pF 35pF 35pF 35pF 35pF 9 R1 Specifications GAL26CLV12 Electronic Signature Output Register Preload An electronic signature (ES) is provided in every GAL26CLV12D device. It contains 64 bits of reprogrammable memory that can contain user-defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. Security Cell A security cell is provided in every GAL26CLV12D device to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell. The GAL26CLV12D device includes circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing test vectors perform output register preload automatically. Input Buffers Latch-Up Protection GAL26CLV12D devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. GAL26CLV12D devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch. The input and I/O pins on the GAL26CLV12D also have built-in active pull-ups. As a result, floating inputs will float to a TTL high (logic 1). However, Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to an adjacent active input, Vcc, or ground. Doing so will tend to improve noise immunity and reduce Icc for the device. (See equivalent input and I/O schematics on the following page.) Device Programming GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers (see the the GAL Development Tools section). Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle. Typical Input Pull-up Characteristic 0 Input Current (µA) -10 -20 -30 -40 -50 -60 -70 Input Voltage (V) 10 4 3.5 3 2.5 2 1.5 1 0.5 0 -80 Specifications GAL26CLV12 Power-Up Reset Vcc Vcc (min.) t su t wl CLK t pr INTERNAL REGISTER Q - OUTPUT Internal Register Reset to Logic "0" ACTIVE LOW OUTPUT REGISTER Device Pin Reset to Logic "1" ACTIVE HIGH OUTPUT REGISTER Device Pin Reset to Logic "0" Circuitry within the GAL26CLV12D provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1µs MAX). As a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. The timing diagram for power-up is shown below. Because of the asyn- chronous nature of system power-up, some conditions must be met to provide a valid power-up reset of the GAL26CLV12D. First, the Vcc rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements. Input/Output Equivalent Schematics PIN PIN Feedback Vcc Active Pull-up Circuit Active Pull-up Circuit Vcc Vref Tri-State Control Vcc ESD Protection Circuit Vcc Vref Data Output PIN PIN ESD Protection Circuit Typ. Vref = Vcc Typ. Vref = Vcc Typical Input Feedback (To Input Buffer) Typical Output 11 Specifications GAL26CLV12 GAL26CLV12D: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1 0.95 RISE FALL 1.05 Normalized Tsu RISE FALL 1.05 Normalized Tco 1 0.95 3.15 3.3 3.45 3.6 3 3.15 Supply Voltage (V) Normalized Tpd vs Temp 3.3 3.45 3 0.9 25 50 75 100 RISE FALL 1 -25 0 25 50 75 Delta Tpd vs # of Outputs Switching 0 Delta Tpd (ns) 100 RISE FALL 1.2 1.1 1 0.9 0.8 -55 125 -25 Temperature (deg. C) 0 -0.1 -0.1 -0.2 RISE FALL -0.3 -0.2 -0.3 RISE FALL -0.4 -0.4 -0.5 3 4 5 6 7 8 9 10 11 1 2 1 Number of Outputs Switching 3 4 5 6 7 8 9 10 11 1 2 Number of Outputs Switching Delta Tpd vs Output Loading Delta Tco vs Output Loading 20 20 16 16 RISE FALL 12 Delta Tco (ns) Delta Tpd (ns) 2 8 4 0 RISE FALL 12 8 4 0 -4 -4 -8 0 50 100 150 200 250 0 3 00 50 100 150 200 Output Loading (pF) Output Loading (pF) 12 25 50 75 1 00 Temperature (deg. C) Delta Tco vs # of Outputs Switching 0 2 3.6 Normalized Tsu vs Temp 1.1 Temperature (deg. C) 1 3.45 1.3 0.9 -55 125 3.3 Supply Voltage (V) Normalized Tsu Normalized Tco 1 0 3.15 Normalized Tco vs Temp RISE FALL -25 0.9 3.6 1.2 1.1 0.8 -55 1 Supply Voltage (V) 1.3 1.2 RISE FALL 1.1 0.8 0.9 3 Delta Tco (ns) Normalized Tpd 1.2 1.1 0.9 Normalized Tpd Normalized Tsu vs Vcc Normalized Tco vs Vcc 1.1 250 3 00 1 25 Specifications GAL26CLV12 GAL26CLV12D: Typical AC and DC Characteristic Diagrams Vol vs Iol Voh vs Ioh 0.8 3 0.6 0.4 Voh (V) 2.5 Voh (V) Vol (V) Voh vs Ioh 3 1 2 2.9 2.8 1.5 0.2 0 1 0 5 10 15 20 25 0 30 5 10 Iol (mA) 15 20 2.7 0.00 25 1.00 Ioh(mA) Normalized Icc vs Vcc 3.00 4.00 5.00 Ioh(mA) Normalized Icc vs Temp 1.2 2.00 Normalized Icc vs Freq 1.3 1.35 1 0.9 1.2 Normalized Icc Normalized Icc Normalized Icc 1.3 1.1 1.1 1 0.9 1.25 1.2 1.15 1.1 1.05 0.8 3 3.15 3.3 3.45 0.8 -55 3.6 1 -25 Supply Voltage (V) 25 50 88 100 125 Temperature (deg. C) 0 8 10 7 Iik (mA) 6 5 4 3 20 30 40 2 50 1 0 60 0 0.5 1 1.5 2 2.5 3 Vin (V) 3.5 4 4.5 5 -4 -3.5 -3 -2.5 -2 -1.5 Vik (V) 13 -1 -0.5 1 15 25 50 Frequency (MHz) Input Clamp (Vik) Delta Icc vs Vin (1 input) 9 Delta Icc (mA) 0 0 75 1 00