ispLSI® 3320 Device Datasheet June 2010 All Devices Discontinued! Product Change Notification (PCN) #09-10 has been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line ispLSI 3320 Ordering Part Number ispLSI 3320-70LQ ispLSI 3320-100LQ ispLSI 3320-70LB320 ispLSI 3320-100LB320 Product Status Reference PCN Discontinued PCN#09-10 5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347 Internet: http://www.latticesemi.com ispLSI 3320 ® In-System Programmable High Density PLD Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 160 I/O Pins — 14000 PLD Gates — 480 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic Output Routing Pool (ORP) H0 Output Routing Pool (ORP) I0 Output Routing Pool (ORP) Boundary Scan J0 Output Routing Pool (ORP) Output Routing Pool (ORP) G3 F3 G2 G1 G0 F2 F1 F0 E3 D Q D Q H1 E2 OR D Q H3 D Q D Q OR Array Twin GLB E0 D Q D3 D Q D2 I1 D Q I2 D1 I3 D0 C3 Global Routing Pool (GRP) J1 C2 J2 C1 J3 C0 Output Routing Pool (ORP) • ispLSI FEATURES: — 5V In-System Programmable (ISP™) Using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality — Reprogram Soldered Devices for Faster Debugging E1 AND Array • HIGH-PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 100 MHz Maximum Operating Frequency — tpd = 10 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power H2 Output Routing Pool (ORP) A D LL IS C DE O N VIC TI N ES U ED Array Output Routing Pool (ORP) Features • 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE A0 A1 A2 A3 Output Routing Pool (ORP) • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Enhanced Pin Locking Capability — Five Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity — Pin Compatible with ispLSI 3160 B0 B1 B2 B3 Output Routing Pool (ORP) 0139/3320 Description The ispLSI 3320 is a High-Density Programmable Logic Device containing 480 Registers, 160 Universal I/O pins, five Dedicated Clock Input Pins, ten Output Routing Pools (ORP) and a Global Routing Pool (GRP) which allows complete inter-connectivity between all of these elements. The ispLSI 3320 features 5V in-system programmability and in-system diagnostic capabilities. The ispLSI 3320 offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. • ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms The basic unit of logic on the ispLSI 3320 device is the Twin Generic Logic Block (Twin GLB) labelled A0, A1...J3. There are a total of 40 of these Twin GLBs in the ispLSI 3320 device. Each Twin GLB has 24 inputs, a programmable AND array and two OR/Exclusive-OR Arrays, and eight outputs which can be configured to be either combinatorial or registered. All Twin GLB inputs come from the GRP. Copyright © 2003 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 3320_07 1 December 2003 D0 D1 D2 2 D3 E0 E1 A1 G2 A2 G1 A3 G0 Global Routing Pool (GRP) B0 F3 B1 F2 B2 F1 B3 F0 E2 E3 Output Routing Pool (ORP) Output Routing Pool (ORP) Output Routing Pool (ORP) Input Bus Input Bus Input Bus Input Bus Output Routing Pool (ORP) G3 Input Bus A0 Output Routing Pool (ORP) H1 CLK 0 CLK 1 CLK 2 IOCLK 1 IOCLK 0 Output Routing Pool (ORP) Y0 Y1 Y2 Y3 Y4 C3 H3 H2 I/O 76 I/O 77 I/O 78 I/O 79 C2 I0 I/O 72 I/O 73 I/O 74 I/O 75 Input Bus Output Routing Pool (ORP) I/O 68 I/O 69 I/O 70 I/O 71 Input Bus Output Routing Pool (ORP) I/O 64 I/O 65 I/O 66 I/O 67 C1 I1 I/O 60 I/O 61 I/O 62 I/O 63 C0 I2 I/O 56 I/O 57 I/O 58 I/O 59 I/O 28 I/O 29 I/O 30 I/O 31 I3 I/O 52 I/O 53 I/O 54 I/O 55 I/O 24 I/O 25 I/O 26 I/O 27 J0 I/O 48 I/O 49 I/O 50 I/O 51 I/O 20 I/O 21 I/O 22 I/O 23 J1 I/O 44 I/O 45 I/O 46 I/O 47 I/O 16 I/O 17 I/O 18 I/O 19 J2 I/O 40 I/O 41 I/O 42 I/O 43 J3 I/O 36 I/O 37 I/O 38 I/O 39 TOE I/O 32 I/O 33 I/O 34 I/O 35 A D LL IS C DE O N VIC TI N ES U ED I/O 12 I/O 13 I/O 14 I/O 15 Output Routing Pool (ORP) I/O 0 I/O 1 I/O 2 I/O 3 Output Routing Pool (ORP) I/O 8 I/O 9 I/O 10 I/O 11 Input Bus I/O 4 I/O 5 I/O 6 I/O 7 Input Bus GOE0 TMS/MODE TCK/SCLK BSCAN/ispEN I/O 115 I/O 114 I/O 113 I/O 112 I/O 119 I/O 118 I/O 117 I/O 116 I/O 123 I/O 122 I/O 121 I/O 120 I/O 127 I/O 126 I/O 125 I/O 124 I/O 131 I/O 130 I/O 129 I/O 128 I/O 135 I/O 134 I/O 133 I/O 132 I/O 139 I/O 138 I/O 137 I/O 136 I/O 143 I/O 142 I/O 141 I/O 140 I/O 147 I/O 146 I/O 145 I/O 144 I/O 151 I/O 150 I/O 149 I/O 148 I/O 155 I/O 154 I/O 153 I/O 152 I/O 159 I/O 158 I/O 157 I/O 156 GOE1 Specifications ispLSI 3320 Functional Block Diagram Figure 1. ispLSI 3320 Functional Block Diagram Input Bus Boundary Scan TDI/SDI H0 TRST TDO/SDO I/O 111 I/O 110 I/O 109 I/O 108 I/O 107 I/O 106 I/O 105 I/O 104 I/O 103 I/O 102 I/O 101 I/O 100 I/O 99 I/O 98 I/O 97 I/O 96 I/O 95 I/O 94 I/O 93 I/O 92 I/O 91 I/O 90 I/O 89 I/O 88 I/O 87 I/O 86 I/O 85 I/O 84 I/O 83 I/O 82 I/O 81 I/O 80 RESET 0139/3320 Specifications ispLSI 3320 Description (continued) Clocks in the ispLSI 3320 device are provided through five dedicated clock pins. The five pins provide three clocks to the Twin GLBs and two clocks to the I/O cells. All local logic block outputs are brought back into the GRP so they can be connected to the inputs of any other logic block on the device. The device also has 160 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, a registered input, a latched input, an output or a bidirectional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. The table below lists key attributes of the device along with the number of resources available. A D LL IS C DE O N VIC TI N ES U ED An additional feature of the ispLSI 3320 is the Boundary Scan capability, which is composed of cells connected between the on-chip system logic and the device’s input and output pins. All I/O pins have associated boundary scan registers, with 3-state I/O using three boundary scan registers and inputs using one. The 160 I/O cells are grouped into ten sets of 16 bits. Each of these I/O groups is associated with a logic Megablock through the use of the ORP. Each Megablock is able to provide one Product Term Output Enable (PTOE) signal which is globally distributed to all I/O cells. That PTOE signal can be generated within any GLB in the Megablock. Each I/O cell can select one of 12 available OEs (two Global OEs and ten PTOEs). The ispLSI 3320 supports all IEEE 1149.1 mandatory instructions, which include BYPASS, EXTEST and SAMPLE. Key Attributes of the ispLSI 3320 Attribute Four Twin GLBs, 16 I/O cells and one ORP are connected together to make a logic Megablock. The Megablock is defined by the resources that it shares. The outputs of the four Twin GLBs are connected to a set of 16 I/O cells by the ORP. The ispLSI 3320 Device contains ten of these Megablocks. 40 Registers 480 I/O Pins 160 Global Clocks 5 Global OE 2 Test OE The GRP has as its inputs the outputs from all of the Twin GLBs and all of the inputs from the bidirectional I/O cells. All of these signals are made available to the inputs of the Twin GLBs. Delays through the GRP have been equalized to minimize timing skew and logic glitching. Quantity Twin GLBs 1 Table 1-0003/3320 3 Specifications ispLSI 3320 Absolute Maximum Ratings 1 Supply Voltage Vcc ................................................................................ -0.5 to +7.0V Input Voltage Applied ..................................................................... -2.5 to VCC +1.0V Off-State Output Voltage Applied .................................................. -2.5 to VCC +1.0V Storage Temperature ............................................................................. -65 to 150°C A D LL IS C DE O N VIC TI N ES U ED Case Temp. with Power Applied ........................................................... -55 to 125°C Max. Junction Temp. (TJ) with Power Applied (208-Pin PQFP) ...................... 150°C Max. Junction Temp. (TJ) with Power Applied (320-Ball BGA) ........................ 140°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Condition PARAMETER SYMBOL TA VCC VIL VIH Ambient Temperature MIN. MAX. UNITS 0 70 °C 4.75 5.25 V Input Low Voltage 0 0.8 V Input High Voltage 2.0 VCC +1 Supply Voltage V Table 2-0005/3320 Capacitance (TA=25°C,f=1.0 MHz) TYPICAL UNITS I/O Capacitance 10 pf VCC = 5.0V, VI/O = 2.0V Clock Capacitance 11 pf VCC = 5.0V, VY = 2.0V SYMBOL C1 C2 PARAMETER TEST CONDITIONS Table 2-0006/3320 Data Retention Specifications PARAMETER MINIMUM MAXIMUM UNITS 20 – Years 10000 – Cycles Data Retention ispLSI Erase/Reprogram Cycles Table 2-0008/3320 4 Specifications ispLSI 3320 Switching Test Conditions Figure 2. Test Load GND to 3.0V Input Pulse Levels + 5V ≤ 3 ns 10% to 90% Input Rise and Fall Time Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load R1 Device Output See Figure 2 Table 2-0003/3320 3-state levels are measured 0.5V from steady-state active level. Test Point CL* A D LL IS C DE O N VIC TI N ES U ED R2 *CL includes Test Fixture and Probe Capacitance. Output Load conditions (See Figure 2) 0213A TEST CONDITION A B C R1 R2 CL 470Ω 390Ω 35pF Active High ∞ 390Ω 35pF Active Low 470Ω 390Ω 35pF Active High to Z at VOH -0.5V ∞ 390Ω 5pF Active Low to Z at VOL +0.5V 470Ω 390Ω 5pF Table 2 - 0004A DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL VOL VOH IIL IIH IIL-isp IIL-PU IOS1 ICC2, 4 CONDITION PARAMETER 3 MIN. TYP. MAX. UNITS Output Low Voltage IOL= 8 mA – – 0.4 V Output High Voltage IOH = -4 mA 2.4 – – V Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (Max.) – – -10 µA Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC – – 10 µA ispEN Input Low Leakage Current 0V ≤ VIN ≤ VIL – – -150 µA I/O Active Pull-Up Current 0V ≤ VIN ≤ VIL – – -150 µA Output Short Circuit Current VCC = 5V, VOUT = 0.5V – – -200 mA Operating Power Supply Current VIL = 0.0V, VIH = 3.0V, fCLOCK = 1 MHz – 370 – mA 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems Table 2-0007/3320 by tester ground degradation. Characterized but not 100% tested. 2. Measured using twenty 16-bit counters. 3. Typical values are at VCC = 5V and TA= 25°C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC . 5 Specifications ispLSI 3320 External Switching Characteristics1, 2, 3 Over Recommended Operating Conditions 5 PARAMETER DESCRIPTION -100 1 -70 MIN. MAX. MIN. MAX. UNITS A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 10.0 – 15.0 ns A 2 Data Propagation Delay – 13.0 – 18.0 ns A 3 Clock Frequency with Internal Feedback 3 100 – 70.0 – MHz 77.0 – 50.0 – MHz – 4 Clock Frequency with External Feedback ( 1 tsu2 + tco1 ) A D LL IS C DE O N VIC TI N ES U ED tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis ttoeen ttoedis twh twl tsu3 th3 TEST 2 # COND. 1. 2. 3. 4. 5. 4 – 5 Clock Frequency, Maximum Toggle – 6 GLB Reg. Setup Time before Clock, 4 PT Bypass 100 – 83.0 – MHz 6.0 – 9.0 – ns A 7 GLB Reg. Clock to Output Delay, ORP Bypass – 6.0 – 9.0 ns – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 – 0.0 – ns – 9 GLB Reg. Setup Time before Clock 7.0 – 11.0 – ns – 10 GLB Reg. Clock to Output Delay – 7.0 – 10.0 ns – 11 GLB Reg. Hold Time after Clock 0.0 – 0.0 – ns A 12 Ext. Reset Pin to Output Delay – 13.5 – 15.0 ns – 13 Ext. Reset Pulse Duration 6.5 – 12.0 – ns B 14 Input to Output Enable – 18.0 – 21.0 ns C 15 Input to Output Disable – 18.0 – 21.0 ns B 16 Global OE Output Enable – 9.0 – 12.0 ns C 17 Global OE Output Disable – 9.0 – 12.0 ns B 18 Test OE Output Enable – 12.0 – 15.0 ns C 19 Test OE Output Disable – 12.0 – 15.0 ns – 20 Ext. Synchronous Clock Pulse Duration, High 5.0 – 6.0 – ns – 21 Ext. Synchronous Clock Pulse Duration, Low 5.0 – 6.0 – ns – 22 I/O Reg Setup Time before Ext. Synchronous Clock (Y3, Y4) 4.5 – 5.0 – ns – 23 I/O Reg Hold Time after Ext. Sync Clock (Y3, Y4) 0.0 – 0.0 – ns Unless noted otherwise, all parameters use 20 PTXOR path and ORP. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Reference Switching Test Conditions section. 6 Table 2-0030/3320 Specifications ispLSI 3320 Internal Timing Parameters1 Over Recommended Operating Conditions PARAMETER 2 # DESCRIPTION -100 -70 MIN. MAX. MIN. MAX. UNITS Inputs 24 I/O Register Bypass – 1.5 – 3.2 ns 25 I/O Latch Delay – 13.0 – 18.2 ns 7.5 – 9.0 – ns 26 I/O Register Setup Time before Clock A D LL IS C DE O N VIC TI N ES U ED tiobp tiolat tiosu tioh tioco tior 27 I/O Register Hold Time after Clock -3.0 – -4.0 – ns 28 I/O Register Clock to Out Delay – 2.5 – 4.2 ns 29 I/O Register Reset to Out Delay – 2.5 – 4.2 ns 30 GRP Delay – 3.0 – 3.5 ns 31 Feedback Delay – 1.1 – 1.6 ns 32 4 Product Term Bypass Path Delay (Comb.) – 3.5 – 5.3 ns 33 4 Product Term Bypass Path Delay (Reg.) – 3.5 – 3.8 ns 34 1 Product Term/XOR Path Delay – 4.5 – 5.8 ns 35 20 Product Term/XOR Path Delay – 4.5 – 5.8 ns – 5.5 – 7.3 ns – 0.5 – 0.5 ns 38 GLB Register Setup Time before Clock 1.0 – 2.5 – ns 39 GLB Register Hold Time after Clock 4.9 – 6.3 – ns 40 GLB Register Clock to Output Delay – 0.5 – 1.0 ns 41 GLB Register Reset to Output Delay – 1.0 – 1.0 ns 42 GLB Product Term Reset to Register Delay – 7.9 – 11.5 ns 43 GLB Product Term Output Enable to I/O Cell Delay – 9.5 – 9.3 ns 3.2 3.2 4.5 4.5 ns 45 ORP Delay – 1.5 – 2.0 ns 46 ORP Bypass Delay – 0.0 – 0.0 ns GRP tgrp tfeedback GLB t4ptbp t4ptbr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck 36 XOR Adjacent Path Delay 3 37 GLB Register Bypass Delay 44 GLB Product Term Clock Delay ORP torp torpbp 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. 7 Table 2-0036/3320 Specifications ispLSI 3320 Internal Timing Parameters1 Over Recommended Operating Conditions PARAMETER 2 # DESCRIPTION -100 -70 MIN. MAX. MIN. MAX. UNITS Outputs 47 Output Buffer Delay – 2.0 – 3.0 ns 48 Output Buffer Delay, Slew Limited Adder – 12.0 – 13.0 ns 49 I/O Cell OE to Output Enabled – 4.0 – 5.0 ns A D LL IS C DE O N VIC TI N ES U ED tob tobs toen todis 50 I/O Cell OE to Output Disabled – 4.0 – 5.0 ns 51 Clock Delay, Y0 or Y1 or Y2 to Global GLB Clock Line 3.0 3.0 4.0 4.0 ns 52 Clock Delay, Y3 or Y4 to I/O Cell Global Clock Line 3.0 3.0 4.0 4.0 ns 53 Global Reset to GLB and I/O Registers – 9.0 – 9.0 ns 54 Global OE Pad Buffer – 5.0 – 7.0 ns 55 Test OE Pad Buffer – 8.0 – 10.0 ns Clocks tgy0/1/2 tioy3/4 Global Reset tgr tgoe ttoe 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 8 Table 2-0037/3320 Specifications ispLSI 3320 ispLSI 3320 Timing Model I/O Cell GRP GLB Feedback ORP I/O Cell #31 #32 I/O Reg Bypass I/O Pin (Input) #24 #30 Input D Register Q RST #25 - 29 4 PT Bypass GLB Reg Bypass ORP Bypass #33 #37 #46 20 PT XOR Delays GLB Reg Delay ORP Delay D #34 - 36 Q #45 #47, 48 #49, 50 I/O Pin (Output) A D LL IS C DE O N VIC TI N ES U ED #53 GRP RST #53 Reset Y3,4 #38 - 41 #52 Control RE PTs OE #42 - 44 CK #51 Y0,1,2 #54 GOE0,1 #55 TOE 0902/3320 Derivations of tsu, th and tco from the Product Term Clock 1 tsu = = = 2.3 ns = Logic + Reg su - Clock (min) (tiobp + tgrp + t20ptxor) + (tgsu) - (tiobp + tgrp + tptck(min)) (#24+ #30+ #35) + (#38) - (#24+ #30+ #44) (1.5 + 3.0 + 4.5) + (1.0) - (1.5 + 3.0 + 3.2) th = = = 3.6 ns = Clock (max) + Reg h - Logic (tiobp + tgrp + tptck(max)) + (tgh) - (tiobp + tgrp + t20ptxor) (#24+ #30+ #44) + (#39) - (#24+ #30+ #35) (1.5 + 3.0 + 3.2) + (4.9) - (1.5 + 3.0 + 4.5) tco = = = 11.7 ns = Clock (max) + Reg co + Output (tiobp + tgrp + tptck(max)) + (tgco) + (torp + tob) (#24 + #30 + #44) + (#40) + (#45 + #47) (1.5 + 3.0 + 3.2) + (0.5) + (1.5 + 2.0) Table 2-0042/3320 Note: Calculations are based on timing specs for the ispLSI 3320-100L. 9 Specifications ispLSI 3320 Power Consumption Figure 3 shows the relationship between power and operating speed. Power consumption in the ispLSI 3320 device depends on two primary factors: the speed at which the device is operating and the number of product terms used. Figure 3. Typical Device Power Consumption vs fmax 800 ispLSI 3320 ICC (mA) A D LL IS C DE O N VIC TI N ES U ED 700 600 500 400 300 200 0 25 50 75 100 fmax (MHz) Notes: Configuration of 20 16-bit Counters Typical Current at 5V, 25° C ICC can be estimated for the ispLSI 3320 using the following equation: ICC = 60 + (# of PTs * 0.5) + (# of nets * Max. freq * 0.0095) where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max. freq = Highest Clock Frequency to the device The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 0127A/3320 10 Specifications ispLSI 3320 Signal Descriptions Signal Name GOE0, GOE1 Global Output Enable input pins. Description I/O Input/Output Pins – These are the general purpose I/O pins used by the logic array. Test Output Enable pin – This pin tristates all I/O pins when a logic low is driven. RESET Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Y0, Y1, Y2 Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the GLBs on the device. Y3, Y4 Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the I/O cells on the device. A D LL IS C DE O N VIC TI N ES U ED TOE BSCAN/ispEN Input – Dedicated in-system programming enable input pin. When this pin is high, the BSCAN TAP controller pins TMS, TDI, TDO and TCK are enabled. When this pin is brought low, the ISP State Machine control pins MODE, SDI, SDO and SCLK are enabled. High-to-low transition of this pin will put the device in the programming mode and put all I/O pins in the high-Z state. TDI/SDI Input – This pin performs two functions. It is the Test Data input pin when ispEN is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI is also used as one of the two control pins for the ISP State Machine. TCK/SCLK Input – This pin performs two functions. It is the Test Clock input pin when ispEN is logic high. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. TMS/MODE Input – This pin performs two functions. It is the Test Mode Select input pin when ispEN is logic high. When ispEN is logic low, it functions as a pin to control the operation of the ISP State Machine. TRST Input – Test Reset, active low to reset the Boundary Scan State Machine. TDO/SDO Output – This pin performs two functions. When ispEN is logic low, it functions as the pin to read the ISP data. When ispEN is high, it functions as Test Data Out. GND Ground (GND) VCC Vcc 1 NC No Connect. 1. NC pins are not to be connected to any active signals, VCC or GND. 11 Specifications ispLSI 3320 Signal Locations Signal 208-Pin PQFP 320-Ball BGA GOE0, GOE1 133, 134 AD12, AC11 TOE 30 B14 RESET 28 D13 Y0, Y1, Y2, Y3, Y4 132, 130, 129, 128, 127 AA12, AC13, AB13, AA13, AD13 BSCAN/ispEN 27 B12 TDI/SDI 25 C12 TCK/SCLK 24 D12 A D LL IS C DE O N VIC TI N ES U ED TMS/MODE 23 A12 TRST 29 A13 TDO/SDO 185 M4 GND 11, 26, 42, 53, 65, 78, 92, 104, 115, 131, 146, 157, 169, 183, 196, 208 A16, B13, C8, D6, D19, F4, F21, H22, J1, M2, N23, T24, U3, W4, W21, AA6, AA19, AB17, AC12, AD9 VCC 14, 39, 58, 80, 99, 118, 143, 162, 181, 203 B10, B18, C3, D4, D21, G2, K23, R2, V23, AA4, AA21,AC7, AC15 NC1 76, 77, 79, 81, 180, 182, 184 A1, A2, A3, A6, A9, A11, A14, A20, A23, A24, B1, B2, B5, B8, B9, B16, B17, B20, B23, B24, C5, C13, C17, C20, C24, D7, D11, D14, D17, D20, E1, E2, E3, E4, E22, E23, F24, G21, G23, H2, H3, H4, H23, J2, J23, J24, K3, L1, L4, L21, L24, M3, M21, M22, M23, N2, N3, N4, N21, N22, N24, P1, P4, P21, P24, R22, T1, T2, T23, U2, U21, U22, U23, V2, V4, W1, Y2, Y3, Y21, Y22, Y23, Y24, AA5, AA8, AA11, AA14, AA18, AB1, AB5, AB8, AB12, AB20, AC1, AC2, AC5, AC8, AC9, AC16, AC17, AC20, AC23, AC24, AD1, AD2, AD5, AD11, AD14, AD16, AD19, AD22, AD23, AD24 1. NC pins are not to be connected to any active signals, VCC or GND. 12 Specifications ispLSI 3320 I/O Locations PQFP BGA Signal PQFP BGA Signal I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 31 32 33 34 35 36 37 38 40 41 43 44 45 46 47 48 49 50 51 52 54 55 56 57 59 60 61 62 63 64 66 67 68 69 70 71 72 73 74 75 C14 A15 B15 C15 D15 A17 C16 D16 A18 A19 C18 B19 D18 C19 A21 B21 A22 C21 B22 C22 C23 D22 E21 D23 D24 F22 E24 F23 G22 H21 G24 J21 J22 H24 K21 K22 K24 L22 L23 M24 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 I/O 48 I/O 49 I/O 50 I/O 51 I/O 52 I/O 53 I/O 54 I/O 55 I/O 56 I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 I/O 64 I/O 65 I/O 66 I/O 67 I/O 68 I/O 69 I/O 70 I/O 71 I/O 72 I/O 73 I/O 74 I/O 75 I/O 76 I/O 77 I/O 78 I/O 79 82 83 84 85 86 87 88 89 90 91 93 94 95 96 97 98 100 101 102 103 105 106 107 108 109 110 111 112 113 114 116 117 119 120 121 122 123 124 125 126 P23 P22 R24 R23 R21 U24 T22 T21 V24 W24 V22 W23 V21 W22 AA24 AA23 AB24 AA22 AB23 AB22 AC22 AB21 AA20 AC21 AD21 AB19 AD20 AC19 AB18 AA17 AC18 AD18 AA16 AB16 AD17 AA15 AB15 AD15 AB14 AC14 I/O 80 I/O 81 I/O 82 I/O 83 I/O 84 I/O 85 I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 I/O 96 I/O 97 I/O 98 I/O 99 I/O 100 I/O 101 I/O 102 I/O 103 I/O 104 I/O 105 I/O 106 I/O 107 I/O 108 I/O 109 I/O 110 I/O 111 I/O 112 I/O 113 I/O 114 I/O 115 I/O 116 I/O 117 I/O 118 I/O 119 PQFP BGA Signal PQFP BGA 135 136 137 138 139 140 141 142 144 145 147 148 149 150 151 152 153 154 155 156 158 159 160 161 163 164 165 166 167 168 170 171 172 173 174 175 176 177 178 179 AB11 AD10 AC10 AB10 AA10 AD8 AB9 AA9 AD7 AD6 AB7 AC6 AA7 AB6 AD4 AC4 AD3 AB4 AC3 AB3 AB2 AA3 Y4 AA2 AA1 W3 Y1 W2 V3 U4 V1 T4 T3 U1 R4 R3 R1 P3 P2 N1 I/O 120 I/O 121 I/O 122 I/O 123 I/O 124 I/O 125 I/O 126 I/O 127 I/O 128 I/O 129 I/O 130 I/O 131 I/O 132 I/O 133 I/O 134 I/O 135 I/O 136 I/O 137 I/O 138 I/O 139 I/O 140 I/O 141 I/O 142 I/O 143 I/O 144 I/O 145 I/O 146 I/O 147 I/O 148 I/O 149 I/O 150 I/O 151 I/O 152 I/O 153 I/O 154 I/O 155 I/O 156 I/O 157 I/O 158 I/O 159 186 187 188 189 190 191 192 193 194 195 197 198 199 200 201 202 204 205 206 207 1 2 3 4 5 6 7 8 9 10 12 13 15 16 17 18 19 20 21 22 M1 L2 L3 K1 K2 K4 H1 J3 J4 G1 F1 G3 F2 G4 F3 D1 D2 C1 D3 C2 B3 C4 D5 B4 A4 C6 A5 B6 C7 D8 B7 A7 D9 C9 A8 D10 C10 A10 C11 B11 A D LL IS C DE O N VIC TI N ES U ED Signal 13 Specifications ispLSI 3320 Pin Configuration 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 GND I/O 139 I/O 138 I/O 137 I/O 136 VCC I/O 135 I/O 134 I/O 133 I/O 132 I/O 131 I/O 130 GND I/O 129 I/O 128 I/O 127 I/O 126 I/O 125 I/O 124 I/O 123 I/O 122 I/O 121 I/O 120 TDO/SDO NC1 GND NC1 VCC NC1 I/O 119 i/O 118 I/O 117 I/O 116 I/O 115 I/O 114 I/O 113 I/O 112 I/O 111 I/O 110 GND I/O 109 I/O 108 I/O 107 I/O 106 I/O 105 I/O 104 VCC I/O 103 I/O 102 I/O 101 I/O 100 GND ispLSI 3320 208-Pin PQFP (with Heat Spreader) Pinout Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 A D LL IS C DE O N VIC TI N ES U ED I/O 140 I/O 141 I/O 142 I/O 143 I/O 144 I/O 145 I/O 146 I/O 147 I/O 148 I/O 149 GND I/O 150 I/O 151 VCC I/O 152 I/O 153 I/O 154 I/O 155 I/O 156 I/O 157 I/O 158 I/O 159 TMS/MODE TCK/SCLK TDI/SDI GND BSCAN/ispEN RESET 1TRST/NC TOE I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 VCC I/O 8 I/O 9 GND I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 ispLSI 3320 GND I/O 20 I/O 21 I/O 22 I/O 23 VCC I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 GND I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 1NC 1NC GND 1NC VCC 1NC I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 I/O 48 I/O 49 GND I/O 50 I/O 51 I/O 52 I/O 53 I/O 54 I/O 55 VCC I/O 56 I/O 57 I/O 58 I/O 59 GND 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Top View 1. NC pins are not to be connected to any active signal, VCC or GND. 208MQUAD/3320 14 I/O 99 I/O 98 I/O 97 I/O 96 I/O 95 I/O 94 I/O 93 I/O 92 I/O 91 I/O 90 GND I/O 89 I/O 88 VCC I/O 87 I/O 86 I/O 85 I/O 84 I/O 83 I/O 82 I/O 81 I/O 80 GOE1 GOE0 Y0 GND Y1 Y2 Y3 Y4 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 VCC I/O 71 I/O 70 GND I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 I/O 63 I/O 62 I/O 61 I/O 60 Specifications ispLSI 3320 Signal Configuration ispLSI 3320 320-Ball BGA Signal Diagram 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 NC1 NC1 I/O 16 I/O 14 B NC1 NC1 I/O 18 I/O 15 C I/O 20 I/O 19 I/O 17 I/O 23 I/O I/O VCC NC1 GND 21 12 NC1 NC1 I/O 9 I/O 8 6 5 4 3 2 1 I/O I/O I/O I/O I/O TMS/ NC1 TRST MODE NC1 157 NC1 154 151 NC1 146 144 NC1 NC1 NC1 A NC1 I/O VCC NC1 NC1 11 I/O I/O I/O I/O I/O ispEN/ I/O TOE GND BSCAN VCC NC1 NC1 NC1 NC1 NC1 2 159 150 147 143 140 B NC1 I/O 13 I/O 6 I/O 3 TDI/ I/O I/O I/O I/O I/O I/O I/O I/O GND NC1 VCC SDI 158 156 153 148 145 139 137 141 C I/O 7 I/O 4 I/O I/O I/O I/O I/O I/O I/O VCC NC1 GND 155 152 149 142 138 136 135 D NC1 NC1 NC1 NC1 E I/O 10 I/O I/O 5 GND 1 7 NC1 I/O 0 NC1 A D LL IS C DE O N VIC TI N ES U ED A 8 D I/O 24 E I/O 26 NC1 NC1 F NC1 I/O 27 I/O GND 25 I/O I/O I/O GND 134 132 130 F G I/O 30 NC1 I/O 28 NC1 I/O I/O I/O VCC 133 131 129 G H I/O 33 I/O NC1 GND 29 I/O 126 H NC1 TCK/ NC1 RESET SCLK NC1 I/O 22 NC1 NC1 NC1 J NC1 NC1 I/O 32 I/O 31 I/O I/O 1 128 127 NC GND J K I/O I/O VCC 36 35 I/O 34 I/O I/O I/O NC1 125 124 123 K L NC1 I/O 38 NC1 I/O I/O NC1 122 121 L M I/O 39 SDO/ I/O 1 TDO NC GND 120 M N NC1 GND NC1 NC1 I/O 119 N NC1 NC1 I/O I/O NC1 117 118 P I/O 44 I/O I/O I/O VCC 116 114 115 R I/O 47 I/O I/O 1 1 111 112 NC NC T NC1 NC1 NC1 I/O I/O GND NC1 109 113 U NC1 I/O I/O NC1 110 108 V GND I/O I/O NC1 105 107 W I/O I/O NC1 NC1 102 106 Y P R T NC1 I/O 42 I/O 37 NC1 ispLSI 3320 NC1 NC1 NC1 I/O 40 I/O 43 GND NC1 I/O 41 NC1 I/O 46 U I/O 45 V I/O I/O VCC 48 50 W I/O 49 Y NC1 NC1 NC1 NC1 I/O 51 Bottom View NC1 NC1 NC1 I/O 52 I/O GND 53 AA I/O 54 I/O 55 I/O I/O VCC GND NC1 57 62 I/O 72 I/O 75 NC1 Y3 Y0 NC1 I/O 84 I/O 87 NC1 I/O I/O I/O I/O GND NC1 VCC 92 101 103 104 AA AB I/O 56 I/O 58 I/O 59 I/O 61 NC1 I/O 65 I/O I/O GND 68 73 I/O 76 I/O 78 Y2 NC1 I/O 80 I/O 83 I/O 86 NC1 I/O 90 AC NC1 NC1 I/O 60 I/O 63 NC1 I/O 67 I/O 70 NC1 NC1 VCC I/O 79 Y1 GND AD NC1 NC1 NC1 I/O 64 I/O NC1 66 I/O 71 I/O 74 NC1 Y4 I/O 69 NC1 I/O 77 GOE I/O 1 82 I/O 93 NC1 I/O 97 I/O 99 I/O NC1 100 AB I/O 91 NC1 I/O 95 I/O 98 NC1 NC1 AC I/O 88 I/O 89 NC1 I/O 94 I/O 96 NC1 NC1 AD 7 6 5 4 3 NC1 NC1 VCC GOE I/O I/O NC1 GND 0 81 85 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 2 1 320BGA/3320 1. NCs are not to be connected to any active signals, Vcc or GND. Note: Ball A1 indicator dot on top side of package. 15 Specifications ispLSI 3320 Part Number Description ispLSI 3320 – XXX X XXXX X Device Family Grade Blank = Commercial Device Number Package Q = PQFP (with Heat Spreader) B320 = BGA A D LL IS C DE O N VIC TI N ES U ED Speed 100 = 100 MHz fmax 70 = 70 MHz fmax Power L = Low 0212A/3320 Ordering Information COMMERCIAL FAMILY ispLSI fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE 100 10 ispLSI 3320-100LQ 208-Pin PQFP 100 10 ispLSI 3320-100LB320 320-Ball BGA 70 15 ispLSI 3320-70LQ 208-Pin PQFP 70 15 ispLSI 3320-70LB320 320-Ball BGA Table 2-0041A/3320 16