TWR-KV31F120M - Freescale Semiconductor

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Revisions
TABLE OF CONTENTS
Notes & Block Diagram
MKV31F512VLL12 (100LQFP)
Power Section
Peripherals
TWRPI Modules
OpenSDA
Elevator Connector
D
Rev
X1
Description
Initial Release
Date
Approved
06/11/2013 Mario Guardado
A
Release to production
07/10/2013 Mario Guardado
AX1
Respin release to CAD
09/20/2013 Mario Guardado
B
Respin release to production
10/02/2013 Mario Guardado
C
Socketless prototype release
01/20/13
D
Mario Guardado
C
C
TWR-KV31F120M
B
B
Microcontroller Solutions Group
A
A
6501 William Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to Freescale Semiconductor and shall not be used for
engineering design, procurement or manufacture in whole or in part without the express written permission
of Freescale Semiconductor.
ICAP Classification:
FCP: ____
FIUO: X
PUBI: ____
Designer:
Drawing Title:
Rafael del Rey
X-TWR-KV31F120M
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Drawn by:
Rafael del Rey
Page Title:
Approved:
Mario Guardado
Size
C
Document Number
Date:
Wednesday, January 22, 2014
TABLE OF CONTENTS
Rev
C
SCH-27959 PDF: SPF-27959
Sheet
1
1
of
9
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1
Power & Ground Nets
1. Unless Otherwise Specified:
All resistors are in ohms
All capacitors are in uF
All voltages are DC
NET
VOLTAGE
P5V_TRG_SDA
5V
Output of USB power switch controlled by the VTRG_EN signal from
the OpenSDA and the ELE_PS_SENSE signal from the TWR elevator
connectors. Goes to regulator input select header.
2. Interrupted lines coded with the same letter or letter
combinations are electrically connected.
D
USB0_VBUS
3. Device type number is for reference only. The number
varies with the manufacturer.
4. Special signal usage:
_B Denotes - Active-Low Signal
<> or [] Denotes - Vectored Signals
5V
SDA_VOUT33
5. Interpret diagram in accordance with American
National Standards Institute specifications, current
revision, with the exception of logic block symbology.
P5V_ELEV
P1V8
V_BRD
VREG_IN
C
Block Diagram
D
USB power from primary elevator Pin A57.
3.3V
Output of OpenSDA's K20 internal regulator to power OpenSDA's circuitry
5V
P3V3_REG
DESCRIPTION
Power to the elevator boards.
3.3V
1.8V
Output of 3.3V regulator or from the Elevator connectors. May also be
supplied externally by connecting to the board voltage select header at
pin 3.
Output of the 1.8V regulator.
1.8 -3.3V
Output of 1.8v or 3.3V regulators as selected by the board voltage select
header. May also be supplied externally by connecting to the board
voltage select header at pin 3.
5V
Power into the on board voltage regulators.
MCU_PWR
1.8-3.3V
MCU digital power. Filtered from V_BRD
MCU_VDD
1.8-3.3V
MCU digital power input after current measurement jumper
VDDA
1.8-3.3V
VDDA power for MCU and analog circuits. Filtered from MCU_PWR.
C
VREFH
3.3V
Upper reference voltage for ADC on the MCU. Filtered from VDDA.
VREFL
0V
Lower reference voltage for ADC on the MCU. Filtered from VSSA.
VSSA
0V
VSSA power for MCU and analog circuits. Filtered from GND.
GND
0V
Digital and Analog Ground.
B
B
A
A
ICAP Classification:
Drawing Title:
FCP: ___
FIUO: X
PUBI: ___
X-TWR-KV31F120M
Page Title:
NOTES & BLOCK DIAGRAM
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Size
C
Document Number
Date:
Wednesday, January 22, 2014
Rev
C
SCH-27959 PDF: SPF-27959
1
Sheet
2
of
9
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1
KV31 - 100LQFP
JTAG_TCLK/EZP_CLK
JTAG_TMS/EZP_DI
pg(3,5,9) SWD_CLK_KV3x
pg(3,5,7,9) SWD_DIO_TGTMCU
PTA[1..17]
3
C529
DNP
8MHz_XTL R559 0
18PF
R556 0
DNP
pg(5,8,9) PTB[0..23]
D
PTB[0..23]
PTA4
PTA5
PTA12
PTA13
PTA14
PTA15
PTA16
PTA17
EXTAL0
XTAL0
PTB9
PTB10
PTB11
SERIAL RX/TX
TX
POKA-YOKE: TX
RX
Place both RX
resistors
with the same orientation
and provide same airgap
between RX to TX resistors
terminals in a square fashion.
PTA4/NMI_b
PTA5
FTM1_CH0/FTM1_QD_PHA
FTM1_CH1/FTM1_QD_PHB
ADC0_SE8/ADC1_SE8
ADC0_SE9/ADC1_SE9
ADC0_SE13
SPI1_PCS1
SPI1_PCS0
SPI1_SCK
pg(5,7) UART0_RX_TGTMCU
pg(5,7) UART0_TX_TGTMCU
PTB18
PTB19 LED3
PTB2
UART0_RTS
PTB20
PTB21
PTB22
PTB23
PTC[0..18]
PTC[0..18]
JTAG_TDI/EZP_DI
JTAG_TDO/EZP_DO
0
DNP
PTC0
PTC1
PTC2
PTC3
PTC4
PTC5
PTC6
PTC7
PTC8
PTC9
C
0 R545
0
R544
53
54
56
57
58
59
UART0_RX_PKYK62
UART0_TX_PKYK 63
64
65
55
66
67
68
69
70
71
72
73
76
77
78
79
80
81
82
83
84
85
86
87
90
91
92
FTM0_CH0
SPI0_PCS1
FTM0_CH3
FTM0_CH2
PTC6/LLWU_P10
ADC1_SE4b
ADC1_SE6b
pg(3,9) ADC1_SE6b
PTC11
PTC12
PTC13
PTC14
PTC15
PTC16
PTC17
PTC18
PTC11/LLWU_P11
26
TP10
PTA0/JTAG_TCLK/SWD_CLK/EZP_CLK/UART0_CTS/UART0_COL/FTM0_CH5/EWM_IN
PTA1/JTAG_TDI/EZP_DI/UART0_RX/FTM0_CH6/CMP0_OUT/FTM2_QD_PHA/FTM1_CH1
PTA2/JTAG_TDO/TRACE_SWO/EZP_DO/UART0_TX/FTM0_CH7/CMP1_OUT/FTM2_QD_PHB/FTM1_CH0
PTA3/JTAG_TMS/SWD_DIO/UART0_RTS/FTM0_CH0/FTM2_FLT0/EWM_OUT
PTA4/LLWU_P3/NMI/EZP_CS/FTM0_CH1/FTM0_FLT3
PTA5/FTM0_CH2/I2S0_TX_BCLK/JTAG_TRST
PTA12/FTM1_CH0/I2S0_TXD0/FTM1_QD_PHA
PTA13/LLWU_P4/FTM1_CH1/I2S0_TX_FS/FTM1_QD_PHB
PTA14/SPI0_PCS0/UART0_TX/I2S0_RX_BCLK
PTA15/SPI0_SCK/UART0_RX/I2S0_RXD0
PTA16/SPI0_SOUT/UART0_CTS/UART0_COL/I2S0_RX_FS
PTA17/ADC1_SE17/SPI0_SIN/UART0_RTS/I2S0_MCLK
PTA18/EXTAL0/FTM0_FLT2/FTM_CLKIN0
PTA19/XTAL0/FTM0_FLT0/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1
24
23
22
U2
PIN FUNCTIONS USED
ADC0_DM0/ADC1_DM3
ADC0_DP0/ADC1_DP3
ADC0_DM1
ADC0_DP1
ADC1_DM0/ADC0_DM3
ADC1_DP0/ADC0_DP3
ADC1_DM1/ADC0_DM2
PTB0/LLWU_P5/ADC0_SE8/ADC1_SE8/I2C0_SCL/FTM1_CH0/FTM1_QD_PHA/UART0_RX
ADC1_DP1/ADC0_DP2
PTB1/ADC0_SE9/ADC1_SE9/I2C0_SDA/FTM1_CH1/FTM0_FLT2/EWM_IN/FTM1_QD_PHB/UART0_TX
PTB3/ADC0_SE13/I2C0_SDA/UART0_CTS/UART0_COL/FTM0_FLT0
DAC0_OUT/CMP1_IN3/ADC0_SE23
PTB9/SPI1_PCS1/UART3_CTS/FBA_AD20
DAC1_OUT/CMP0_IN4/ADC1_SE23
PTB10/ADC1_SE14/SPI1_PCS0/UART3_RX/FBA_AD19/FTM0_FLT1
PTB11/ADC1_SE15/SPI1_SCK/UART3_TX/FBA_AD18/FTM0_FLT2
RESET
PTB16/SPI1_SOUT/UART0_RX/FTM_CLKIN0/FBA_AD17/EWM_IN
PTB17/SPI1_SIN/UART0_TX/FTM_CLKIN1/FBA_AD16/EWM_OUT
PTD0/LLWU_P12/SPI0_PCS0/UART2_RTS/FTM3_CH0/FBA_ALE/FBA_CS1/FBA_TS
PTB18/FTM2_CH0/I2S0_TX_BCLK/FBA_AD15/FTM2_QD_PHA
PTD1/ADC0_SE5B/SPI0_SCK/UART2_CTS/FTM3_CH1/FBA_CS0
PTB19/FTM2_CH1/I2S0_TX_FS/FBA_OE/FTM2_QD_PHB
PTD2/LLWU_P13/SPI0_SOUT/UART2_RX/FTM3_CH2/FBA_AD4/I2C0_SCL
PTB2/ADC0_SE12/I2C0_SCL/UART0_RTS/FTM0_FLT1/FTM0_FLT3
PTD3/SPI0_SIN/UART2_TX/FTM3_CH3/FBA_AD3/I2C0_SDA
PTB20/FBA_AD31/CMP0_OUT
PTD4/LLWU_P14/SPI0_PCS1/UART0_RTS/FTM0_CH4/FBA_AD2/EWM_IN/SPI1_PCS0
PTB21/FBA_AD30/CMP1_OUT
PTD5/ADC0_SE6B/SPI0_PCS2/UART0_CTS/UART0_COL/FTM0_CH5/FBA_AD1/EWM_OUT/SPI1_SCK
PTB22/FBA_AD29
PTD6/LLWU_P15/ADC0_SE7B/SPI0_PCS3/UART0_RX/FTM0_CH6/FBA_AD0/FTM0_FLT0/SPI1_SOUT
PTB23/SPI0_PCS5/FBA_AD28
PTD7/UART0_TX/FTM0_CH7/FTM0_FLT1/SPI1_SIN
PTC0/ADC0_SE14/SPI0_PCS4/PDB0_EXTRG/FBA_AD14/FTM0_FLT1/SPI0_PCS0
PTC1/LLWU_P6/ADC0_SE15/SPI0_PCS3/UART1_RTS/FTM0_CH0/FBA_AD13/I2S0_TXD0
PTC2/ADC0_SE4B/CMP1_IN0/SPI0_PCS2/UART1_CTS/FTM0_CH1/FBA_AD12/I2S0_TX_FS
PTC3/LLWU_P7/CMP1_IN1/SPI0_PCS1/UART1_RX/FTM0_CH2/CLKOUT/I2S0_TX_BCLK
PTC4/LLWU_P8/SPI0_PCS0/UART1_TX/FTM0_CH3/FBA_AD11/CMP1_OUT
PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/I2S0_RXD0/FBA_AD10/CMP0_OUT/FTM0_CH2
PTC6/LLWU_P10/CMP0_IN0/SPI0_SOUT/PDB0_EXTRG/I2S0_RX_BCLK/FBA_AD9/I2S0_MCLK/I2C0_SCL
PTC7/CMP0_IN1/SPI0_SIN/I2S0_RX_FS/FBA_AD8/I2C0_SDA
PTC8/ADC1_SE4B/CMP0_IN2/FTM3_CH4/I2S0_MCLK/FBA_AD7
PTC9/ADC1_SE5B/CMP0_IN3/FTM3_CH5/I2S0_RX_BCLK/FBA_AD6/FTM2_FLT0
PTC10/ADC1_SE6B/I2C1_SCL/FTM3_CH6/I2S0_RX_FS/FBA_AD5
PTC11/LLWU_P11/ADC1_SE7B/I2C1_SDA/FTM3_CH7/FBA_RW
PTC12/FBA_AD27/FTM3_FLT0
PTC13/FBA_AD26
PTC14/FBA_AD25
PTC15/FBA_AD24
PTC16/UART3_RX/FBA_CS5/FBA_TSIZ1/FBA_BE23_16_BLS15_8
PTC17/UART3_TX/FBA_CS4/FBA_TSIZ0/FBA_BE31_24_BLS7_0
PTC18/UART3_RTS/FBA_TBST/FBA_CS2/FBA_BE15_8_BLS23_16
VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18
ADC1_SE18
pg(5,6,9) VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18
VREFL
VREFL
PTA1
PTA2
34
35
36
37
38
39
42
43
44
45
46
47
50
51
VDDA
DNP
pg(3,9) ADC0_SE8/ADC1_SE8
pg(3,9) ADC0_SE9/ADC1_SE9
pg(3,9) ADC0_SE13
pg(5,6,8,9)
PIN FUNCTIONS USED
VREFH
NET NAMES
8
30
40
48
61
75
89
0
R557
R554
0
DNP
VREFH
PTE0/CLKOUT32K/ADC1_SE4A/SPI1_PCS1/UART1_TX/I2C1_SDA
PTE1/LLWU_P0/ADC1_SE5A/SPI1_SOUT/UART1_RX/I2C1_SCL/SPI1_SIN
PTE2/LLWU_P1/ADC1_SE6A/SPI1_SCK/UART1_CTS
PTE3/ADC1_SE7A/SPI1_SIN/UART1_RTS/SPI1_SOUT
PTE4/LLWU_P2/SPI1_PCS0/UART3_TX
PTE5/SPI1_PCS2/UART3_RX/FTM3_CH0
PTE6/SPI1_PCS3/UART3_CTS/I2S0_MCLK/FTM3_CH1
PTE16/ADC0_SE4A/SPI0_PCS0/UART2_TX/FTM_CLKIN0/FTM0_FLT3
PTE17/ADC0_SE5A/SPI0_SCK/UART2_RX/FTM_CLKIN1/LPTMR0_ALT3
PTE18/ADC0_SE6A/SPI0_SOUT/UART2_CTS/I2C0_SDA
PTE19/ADC0_SE7A/SPI0_SIN/UART2_RTS/I2C0_SCL
PTE24/ADC0_SE17/FTM0_CH0/I2C0_SCL/EWM_OUT
PTE25/ADC0_SE18/FTM0_CH1/I2C0_SDA/EWM_IN
PTE26/CLKOUT32K
ADC0_DM0/ADC1_DM3
ADC0_DP0/ADC1_DP3
15
14
21
20
ADC1_DM0/ADC0_DM3
ADC1_DP0/ADC0_DP3
1
2
3
4
5
6
7
10
11
12
13
31
32
33
ADC1_DM0/ADC0_DM3
ADC1_DP0/ADC0_DP3
SERIAL RX/TX
TX
POKA-YOKE: TX
RX
Place both RX
resistors
with the same orientation
and provide same airgap
between RX to TX resistors
terminals in a square fashion.
pg(5,6,9)
pg(3,9)
ADC1_DM1 pg(9)
ADC1_DP1 pg(9)
DAC0_OUT/ADC0_SE23
DAC1_OUT/ADC1_SE23
52
93
94
95
96
97
98
99
100
pg(5,6,9)
pg(3,9)
ADC0_DM1 pg(9)
ADC0_DP1 pg(8,9)
17
16
27
28
NET NAMES
ADC0_DM0/ADC1_DM3
ADC0_DP0/ADC1_DP3
DAC0_OUT/ADC0_SE23
pg(6,8,9)
DAC1_OUT/ADC1_SE23
pg(5,6,8,9)
RST_TGTMCU_b pg(3,5,6,7,8,9) PTD[0..7]
INT1/PTD0
I2C0_SCL_PKYK R532
I2C0_SDA_PKYK R533
0 I2C0_SCL
0 I2C0_SDA
FTM0_CH4
FTM0_CH5
FTM0_CH6
LED4/PTD7
UART1_TX_PKYK R536
UART1_RX_PKYK R537
0 LED2/UART1_TX
0 LED1/UART1_RX/SPI1_SOUT
ADC1_SE6a
SPI1_SIN
0 UART3_TX
0 UART3_RX/FTM3_CH0
FTM3_CH1
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
SPI0_SIN
INT2/PTE24
UART3_TX_PKYK R67
UART3_RX_PKYK R65
PTD[0..7]
PTD0
PTD1
PTD2
PTD3
PTD4
PTD5
PTD6
PTD7
PTE[0..26]
pg(5,6,8,9)
PTE[0..26] pg(5,6,8,9)
PTE0
PTE1
PTE2
PTE3
PTE4
PTE5
PTE6
PTE16
PTE17
PTE18
PTE19
PTE24
PTE25
PTE26
CLKOUT32K
C
NOTE TO USER:
In MCU Symbol, UART3
and LPUART0 share pin allocation
9
29
41
49
60
74
88
C528
19
18
VSSA
R558
1.0M
DNP
VDDA
25
HDR_1X3
X501
8.00MHZ
2
MCU_VDD
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
C530
DNP
18PF
1
pg(6,8) CLKIN0
To improve EMC performance
Remove J501 and install
R587 or R588 accordingly R561
CLKIN0
J25
Default: 1-2
3
8MHz_EXTAL Shunt PN: 211-30053
2
1
V_BRD
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
pg(5,8,9) PTA[1..17]
D
CAD NOTE:
Near processor decoupling & filter circuitry
is on page 05 Power Section
MKV31F512VLL12
0.1UF
VSSA
Motor control filters
B
pg(5,8) ADC0_SE8/ADC1_SE8_RC
100
B
R555
C522
220PF
pg(5,8) ADC0_DP0/ADC1_DP3_RC
100
100
100
ADC0_DP0/ADC1_DP3
pg(3,9)
ADC1_DP0/ADC0_DP3
pg(3,9)
ADC0_SE9/ADC1_SE9
pg(3,9)
CC0805_OV
R72
C22
220PF
pg(5,8) ADC0_SE9/ADC1_SE9_RC
pg(3,9)
CC0805_OV
R71
C21
220PF
pg(5,8) ADC1_DP0/ADC0_DP3_RC
ADC0_SE8/ADC1_SE8
CC0805_OV
R549
C516
220PF
CC0805_OV
SHORTING HEADER ON BOTTOM LAYER
Cortex Debug+ETM Connector
MCU_PWR
C18
R64
10.0K
R68
PTA4 EZP_CS_b
0
EZP_CSR_b
DNP
J20
2
1
*Default: no shunt
(Disconnect Target Power)
TGT_PWR
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
JTAG_TMS
JTAG_TCLK
JTAG_TDO
JTAG_TDI
JTAG_RST
SWD_DIO_TGTMCU
100
R534
C505
220PF
pg(3,5,9)
pg(5,8) ADC0_SE13_RC
100
ADC1_SE6b
pg(3,9)
ADC0_SE13
pg(3,9)
CC0805_OV
R547
C513
2200PF
pg(7)
J19
1
3
5
KEY - PIN 7
P5V_TRG_SDA
SWD_CLK_KV3x
SWD_CLK_TGTMCU
A
0.1UF
1
2
J18
DNP
HDR 1X2 TH
MCU_PWR
pg(5,8) ADC1_SE6b_RC
Jumper is shorted by a cut-trace
on bottom layer. Cutting the trace
will effectively isolate the on-board
MCU from the OpenSDA
debug interface.
CC0805_OV
For socket interconnection
EXTAL0
XTAL0
UART0_RX_PKYK
UART0_TX_PKYK
pg(3,5,7,9)
PTA2
PTA1
I2C0_SCL_PKYK
I2C0_SDA_PKYK
UART1_TX_PKYK
UART1_RX_PKYK
UART3_TX_PKYK
UART3_RX_PKYK
RST_TGTMCU_b pg(3,5,6,7,8,9)
R66
0
A
pg(9)
pg(9)
pg(9)
pg(9)
pg(9)
pg(9)
pg(9)
pg(9)
ICAP Classification:
Drawing Title:
FCP: ___
FIUO: X
PUBI: ___
X-TWR-KV31F120M
Page Title:
HDR_19P
MKV31F512VLL12 (100LQFP)
HDR 1X2 TH
5
EXTAL0 pg(9)
XTAL0 pg(9)
UART0_RX_PKYK
UART0_TX_PKYK
I2C0_SCL_PKYK
I2C0_SDA_PKYK
UART1_TX_PKYK
UART1_RX_PKYK
UART3_TX_PKYK
UART3_RX_PKYK
4
3
2
Size
C
Document Number
Date:
Wednesday, January 22, 2014
Rev
C
SCH-27959 PDF: SPF-27959
1
Sheet
3
of
9
5
4
3
2
1
BOARD POWER SELECTOR:
1-3: 3.3 V from regulator (default)
3-5: 1.8 V from regulator
P3V3_REG
D
System Power
D
R35
POLED_R
A
V_BRD
180
P3V3_MOTOR
TP2
Default: 1-3
(Power from
3.3V regulator)
DNP
R37
PU_PO_LED
1
Q1
BC847C
TP3
J1
1
2
3
DNP
VREG_IN
2.7K
HDR TH 1X3
4
U500
USB0_VBUS
1
VREG IN
SELECTOR
C500
C501
0.1UF
10uF
U501
TAB
VIN
OUTPUT
1
IN
GND
MIC2920A-3.3WS
2
OUT
1
3
5
P1V8
TAB
3
J5
C502
10uF
4
3
P1V8
GND
MIC5239-1.8
2
C6
10uF
2
4
6
C7
0.1UF
C9
0.1UF
C11
0.1UF
R36
4.7K
POLED
YEL/GRN
2
P5V_TRG_SDA
D2
POWER ON
TP11
C
Default: 1-2
(Power from OpenSDA USB)
P3V3_REG
C
MSS1P3L
3
D1
A
C13
0.1UF
HDR_2X3
C504
10uF
BOARD POWER
SELECTOR
(See Table)
Note that not all functions of the board will operate at 1.8V.
Also, please check that tower boards used with this board
have the correct I/O voltages when this board is set to 1.8V.
C
C
PWR_MCU
Default: 1-2
(Enable VDDA)
V_BRD
MCU_PWR
J13 *Default: 1-2
TP5
1
2
0
HDR 1X2 TH
Default shunt 1-2
C514
C508
C515
C506
C507
C510
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
TP518
VREFH
SH505
VDDA_HDR
0
MCU_VDD
C518
VDDA
TP519
SH500
1
2
SH1
SH503
J14
HDR 1X2 TH
*Default: 1-2
0
C525
C527
0.1UF
0.01UF
VSSA
0
SH502
0
C524
C520
0.1UF
0.01UF
VREFL
R58
10.0 DNP
For dynamic measurements
CAD NOTE:
Place this circuitry near the processor
B
B
GND LOOP TEST PADS
GND LOOP TEST LOOPS
TP4
TP513
TP501
TP500
TP12
TP1
TP9
CAD NOTE:
Place ground test loops
in the four corners
away from sensitive signals
that might short
with scope probe alligator clips
TP517
A
A
ICAP Classification:
Drawing Title:
FCP: ___
FIUO: X
PUBI: ___
X-TWR-KV31F120M
Page Title:
POWER SECTION
5
4
3
2
Size
C
Document Number
Date:
Wednesday, January 22, 2014
Rev
C
SCH-27959 PDF: SPF-27959
1
Sheet
4
of
9
5
4
3
2
1
V_BRD
R56
180
A LEDRD
A LEDYL
D
R62
180
D3
LED_YELLOW
R69
180
A LEDGR
Resistor allow
18.3mA @ 3.3V
R44
180
A LEDOR
LEDS
D4
RED
D6
ORANGE
OPTIONAL RGB LED
1
R
pg(3,5,8,9)
PTB[0..23]
pg(3,5,6,8,9)
PTD[0..7]
pg(3,5,6,8,9)
PTE[0..26]
C
C
C
C
4
TRI_GR
3
TRI_BL
G
2
PTB[0..23]
D
TRI_RED
D7
YEL/GRN
B
CLV1A-FKB-CJ1M1F1BB7R4S3
D5
PTD[0..7]
Default: 1-2, 3-4, 5-6, 7-8
(Enable LEDs)
PTE[0..26]
J17
1
3
5
7
PTE1
PTE0
PTB19
PTD7
LED_J_PTE1
LED_J_PTE0
LED_J_PTB19
LED_J_PTD7
2
4
6
8
LED_J_PTB19
R59
270 DNP
LED_J_PTD7
R61
1.0K DNP
LED_J_PTE0
R60
330 DNP
HDR_2X4
Female Motor Connector 2x20
C
pg(3,5,8,9)
PTA[1..17]
pg(3,5,8,9)
PTB[0..23]
pg(3,5,6,8,9)
PTC[0..18]
pg(3,5,6,8,9)
PTD[0..7]
pg(3,5,6,8,9)
PTE[0..26]
PTA[1..17]
C
PTB[0..23]
PTC[0..18]
PTD[0..7]
PTE[0..26]
MCTRL_RST
R78
0
MCTRL_PIN6
R76
100
RST_TGTMCU_b pg(3,6,7,8,9)
PTE16
P3V3_MOTOR
J500
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
pg(3,7) UART0_TX_TGTMCU
pg(3,7) UART0_RX_TGTMCU
PTC1
PTC2
PTA13
PTA12
PTE5
PTE6
PTD3
PTD2
PTA1
PTA2
pg(3,9) SWD_CLK_KV3x
pg(3,7,9) SWD_DIO_TGTMCU
JTAG_TCLK/EZP_CLK
JTAG_TMS/EZP_DI
B
PTE16
pg(3,6,9) ADC1_DM0/ADC0_DM3
pg(3,6,9) VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18
100
R54 MCTRL_PIN29
100
100
100
R531 MCTRL_PIN33
R530 MCTRL_PIN35
R527 MCTRL_PIN37
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
PTB18
HDR_2X20
ADC1_SE6b_RC
pg(3,8)
PTA4
ADC0_SE13_RC pg(3,8)
ADC0_SE9/ADC1_SE9_RC
pg(3,8)
ADC0_SE8/ADC1_SE8_RC
ADC1_DP0/ADC0_DP3_RC
ADC0_DP0/ADC1_DP3_RC
pg(3,8)
pg(3,8)
pg(3,8)
ADC0_DM0/ADC1_DM3
DAC1_OUT/ADC1_SE23
pg(3,6,9)
pg(3,6,8,9)
PTC5
PTC4
MCTRL_PIN38
R528
100
PTD4
PTD5
PTB2
MCTRL_PIN40
R524
100
PTE4
B
PUSH BUTTONS
pg(3,5,8,9)
PTA[1..17]
pg(3,5,6,8,9)
PTC[0..18]
pg(3,5,6,8,9)
PTE[0..26]
2
PTA[1..17]
PTC[0..18]
PTE[0..26]
4
PTE25
PTA4
2
4
1
3
SW3
EVQP1K05M
A
1
3
2
4
1
3
SW4
EVQP1K05M
C20
C19
1000PF
1000PF
PTC11
SW2
EVQP1K05M
C17
1000PF
PTC6
2
4
1
3
SW1
EVQP1K05M
C8
1000PF
A
ICAP Classification:
Drawing Title:
FCP: ___
FIUO: X
PUBI: ___
X-TWR-KV31F120M
Page Title:
PERIPHERALS
5
4
3
2
Size
C
Document Number
Date:
Wednesday, January 22, 2014
Rev
C
SCH-27959 PDF: SPF-27959
1
Sheet
5
of
9
5
4
3
V_BRD
VDDA
GENERAL PURPOSE
TWRPI
J15
V_BRD
C14
R43
10.0K
NET NAMES
pg(3,5,8,9)
J7
0.1UF
1
3
5
7
9
11
13
15
17
19
PIN FUNCTIONS USED
ADC1_SE23
DAC1_OUT/ADC1_SE23
VREG_IN
TWRPI_ADC1
TWRPI_ID0
pg(3,5,9) ADC1_DM0/ADC0_DM3
2
4
6
8
10
12
14
16
18
20
GPT_VBRD
2
Default: 1-2
(Remove to measure
1
TWRPI current)
HDR 1X2 TH
R55
0
CON_2X10
D
V_BRD
V_BRD
C15
R52
R39
10.0K
C16
0.1UF
NET NAMES
PIN FUNCTIONS USED
PTD2
NET NAMES
VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18
R49
0 TWRPI_SPI0_SIN
PTC3
PTD0
PTE1
RST_TGTMCU_b
1
3
5
7
9
11
13
15
17
19
TWRPI_I2C0_SCL
PTE19
TWRPI_ID1
PIN FUNCTIONS USED
4.7K
TWRPI_ADC0
ADC1_SE18
TWRPI_SPI0_PCS0
TWRPI_GPIO0
TWRPI_UART_RX
R38
2
4
6
8
10
12
14
16
18
20
PIN FUNCTIONS USED
4.7K
PTD3
TWRPI_I2C0_SDA
TWRPI_SPI0_SOUT
TWRPI_SPI0_SCK
0 TWRPI_GPIO4
NET NAMES
0
0
Not all TWRPI boards will work at 1.8V.
R48 PTE18
R50 PTE17
TWRPI_GPIO1
PTD1
TWRPI_UART_TX
TWRPI_GPIO5
PTE0
PTD7
Check that TWRPI boards will work at 1.8V
before using them with this board when
V_BRD is jumpered for 1.8V.
CON_2X10
VSSA
R40
pg(3,5,6,7,8,9)
Note: The TWRPI connectors are powered
by V_BRD which may be 1.8V or 3.3V.
J6
0.1UF
PTC7
VSSA
V_BRD
1
R53
GPT_VDA
D
2
0 DNP
CLKIN0 pg(3,8)
RST_TGTMCU_b
PTC8
VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18
pg(3,5,9) VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18
ADC0_DM0/ADC1_DM3
pg(3,5,9) ADC0_DM0/ADC1_DM3
PTD[0..7]
C
PTC[0..18]
MMA8451Q ACCELEROMETER /
FXOS87000CQ COMBO ACC + MAGNETOMETER
pg(3,5,6,8,9)
PTD[0..7]
PTD[0..7]
V_BRD
P3V3_REG
R47
0
Default: 1-2
(Enable CLK)
I2C_SCL_SNSR
I2C0_SCL
J9
HDR 1X2 TH
I2C_SDA_SNSR
I2C0_SDA
Default: 1-2
(Enable DATA)
U1
4
6
J12
HDR 1X2 TH
SA0_SNSR
7
V_BRD
BYP_SNSR
R529
10K
J4
2
1
C12
V_BRD
HDR 1X2 TH
J8
INT1
INT2
BYP
NC3
NC8
NC13
NC15
NC16
C4
0.1UF
SA1_FXOS8700CQ
2
1
HDR 1X2 TH
DNP
Default: No Jumper
This jumper can
only be populated with
FXOS8700CQ
option
PTD[0..7]
C10
INT1
11
9
3
8
13
15
16
PTD[0..7]
pg(3,5,6,8,9)
4.7uF
PTE[0..26]
SA0
5
10
12
Default: 1-X
SCL
SDA
GND1
GND2
GND3
2
B
I2C Address
Select
VDD_OPT
DNP
0.1UF
2
1
PTD3
0
C5
0.1UF
2
1
PTD2
R46
1
2
PTC[0..18]
INT2
RSVD3_SNSR
RSVD8_SNSR
1
2
pg(3,5,8,9)
PTE[0..26]
14
PTD[0..7]
1
PTE[0..26]
pg(3,5,6,8,9)
VDD
pg(3,5,6,8,9)
VDDIO
C
R525 0
DNP
RST_FXOS8700CQ
MMA8451Q
/FXOS8700CQ
R42
0
DNP
C503
0.1UF
DNP
R51
10K
PTE[0..26]
pg(3,5,6,8,9)
PTD0
J11
HDR 1X2 TH
PTE24
Default: 1-X
1-2 : Enable ACCELEROMETER
J10
HDR 1X2 TH
Default: 1-X
1-2 : Enable ACCELEROMETER
B
RST_TGTMCU_b pg(3,5,6,7,8,9)
R41
10K
DNP
(Optional for
always run)
Populate these components
to enable FXOS8700CQ
compatibiity
POTENTIOMETER
1
V_BRD
5K
POT_5K
2
3
C3
0.1UF
DAC0_OUT/ADC0_SE23
A
pg(3,8,9)
2
1
R526
A
J3
HDR 1X2 TH
Default: 1-2
(Enable POTENTIOMETER)
ICAP Classification:
Drawing Title:
FCP: ___
FIUO: X
PUBI: ___
X-TWR-KV31F120M
Page Title:
TWRPI MODULES
5
4
3
2
Size
C
Document Number
Date:
Wednesday, January 22, 2014
Rev
C
SCH-27959 PDF: SPF-27959
1
Sheet
6
of
9
5
4
3
2
OpenSDA Interface
P3V3_SDA
RESET
SDA_RST_TGTMCU_J_B
P3V3_SDA
1
V_TGTMCU
U511
1
6
R560
10.0K
DNP
4
U507
VCCA
VCCB
B
A
GND
1
VDD1
C523
10uF
C517
1.0UF
0.1UF
7
GND
VDDA
GND
8
JTAG_TCLK/SWD_CLK/EZP_CLK/TSI0_CH1/PTA0/UART0_CTS/UART0_COL/FTM0_CH5
JTAG_TDI/EZP_DI/TSI0_CH2/PTA1/UART0_RX/FTM0_CH6
JTAG_TDO/TRACE_SWO/EZP_DO/TSI0_CH3/PTA2/UART0_TX/FTM0_CH7
JTAG_TMS/SWD_DIO/TSI0_CH4/PTA3/UART0_RTS/FTM0_CH0
NMI/EZP_CS/TSI0_CH5/PTA4/FTM0_CH1/LLWU_P3
L500
11
J21
MICRO USB AB 5
TC_SDA_USB_ID_TP
5
GND
Jumper is shorted by a cut-trace
on bottom layer. Cutting the trace
will effectively isolate the on-board
RESET from the OpenSDA
debug interface.
SDA_EXTAL
SDA_XTAL
1
X500
C509
22PF
DNP
ADC0_SE8/TSI0_CH0/PTB0/I2C0_SCL/FTM1_CH0/FTM1_QD_PHA/LLWU_P5
ADC0_SE9/TSI0_CH6/PTB1/I2C0_SDA/FTM1_CH1/FTM1_QD_PHB
C512
22PF
DNP
8.00MHZ
20
21
GND
GND
UART1_TX_TGTMCU_R
UART1_RX_TGTMCU_R
P3V3_SDA
R74
4.7K
VSS1
GND
SDA_RST
ADC0_SE15/TSI0_CH14/PTC1/SPI0_PCS3/UART1_RTS/FTM0_CH0/I2S0_TXD0/LLWU_P6
ADC0_SE4B/CMP1_IN0/TSI0_CH15/PTC2/SPI0_PCS2/UART1_CTS/FTM0_CH1/I2S0_TX_FS
CMP1_IN1/PTC3/SPI0_PCS1/UART1_RX/FTM0_CH2/I2S0_TX_BCLK/LLWU_P7
PTC4/SPI0_PCS0/UART1_TX/FTM0_CH3/CMP1_OUT/LLWU_P8
PTC5/SPI0_SCK/LPTMR0_ALT2/I2S0_RXD0/CMP0_OUT/LLWU_P9
CMP0_IN0/PTC6/SPI0_SOUT/PDB0_EXTRG/I2S0_RX_BCLK/I2S0_MCLK/LLWU_P10
CMP0_IN1/PTC7/SPI0_SIN/USB_SOF_OUT/I2S0_RX_FS
1
6
GND
U506A
2
4
B
3
0
UART0_TX_TGTMCU pg(3,5)
Output to system
from Level shifter
5
DIR
GND UART1_RX_TGTMCU_BUF
3
2
A
GND
R539
0
UART0_RX_TGTMCU pg(3,5)
SN74LVC1T45
DNP
GND
GND
P3V3_SDA
7
P3V3_SDA
TP507
V_TGTMCU
Output to system
from Level shifter
74LVC125ADB
TP6
LED GREEN
GND
U506C
R73
330
GND
8
SDA_SPI0_SIN
C
GND
4
VCCA
VCCB
B
C
5
OE
TXB0101
12
P5V_SDA
SDA_SPI0_SCK TP510
0
R538
0
SWD_DIO_TGTMCU pg(3,5,9)
SWD_CLK_TGTMCU pg(3)
U506D
V_TGTMCU
P3V3_SDA
1
6
11
74LVC125ADB
R548
10.0K
DNP
TP512
SDA_USB_P5V_SENSE
R535
GND
SDA_SWD_EN_B
POWER_EN
VTRG_FAULT_B
SWD_DIO_TGTMCU_LVL
3
2
A
GND
74LVC125ADB
SDA_LED
13
29
30
31
32
SWD_DIO_TGTMCU_BUF
9
TP506
TP511
PTD4/SPI0_PCS1/UART0_RTS/FTM0_CH4/EWM_IN/LLWU_P14
ADC0_SE6B/PTD5/SPI0_PCS2/UART0_CTS/UART0_COL/FTM0_CH5/EWM_OUT
ADC0_SE7B/PTD6/SPI0_PCS3/UART0_RX/FTM0_CH6/FTM0_FLT0/LLWU_P15
PTD7/CMT_IRO/UART0_TX/FTM0_CH7/FTM0_FLT1
1
6
10
D8
EPAD
SDA_LED_R
33
C23
0.1UF
GND
A
U502
C
PU/PD LOGIC:
SERIAL INTERFACE
IS ALWAYS RESET
WHEN USB PORT
IS DISCONNECTED
RST_TGTMCU_B pg(3,5,6,8,9)
DNP
U504
VCCA
VCCB
VCC
SDA_SPI0_SOUT
R75
10.0K
Output to system
from Level shifter
0
DNP
R541
P3V3_SDA
V_TGTMCU
0.1UF
SDA_SPI0_RST_B
TP505
SDA_SPI0_CS
TP508
UART1_TX_TGTMCU_R
UART1_RX_TGTMCU_R
SDA_SPI0_SCK
SDA_SPI0_SOUT
SDA_SPI0_SIN
22
23
24
25
26
27
28
R563
SN74LVC1T45
1
14
2
UART1_TX_TGTMCU_BUF
4
B
GND
C511
P5V_SDA
1
6
VCCA
VCCB
A
GND
P3V3_SDA
10.0K
GND
DIR
R542
RESET
GND
3
2
GND
Isolation
Resistors
P3V3_SDA
V_TGTMCU
U505
5
SDA_RST_TGTMCU_B
TP509
SDA_SWD_OE_B
19
2
330 OHM
D
TARGET MCU
INTERFACE
SIGNALS
SDA_RST_TGTMCU_J_B
1
2
J27
DNP
HDR 1X2 TH
3
EXTAL32
XTAL32
TC_EXTAL_TP
TC_XTAL_TP
TP515
TP516
2
2
2
GND
L1
1
17
18
VREGIN
VOUT33
USB0_DM
USB0_DP
10
9
100
RED
GND
GND
C521
2.2UF
U510U4 U5
S2
S4
EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0
XTAL0/PTA19/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1
TP8
1
SDA_USB_CONN_DP
4
33 SDA_USB_DN
33 SDA_USB_DP
1
5V
DD+
ID
3
R553
R552
A SDA_RST_LED
0.1UF
GND
SDA_SWD_EN_B
P5V_SDA
SDA_VOUT33
6
5
4
3
V_TGTMCU
SHORTING HEADER ON BOTTOM LAYER
GND
SDA_USB_CONN_DN
2
G
SDA_USBSHIELD
C526
1.0UF
330 OHM
P5V0_SDA_USB_CONN_VBUS
1
R83
C
EVQ-PE105K
TP514
R551
10.0K
VBAT
2
1
S1
S3
1
D9
C25
SDA_JTAG_TCLK
SDA_JTAG_TDI
SDA_JTAG_TDO
SDA_JTAG_TMS
SDA_SWD_EN_B
12
13
14
15
16
RST Push Button
Bypass
1-2: Default.
2-3: Reset signal direct to the MCU,
to use when OpenSDA is not powered.
SW5
SW1_RST_B
1
2
P3V3_SDA
VSSA
GND
P3V3_SDA
P5V_SDA
You can rename
signal names in
blue/orange
boxes below
according to
your system
GND
J26
HDR TH 1X3
2
GND
R562
2.2K
DNP
3
2
1
2
3
C519
V_TGTMCU
5
TXS0101
P3V3_SDA
D
OE
SWD_CLK_TGTMCU_BUF 4
0603 package
for hand removal
U503
VCCA
VCCB
B
5
DIR
3
2
A
GND
SWD_CLK_TGTMCU_LVL
SN74LVC1T45
R550
15K
DNP
PK20DX128VFM5
GND
OPEN SDA
POWER OUTPUTS
OPEN SDA
INPUT POWER
i path
P3V3_SDA
GND
SDA_VOUT33
SH504
OpenSDA INTERFACE JTAG CONNECTOR
P5V_SDA
(To enable 5v from
USB connector)
P3V3_SDA
P5V_SDA
C24
C26
18PF
DNP
0.1UF
R84
10.0K
J24
P3V3_SDA
1
3
5
7
9
C27
B
2
4
6
8
10
This pullup-pulldown
set defines a default
ON state.
SDA_JTAG_TMS
SDA_JTAG_TCLK
SDA_JTAG_TDO
SDA_JTAG_TDI
SDA_RST
10.0K
R82
GND
U6
1
MIC2005_CSLEW
5
VTRG_EN
(Swap DNP for
default OFF state)
3
R80
15K
DNP
VIN
CSLEW
ENABLE
VOUT
FAULT
GND
GND
POWER_EN
GND
R79
2
P5V_TRG_SDA can provide up to 450mA
(per USB spec) of power at 5VDC
to your system
GND
R81
10.0K
2
B
VTRG_FAULT_B
1
Q2
NTS4001NT1G
SDA_VOUT33 can provide up to 120mA
of power at 3.3VDC to your system
P3V3_SDA
MIC2005-0.8YM6
ACTIVE HIGH
i path
4
3
GND
1.0K
i path
Note: You can power openSDA
with your own power supplies
by replacing this rail
(SDA_VOUT33)
with your 3.3V power supply rail
P5V_TRG_SDA
6
0.1UF
HDR 2X5
0
3.3VDC, 10mA should be provided
to this rail (P3V3_SDA)
in order to power openSDA
module
PWR SWITCH
R77
180K
ELE_PS_SENSE
A signal high
will disable
USB switch
TP7
i path
V_TGTMCU SH506
GND
0
GND
I/O POWER
INPUT
V_BRD
V_BRD is supported
from 1.8V to 5V
Power should be provided
to this rail for the logic
related to your platform I/O
UART1_RX_TGTMCU_BUF
R546
SDA_SPI0_SOUT
R540
SDA_SPI0_SIN
R543
0 SWD_CLK_TGTMCU_BUF
TP_74125_SPARE_EN
OPTIONAL
TOWER SPECIFIC
INTERFACING
CIRCUITRY
0 SWD_DIO_TGTMCU_BUF
DNP
4
DNP
TP503
TP_74125_SPARE_IN
0 SWD_DIO_TGTMCU_BUF
5
74LVC125ADB
U506B
6
TP504
TP_74125_SPARE_OUT
TP502
DNP
(For enablement purposes)
3
Copy this whole page to your schematic.
Update netnames in designed boxes
according to your system net naming.
B
74LVCH1T45
UART1_TX_ELEV
You can entirely remove
the contents in this box
when interfacing openSDA
in a non-Tower system.
VCCB
A
6
GND
J22
4
3
2
1
2
HDR TH 1X3
UART1_RX_ELEV_BUF
GND
V_TGTMCU
U508
P3V3_ELEV1
5
A
VCCA
DIR
GND
3
To implement OpenSDA interface in your system:
V_TGTMCU
U509
P3V3_ELEV1
5
UART1_RX_ELEV
SDA_SPI0_SCK
VCCA
DIR
VCCB
A
B
GND
6
4
2
Jumpers config:
1-2 Elevator UART
2-3 OpenSDA UART (Default)
UART1_TX_ELEV_BUF
J23
HDR TH 1X3
1
2
3
TOWER
INTERFACE
SIGNALS
UART1_TX_TGTMCU_BUF
P3V3_REG
74LVCH1T45
P3V3_ELEV
GND
SH501
0
TWR System
3.3V Supply
A
UART1_TX_ELEV pg(8)
UART1_RX_ELEV pg(8)
TP520
D500
A
P5V_ELEV
C
MSS1P3L
TWR System
5V Supply
C531
10uF
GND
ELE_PS_SENSE pg(8)
If that is the case, please populate
all isolation resistors
P3V3_REG and P5V_ELEV
can provide 3.3V and 5V power
respectively to your TWR system.
ICAP Classification:
Drawing Title:
4
3
FIUO: X
PUBI: ___
OpenSDA Interface
Size
D
Document Number
2
Rev
C
SCH-27959 PDF: SPF-27959
Date:
5
FCP: ___
X-TWR-KV31F120M
Page Title:
Wednesday, January 22, 2014
1
Sheet
7
of
9
5
4
3
2
1
ELEVATOR CONNECTOR
pg(7) ELE_PS_SENSE
PTA[1..17]
pg(3,5,9) PTA[1..17]
D
PTB[0..23]
pg(3,5,9) PTB[0..23]
pg(3,5,6,9)
PTC[0..18]
pg(3,5,6,9)
PTD[0..7]
pg(3,5,6,9)
PTE[0..26]
D
PTC[0..18]
PTD[0..7]
PTE[0..26]
P5V_ELEV
P5V_ELEV
P5V_ELEV
P5V_ELEV
P3V3_REG
P3V3_REG
NET NAMES
PTB11
PTB9
PTB10
PTE1
PTE3
PTB2
PTC0
PTC15
C
PTE26
PTE2
PIN FUNCTIONS USED
SPI1_SCK
R34
R18
R33
R17
R32
SPI1_PCS0
SPI1_SOUT
SPI1_SIN
UART0_RTS
RTC_CLKOUT
ADC1_SE6a
pg(3,6) CLKIN0
pg(3,5) ADC0_SE9/ADC1_SE9_RC
pg(3,5) ADC1_SE6b_RC
pg(3,5) ADC0_SE13_RC
pg(3,5,6,9) DAC1_OUT/ADC1_SE23
PTE6
PTD6
FTM0_CH6
0
0
0
0
0
SPI1_CLK_ELEV_B
SPI1_CS1_ELEV_B
SPI1_CS0_ELEV_B
SPI1_MOSI_ELEV_B
SPI1_MISO_ELEV_B
R16
R31
R15
R30
R14
0
0
0
0
0
UART1_RTS_ELEV
GPIO2/SDHC1_D1_ELEV
GPIO2_ELEV
CLKIN1_ELEV
CLKOUT1_ELEV
R29
R13
R28
R12
0
0
0
0
AN7_ELEV
AN6_ELEV
AN5_ELEV
AN4_ELEV
R27
R11
R26
R10
0
0
0
0
DAC1_ELEV
TMR3_ELEV
TMR2_ELEV
GPIO4_ELEV
R25
R9
0
0
PWM5_ELEV
PWM4_ELEV
R8
R24
R7
R23
R6
0
0
0
0
0
SPI0_MISO_B_ELEV
SPI0_MOSI_B_ELEV
SPI0_CS0_B_ELEV
SPI0_CS1_B_ELEV
SPI0_CLK_ELEV
PTC18
PTD5
PTD4
FTM0_CH5
FTM0_CH4
PTE19
PTE18
PTE16
PTC3
PTE17
PTA5
PTC14
PTB23
PTC13
PTC16
PTC12
PTC17
B
PTB18
PTC9
SPI0_PCS1
SPI0_SCK
R5
0
GPIO5_ELEV
R4
R22
R3
R21
R2
R20
R1
R19
0
0
0
0
0
0
0
0
IRQ_H_ELEV
IRQ_G_ELEV
IRQ_F_ELEV
IRQ_E_ELEV
IRQ_D_ELEV
IRQ_C_ELEV
IRQ_B_ELEV
IRQ_A_ELEV
P3V3_REG
J16A
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
5V_1
GND_1
3.3V_1
ELE_PS_SENSE_1
GND_2
GND_3
SDHC_CLK/SPI1_CLK
SDHC_D3/SPI1_CS1
SDHC_D3/SPI1_CS0
SDHC_CMD/SPI1_MOSI
SDHC_D0/SPI1_MISO
5V_2
GND_9
3.3V_4
3.3V_5
GND_10
GND_11
I2C0_SCL
I2C0_SDA
GPIO9/UART1_CTS
GPIO8/SDHC_D2
GPIO7/SD_WP_DET
ETH_COL_1
ETH_RXER_1
ETH_TXCLK_1
ETH_TXEN_1
ETH_TXER
ETH_TXD3
ETH_TXD2
ETH_TXD1_1
ETH_TXD0_1
GPIO1/UART1_RTS
GPIO2/SDHC_D1
GPIO3
CLKIN0
CLKOUT1
GND_4
AN7
AN6
AN5
AN4
GND_5
DAC1
TMR3
TMR2
GPIO4
3.3V_2
PWM7
PWM6
PWM5
PWM4
CAN0_RX
CAN0_TX
1WIRE
SPI0_MISO/IO1
SPI0_MOSI/IO0
SPI0_CS0
SPI0_CS1
SPI0_CLK
GND_6
I2C1_SCL
I2C1_SDA
GPIO5/SPI0_HOLD/IO3
RSRV_B53
RSRV_B54
IRQ_H
IRQ_G
IRQ_F
IRQ_E
IRQ_D
IRQ_C
IRQ_B
IRQ_A
EBI_ALE/EBI_CS1
EBI_CS0
GND_7
EBI_AD15
EBI_AD16
EBI_AD17
EBI_AD18
EBI_AD19
EBI_R/W
EBI_OE
EBI_D7
EBI_D6
EBI_D5
EBI_D4
EBI_D3
EBI_D2
EBI_D1
EBI_D0
GND_8
3.3V_3
ETH_CRS
ETH_MDC_1
ETH_MDIO_1
ETH_RXCLK_1
ETH_RXDV_1
ETH_RXD3
ETH_RXD2
ETH_RXD1_1
ETH_RXD0_1
I2S0_MCLK
I2S0_DOUT_SCK
I2S0_DOUT_WS
I2S0_DIN0
I2S0_DOUT0
GND_12
AN3
AN2
AN1
AN0
GND_13
DAC0
TMR1
TMR0
GPIO6
3.3V_6
PWM3
PWM2
PWM1
PWM0
UART0_RX
UART0_TX
UART1_RX
UART1_TX
VSSA
VDDA
CAN1_RX
CAN1_TX
GND_14
GPIO14
GPIO15
GPIO16/SPI0_WP/IO2
GPIO17
USB0_DM
USB0_DP
USB0_ID
USB0_VBUS
I2S0_DIN_SCK
I2S0_DIN_WS
I2S0_DIN1
I2S0_DOUT1
RSTIN
RSTOUT
CLKOUT0
GND_15
EBI_AD14
EBI_AD13
EBI_AD12
EBI_AD11
EBI_AD10
EBI_AD9
EBI_AD8
EBI_AD7
EBI_AD6
EBI_AD5
EBI_AD4
EBI_AD3
EBI_AD2
EBI_AD1
EBI_AD0
GND_16
3.3V_7
PCI EXPRESS TOWER SYSTEM
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
P3V3_REG
J16B
PIN FUNCTIONS USED
I2C0_SCL_ELEV
I2C0_SDA_ELEV
GPIO9_ELEV
GPIO8_ELEV
GPIO7_ELEV
R512
R500
R513
R501
R514
0
0
0
0
0
NET NAMES
PTD2
PTD3
PTA16
PTB21
PTB22
I2C0_SCL
I2C0_SDA
AN3_ELEV
AN2_ELEV
AN1_ELEV
AN0_ELEV
DAC0_ELEV
R515
R502
R516
R503
R517
0
0
0
0
0
TMR1_ELEV
TMR0_ELEV
R504
R518
0
0
FTM1_CH1/FTM1_QD_PHB
FTM1_CH0/FTM1_QD_PHA
PTA13
PTA12
PWM3_ELEV
PWM2_ELEV
PWM1_ELEV
PWM0_ELEV
UART0_RX_ELEV
UART0_TX_ELEV
UART1_RX_ELEV
UART1_TX_ELEV
VSSA_ELEV
VDDA_ELEV
R519
R505
R520
R506
R521
R507
0
0
0
0
0
0
FTM0_CH3
FTM0_CH2
FTM0_CH1
FTM0_CH0
UART3_RX
UART3_TX
PTC4
PTC5
PTC2
PTC1
R522
R508
0
0
GPIO14_ELEV
GPIO15_ELEV
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
ADC0_DP1 pg(3,9)
ADC0_DP0/ADC1_DP3_RC
ADC1_DP0/ADC0_DP3_RC
ADC0_SE8/ADC1_SE8_RC
DAC0_OUT/ADC0_SE23
UART1_RX_ELEV
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
D64
D65
D66
D67
D68
D69
D70
D71
D72
D73
D74
D75
D76
D77
D78
D79
D80
D81
D82
pg(3,5)
pg(3,5)
pg(3,5)
pg(3,6,9)
PTE5
PTE4
pg(7)
UART1_TX_ELEV pg(7)
VDDA
VSSA
R509
R523
PTB20
PTA14
0
0
USB0_VBUS
USB0_VBUS
RST_TGTMCU_b pg(3,5,6,7,9)
RSTIN_ELEV_B
R511
RSTOUT_ELEV_B R510
0
0
PTC7
5V_3
GND_17
3.3V_8
ELE_PS_SENSE_2
GND_18
GND_19
SPI2_CLK
SPI2_CS1
SPI2_CS0
SPI2_MOSI
SPI2_MISO
5V_4
GND_25
3.3V_11
3.3V_12
GND_26
GND_27
I2C2_SCL
I2C2_SDA
GPIO25
ULPI_STOP
ULPI_CLK
ETH_COL_2
GPIO26
ETH_RXER_2
ETH_MDC_2
ETH_TXCLK_2
ETH_MDIO_2
ETH_TXEN_2
ETH_RXCLK_2
GPIO18
ETH_RXDV_2
GPIO19/SDHC_D4
GPIO27/SDHC_D6
GPIO20/SDHC_D5
GPIO28/SDHC_D7
ETH_TXD1_2
ETH_RXD1_2
ETH_TXD0_2
ETH_RXD0_2
ULPI_NEXT/USB_HS_DM
ULPI_DATA0/I2S1_MCLK
ULPI_DIR/USB_HS_DP
ULPI_DATA1/I2S1_DOUT_SCK
UPLI_DATA5/USB_HS_VBUS
ULPI_DATA2/I2S1_DOUT_WS
ULPI_DATA6/USB_HS_ID
ULPI_DATA3/I2S1_DIN0
ULPI_DATA7
ULPI_DATA4/I2S1_DOUT0
GND_20
GND_28
LCD_HSYNC/LCD_P24
AN11
LCD_VSYNC/LCD_P25
AN10
AN13
AN9
AN12
AN8
GND_21
GND_29
LCD_CLK/LCD_P26
GPIO29/UART2_DCD
TMR11
TMR9
TMR10
TMR8
GPIO21
GPIO30/UART3_DCD
3.3V_9
3.3V_13
PWM15
PWM11
PWM14
PWM10
PWM13
PWM9
PWM12
PWM8
CAN2_RX
UART2_RXD/TSI0
CAN2_TX
UART2_TXD/TSI1
LCD_CONTRAST
UART2_RTS/TSI2
LCD_OE/LCD_P27
UART2_CTS/TSI3
LCD_D0/LCD_P0
UART3_RXD/TSI4
LCD_D1/LCD_P1
UART3_TXD/TSI5
LCD_D2/LCD_P2
UART3_RTS/CAN3_RX
LCD_D3/LCD_P3
UART3_CTS/CAN3_TX
GND_22
GND_30
GPIO23
LCD_D4/LCD_P4
GPIO24
LCD_D5/LCD_P5
LCD_D12/LCD_P12
LCD_D6/LCD_P6
LCD_D13/LCD_P13
LCD_D7/LCD_P7
LCD_D14/LCD_P14
LCD_D8/LCD_P8
IRQ_P/SPI2_CS2
LCD_D9/LCD_P9
IRQ_O/SPI2_CS3
LCD_D10/LCD_P10
IRQ_N
LCD_D11/LCD_P11
IRQ_M
I2S1_DIN_SCK
IRQ_L
I2S1_DIN_WS
IRQ_K
I2S1_DIN1
IRQ_J
I2S1_DOUT1
IRQ_I
LCD_D15/LCD_P15
LCD_D18/LCD_P18/SD_RX_0+
LCD_D16/LCD_P16/SD_GND
LCD_D19/LCD_P19/SD_RX_0LCD_D17/LCD_P17/SD_GND
GND_23
GND_31
EBI_AD20/LCD_P42/SD_GND EBI_BE_32_24/LCD_P28/SD_TX_0+
EBI_AD21/LCD_P43/SD_GND EBI_BE_23_16/LCD_P29/SD_TX_0EBI_AD22/LCD_P44/SD_RX_1+
EBI_BE_15_8/LCD_P30/SD_GND
EBI_AD23/LCD_P45/SD_RX_1EBI_BE_7_0/LCD_P31/SD_GND
EBI_AD24/LCD_P46/SD_GND
EBI_TSIZE0/LCD_P32/SD_TX_1+
EBI_AD25/LCD_P47/SD_GND
EBI_TSIZE1/LCD_P33/SD_TX_1EBI_AD26/LCD_P48/SD_RX_2+
EBI_TS/LCD_P34/SD_GND
EBI_AD27/LCD_P49/SD_RX_2EBI_TBST/LCD_P35/SD_GND
EBI_AD28/LCD_P50/SD_GND
EBI_TA/LCD_P36/SD_TX_2+
EBI_AD29/LCD_P51/SD_GND
EBI_CS4/LCD_P37/SD_TX_2EBI_AD30/LCD_P52/SD_RX_3+
EBI_CS3/LCD_P38/SD_GND
EBI_AD31/LCD_P53/SD_RX_3EBI_CS2/LCD_P39/SD_GND
LCD_D20/LCD_P20/SD_GND
EBI_CS1/LCD_P40/SD_TX_3+
LCD_D21/LCD_P21/SD_REFCLK+
GPIO31/LCD_P41/SD_TX_3LCD_D22/LCD_P22/SD_REFCLKLCD_D23/LCD_P23/SD_GND
GND_24
GND_32
3.3V_10
3.3V_14
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
C55
C56
C57
C58
C59
C60
C61
C62
C63
C64
C65
C66
C67
C68
C69
C70
C71
C72
C73
C74
C75
C76
C77
C78
C79
C80
C81
C82
C
B
PRIMARY
PCI EXPRESS TOWER SYSTEM
P5V_ELEV
P3V3_REG
C2
10uF
C1
10uF
SECONDARY
Note that signals coming from the elevator are usually 3.3V.
They should not be used when the board is configured for
1.8V operation.
A
A
ICAP Classification:
Drawing Title:
FCP: ___
FIUO: X
PUBI: ___
X-TWR-KV31F120M
Page Title:
ELEVATORS
5
4
3
2
Size
C
Document Number
Date:
Wednesday, January 22, 2014
Rev
C
SCH-27959 PDF: SPF-27959
1
Sheet
8
of
9
4
3
MCU_VDD
pg(3,5) SWD_CLK_KV3x
pg(3,5,7) SWD_DIO_TGTMCU
pg(3,5,8) PTA[1..17]
2
VDDA
VREFH
22
5
VREFL
1
PTA[1..17]
PTB[0..23]
EXTAL0
XTAL0
pg(3) ADC0_SE8/ADC1_SE8
pg(3) ADC0_SE9/ADC1_SE9
pg(3) ADC0_SE13
PTB9
PTB10
PTB11
pg(3,5,6,8)
PTC[0..18]
PTC[0..18]
PTB18
PTB19
PTB2
PTB20
PTB21
PTB22
PTB23
PTC0
PTC1
PTC2
PTC3
PTC4
PTC5
PTC6
PTC7
PTC8
PTC9
C
ADC0_SE8/ADC1_SE8
ADC0_SE9/ADC1_SE9
ADC0_SE13
SPI1_PCS1
SPI1_PCS0
SPI1_SCK
LED3
UART0_RTS
53
54
56
57
58
59
UART0_RX_PKYK62
UART0_TX_PKYK 63
64
65
55
66
67
68
69
70
71
72
73
76
77
78
79
80
81
82
83
84
85
86
87
90
91
92
FTM0_CH0
SPI0_PCS1
FTM0_CH3
FTM0_CH2
PTC6/LLWU_P10
ADC1_SE4b
ADC1_SE6b
pg(3) ADC1_SE6b
PTC11
PTC12
PTC13
PTC14
PTC15
PTC16
PTC17
PTC18
PTC11/LLWU_P11
26
24
VREFL
VDDA
VREFH
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
ADC0_DM0/ADC1_DM3
ADC0_DP0/ADC1_DP3
ADC0_DM1
ADC0_DP1
ADC1_DM0/ADC0_DM3
ADC1_DP0/ADC0_DP3
ADC1_DM1/ADC0_DM2
ADC1_DP1/ADC0_DP2
PTB0/LLWU_P5/ADC0_SE8/ADC1_SE8/I2C0_SCL/FTM1_CH0/FTM1_QD_PHA/UART0_RX
PTB1/ADC0_SE9/ADC1_SE9/I2C0_SDA/FTM1_CH1/FTM0_FLT2/EWM_IN/FTM1_QD_PHB/UART0_TX
PTB3/ADC0_SE13/I2C0_SDA/UART0_CTS/UART0_COL/FTM0_FLT0
DAC0_OUT/CMP1_IN3/ADC0_SE23
PTB9/SPI1_PCS1/UART3_CTS/FBA_AD20
DAC1_OUT/CMP0_IN4/ADC1_SE23
PTB10/ADC1_SE14/SPI1_PCS0/UART3_RX/FBA_AD19/FTM0_FLT1
PTB11/ADC1_SE15/SPI1_SCK/UART3_TX/FBA_AD18/FTM0_FLT2
RESET
PTB16/SPI1_SOUT/UART0_RX/FTM_CLKIN0/FBA_AD17/EWM_IN
PTB17/SPI1_SIN/UART0_TX/FTM_CLKIN1/FBA_AD16/EWM_OUT
PTD0/LLWU_P12/SPI0_PCS0/UART2_RTS/FTM3_CH0/FBA_ALE/FBA_CS1/FBA_TS
PTB18/FTM2_CH0/I2S0_TX_BCLK/FBA_AD15/FTM2_QD_PHA
PTD1/ADC0_SE5B/SPI0_SCK/UART2_CTS/FTM3_CH1/FBA_CS0
PTB19/FTM2_CH1/I2S0_TX_FS/FBA_OE/FTM2_QD_PHB
PTD2/LLWU_P13/SPI0_SOUT/UART2_RX/FTM3_CH2/FBA_AD4/I2C0_SCL
PTB2/ADC0_SE12/I2C0_SCL/UART0_RTS/FTM0_FLT1/FTM0_FLT3
PTD3/SPI0_SIN/UART2_TX/FTM3_CH3/FBA_AD3/I2C0_SDA
PTB20/FBA_AD31/CMP0_OUT
PTD4/LLWU_P14/SPI0_PCS1/UART0_RTS/FTM0_CH4/FBA_AD2/EWM_IN/SPI1_PCS0
PTB21/FBA_AD30/CMP1_OUT
PTD5/ADC0_SE6B/SPI0_PCS2/UART0_CTS/UART0_COL/FTM0_CH5/FBA_AD1/EWM_OUT/SPI1_SCK
PTB22/FBA_AD29
PTD6/LLWU_P15/ADC0_SE7B/SPI0_PCS3/UART0_RX/FTM0_CH6/FBA_AD0/FTM0_FLT0/SPI1_SOUT
PTB23/SPI0_PCS5/FBA_AD28
PTD7/UART0_TX/FTM0_CH7/FTM0_FLT1/SPI1_SIN
PTC0/ADC0_SE14/SPI0_PCS4/PDB0_EXTRG/FBA_AD14/FTM0_FLT1/SPI0_PCS0
PTC1/LLWU_P6/ADC0_SE15/SPI0_PCS3/UART1_RTS/FTM0_CH0/FBA_AD13/I2S0_TXD0
PTC2/ADC0_SE4B/CMP1_IN0/SPI0_PCS2/UART1_CTS/FTM0_CH1/FBA_AD12/I2S0_TX_FS
PTC3/LLWU_P7/CMP1_IN1/SPI0_PCS1/UART1_RX/FTM0_CH2/CLKOUT/I2S0_TX_BCLK
PTC4/LLWU_P8/SPI0_PCS0/UART1_TX/FTM0_CH3/FBA_AD11/CMP1_OUT
PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/I2S0_RXD0/FBA_AD10/CMP0_OUT/FTM0_CH2
PTC6/LLWU_P10/CMP0_IN0/SPI0_SOUT/PDB0_EXTRG/I2S0_RX_BCLK/FBA_AD9/I2S0_MCLK/I2C0_SCL
PTC7/CMP0_IN1/SPI0_SIN/I2S0_RX_FS/FBA_AD8/I2C0_SDA
PTC8/ADC1_SE4B/CMP0_IN2/FTM3_CH4/I2S0_MCLK/FBA_AD7
PTC9/ADC1_SE5B/CMP0_IN3/FTM3_CH5/I2S0_RX_BCLK/FBA_AD6/FTM2_FLT0
PTC10/ADC1_SE6B/I2C1_SCL/FTM3_CH6/I2S0_RX_FS/FBA_AD5
PTC11/LLWU_P11/ADC1_SE7B/I2C1_SDA/FTM3_CH7/FBA_RW
PTC12/FBA_AD27/FTM3_FLT0
PTC13/FBA_AD26
PTC14/FBA_AD25
PTC15/FBA_AD24
PTC16/UART3_RX/FBA_CS5/FBA_TSIZ1/FBA_BE23_16_BLS15_8
PTC17/UART3_TX/FBA_CS4/FBA_TSIZ0/FBA_BE31_24_BLS7_0
PTC18/UART3_RTS/FBA_TBST/FBA_CS2/FBA_BE15_8_BLS23_16
PTE0/CLKOUT32K/ADC1_SE4A/SPI1_PCS1/UART1_TX/I2C1_SDA
PTE1/LLWU_P0/ADC1_SE5A/SPI1_SOUT/UART1_RX/I2C1_SCL/SPI1_SIN
PTE2/LLWU_P1/ADC1_SE6A/SPI1_SCK/UART1_CTS
PTE3/ADC1_SE7A/SPI1_SIN/UART1_RTS/SPI1_SOUT
PTE4/LLWU_P2/SPI1_PCS0/UART3_TX
PTE5/SPI1_PCS2/UART3_RX/FTM3_CH0
PTE6/SPI1_PCS3/UART3_CTS/I2S0_MCLK/FTM3_CH1
PTE16/ADC0_SE4A/SPI0_PCS0/UART2_TX/FTM_CLKIN0/FTM0_FLT3
PTE17/ADC0_SE5A/SPI0_SCK/UART2_RX/FTM_CLKIN1/LPTMR0_ALT3
PTE18/ADC0_SE6A/SPI0_SOUT/UART2_CTS/I2C0_SDA
PTE19/ADC0_SE7A/SPI0_SIN/UART2_RTS/I2C0_SCL
PTE24/ADC0_SE17/FTM0_CH0/I2C0_SCL/EWM_OUT
PTE25/ADC0_SE18/FTM0_CH1/I2C0_SDA/EWM_IN
PTE26/CLKOUT32K
VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18
9
29
41
49
60
74
88
pg(3,5,6) VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18
19
18
ADC0_DM0/ADC1_DM3
ADC0_DP0/ADC1_DP3
15
14
21
20
ADC1_DM0/ADC0_DM3
ADC1_DP0/ADC0_DP3
17
16
DAC0_OUT/ADC0_SE23
pg(3,6,8)
DAC1_OUT/ADC1_SE23
pg(3,5,6,8)
RST_TGTMCU_b pg(3,5,6,7,8)
PTD[0..7]
52
1
2
3
4
5
6
7
10
11
12
13
31
32
33
pg(3,5,6)
pg(3)
ADC1_DM1 pg(3)
ADC1_DP1 pg(3)
27
28
93
94
95
96
97
98
99
100
pg(3,5,6)
pg(3)
ADC0_DM1 pg(3)
ADC0_DP1 pg(3,8)
PTD[0..7]
pg(3,5,6,8)
PTD0
PTD1
I2C0_SCL_PKYK
I2C0_SDA_PKYK
PTD4
PTD5
PTD6
PTD7
PTE[0..26]
PTE[0..26]
pg(3,5,6,8)
UART1_TX_PKYK
UART1_RX_PKYK
PTE2
PTE3
C
UART3_TX_PKYK
UART3_RX_PKYK
PTE6
PTE16
PTE17
PTE18
PTE19
PTE24
PTE25
PTE26
VSSA
pg(3,5,8) PTB[0..23]
PTA0/JTAG_TCLK/SWD_CLK/EZP_CLK/UART0_CTS/UART0_COL/FTM0_CH5/EWM_IN
PTA1/JTAG_TDI/EZP_DI/UART0_RX/FTM0_CH6/CMP0_OUT/FTM2_QD_PHA/FTM1_CH1
PTA2/JTAG_TDO/TRACE_SWO/EZP_DO/UART0_TX/FTM0_CH7/CMP1_OUT/FTM2_QD_PHB/FTM1_CH0
PTA3/JTAG_TMS/SWD_DIO/UART0_RTS/FTM0_CH0/FTM2_FLT0/EWM_OUT
PTA4/LLWU_P3/NMI/EZP_CS/FTM0_CH1/FTM0_FLT3
PTA5/FTM0_CH2/I2S0_TX_BCLK/JTAG_TRST
PTA12/FTM1_CH0/I2S0_TXD0/FTM1_QD_PHA
PTA13/LLWU_P4/FTM1_CH1/I2S0_TX_FS/FTM1_QD_PHB
PTA14/SPI0_PCS0/UART0_TX/I2S0_RX_BCLK
PTA15/SPI0_SCK/UART0_RX/I2S0_RXD0
PTA16/SPI0_SOUT/UART0_CTS/UART0_COL/I2S0_RX_FS
PTA17/ADC1_SE17/SPI0_SIN/UART0_RTS/I2S0_MCLK
PTA18/EXTAL0/FTM0_FLT2/FTM_CLKIN0
PTA19/XTAL0/FTM0_FLT0/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1
U3
25
PTA4
PTA5
PTA12
PTA13
PTA14
PTA15
PTA16
PTA17
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
34
35
36
37
38
39
42
43
44
45
46
47
50
51
PTA1
PTA2
23
D
8
30
40
48
61
75
89
D
MKV10FN512VLL12 + IC500-1004-004P
DNP
VSSA
B
B
For socket interconnection
EXTAL0
XTAL0
UART0_RX_PKYK
UART0_TX_PKYK
A
I2C0_SCL_PKYK
I2C0_SDA_PKYK
UART1_TX_PKYK
UART1_RX_PKYK
UART3_TX_PKYK
UART3_RX_PKYK
EXTAL0 pg(3)
XTAL0 pg(3)
UART0_RX_PKYK pg(3)
UART0_TX_PKYK pg(3)
I2C0_SCL_PKYK pg(3)
I2C0_SDA_PKYK pg(3)
UART1_TX_PKYK pg(3)
UART1_RX_PKYK pg(3)
UART3_TX_PKYK pg(3)
UART3_RX_PKYK pg(3)
A
ICAP Classification:
Drawing Title:
FCP: ___
FIUO: X
PUBI: ___
X-TWR-KV31F120M
Page Title:
CPU SKT
5
4
3
2
Size
C
Document Number
Date:
Wednesday, January 22, 2014
Rev
C
SCH-27959 PDF: SPF-27959
1
Sheet
9
of
9