APPLICATION NOTES A V A I L A B L E • AN64 ® • AN66 X88C75AN62 SLIC E2 X88C75 SLIC® E2 Microperipheral SLIC Port Expander and E2 Memory FEATURES • High Performance CMOS —Fast Access Time, 120ns —Low Power • 60mA Active • 100µA Standby • PDIP, PLCC, and TQFP Packaging Available • Highly Integrated Microcontroller Peripheral —8K x 8 E2 Memory —2 x 8 General Purpose Bidirectional I/O Ports —16 x 8 General Purpose Registers —Integerated Interrupt Controller Module —Internal Programmable Address Decoding • Self Loading Integrated Code (SLIC) —On-Chip BIOS and Boot Loader —IBM/PC Based Interface Software(XSLIC) • Concurrent Read During Write —Dual Plane Architecture • Isolates Read/Write Functions Between Planes • Allows Continuous Execution Of Code From One Plane While Writing In The Other Plane • Multiplexed Address/Data Bus —Direct Interface to Popular 80C51 Family of Microcontrollers • Software Data Protection —Protect Entire Array During Power-up/-down • Block Lock™ Data Protection —Set Write Lockout in 1K Blocks • Toggle Bit Polling DESCRIPTION The X88C75 SLIC is a highly integrated peripheral for the 80C51 family of microcontrollers. The device integrates 8K-bytes of 5V byte-alterable nonvolatile memory, two bidirectional 8-bit ports, 16 general purpose registers, programmable internal address decoding and a multiplexed address and data bus. The 5V byte-alterable nonvolatile memory can be used as program storage, data storage, or a combination of both. The memory array is separated into two 4K-bytes sections which allows read accesses to one section while a write operation is taking place in the other section. The nonvolatile memory also features Software Data Protection to protect the contents during power transitions, and an advanced Block Protect register PIN CONFIGURATIONS DIP RESET 1 48 VCC A12 2 47 WR PLCC TQFP 44 A9 A15 6 43 A11 NC 7 42 NC A14 7 39 A11 A14 8 41 IRQ A13 8 38 IRQ A13 9 40 STRB PA7 9 37 STRB PA7 10 39 PB7 PA6 10 36 PB7 PA5 11 35 PB6 PA4 12 34 PB5 13 33 PB4 PA2 14 32 PB3 PA1 15 31 PB2 PA0 16 30 PB1 A/D0 17 29 PB0 35 PB3 PA2 15 34 PB2 PA1 16 33 PB1 PA0 17 32 PB0 NC 18 31 NC A/D0 19 30 RD A/D1 20 29 A10 A/D2 21 28 CE A/D3 22 27 A/D7 A/D4 23 26 A/D6 VSS 24 25 A/D5 ©Xicor, Inc. 1994, 1995, 1996 Patents Pending 2887-2.5 4/11/97 T0/C0/D1 SH A9 A8 ALE WR VCC 18 19 20 21 22 23 24 25 26 27 28 RD 14 A10 PA3 CE PB4 33 A/D7 36 X88C75 SLIC A/D6 13 PA3 4 1 44 43 42 41 40 A/D5 PB5 2 VSS PB6 37 3 A/D4 PA4 38 X88C75 4 A/D3 12 5 A/D2 11 PA5 6 A/D1 PA6 INDEX CORNER RESET 5 A12 A8 STRA WC ALE 45 PSEN 46 4 STRA 3 A15 WC PSEN 2887 ILL F02.4 Concurrent Read During Write, Block Lock, and SLIC® E2 are registered trademarks of Xicor, Inc. 2887ILL ILLF01 F01 2887 1 Characteristics subject to change without notice X88C75 SLIC® E2 which allows Individual blocks of the memory to be configured as read-only or read/write. Reading and writing of the nonvolatile memory array is analogous to RAM operation. During a write operation to either the nonvolatile memory or the control registers, ALE latches the address to be written into the X88C75. The rising edge of WR latches the data to be written. Each bidirectional port consists of 8 general purpose I/O lines and 1 data strobe line. The ports also feature a configurable interrupt request output. The nonvolatile memory of the X88C75 is internally organized as two independent arrays of 4K-bytes with the A12 input selecting which of the two planes of memory is to be accessed. While the processor is executing code out of one plane, write operations can take place in the other plane; allowing the processor to continue execution of code out of the X88C75 during a byte or page write to the device. This feature is called Concurrent Read During Write. Access to the X88C75 is accomplished through the multiplexed address/data bus of the 80C51 type controllers. An internal programmable address decoder maps the internal memory and register locations into the desired address space. ARCHITECTURAL OVERVIEW The X88C75 incorporates the interface circuitry normally needed to decode the control signals and demultiplex the address/data bus to provide a “seamless” interface. The X88C75 also features an advanced implementation of the Software Data Protection scheme, called Block Lock Protect, which allows the nonvolatile memory array to be treated as 8 independent sections of 1K-bytes. Each of these sections can be independently enabled for write operations. This allows segmentation of the memory contents into writable and non-writable sections, thereby, allowing certain sections of the device to be secured so that updates can only occur in a controlled environment. (e.g. in an automotive application, only at The control inputs on the X88C75 are configured such that it is possible to directly connect them to the proper interface signals of the 80C51 microcontroller. The reading of data from the chip is controlled either by the PSEN or the RD signal, which essentially maps the X88C75 into both the Program and the Data Memory address map. FUNCTIONAL DIAGRAM ADDRESS A0–A15 LATCH I/O0–I/O7 I/O BUFFER & LATCH CE LEFT PLANE DECODE RIGHT PLANE DECODE 1K X 8 1K X 8 1K X 8 E2PROM 1K X 8 E2PROM 1K X 8 1K X 8 1K X 8 1K X 8 16 X 8 GENERAL PURPOSE REGISTERS PORT A PORT B WR RD ALE DATA I/O BUS MASTER CONTROL LOGIC PORT SELECT PSEN WC RESET IRQ MEM. SDP DECODE MAP CONFIG REGISTER 2 PORT SPECIAL FUNCTION REGISTERS 2887 ILL F03 X88C75 SLIC® E2 an authorized service center). The Block Protect configuration is stored in a nonvolatile register, ensuring that the configuration data will be maintained after the device is powered-down. Write A write is performed by latching the addresses on the falling edge of ALE. The WR is strobed LOW followed by valid data being presented on the AD0–AD7 pins. The data will be latched into the X88C75 on the rising edge of WR. The X88C75 write control input, serves as an external control over the completion of a previously initiated page load cycle. Page Write Operation E2 The X88C75 also features the industry standard 5V memory characteristics such as byte or page mode write and Toggle Bit Polling. The X88C75 supports page mode write operations. This allows the microcontroller to write from one to thirty-two bytes of data to the X88C75. Each individual write within a page write operation must conform to the byte write timing requirements. The falling edge of WR starts a timer delaying the internal programming cycle 100µs: therefore, each successive write operation must begin within 100µs of the last byte written. The waveform on page 4 illustrates the sequence and timing requirements. Read A HIGH to LOW transition on ALE latches the address; the data will be output on the AD pins after either RD or PSEN goes LOW (tRDLV). PIN DESCRIPTIONS PIN NAME I/O RESET I PSEN I STRA, STRB I/O PA7–PA0 I/O PB7–PB0 I/O A15–A8 AD7–AD0 I I/O WR I RD I IRQ O WC I CE I ALE I DESCRIPTION RESET is used to initialize the internal static registers and has no effect on the E2 memory operations. The default active level is HIGH, but it can be reconfigured in EEM register. Content of E2 memory can be read by lowering the PSEN and holding both RD and WR HIGH. The device then places on the data bus (AD7–AD0) the contents of E2 memory at the latched address. The STRA controls port A and STRB controls port B. When ports are configured as inputs, a valid transition on their strobe pins will latch into their port data register the data present at the port input pins. Writing to an output port data register generates a pulse of fixed duration on its corresponding strobe pin. The output data presented at the output pins stay valid until the next data is written to the output port data register. The I/O lines of port A. The output driver can be configured as either CMOS or open-drain using the AWO bit in CR. The I/O direction bit (DIRA) in CR is used to select port A I/O mode. The I/O lines of port B. The output driver can be configured as either CMOS or open-drain using the BWO bit in CR. The I/O direction bit (DIRB) in CR is used to select port B I/O mode. Non-multiplexed high-order Address Bus inputs for the upper byte of the address. Multiplexed low-order Address and Data Bus. The addresses are latched when ALE makes a HIGH to LOW transition. During a byte/page write cycle WR is brought LOW while RD is held HIGH and the data is placed on the Data Bus. The rising edge of WR will latch the data into the device. The RD input is active LOW and is used to read content of either the E2 memory or the SFR at the latched address. Both PSEN and WR signals must be held HIGH during RD controlled read operation. The IRQ is an open-drain output. It can be configured to signal latching of new data into any of the ports, and/or completion of the E2 memory internal write cycle. WC input has to be held LOW during a write cycle. It can be permanently tied HIGH in order to disable write to the E2 memory. Taking WC HIGH prior to tBLC (100µs, the time delay from the last write cycle to the start of internal programming cycle) will inhibit the write operation. The device select (CE) is an active LOW input. This signal has to be asserted prior to ALE HIGH to LOW transition in order to generate a valid internal device select signal. Holding this pin HIGH and ALE LOW will place the device in standby mode. The ports stay active at all times. Address Latch Enable input is used to latch the addresses present on the address lines A15–A8 and AD7–AD0 into the device. The addresses are latched when ALE transitions from HIGH to LOW. 2887 PGM T01.1 3 X88C75 SLIC® E2 Page Write Operation OPERATION BYTE 1 BYTE 0 BYTE 2 LAST BYTE READ (1)(2) AFTER tWC READY FOR NEXT WRITE OPERATION CE ALE A/D0–A/D7 A8–A12 AIN DIN A12=n AIN AIN DIN A12=n AIN DIN AIN DIN A12=n A12=n AIN DOUT A12=x ADDR AIN Next Address WR PSEN(RD) tBLC tWC 2887 ILL F04 Toggle Bit Polling Because the X88C75 typical write timing is less than the specified 5ms, Toggle Bit Polling has been provided to determine the early completion of a write cycle. During the internal programming cycle, I/O6 will toggle from “1” to “0” and “0” to “1” on subsequent attempts to read from the memory plane that is being updated. When the internal cycle is complete, the toggling will cease and the device will be accessible for additional read or write operations. Due to the dual plane architecture, reads for polling must occur from the plane that was written; that is, the state of A12 during a write must match the state of A12 during polling. Figure 1. Toggle Bit Polling OPERATION LAST BYTE WRITTEN I/O6=X I/O6=X I/O6=X I/O6=X X88C75 READY FOR NEXT OPERATION CE ALE A/D0–A/D7 A8–A12 AIN DIN A12=n AIN DOUT A12=n AIN DOUT AIN DOUT A12=n A12=n AIN DOUT A12=x AIN ADDR WR RD 2887 ILL F05 4 X88C75 SLIC® E2 DATA PROTECTION Figure 3. Sequence to Deactivate Software Data Protection The X88C75 provides two levels of data protection through software control. There is a global software data protection feature similar to the industry standard for E2PROMs and a new Block Lock Protect write lockout protection providing a secondary level data security option. AA b2 b1 b0 P 555 55 b2 b1 b0 P AAA Software Data Protection (SDP) can be employed to protect the entire array against inadvertent writes during power-up/power-down operations. The X88C75 is shipped from the factory with SDP enabled. With SDP enabled, inadvertent attempts to write to the X88C75 will be blocked. A0 b2 b1 b0 P 555 AA b2 b1 b0 P 555 The system can still write data, but only when the write operation (page or byte) is preceded by the three-byte command sequence. All write operations, both the command sequence and any data write operations must conform to the page write timing requirements. 80 b2 b1 b0 P AAA Software Data Protection Delay of tWC The SDP mode is also enabled anytime one of the nonvolatile configuration registers are modified. These include writing to EE map, SFR map, and BPR. Exit Routine 2887 ILL F07 b2 b1 b0 Reference the A15–A13 setting in EEM register P = Address bit (A12) of the memory plane not being read. Figure 2. Writing With SDP Enabled AA b2 b1 b0 P 555 Block Lock Protect Write Lockout 55 b2 b1 b0 P AAA A0 b2 b1 b0 P 555 The X88C75 provides a second level of data security referred to as Block Lock Protect write lockout (or Block Protect). This is accessed through an extension of the SDP command sequence. Block Protect allows the user to lockout writes to 1K x 8 blocks of memory. Unlike SDP which prevents inadvertent writes, but still allows easy system access to writing the memory, Block Protect will lockout all attempts unless it is specifically disabled by issuing the deactivation sequence. This feature can be used to set a higher level of protection in a system where a portion of the memory is used to store the system kernel and protect it from the application programs residing in the other blocks. Perform Byte or Page Write Operations Delay of tWC Exit Routine Setting write lockout is accomplished by writing a fivebyte command sequence opening access to the Block Protect Register (BPR). After the fifth byte is written, the user writes to the BPR, selecting which blocks to protect or unprotect. All write operations, both the command sequence and writing the data to the BPR, must conform to the page write timing requirements. It should be noted 2887 ILL F06 b2 b1 b0 Reference the A15–A13 setting in EEM register P = Address bit (A12) of the updated memory plane 5 X88C75 SLIC® E2 that accessing the BPR automatically sets the upper level SDP. If for some reason the user does not want SDP enabled, they may reset it using the normal reset command sequence. This will not affect the state of the BPR and any 1K x 8 blocks that were set to the write lockout state will remain in the write lockout state. Figure 5. Setting BPR Command Sequence AA b2 b1 b0 P 555 55 b2 b1 b0 P AAA A0 b2 b1 b0 P 555 AA b2 b1 b0 P 555 C0 b2 b1 b0 P AAA Figure 4. Block Protect Register Format MSB 7 6 5 4 LSB 3 2 1 0 BLOCK ADDRESS 0000-03FF 0400-07FF 0800-0BFF 0C00-0FFF 1000-13FF Write BPR mask value to any address 1400-17FF 1800-1BFF 1C00-1FFF “1” = Protect, “0” = Unprotect Block Specified Delay of tWC 2887 ILL F08.1 The BPR format and block map are illustrated above. The command sequence is illustrated to the right. Exit Routine 2887 ILL F09.1 (BPR Register Set Global SDP Set) b2 b1 b0 Reference the A15–A13 setting in E2M register P = Address bit (A12) of the memory plane not being read. Figure 6. Microcontroller Map 0000 1FFF 0000 0030 RESET/ISR VECTORS SLIC 0150 USER APPLICATION CODE/DATA 8K BYTES OF BYTE ALTERABLE DUAL PLANE ARCHITECTURED NON-VOLATILE MEMORY (MAPPABLE TO ANY 8K PAGE BY THE E2M BITS 2–0) 1F00 SLIC 1FFF SRF (SPECIAL FUNCTION REGISTER) BLOCK (MAPPABLE TO ANY 1K PAGE BY THE SFRM REGISTER) FC00 FFFF FFFF 2887 ILL F29.1 6 X88C75 SLIC® E2 Figure 7. On-Chip Registers 7 6 5 4 3 2 1 0 FC00 0 0 A15 A14 A13 A12 A11 A10 SFRM* Special Function Register Memory Map Register FC08 MSB LSB PDRB Port Data Register B FC10 MSB LSB PDRA Port Data Register A FC18 INT EOW ISR Interrupt Status Register FC20 IRST AWO BWO DIRA DIRB STRA STRB CR Configuration Register FC28 MSB LSB PPRB Port Pin Register B FC30 MSB LSB PPRA Port Pin Register A FC38 0 A13 EEM* E2 Memory Map Register FE00 MSB INTA INTB ENA 1 0 LAM 0 ENB ENEE RST A15 0 A14 LSB 16 Bytes General Purpose SRAM FE0F MSB LSB NOTE: * The value returned by reading these registers is the complement of the actual data. These registers are nonvolatile and a special SDP sequence is used to alter their contents. All the other registers are initialized by a valid reset input signal and when the device is power cycled. 2887 ILL F30.2 SFR Map Register (SFRM) Programmable Address Decoding The X88C75 features an internal programmable address decoder which allows the nonvolatile memory array and the internal registers to be mapped in various locations of the 64K-byte memory map. The register set is mappable into a 1K-byte block, while the nonvolatile memory array is mappable into an 8K-byte block. The mapping is controlled by two nonvolatile configuration registers, the SFR Map Register and the E2 Memory Map Register. Their bits are mapped as follows: Default = 3F 7 6 5 4 3 2 1 0 0 0 A15 A14 A13 A12 A11 A10 2887 ILL F10 A15-A10 The A15-A10 are upper address bits for the 1K-byte page where the SFR memory is mapped. 7 X88C75 SLIC® E2 BITS 7:6 Figure 8. Setting the SFR Map Register Setting these two bits to any combination other than “00” or “11” will interfere with device proper operation. AA b2 b1 b0 P 555 E2 Memory Map Register (EEM) 55 b2 b1 b0 P AAA A0 b2 b1 b0 P 555 A15-A13 AA b2 b1 b0 P 555 Modifying these three bits changes the location of the program memory within the address map.The A15-A13 correspond to the upper three address bits of the 8Kbyte page where program memory will be mapped. D0 b2 b1 b0 P AAA Desired Value b2 b1 b0 P XXX Default = 08 7 6 5 4 3 2 1 0 0 0 LAM 0 RST A15 A14 A13 2887 ILL F11 RST The RST bit controls the polarity of the RESET input pin. Delay of tWC “0” = RESET is Active LOW “1” = RESET is Active HIGH Exit Routine LAM Port B can be configured as either a general purpose I/O port (normal I/O mode), or latched address mode (LAM). The LAM option programs port B to output the demultiplexed low order byte of the address latched into the X88C75 by ALE. The LAM bit selects between these two modes. Figure 9. Setting Program Memory Map Register “0” = PORT B is I/O Port “1” = Port B outputs low address byte (A7-A0) Setting the Mapping Registers The mapping registers are written using a modified version of the Software Data Protection sequence. All timings must adhere to the normal Software Data Protection sequence. The complemented contents of the SFR map register and the E2 memory map register can be read by the microcontroller at their corresponding SFR addresses. The physical memory location of these registers can be derived by adding the following offset to the SFR base address: SFR Map Register 00H E2 Memory Map Register 38H 2887 ILL F12.1 X = Don’t Care B[2:0] = E2M [2:0] P = Address bit (A12) of the memory plane not being read. AA b2 b1 b0 P 555 55 b2 b1 b0 P AAA A0 b2 b1 b0 P 555 AA b2 b1 b0 P 555 E0 b2 b1 b0 P AAA Desired Value b2 b1 b0 P XXX Delay of tWC Exit Routine X = Don’t Care B[2:0] = E2M [2:0] P = Address bit (A12) of the memory plane not being read. If the regions specified in the map registers overlap, only the SFR will be accessible. 8 2887 ILL F13.1 X88C75 SLIC® E2 Interrupt Status Register (ISR) status flag (INTA, INTB) in ISR is forced to “0” by the interrupt service routine. Interrupt service routine should examine the interrupt status flags (INTA, INTB) and identify the source of pending interrupt. The Interrupt Status Register is a volatile register used to configure the interrupt condition for the I/O ports as well as to determine the interrupt status of the ports. The X88C75 ports can generate an interrupt to the microcontroller upon the proper transition (as specified in the configuration register) on either STRA or STRB pins when the corresponding I/O port is configured as an input. The E2 memory interrupt status flag (EOW) is another means to detect the early completion of a write cycle. When ENEE is enabled, the hardware will set the EOW flag, and interrupt the microcontroller at the end of an internal programming cycle. Toggle Bit Polling can be replaced by this hardware interrupt, which reduces the software overhead. The EOW flag should be cleared by software. The interrupt status register bits are mapped as follows. The INT flag is set when any of the input strobes are toggled provided that their corresponding interrupt enable bits (ENA, ENB) are set. The INT flag is cleared when latched data is read (PDR) or pending interrupt Figure 10. Interrupt Status Register 7 INT 6 5 4 INTA INTB ENA 3 2 ENB ENEE 1 0 0 EOW Interrupt Flag “0” = No pending interrupt “1” = Interrupt request EEPROM Interrupt Status “0” = Programming in progress “1” = Set by hardware when it completes programming the previously written data Port A – Interrupt Status “0” = No pending interrupt “1” = Port A latched data when a valid transition occurred on the STRA and port A was an input port. Port B – Interrupt Status “0” = No pending interrupt “1” = Port B latched data when a valid transition occurred on the STRB and port B was an input port. EEPROM Interrupt Enable “0” = Mask off interrupt “1” = Interrupt enabled Port A – Interrupt Enable “0” = Mask off interrupt “1” = Interrupt enabled Port B – Interrupt Enable “0” = Mask off interrupt “1” = Interrupt enabled 9 2887 ILL F14.1 X88C75 SLIC® E2 Configuration Register (CR) Port Pin Registers (PPR) The Configuration Register is a volatile register used to configure the operation of the I/O ports. The configuration register allows the microcontroller to designate whether each of the two ports is an input or output, what type of output drive is to be used, and what is the polarity of the two strobe lines, STRA and STRB. The bit map of configuration register is shown below. The read-only Port Pin Registers are used for reading the current status of the external I/O port pins. Accessing the PPR causes the values on the port pins to be placed on the data bus. The port direction control bits in configuration register set the direction for the entire port and no control mechanism is provided to program the direction of individual pins. However, the ports have a flexible architecture which allows operating the I/O ports in bidirectional mode using the PPR read feature. The IRST bit in the configuration register controls the method used to clear the port interrupt request flags(INTA, INTB). The interrupts are reset by either reading the interrupt source or writing to the Interrupt Status Register. The interrupt must be disabled prior to changing strobe polarity bits(STPA, SPTB), or port direction bits (DIRA, DIRB) in CR. Otherwise, any attempt to modify status of these bits may cause an interrupt to occur. A port can be operated in input/output mode by configuring it as an open-drain output port. The port wire-OR bit (AWO, or BWO in CR) and its port data direction bit (DIRA, or DIRB in CR) should be set to “1”. The PDR bits which correspond to the port pins assigned as inputs should be programmed to “1”. For monitoring the status of the input pins, the PPR can be read. In this application the port strobe pin and the PDR latch are in output mode. In open-drain mode, there are weak internal pull-ups on the port pins, however external pull-ups must be used for proper switching of the I/O lines. Port Data Registers (PDR) The PDRA/PDRB are byte-wide latches which hold port data. When a port is configured as output, the outputs of its PDR latch are connected to the port pins. Writing to PDR generates a pulse on the port strobe pin and latches the data. If a port is configured as an input, the inputs of its PDR latch are connected to the port pins. External data is latched into PDR on the positive edge of its clock. The port strobe input and strobe polarity bit (STPA, STPB) are XORed to generate the PDR input clock. STATIC RAM BLOCK There are 16 bytes of volatile static RAM registers mapped to the SFR region. They reside in the 200H20FH area offset from the SFR base address. Accessing these registers has to be done through external RAM operations for both writes and reads. Figure 11. Configuration Register 7 6 IRST 1 5 4 3 2 1 0 AWO BWO DIRA DIRB STPA STPB Interrupt Request Reset Mode This bit controls the clearing of the interrupt request flag. “0” = Reading the interrupt source “1” = Writing to the request register Strobe B – Strobe Pin Polarity “0” = Active LOW “1” = Active HIGH Strobe A – Strobe Pin Polarity “0” = Active LOW “1” = Active HIGH Port A – Outputs “0” = CMOS “1” = Open-Drain Port B – Direction Flag “0” = Input mode “1” = Output mode Port B – Outputs “0” = CMOS “1” = Open-Drain Port A – Direction Flag “0” = Input mode “1” = Output mode 10 2887 ILL F15.1 X88C75 SLIC® E2 the port data register. The strobe pulse shape is controlled by the state of the STPA and STPB bits in the configuration register. A “1” forces the valid transition on the corresponding strobe pin as active HIGH ( ), and a “0” sets it to active LOW ( ). PRINCIPLES OF OPERATION I/O Port Operation The expansion ports are accessible to the software using their assigned memory mapped addresses. Each port occupies two addresses in the SFR plane, the Port Data Register and Port Pin Register. These registers and their location in the 1K-byte register memory space is shown on page 7. When an external strobe signal is applied to an input port, the latching of input data is followed by the setting of the interrupt flags. The INTA and INTB interrupt flags are used by ports A and B respectively, and are set along with the INT interrupt flag at the end of strobe pulse input. External interrupt (IRQ) is generated if the interrupt enable flags (ENA and ENB) are set by the software. The former enables the port A interrupt and the latter enables the port B interrupt. The ports can be configured as either inputs or outputs, the DIRA and DIRB bits in the configuration register are used to select between the modes. The input signal on the strobe pin, when the corresponding port is configured as an input, is fed to the clock input of the port latch. These are transparent latches and the trailing edge of the strobe pulse is used to latch the data present on the input pins. The strobe signal polarity is configurable using the STPA and STPB bits in the configuration register. The port output drivers can be either CMOS or opendrain. The wire-OR bits (AWO, BWO) in the configuration register are used to make the selection. When the bits are “0” the CMOS drivers are enabled. Setting these bits will enable the open-drain output drivers. Small pullup resistors should be used on the pins of open-drain ports. Writing to the port data register of an output port will generate a pulse of fixed duration on its strobe pin. The data also simultaneously arrives at the port output pins. The latched data stays there until new data is written to Figure 12. Block Diagram of the I/O Ports STROBE (PORT INPUT) PORT WRITE (PORT OUTPUT) PORT OUTPUT LATCH FOR I/O PIN INPUT I/O PIN OUTPUT PORT READ (PORT INPUT) INTERNAL DATA BUS PIN READ (PORT IN OR OUTPUT) 11 2887 ILL F16.1 X88C75 SLIC® E2 IRQ SOFTWARE CONTROLLED PORT OPERATIONS The IRQ pin is an active LOW open-drain output. In embedded systems applications, this signal is connected to the microcontroller interrupt input pin through either a direct connection or via an interrupt controller. The individual clock signals, that control the PDR input latches and load the external data present on the port pins, are generated by XORing the strobe polarity bit and the strobe input of the port. The strobe polarity bits (STPA, STPB) in CR can be used to program the active edge of the strobe inputs. However, if the external strobe input is permanently tied to VSS or VCC, then the strobe polarity bit controls the PDR input latch clock signal. Table 1 depicts the three sources of interrupts and their associated flags. Under normal conditions, the INT and port interrupt flags are set, if the port which is configured as an input has its strobe line toggled. If the port interrupt enable flag is set, or gets set while the INT flag is set, then the IRQ signal is asserted. The IRQ stays valid as long as the interrupt flags are not cleared by the software or the hardware. When a port strobe and its polarity bit have identical logic levels, the corresponding PDR latch is active and any change in the port inputs will show up at the PDR latch outputs. Holding the strobe input at current levels and changing the strobe polarity bit value will generate a positive transition on the PDR clock signal, causing the latch outputs to reflect the previous logic state of the port pins. The clock transition sets the interrupt flags, and if the interrupts have been enabled, then an external interrupt signal will be asserted. Another interrupt source is the End Of Write flag (EOW) which is set by the hardware at the end of every internal programming cycle. The interrupt from this source is controlled by the ENEE bit in ISR. If ENEE is enabled, then EOW can generate an external interrupt. The interrupt is cleared by setting EOW to “0”. Table 1. X88C75 Interrupt Sources Interrupt Source Interrupt Enable Status Flag INT Flag PORT A PORT B EOW ENA ENB ENEE INTA INTB EOW “1” “1” — This feature allows the port input operation by permanently tying the STRx inputs to VCC or VSS, and using the STPx bits in CR to control PDR latches. Another advantage of this feature are software generated interrupts. Since the clocking of the PDR latch causes the corresponding port INTx flags to be set, by enabling the interrupts the microcontroller is forced to execute the ISR responsible to service the newly latched data. 2887 PGM T02.1 PORTS A & B INTERRUPTS END OF WRITE (EOW) INTERRUPT The X88C75 features two 8-bit I/O ports which are equipped with a configurable interrupt module. The interrupts are used to signal the reception of new data at an input port data latch. When a port is configured as an output, it can no longer generate any interrupts. The internal programming cycle requires several milliseconds for either a single byte write or a page write. The updated memory plane is inaccessible while the programming is in progress. However, the opposite plane is still available for program fetch and data read operations. The input port interrupt mechanism is controlled by the external strobe pins (STRA, STRB). Detecting a valid transition on the pin will set the interrupt flags and latch in the input data. The external interrupts from the ports can be masked off using the interrupt enable bits (ENA, ENB) in ISR. The X88C75 has two means of signaling end of an internal programming cycle. In the Toggle Bit Polling technique, the last written byte is successively read. Bit 6 of read data toggles while the programming cycle is still in progress. The software has to continually monitor device responses and determine if it can again access the plane. Once an external interrupt is asserted, clearing the interrupt flags will cause the IRQ signal to return to its idle state. There are two ways of resetting the interrupt flags. The selection is made using the IRST bit in the configuration register. If IRST is set, then the interrupt flags are cleared by writing “0” to the bit positions corresponding to the interrupt flags (INTA, INTB) in ISR. When the IRST is cleared, reading the PDR automatically clears the interrupt flags. In the other method, at the end of an internal programming cycle, the hardware sets the EOW flag. The software can either poll this flag or enable the interrupts by setting the ENEE bit in ISR. Effective use of EOW is made by clearing it prior to initiating a write operation. If 12 X88C75 SLIC® E2 the interrupt is enabled, an external interrupt will be asserted at the completion of the internal write cycle. The interrupt is cleared by setting EOW to “0”. reload value for 9600 baud rate and write it into the X88C75 location 00E8H. The XSLIC software, a PC based communication driver, automates changing of the default parameters when using its SETUP option menu. The boot-firmware (SLIC) residing on the X88C75 contains a lookup table which can be accessed from the subroutine (EXEC_SUB), located at location 0126H. Two bytes are used per table entry. The EXEC_SUB input requirements are as follows: USING A PORT IN BIDIRECTIONAL MODE In order to use a port in bidirectional mode, it has to be configured as an open drain output port. Small pull-up resistors are required on all port output pins. Bit positions in the Port Data Register corresponding to port inputs should contain “1”. The inputs are then read by accessing PPR. Data is not latched into the device, so the inputs must stay valid throughout the read cycle. The port strobe pin is configured as an output and cannot be used as port latch clock input. R0 = Contains a Function Number from the following Function Table. The table entry at location (014E-014FH) is reserved for user’s application code. This function will be executed on power-up if the SLIC receives any characters other than those for the RESET (ASCII ‘R’), or ID (ASCII ‘X’) commands. The table entry can be changed to point to other code responsible for power-up initialization. This is preferred method than changing the reset vector, since the SLIC code can still be invoked upon power-up. SLIC FUNCTIONS (80C51 Specific SLIC) The resident SLIC E2 has designated memory spaces allocated for its use. The user’s application code should avoid using these areas as part of its code segment, otherwise it will overwrite the SLIC E2. Version 3.0 of the X88C75 SLIC E2 occupies 256 bytes in the upper memory bank, starting at address 1F00H, and 288 bytes in the lower bank’s address range 30H-14FH. Prior to downloading code, assemble and link the source files using the above address information. Use memory space taken up by the SLIC E2 as a run-time data storage, if there is no further need to modify the X88C75 SLIC E2 content. Other functions available through the EXEC_SUB calls is as follows: FUNCTION NO. DESCRIPTION 0 - PROC_PROG Download and program a page 1 - PROC_BPR Program BPR 2 - RESET Start execution from location 0000H 3 - PROC_VER Download and verify a page 4 - DUMMY Command not recognized 5 - INIT_UART Initialize UART parameters to default 6 - PROG_PG Program a page 7 - SEND_CHAR Send a character to the UART 8 - GET_CHAR Read a character from the RAM receive buffer (40H-5FH) 9 - SDP_HI_PLANE Generate SDP off sequence for upper plane 10- SDP_LO_PLANE Generate SDP off sequence for lower plane 11- USER_CODE Execute user’s code Figure 13. 0000H ISR & Reset Vectors 0030H SLIC 0150H User’s Program/Data 01F00H SLIC 2887 ILL F17 2887 PGM T03.1 The current version of the SLIC E2 configures the 80C51 serial port to the variable baud rate mode. It sets a timer 1 reload value for a system clock rate of 11.059MHz. For other clock rates end user must recalculate timer 1 For detailed information about the listed functions, including their input requirements, refer to the SLIC software specification document. 13 X88C75 SLIC® E2 APPLICATION EXAMPLES Example 2 This section gives examples of most widely used embedded systems architectures using the X88C75 and 80C51 microcontroller. However, keep in mind that other microcontrollers are also supported by the X88C75 and/or other SLIC devices that Xicor manufactures. Applications requiring more than 8K bytes of program memory space can be implemented using the basic system architecture depicted in example 1 along with an additional memory device such as the X28C256. Since this device requires non-multiplexed address/data buses, the X88C75 LAM feature is used to output the low order address byte. The SFRM can be mapped to any 64x1K page, but the X28C256 should be mapped to the upper program memory address space and out of the E2M address range (0000-1FFFH.) This technique may also be used for other external byte wide memories such as SRAMs or EPROMs. Example 1 In this system, the X88C75 is the only parallel device residing on the multiplexed address and data bus. There may be other peripherals on the system board which are controlled by the ports on the X88C75. This configuration maps the EEM to a program/data memory address in the range of 0000-1FFFH. The SFRM can be mapped to any of the 64 x 1K pages within the data memory space. Figure 14. Example 1 8051 X88C75 STRA PA A15:8 AD7:0 STRB ALE WR RD PSEN CE RESET ALE WR RD PSEN EA PB 2887 ILL F18 Figure 15. Example 2 8051 X88C75 STRA PA A15:8 X28C256 AD7:0 STRB ALE WR RD PSEN EA PB ALE WR RD PSEN RESET CE A7:0 8 A15 D7:0 A15:8 14 A7-A0 CE OE WE I/O7-I/O0 A14-A8 2887 ILL F19 X88C75 SLIC® E2 Example 3 for the total of 32K-bytes of program memory. Ports A and B are still available to handle any general purpose I/O functions. If an application requires larger program memory storage and both extra ports, then example 2 does not meet this requirement. Since the LAM feature uses port B to output the non-multiplexed address, then port B cannot be also used as general purpose I/O. The solution to this problem is to use X68C64, which interfaces to a multiplexed bus and takes an active HIGH CE input. Example 3 maps the X68C64 to the top 8K program memory space in the range of 8000-FFFFH. This approach provides a total of 16K-bytes of program memory. Using the same approach, two additional X68C64 device can be added and A13-A14 can be used as their CE inputs, Example 4 For those applications using extensive I/O, up to 128 I/O pins are obtained by placing 8 of the X88C75 devices on the same bus. This approach gives a total of 64Kbytes of program memory space, and 128 I/O pins. Note that the SFRM can overlap the E2M address space, however, only the SFR resources are accessible and the associated E2 memory location are not available. Figure 16. Example 3 8051 X88C75 PA STRA A15:8 PB AD7:0 STRB X68C64 ALE WR RD PSEN RESET CE ALE WR RD PSEN EA A15 AD7:0 A15:8 CE E AS SEL WR A/D7-A/D0 A12-A8 2887 ILL F20 X8 8C 7 5 Figure 17. Example 4 8051 STRA PA 128 I/O A15:8 AD7:0 ALE WR RD PSEN EA ALE STRB WR PB RD PSEN CE RESET 2887 ILL F21 15 X88C75 SLIC® E2 ABSOLUTE MAXIMUM RATINGS* Temperature under Bias .................. –65°C to +135°C Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to VSS .................................. –1V to +7V D.C. Output Current ............................................ 5 mA Lead Temperature (Soldering, 10 seconds) .............................. 300°C *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Supply Voltage Limits Commercial Industrial Military 0°C –40°C –55°C +70°C +85°C +125°C X88C75 5V ±10% 2887 PGM T05.1 2887 PGM T04.1 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Max. Units Test Conditions CE = RD = VIL, All I/O’s = Open,Other Inputs = VCC CE = VIH, All I/O’s = Open, Other Inputs = VCC – 0.3V, ALE = VIL CE = VIH, All I/O’s = Open, Other Inputs = VIH, ALE = VIL VIN = VSS to VCC VOUT = VSS to VCC, RD = PSEN = VIH ICC VCC Current (Active) 60 mA ISB1(CMOS) VCC Current (Standby) 100 µA ISB2(TTL) VCC Current (Standby) 2 mA ILI ILO Input Leakage Current Output Leakage Current 10 10 µA µA VlL(3) VIH(3) VOL VOH Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage 0.8 VCC + 0.5 0.4 V V V V –1 2 2.4 IOL = 2.1mA IOH = –400µA 2887 PGM T06.2 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol CI/O(4) CIN(4) Test Max. Units Conditions Input/Output Capacitance Input Capacitance 10 6 pF pF VI/O = 0V VIN = 0V 2887 PGM T07 POWER-UP TIMING Symbol Parameter Max. Units tPUR(4) tPUW(4) Power-Up to Read Power-Up to Write 1 5 ms ms 2887 PGM T08 Notes: (3) VIL min. and VIH max. are for reference only and are not tested. (4) This parameter is periodically sampled and not 100% tested. 16 X88C75 SLIC® E2 A.C. CONDITIONS OF TEST EQUIVALENT A.C. TEST CIRCUIT Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels 0V to 3V 10ns 1.5V 5V 1.92KΩ 2887 PGM T09.1 OUTPUT 1.37KΩ 100pF 2887 ILL F22.2 A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) PSEN Controlled Read Cycle Symbol Parameter Min. tLHLL tAVLL tLLAX tPLDV tPHDX tELLL PWPL tPS tPH tPHDZ (5) tPLDX (5) ALE Pulse Width Address Setup Time Address Hold Time PSEN Read Access Time Data Hold Time Chip Enable Setup Time PSEN Pulse Width PSEN Setup Time PSEN Hold Time PSEN Disable to Output in High Z PSEN to Output in Low Z 80 20 30 Max. 120 0 7 150 30 20 50 10 Units ns ns ns ns ns ns ns ns ns ns ns 2887 PGM T10 PSEN Controlled Read Timing Diagram tPH CE tLHLL tELLL tPH ALE tAVLL A/D0–A/D7 tLLAX AIN DOUT tPHDX tPLDX tPLDV tPHDZ A8–A12 ADDRESS tPS PWPL PSEN 2887 ILL F23 Note: (5) This parameter is periodically sampled and not 100% tested. 17 X88C75 SLIC® E2 RD Controlled Read Cycle Symbol tLHLL tAVLL tLLAX tRLDV tRHDX tELLL PWRL tRDS tRDH tRHDZ (6) tRLDX (6) Parameter Min. ALE Pulse Width Address Setup Time Address Hold Time RD Read Access Time Data Hold Time Chip Enable Setup Time RD Pulse Width RD Setup Time RD Hold Time RD Disable to Output in High Z RD to Output in Low Z 80 20 30 Max. 120 0 7 150 30 20 50 0 Units ns ns ns ns ns ns ns ns ns ns ns 2887 PGM T11 RD Controlled Read Timing Diagram tRDH CE tLHLL tELLL tRDH ALE tAVLL A/D0–A/D7 tLLAX AIN DOUT tRHDX tRLDX tRLDV tRHDZ A8–A12 ADDRESS tRDS PWRL RD 2887 ILL F24 Note: (6) This parameter is periodically sampled and not 100% tested. 18 X88C75 SLIC® E2 WR Controlled Write Cycle Symbol Parameter tLHLL tAVLL tLLAX tDVWH tWHDX tELLL tWLWH tWRS tWRH tBLC tWC (7) Min. ALE Pulse Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time Chip Enable Setup Time WR Pulse Width WR Setup Time WR Hold Time Byte Load Time (Page Write) Write Cycle Time 80 20 30 50 30 7 120 30 20 0.5 Max. Units 100 5 ns ns ns ns ns ns ns ns ns µs ms 2887 PGM T12 WR Controlled Write Timing Diagram tWRH CE tLHLL tELLL tWRH ALE tAVLL A/D0–A/D7 tLLAX AIN DIN tDVWH A8–A12 tWHDX ADDRESS tWRS tWLWH WR 2887 ILL F25 Note: (7) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. 19 X88C75 SLIC® E2 Port Read Diagram 1 STRA/STRB* (IN) 2 PA7:0/PB7:0 3 DATA VALID 4 7 INTERRUPT RECOGNIZED IRQ 6 5 ALE 8 9 PORT ADDRESS A15–A8 10 RD/PSEN 8 AD7–AD0 9 11 DATA VALID A7-A0 2887 ILL F26.1 NOTE: *Figure shows active HIGH strobes. PORT READ TIMING No. 1 2 3 4 5 6 7 8 9 10 11 Symbol tSVSX tDVSV tSVDX tSVIV tIAD tLHLL tRXIX tAVLL tLLAX tLLWL tRLDV Parameter Strobe Pulse Width Data Port Setup Data Port Hold Time Interrupt Request to Strobe IRQ to ALE ALE Pulse Width RD to IRQ Address setup time Address hold time ALE to RD LOW RD Access Time Min. 80 20 30 Max. 50 0 80 30 20 30 30 120 Units ns ns ns ns ns ns ns ns ns ns ns 2887 PGM T13.2 20 X88C75 SLIC® E2 Port Write Diagram 5 ADDRESS A0-A15 A15–A8 2 6 CE 1 ALE 3 4 WR 8 5 AD7–AD0 7 ADDRESS A7-A0 DATA VALID 9 10 6 STRA/STRB* (OUT) 11 PA7:0 / PB7:0 PREVIOUS DATA VALID NEW DATA 2887 ILL F27.1 NOTE: *Figure shows active HIGH strobes. PORT WRITE TIMING No. 1 2 3 4 5 6 7 8 9 10 11 Symbol tLHLL tWCS tLLWL tWLWH tAVLL tLLAX tDVWH tWHDX tSVSX tQVSV tPOS Parameter ALE Pulse Width Write Chip Select Setup Time ALE to WR WR Pulse Width Write Address Setup Time Write Address Hold Time Data Setup Time Data Hold Time Strobe Pulse Width Strobe Access Time Port Output Setup Time Min. 80 20 10 120 20 30 50 10 120 Max. 40 40 Units ns ns ns ns ns ns ns ns ns ns ns 2887 PGM T14.1 21 X88C75 SLIC® E2 LAM (Latch Address Mode) Diagram 2 ADDRESS A15-A8 A15–A8 3 1 ALE 2 ADDRESS A7-A0 AD7–AD0 DATA VALID 3 4 PB7:0 ADDRESS A7–A0 2887 ILL F31 LAM TIMING No. 1 2 3 4 Symbol tLHLL tAVLL tLLAX tPOS Parameter ALE Pulse Width Address Setup Time Address Hold Time Port Output Setup Time Min. 80 20 30 Max. Units ns ns ns ns 20 2887 PGM T15 SYMBOL TABLE WAVEFORM 22 INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed N/A Changing: State Not Known Center Line is High Impedance X88C75 SLIC® E2 PACKAGING INFORMATION 48-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 2.480 (62.99) 2.385 (60.58) 0.580 (14.73) 0.485 (12.32) PIN 1 INDEX PIN 1 0.088 (2.24) 0.040 (1.02) 2.300 (58.42) REF. 0.195 (4.95) 0.125 (3.18) SEATING PLANE 0.030 (0.76) 0.015 (0.38) 0.200 (5.08) 0.115 (2.92) 0.110 (2.79) 0.090 (2.29) 0.070 (17.78) 0.030 (7.62) 0.022 (0.56) 0.014 (0.36) 0.625 (15.88) 0.590 (14.99) 0° 15° TYP. 0.010 (0.25) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 3926 FHD F43.1 23 X88C75 SLIC® E2 PACKAGING INFORMATION 44-PIN PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J SEATING PLANE ±0.004 LEAD CO – PLANARITY — 0.020 (0.51) 0.695 (17.65) 0.685 (17.40) 0.110 (2.79) 0.100 (2.54) 0.655 (16.64) 0.650 (16.51) 0.180 (4.57) 0.165 (4.19) 0.500 (12.70) REF. 0.156 (3.96) 0.145 (3.68) PIN 1 0.695 (17.65) 0.685 (17.40) 0.050 (1.27) REF. 0.655 (16.64) 0.650 (16.51) 0.021 (0.63) 0.013 (0.33) 0.500 (12.70)REF. 0.032 (0.81) 0.026 (0.66) 0.630 (16.00) 0.590 (14.99) 0.011 (0.28) 0.009 (0.23) NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY 24 3926 ILL F29.2 X88C75 SLIC® E2 PACKAGING INFORMATION 44-LEAD THIN QUAD FLAT PACK (TQFP) PACKAGE TYPE L He E L1 PIN 1 D Hd GAGE PLANE 0.25 e b A2 7°±0° DIM C A1 INCHES MIN MAX MIN MAX A1 0.05 0.15 0.002 0.006 A2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 c 0.090 0.200 0.004 0.008 D 9.90 10.10 0.390 0.398 E 9.90 10.10 0.390 0.398 e 0.80 TYP 0.031 TYP Hd 11.90 12.10 0.468 0.476 He 11.90 12.10 0.468 0.476 L1 NOTES: 1. GAGE PLANE DIMENSION IS IN MM. 2. LEAD COPLANARITY SHALL BE 0.10MM [0.004] MAXIMUM. MILLIMETERS 1.00 TYP 0.039 TYP 3926 ILL F36.4 25 X88C75 SLIC® E2 NOTES 26 X88C75 SLIC® E2 ORDERING INFORMATION X88C75 X X SLIC Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C M = Military = –55°C to +125°C Device Package P = 48-Lead Plastic DIP J = 44-Lead PLCC L = 44-Lead TQFP LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. US. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use as critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 27