iCE40 LED Driver Usage Guide October 2014 Technical Note TN1288 Introduction The iCE40™ family of devices is a high logic, smallest footprint, low I/O count FPGA for smartphone and mobile applications to support multi-functionalities in a single chip solution. It enables BOM integration, providing higher value by board space, power and cost savings. It enables quick implementation of new functionalities without having to wait for the next generation ASIC or application processor to support the new functions. iCE40 is a key hardware differentiating feature for smartphone and mobile devices manufacturers to differentiate their product from other vendors. The iCE40 family includes the iCE40HX, iCE40LP, iCE40LM, iCE40 Ultra™, and iCE40 UltraLite™ series of FPGAs. This document describes the features on the LP, LM, Ultra, and UltraLite series for driving LEDs. The iCE40 family includes features such as Embedded RGB PWM IP, high current drive IOs, open drain driver with constant current sinks that enable LED driving applications. The table below compares the features available on each series. Table 1. iCE40 Devices LED Driver Features Comparison Feature iCE40LP (16-WLCSP only) iCE40LM x x iCE40 Ultra iCE40 UltraLite Open Drain Driver with up to 24 mA Constant Current Sink for RGB LED x x Open Drain Driver with up to 500 mA Constant Current Sink for IR LED x x Embedded PWM IP to drive RGB LED x x 24 mA High Drive/High Current Driver for RGB LED Open Drain Driver with up to 100 mA Constant Current Sink for BARCODE LED x Embedded Transceiver IP to drive IR LED x Focusing on the iCE40 Ultra and iCE40 UltraLite, Embedded PWM IP combined with the three RGB drivers of up to 24-mA current provide all the necessary logic to directly drive the service LED, reducing the need for external components. The up to 500-mA IR driver output provides a direct interface to external LED for applications such as IrDA. For iCE40 Ultra, you can implement the IR transceiver and modulation logic that meet your requirements and connect the IR driver directly to the LED. For iCE40 UltraLite, the embedded IR transceiver IP is built in. These features on the iCE40 Ultra and iCE40 UltraLite allow you to target mobile applications to perform functions such as IrDA, Service LED, Barcode Emulation, and others. The featured hardened blocks that together form the IR and Service LED driver solution are: • Embedded PWM IP • Embedded IR Transceiver IP • RGB Driver • IR Driver • LED Driver Current • High Current/High Drive IO’s © 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 tn1288_1.1 iCE40 LED Driver Usage Guide This document provides detailed information of each block. Details on the Embedded PWM IP are available in other related Lattice documents. See Appendix C. LED Connection Diagrams for detailed connection diagrams showing how the LED driver is connected to the LEDs. On the iCE40 Ultra, the hardened blocks have to be interconnected for the IR/Service LED driver solution as shown in Figure 1. Figure 1. Connectivity Block Diagram REDPWM CLK RGB0_PWM RGB0 RGB0 RGBCOLOR[3:0] GREENPWM RGB1_PWM RGB1 BRIGHTNESS[3:0] BREATHRAMP[3:0] Embedded PWM IP (Soft) BLUEPWM RGB2_PWM RGB DRV RGB2 RGB1 RGB2 BLINKRATE[3:0] RGBLED_EN RST PARAMSOK RGB_PU EN LED DRV CUR LED_PU IR_PU IRLED_EN IR DRV IR_LED IR_PWM iCE40 Ultra Figure 2 shows the location of the hardened blocks on the device. Figure 2. iCE40 Ultra Primitive Location Diagram RGB DRV I2C I/O BANK 0 HFOSC IR DRV I2C LFOSC NVCM DSP 5 4Kbit RAM DSP 5 4Kbit RAM 5 4Kbit RAM DSP 5 4Kbit RAM PLB DSP CONFIG SPI I/O BANK 2 I/O BANK 1 2 SPI IRLED iCE40 LED Driver Usage Guide Figure 3. iCE40 UltraLite Primitive Location Diagram I/O BANK 0 RGB DRV HFOSC IR AND BARCODE DRV LFOSC 5 4Kbit RAM 5 4Kbit RAM 5 4Kbit RAM NVCM 5 4Kbit RAM PLB CONFIG I 2C I/O BANK 2 I/O BANK 1 I2 C Figure 4 shows a system diagram for a typical application using the RGB and IR driver. Figure 4. System Diagram for Typical Application Using RGB and IR Driver in iCE40 Ultra VDD RGB LED SPI/I2C SPI/I2C Hard Block User Logic (Soft) Embedded PWM IP RGB Driver VDD Application Processor LED DRV CUR IR TX Modulator (Soft) iCE40 Ultra 3 IR LED IR Driver iCE40 LED Driver Usage Guide Figure 5. System Diagram for Typical Application Using RGB, IR and Barcode Driver in iCE40 UltraLite VDD RGB LED SPI/I2C SPI/I2C Hard Block User Logic (Soft) Embedded PWM IP RGB Driver VDD Application Processor IR LED IR TX Modulator IR Driver iCE40 UltraLite IR RX Carrier Freq Detector Digital Photo Detector VDD BARCODE LED Modulator Barcode Driver As seen from the example above, the SPI/I2C hardened blocks in the iCE40 Ultra and iCE40 UltraLite can be used to efficiently interface the LED driver blocks with an Application Processor. 4 iCE40 LED Driver Usage Guide Embedded RGB PWM IP - ICE40 Ultra The embedded PWM IP is available as primitive on the iCE40 Ultra, refer to UG75, iCE40 Ultra RGB LED Controller User’s Guide for details on ports and functionality. Embedded RGB PWM IP - iCE40 UltraLite The LED Driver hard IP provides logic function to drive multi-color LED (R.G.B), with individual brightness control through Pulse Width Modulation (PWM), automatic blinking control and optional breathe on/off control. Key features of the iCE40 UltraLite RGB PWM IP: • Configurable from FPGA fabric through 8 bit wide write only data bus. • Provide 256 level digital PWM brightness control individually for three colors LED (R, G, B). • User select flick rate between 125 Hz or 250 Hz. • Single level sensitive pin for easy ON/OFF control. • Automatic blink control with configurable ON and OFF period. • Optional breathe ON, breathe OFF capability with adjustable ramp rate with 16 user options. • PWM output polarity selection. • User option to skew the PWM output for R.G.B LED in to reduce simultaneous switching noise. • User option to select PWM mode between square pulses using linear counter approach or PSUDO random pulses using LFSR with spread spectrum. • Functional system clock frequency range from 4 MHz to 64 MHz. • Built in brightness monitor for Red, Green and Blue PWM output to help verification, which could be excluded from final synthesis. 5 iCE40 LED Driver Usage Guide Figure 6. iCE40 UltraLite RGB PWM IP Block Diagram SCI BLOCK LEDDCLK REGISTERS LEDDCS LEDDBR Base Clock Period Generator LEDDDEN LEDDDAT [7:0] LEDDOFR 125 Hz/250 Hz 32 KHz/64 KHz LEDDONR FLICK Rate Generator LEDDEXE ON/OFF Control FPGA Fabric Interface LEDDADR [3:0] LEDDCR0 LEDDON LEDDBCRR LEDDBCFR PWM R PWMOUT0 PWM G PWMOUT1 PWM B PWMOUT2 LEDDPWRR LEDDPWRG LEDDPWRB LEDDRST 6 iCE40 LED Driver Usage Guide Figure 7. iCE40 UltraLite RGB PWM IP Port Level Diagram LEDDCS LEDDCLK PWMOUT0 LEDDDAT7 PWMOUT1 LEDDDAT6 PWMOUT2 LEDDDAT5 LEDDDAT4 LEDDDAT3 LEDDDAT2 LEDDDAT1 LEDDDAT0 LEDDADDR0 LEDDADDR1 LEDDON LEDDADDR2 LEDDADDR3 LEDDDEN LEDDEXE LEDRST SB_LEDDA_IP 7 iCE40 LED Driver Usage Guide Table 2. iCE40 UltraLite RGB PWM Port List Name I/O Level Description Notes LEDDCS I Digital Chip Select to write SB_LEDDA_IP registers LEDDCLK I Digital Clock to write SB_LEDDA_IP registers LEDDDAT7 I Digital Bit 7 data to write to SB_LEDDA_IP registers LEDDDAT6 I Digital Bit 6 data to write to SB_LEDDA_IP registers LEDDDAT5 I Digital Bit 5 data to write to SB_LEDDA_IP registers LEDDDAT4 I Digital Bit 4 data to write to SB_LEDDA_IP registers LEDDDAT3 I Digital Bit 3 data to write to SB_LEDDA_IP registers LEDDDAT2 I Digital Bit 2 data to write to SB_LEDDA_IP registers LEDDDAT1 I Digital Bit 1 data to write to SB_LEDDA_IP registers LEDDDAT0 I Digital Bit 0 data to write to SB_LEDDA_IP registers LEDDADDR3 I Digital Bit 3 address to write to SB_LEDDA_IP registers LEDDADDR2 I Digital Bit 2 address to write to SB_LEDDA_IP registers LEDDADDR1 I Digital Bit 1 address to write to SB_LEDDA_IP registers LEDDADDR0 I Digital Bit 0 address to write to SB_LEDDA_IP registers LEDDDEN I Digital Data enable to indicate data and address are stable Active High LEDDEXE I Digital Enable the IP to run the blinking sequence. When is low, the sequence stop at the nearest OFF state Active High LEDDRST I Digital Reset all registers in the IP Active High PWMOUT0 O Digital Goes to SB_RGBA_DRV, IO Driver for RED LED or FPGA Fabric PWMOUT1 O Digital Goes to SB_RGBA_DRV, IO Driver for GREEN LED or FPGA Fabric PWMOUT2 O Digital Goes to SB_RGBA_DRV, IO Driver for BLUE LED or FPGA Fabric LEDDON O Digital Goes to FPGA routing, indicating LED is on Active High LEDDCLK The clock [LEDDCLK] input coordinates all activities for the internal logic within the LED Control Bus interconnect. And it also served as base clock source for all LED drive IP timing and PWM functionality. All LED Control Bus output signals are registered at the rising edge of [LEDDCLK]. All LED Control Bus input signals are stable before the rising edge of [LEDDCLK]. LEDDCS The Chip Select [LEDDCS] input activate the LED Driver IP block to allow LED Control Bus to communicate to it. This usually connects to the output of the decoding logic from MSB of the address bus, in order to share the same digital bus with other IPs or instances. LEDDDAT[7:0] The data input array LEDDDAT [7:0] is used to pass binary data. The array boundaries are determined by the port size = 8. LEDDADDR[3:0] The address input array LEDDADDR [3:0] is used to pass a binary address. LEDDDEN The Data Enable input LEDDDEN, when asserted, indicates that the data and address on the LED Control Bus are stabilized and ready to be captured. All register on the LED Control Bus only response to the data and address bus when this LEDDDEN is asserted. 8 iCE40 LED Driver Usage Guide LEDDEXE The LED Driver Execute input LEDDEXE, when asserted, starts the LED Driver IP to run the blinking sequence according to the setup defined in the control registers. The LED Driver will keep on repeating the sequence while LEDDEXE remains HIGH. When LEDDEXE goes LOW, the sequence will stop at the nearest OFF state. LEDDRST An active high Power-On Reset for the whole device, include this IP. A typical LED Control Bus write operation is demonstrated in Figure 8. Figure 8. LED Control Bus Write Operation Edge 0 Edge 1 Edge 2 LEDDCLK LEDDCS LEDDDEN LEDDADDR [3:0] LEDDDAT [7:0] VALID ADDRESS VALID DATA For details about RGB PWM IP registers, please refer to Appendix D. RGB PWM IP - LED Control Bus Addressable Registers. Embedded IR Transceiver IP The IR Transceiver hard IP provides logic function to transmit and receive data through Infrared LED data link. It takes the data from soft IP residing in the FPGA fabric to transmit with user specified frequency. In user enabled learning mode, it receives data from Infrared receiver and sends the received data back to the FPGA fabric along with the measured receiving frequency. The IR Transceiver IP communicates with the host via an 8 bit wide digital bus. Key features of the iCE40 UltraLite IR Transceiver IP: • Functional system clock frequency range from 12 MHz to 64 MHz. • User select IR transmits clock frequency from 25 kHz to 120 kHz. • Learning mode to discover transmit frequency and receiving data (ON/OFF counts). • User configurable input digital filter to filter out input noise less than N system clock cycles. • User selectable output polarity. • User selectable duty cycle for the ON pulses, 1/2 or 1/3 of the transceiver clock period. • Optional user specified maximum pulse count in learning mode to save time at the end of IR command sequence. • User option for the transceiver clock frequency evaluation occurrence, once at the beginning of the IR command sequence or at beginning of every ON pulse group. • Configurable from FPGA fabric through 8 bit wide write data bus and 8 bit read data bus. 9 iCE40 LED Driver Usage Guide Figure 9. iCE40 UltraLite IR Transceiver IP Block Diagram SCI BLOCK CLKI CSI IDENI IWEI FPGA Fabric Interface ADRI [3:0] REGISTERS IRSYSFR (4 Bytes) Calculation Unit (Transmit Frequency Count/ Receiving Frequency) IRTCVFR (4 Bytes) WDATA [7:0] IRTCVCR RDATA [7:0] IRTCVSR IRTCV CONTROL BUSY DRDY ERR EXE Data Receiver Digital Filter LEARN IRIN IRTCVDR (2 Bytes) Transmit Buffer RST 10 DataTransmitter IROUT iCE40 LED Driver Usage Guide Figure 10. iCE40 UltraLite IR Transceiver IP Port Level Diagram CLKI EXE CSI DENI WEI LEARN RST ADRI[3:0] WDATA[7:0] SB_IR_IP RDATA[7:0] IRIN BUSY DRDY IROUT ERR 11 iCE40 LED Driver Usage Guide Table 3. iCE40 UltraLite IR Transceiver Port List Name I/O Level I Digital Clock input for IR IP I Digital Select Signal to activate the IP. This usually connects to the output of the decoding logic from MSB of the address bus Active High I Digital Data Enable. When asserted, indicates that the data and address on the IR Transceiver Control Bus are stabilized and ready to be captured. Active High I Digital Data Write Enable. Asserted during WRITE and de-asserted during READ cycle. Active High ADRI3 I Digital Control Register Address Bit 3 ADRI2 I Digital Control Register Address Bit 2 ADRI1 I Digital Control Register Address Bit 1 ADRI0 I Digital Control Register Address Bit 0 WDATA7 I Digital Write Data Input Bit 7 WDATA6 I Digital Write Data Input Bit 6 WDATA5 I Digital Write Data Input Bit 5 WDATA4 I Digital Write Data Input Bit 4 WDATA3 I Digital Write Data Input Bit 3 WDATA2 I Digital Write Data Input Bit 2 WDATA1 I Digital Write Data Input Bit 1 WDATA0 I Digital Write Data Input Bit 0 RDAT7 O Digital Read Data Output Bit 7 RDATA6 O Digital Read Data Output Bit 6 RDATA5 O Digital Read Data Output Bit 5 RDATA4 O Digital Read Data Output Bit 4 RDATA3 O Digital Read Data Output Bit 3 RDATA2 O Digital Read Data Output Bit 2 RDATA1 O Digital Read Data Output Bit 1 RDATA0 O Digital Read Data Output Bit 0 I Digital Execute. when asserted, starts the IR Transceiver Hard IP to transmit or receive IR data Active High I Digital Learning Mode control. when asserted; the IR Transceiver is in learning mode. The IR Transceiver will receive data instead of transmit data. Active High O Digital Busy status output CLKI CSI DENI WEI EXE LEARN BUSY Description DRDY O Digital Data Buffer Ready status output ERR O Digital Data Error status I Digital System Reset.When asserted, all SCI registers will be reset to Zero and IROUT will be reset to OFF state RST IRIN I Digital Modulated ON/OFF pulse from IR sensor IROUT O Digital Modulated ON/OFF pulse for IR Transmit Notes CLKI The clock input coordinates all activities for the internal logic within the IR Transceiver Control Bus interconnect. And it also served as base clock source for all IR Transceiver Hard IP timing and Modulation functionality. All IR Transceiver Control Bus output signals are registered at the rising edge of CLKI. All IR Transceiver Control Bus input signals are stable before the rising edge of CLKI. 12 iCE40 LED Driver Usage Guide CSI The Chip Select input activate the IR Transceiver Hard IP block to allow IR Transceiver Control Bus to communicate to it. This usually connects to the output of the decoding logic from MSB of the address bus, in order to share the same digital bus with other IPs or instances. DENI The Data Enable input, when asserted, indicates that the data and address on the IR Transceiver Control Bus are stabilized and ready to be captured. All register on the IR Transceiver Control Bus only response to the data and address bus when this DENI is asserted. WEI The Data Write Enable input indicates whether the current IR Transceiver Control Bus is a READ or WRITE cycle. The signal is negated during READ cycles, and is asserted during WRITE cycles. ADRI[3:0] The address input array ADRI [3:0] is used to pass a binary address. WDATA[7:0] The data input array is used to pass binary data for write. RDATA[7:0] The data input array is used to pass binary data for read. A typical LED Control Bus read operation is demonstrated in Figure 11. Figure 11. Typical IR Transceiver Control Bus Read Operation I Edge 0 Edge 1 Edge 2 CLKI CSI DENI ADRI [3:0] VALID ADDRESS WDATA [7:0] VALID DATA RDATA [7:0] 13 iCE40 LED Driver Usage Guide Figure 12. Typical IR Transceiver Control Bus Write Operation Edge 0 Edge 1 Edge 2 CLKI CSI DENI ADRI [3:0] VALID ADDRESS WDATA [7:0] VALID DATA RDATA [7:0] For details about IR Transceiver IP registers, please refer to Appendix E. IR Transceiver IP. iCE40 Ultra RGB Driver iCE40 Ultra supports an RGB DRV hardened IP block that provides high current drive outputs. This allows the iCE40 Ultra device to drive Service LED signals directly, reducing the need for an external component. There is one such block per device located at the top IO bank. The RGB LED driver block provides an open-drain driver for the LED DIODE with constant current from 4 mA to 24 mA in 4 mA step with +/-10% accuracy. Each of the 4 mA steps is controlled by an hdl attribute. The LED driver reference can be enabled within 100 µs time. Key features of the iCE40 Ultra RGB Driver: • Supports three Service LEDs (RGB) with sink current between 4 mA and 24 mA in steps of 4 mA per device ball. • Supports pins being independently configured as either a high-current sink or an OD GPIO. • Accuracy of within ± 10% of the amount of current being sunk at all steps when the voltage at the device pin is at least 0.5 V. Current matching within ± 5% across all three Service LEDs for the same current sink setting (for example, if all three LED pins are programmed to sink 12 mA, their actual sink current is within 5% of each other in the worst case.) • Consumes ≤ 0.5 µA typical static current (typical, 1.2 V, 25 °C) and ≤ 1 µA max static leakage current per device ball when operating in standby mode (LED off). Consumes ≤ 1.0 mA of current (typical, 1.2 V, 25 °C) per device ball associated with the support circuitry (excluding the actual current being sunk) when operating in LED on mode. • Wakeup time (from off to on -- fully functional) ≤ 100 µsec. 14 iCE40 LED Driver Usage Guide Figure 13. iCE40 Ultra RGB Driver Block Diagram VDD 4mA 4mA 4mA 4mA 4mA 4mA Connection of segments controlled by HDL attribute VDD RED GREEN BLUE RGB Driver Block Figure 14. iCE40 Ultra RGB Port Level Diagram RGBPU RGBLEDEN SB_RGB_DRV RGB0PWM RGB0 RGB1PWM RGB1 RGB2PWM RGB2 15 Constant Current Sinks iCE40 LED Driver Usage Guide Table 4. iCE40 Ultra RGB Port List Name I/O Level RGB0 O IOPAD 24 mA RGB PAD 64 kHz RGB1 O IOPAD 24 mA RGB PAD 64 kHz RGB2 O IOPAD 24 mA RGB PAD 64 kHz RGBLEDEN I Digital Enable Control for RGB LED Active HIGH I Digital Pulse width modulated control signal for RGB_PAD0 64 kHz, Active HIGH I Digital Pulse width modulated control signal for RGB_PAD1 64 kHz, Active HIGH I Digital Pulse width modulated control signal for RGB_PAD2 64 kHz, Active HIGH I Analog Power up Connects to LED_DRV_CUR primitive. RGB0PWM RGB1PWM RGB2PWM RGBPU Description Notes RGB0 Open-drain output of the RGB Driver connected to the device pin for RED LED RGB1 Open-drain output of the RGB Driver connected to the device pin for GREEN LED RGB2 Open-drain output of the RGB Driver connected to the device pin for BLUE LED RGBLEDEN Input to the RGB Driver, Enable Control for RGB LED, Active HIGH RGB0PWM Input to the RGB Driver, pulse width modulated control signal for controlling RGB0 output. Connects to Embedded PWM IP or FPGA logic, Active HIGH RGB1PWM Input to the RGB Driver, pulse width modulated control signal for controlling RGB1 output. Connects to Embedded PWM IP or FPGA logic, Active HIGH RGB2PWM Input to the RGB Driver, pulse width modulated control signal for controlling RGB2 output. Connects to Embedded PWM IP or FPGA logic, Active HIGH RGBPU Input to the RGB Driver, reference current signal must be connected to output of RGB CUR Driver primitive SB_RGB_DRV Attribute Description The SB_RGB_DRV primitive contains the following parameter and their default values: Parameter RGB0_CURRENT = “0b000000”; Parameter RGB1_CURRENT = “0b000000”; Parameter RGB2_CURRENT = “0b000000”; Parameter values: “0b000000” = 0mA. // Set this value to use the associated SB_IO_OD instance at RGB LED location. “0b000001” = 4 mA “0b000011” = 8 mA “0b000111” = 12 mA 16 iCE40 LED Driver Usage Guide “0b001111” = 16 mA “0b011111” = 20 mA “0b111111” = 24 mA RGB PAD can also be used as an open-drain GPIO with LVCMOS. These are the differences in characteristic compare to regular iCE40 GPIO. • No P-channel pull up driver. • No weak pull up. • LVCMOS input buffer will be power down when using as RGB Driver. iCE40 UltraLite RGB Driver iCE40 UltraLite supports an RGB DRV hardened IP block that provides high current drive outputs. This allows the iCE40 UltraLite device to drive Service LED signals directly, reducing the need for an external component. There is one such block per device located at the top IO bank. The RGB LED driver block provides an open-drain driver for the LED DIODE with constant current from 4 mA to 24 mA in 4 mA step in full current mode or from 2 mA to 12 mA in 2 mA step in half current mode with up to +/-10% accuracy. Each of the steps is controlled by an hdl attribute. The LED driver reference can be enabled within 100 µs time. Key features of the iCE40 UltraLite RGB Driver: • Supports three Service LEDs (RGB) with sink current between 4 mA and 24 mA in steps of 4 mA or 2 mA and 12 mA in steps of 2 mA per device ball. • Supports pins being independently configured as either a high-current sink or an OD GPIO. • Accuracy of up to ± 10% of the amount of current being sunk at all steps when the voltage at the device pin is at least 0.5 V. Current matching within ± 5% across all three Service LEDs for the same current sink setting (for example, if all three LED pins are programmed to sink 12 mA, their actual sink current is within 5% of each other in the worst case.) • Consumes ≤ 0.5 µA typical static current (typical, 1.2 V, 25 °C) and ≤ 1 µA max static leakage current per device ball when operating in standby mode (LED off). Consumes ≤ 1.0 mA of current (typical, 1.2 V, 25 °C) per device ball associated with the support circuitry (excluding the actual current being sunk) when operating in LED on mode. • Wakeup time (from off to on -- fully functional) ≤ 100 µsec. 17 iCE40 LED Driver Usage Guide Figure 15. iCE40 UltraLite RGB Driver Block Diagram VDD 4mA 4mA 4mA 4mA 4mA 4mA Connection of segments controlled by HDL attribute VDD RED GREEN BLUE RGB Driver Block Figure 16. iCE40 UltraLite RGB Port Level Diagram CURREN RGBLEDEN SB_RGBA_DRV RGB0PWM RGB0 RGB1PWM RGB1 RGB2PWM RGB2 18 Constant Current Sinks iCE40 LED Driver Usage Guide Table 5. iCE40 UltraLite RGB Port List Name I/O Level RGB0 O IOPAD Up to 24 mA RGB PAD 64 kHz RGB1 O IOPAD Up to 24 mA RGB PAD 64 kHz RGB2 O IOPAD Up to 24 mA RGB PAD 64 kHz RGBLEDEN I Digital Enable Control for RGB LED Active HIGH I Digital Pulse width modulated control signal for RGB_PAD0 64 kHz, Active HIGH I Digital Pulse width modulated control signal for RGB_PAD1 64 kHz, Active HIGH I Digital Pulse width modulated control signal for RGB_PAD2 64 kHz, Active HIGH I Digital Power up Power up signal, Active HIGH. RGB0PWM RGB1PWM RGB2PWM CURREN Description Notes RGB0 Open-drain output of the RGB Driver connected to the device pin for RED LED RGB1 Open-drain output of the RGB Driver connected to the device pin for GREEN LED RGB2 Open-drain output of the RGB Driver connected to the device pin for BLUE LED RGBLEDEN Input to the RGB Driver, Enable Control for RGB LED, Active HIGH RGB0PWM Input to the RGB Driver, pulse width modulated control signal for controlling RGB0 output. Connects to Embedded PWM IP or FPGA logic, Active HIGH RGB1PWM Input to the RGB Driver, pulse width modulated control signal for controlling RGB1 output. Connects to Embedded PWM IP or FPGA logic, Active HIGH RGB2PWM Input to the RGB Driver, pulse width modulated control signal for controlling RGB2 output. Connects to Embedded PWM IP or FPGA logic, Active HIGH CURREN Input enabling mixed signal control block to supply reference current to RGB driver. Enabling the mixed signal control block takes 100 µs to reach a stable reference current value. 19 iCE40 LED Driver Usage Guide SB_RGBA_DRV Attribute Description The SB_RGBA_DRV primitive contains the following parameter and their default values: Parameter CURRENT_MODE = “0b0”; Parameter RGB0_CURRENT = “0b000000”; Parameter RGB1_CURRENT = “0b000000”; Parameter RGB2_CURRENT = “0b000000”; Parameter values: “0b0” = Full Current Mode “0b1” = Half Current Mode “0b000000” = 0mA. // Set this value to use the associated SB_IO_OD instance at RGB LED location. “0b000001” = 4 mA for Full Mode; 2 mA for Half Mode “0b000011” = 8 mA for Full Mode; 4 mA for Half Mode “0b000111” = 12 mA for Full Mode; 6mA for Half Mode “0b001111” = 16 mA for Full Mode; 8 mA for Half Mode “0b011111” = 20 mA for Full Mode; 10 mA for Half Mode “0b111111” = 24 mA for Full Mode; 12 mA for Half Mode RGB PAD can also be used as an open-drain GPIO with LVCMOS. These are the differences in characteristic compare to regular iCE40 GPIO. • No P-channel pull up driver. • No weak pull up. • LVCMOS input buffer will be power down when using as RGB Driver. 20 iCE40 LED Driver Usage Guide iCE40 Ultra IR Driver iCE40 Ultra supports a single IR DRV IP block located at the top IO bank. The IR driver output provides a direct interface to external LED for applications such as IrDA functions. The user simply implements the modulation logic that meets his needs, and connects the IR driver directly to the LED, reducing the need for external component. The IR LED driver block provides open-drain driver for IR LED DIODE with constant current from 50 mA to 500 mA in steps of 50 mA with +/-10% accuracy. Each of the 50 mA steps is controlled by an hdl attribute. The IR LED driver reference can be enabled within 100 µs time. Key features of the iCE40 UltraLite IR Driver: • Supports one IR LED with sink current between 50 mA and 500 mA in 50 mA steps. • Supports pins being independently configured as either a high-current sink or an OD GPIO. • Accuracy of within ± 10% of the amount of current being sunk at all steps when the voltage at the device pin is at least 0.8 V. • Consumes ≤ 5 µA static current (typical, 1.2 V, 25 °C) and ≤ 10 µA max static leakage current per device ball when operating in standby mode (LED off) and consume ≤ 1.0 mA of current (typical, 1.2 V, 25 °C) per device ball associated with the support circuitry (excluding the actual current being sunk) when operating in LED on mode. • Wakeup time (from off to on -- fully functional) ≤ 100 µsec. Figure 17. Functional Equivalent Block Diagram VDD + VF IRLED 50 mA 50 mA 50 mA 50 mA 50 mA 50 mA 50 mA 50 mA 50 mA 50 mA Constant Constant Constant Constant Constant Constant Constant Constant Constant Constant Current Current Current Current Current Current Current Current Current Current GND 21 iCE40 LED Driver Usage Guide Figure 18. IR Port Level CURREN IRLEDEN SB_IR400_DRV IRLED IRPWM Table 6. IR Port List Name I/O Level Description Notes IRLED O OPAD Up to 400 mA IR PAD 100 kHz IRLEDEN I Digital Enable Control for IR LED Active HIGH I Digital Pulse width modulated control signal for IR_PAD 100 kHz, Active HIGH I Digital Connects to LED_DRV_CUR primitive Power up signal IRPWM IRPU Signal Description IRLED Output of the IR Driver connected to the device pin for IR LED IRLEDEN Input to the IR Driver, Enable Control for IR LED, Active HIGH IRPWM Input to the IR Driver, pulse width modulated control signal for controlling IRLED output. Connects to FPGA logic, Active HIGH IRPU Input to the RGB Driver, reference current signal must be connected to output of RGB CUR Driver primitive SB_IR_DRV Attribute Description The SB_IR_DRV primitive contains the following parameter and their default values: Parameter IR_CURRENT = “0b0000000000”; Parameter Values: “0b0000000000” = 0 mA. // Set this value to use the associated SB_IO_OD instance at IR LED location. “0b0000000001” = 50 mA “0b0000000011” = 100 mA “0b0000000111” = 150mA “0b0000001111” = 200 mA “0b0000011111” = 250 mA “0b0000111111” = 300 mA “0b0001111111” = 350 mA “0b0011111111” = 400 mA “0b0111111111” = 450 mA “0b1111111111” = 500 mA 22 iCE40 LED Driver Usage Guide iCE40 UltraLite IR 400 mA Driver iCE40 UltraLite supports a single IR DRV IP block located at the top IO bank. The IR driver output provides a direct interface to external LED for applications such as IrDA functions. The user simply implements the modulation logic that meets his needs, and connects the IR driver directly to the LED, reducing the need for external component. The IR LED driver block provides open-drain driver for IR LED DIODE with constant current from 50 mA to 400 mA in steps of 50 mA in full current mode or from 25 mA to 200 mA in steps of 25 mA in half current mode with up to +/-10% accuracy. Each of the steps is controlled by an hdl attribute. The IR LED driver reference can be enabled within 100 µs time. Key features of the iCE40 UltraLite 400 mA IR Driver: • Supports one IR LED with sink current between 50 mA and 400 mA in 50 mA steps in full current mode or between 25 mA and 200 mA in 25 mA steps. • Supports pins being independently configured as either a high-current sink or an OD GPIO. • Accuracy of up to ± 10% of the amount of current being sunk at all steps when the voltage at the device pin is at least 0.8 V. • Consumes ≤ 5 µA static current (typical, 1.2 V, 25 °C) and ≤ 10 µA max static leakage current per device ball when operating in standby mode (LED off) and consume ≤ 1.0 mA of current (typical, 1.2 V, 25 °C) per device ball associated with the support circuitry (excluding the actual current being sunk) when operating in LED on mode. • Wakeup time (from off to on -- fully functional) ≤ 100 µsec. Figure 19. Functional Equivalent Block Diagram 400 mA IR Driver and 100 mA Barcode Driver with GPIO Open Drain Driver + VF + VF Barcode GPIOOD 16.6 mA Constant Current 50 mA Constant Current IR 50 mA Constant Current 50 mA Constant Current 50 mA Constant Current 50 mA Constant Current 16.6 mA Constant Current 16.6 mA Constant Current VSSIO 23 50 mA Constant Current 50 mA Constant Current 50 mA Constant Current 50 mA Constant Current GPIOOD iCE40 LED Driver Usage Guide Figure 20. IR Port Level CURREN IRLEDEN SB_IR400_DRV IRLED IRPWM Table 7. IR Port List Name I/O Level Description Notes IRLED O OPAD Up to 400 mA IR PAD 100 kHz IRLEDEN I Digital Enable Control for IR LED Active HIGH IRPWM I Digital Pulse width modulated control signal for IR_PAD 100 kHz, Active HIGH CURREN I Digital Power up Power up signal, Active HIGH Signal Description IRLED Output of the IR Driver connected to the device pin for IR LED IRLEDEN Input to the IR Driver, Enable Control for IR LED, Active HIGH IRPWM Input to the IR Driver, pulse width modulated control signal for controlling IRLED output. Connects to FPGA logic, Active HIGH CURREN Input enabling mixed signal control block to supply reference current to RGB driver. Enabling the mixed signal control block takes 100 µs to reach a stable reference current value. SB_IR400_DRV Attribute Description The SB_IR400_DRV primitive contains the following parameter and their default values: Parameter CURRENT_MODE = "0b0"; Parameter IR400_CURRENT = “0b0000000000”; Parameter Values: “0b0” = Full Current Mode. // SB_BARDODE_DRV and SB_IR400_DRV are sharing same bit for Current Mode. So they have to be either all Full Current Mode or all Half Current Mode. “0b1” = Half Current Mode “0b00000000” = 0 mA. // Set this value to use the associated SB_IO_OD instance at IR LED location. “0b00000001” = 50 mA for Full Mode; 25 mA for Half Mode “0b00000011” = 100 mA for Full Mode; 50 mA for Half Mode “0b00000111” = 150 mA for Full Mode; 75 mA for Half Mode “0b00001111” = 200 mA for Full Mode; 100 mA for Half Mode “0b00011111” = 250 mA for Full Mode; 125 mA for Half Mode “0b00111111” = 300 mA for Full Mode; 150 mA for Half Mode “0b01111111” = 350 mA for Full Mode; 175 mA for Half Mode “0b11111111” = 400 mA for Full Mode; 200 mA for Half Mode 24 iCE40 LED Driver Usage Guide iCE40 UltraLite Barcode Driver The BARCODE driver output provides a direct interface to external LED for an application such as BARCODE scan. The user simply implements the logic that meets his needs, and connects the BARCODE driver directly to the LED, reducing the need for external component. The BARCODE LED driver block provides open-drain driver for BARCODE LED DIODE with constant current from 0 mA to 100 mA in steps of 16.66 mA in full current mode or from 0 mA to 50 mA in steps of 8.3 mA in half current mode with up to +/-10% accuracy. Each of the steps is controlled by an hdl attribute. The BARCODE LED driver reference can be enabled within 100 µs time. Key features of the iCE40 UltraLite BARCODE Driver: • Supports one BARCODE LED with sink current between 0 mA and 100 mA in 16.6 mA steps in full current mode or between 0 mA and 50 mA in 8.3 mA steps. • Supports pins being independently configured as either a high-current sink or an OD GPIO. • Accuracy of up to ± 10% of the amount of current being sunk at all steps when the voltage at the device pin is at least 0.8 V. • Consumes ≤ 5 µA static current (typical, 1.2 V, 25 °C) and ≤ 10 µA max static leakage current per device ball when operating in standby mode (LED off) and consume ≤ 1.0 mA of current (typical, 1.2 V, 25 °C) per device ball associated with the support circuitry (excluding the actual current being sunk) when operating in LED on mode. • Wakeup time (from off to on -- fully functional) ≤ 100 µsec. Figure 21. Functional Equivalent Block Diagram 400 mA IR Driver and 100 mA Barcode Driver with GPIO Open Drain Driver + VF + VF Barcode GPIOOD 16.6 mA Constant Current 50 mA Constant Current IR 50 mA Constant Current 50 mA Constant Current 50 mA Constant Current 50 mA Constant Current 16.6 mA Constant Current 16.6 mA Constant Current VSSIO 25 50 mA Constant Current 50 mA Constant Current 50 mA Constant Current 50 mA Constant Current GPIOOD iCE40 LED Driver Usage Guide Figure 22. IR Port Level CURREN BARCODEEN SB_BARCODE_DRV BARCODE BARCODEPWM Table 8. IR Port List Name I/O Level Description Notes BARCODE O OPAD Up to 100 mA BARCODE PAD 100 kHz BARCODEEN I Digital Enable Control for BARCODE LED Active HIGH I Digital Pulse width modulated control signal for 100 kHz, Active HIGH BARCODE_PAD I Digital Power up BARCODEPWM CURREN Power up signal, Active HIGH Signal Description BARCODE Output of the BARCODE Driver connected to the device pin for BARCODE LED BARCODEEN Input to the BARCODE Driver, Enable Control for BARCODE LED, Active HIGH BARCODEPWM Input to the BARCODE Driver, pulse width modulated control signal for controlling BARCODE output. Connects to FPGA logic, Active HIGH CURREN Input enabling mixed signal control block to supply reference current to RGB driver. Enabling the mixed signal control block takes 100 µs to reach a stable reference current value. SB_BARCODE_DRV Attribute Description The SB_BARCODE_DRV primitive contains the following parameter and their default values: Parameter CURRENT_MODE = "0b0"; Parameter BARCODE_CURRENT = “0b0000000000”; Parameter Values: “0b0” = Full Current Mode. // SB_BARDODE_DRV and SB_IR400_DRV are sharing same bit for Current Mode. So they have to be either all Full Current Mode or all Half Current Mode. “0b1” = Half Current Mode “0b0000” = 0 mA. // Set this value to use the associated SB_IO_OD instance at BARCODE LED location. “0b0001” = 16.6 mA for Full Mode; 8.3 mA for Half Mode “0b0011” = 33.3 mA for Full Mode; 16.6 mA for Half Mode “0b0111” = 50 mA for Full Mode; 25 mA for Half Mode “0b1001” = 66.6 mA for Full Mode; 33.3 mA for Half Mode “0b1010” = 83.8 mA for Full Mode; 41.6 mA for Half Mode “0b1111” = 100 mA for Full Mode; 50 mA for Half Mode 26 iCE40 LED Driver Usage Guide iCE40 UltraLite IR 500 mA Driver iCE40 UltraLite provides a way to combine IR driver and BARCODE driver to provide up to 500 mA sink current IR driver. The IR driver output provides a direct interface to external LED for applications such as IrDA functions. The user simply implements the modulation logic that meets his needs, and connects the IR driver directly to the LED, reducing the need for external component. The IR LED driver block provides open-drain driver for IR LED DIODE with constant current from 50 mA to 400 mA in steps of 50 mA in full current mode or from 25 mA to 200 mA in steps of 25 mA in half current mode with up to +/-10% accuracy. Each of the steps is controlled by an hdl attribute. The IR LED driver reference can be enabled within 100 µs time. Key features of the iCE40 UltraLite 500 mA IR Driver: • BARCODE pad and IR pad need to be shorted together on the board level. • Supports one IR LED with sink current between 50 mA and 500 mA in 50 mA steps in full current mode or between 25 mA and 250 mA in 25 mA steps. • Supports pins being independently configured as either a high-current sink or an OD GPIO. • Accuracy of up to ± 10% of the amount of current being sunk at all steps when the voltage at the device pin is at least 0.8 V. • Consumes ≤ 5 µA static current (typical, 1.2 V, 25 °C) and ≤ 10 µA max static leakage current per device ball when operating in standby mode (LED off) and consume ≤ 1.0 mA of current (typical, 1.2 V, 25 °C) per device ball associated with the support circuitry (excluding the actual current being sunk) when operating in LED on mode. • Wakeup time (from off to on -- fully functional) ≤ 100 µsec. Figure 23. Functional Equivalent Block Diagram 500 mA IR Driver with GPIO Open Drain Driver + VF Barcode GPIOOD 16.6 mA Constant Current 50 mA Constant Current IR 50 mA Constant Current 50 mA Constant Current 50 mA Constant Current 50 mA Constant Current 16.6 mA Constant Current 16.6 mA Constant Current VSSIO 27 50 mA Constant Current 50 mA Constant Current 50 mA Constant Current 50 mA Constant Current GPIOOD iCE40 LED Driver Usage Guide Figure 24. IR Port Level ICURREN IRLEDEN IRLED1 IRPWM Short 2 outputs on board SB_IR500_DRV IRLED2 Table 9. IR Port List I/O Level IRLED1 Name O OPAD IRLED2 O IRLEDEN I I I IRPWM CURREN Description Notes Up to 400 mA IR PAD 100 kHz OPAD Up to 100 mA BARCODE PAD 100 kHz Digital Enable Control for IR LED Active HIGH Digital Pulse width modulated control signal for IR_PAD 100 kHz, Active HIGH Digital Power up Power up signal, Active HIGH Signal Description IRLED1 Output of the IR Driver connected to the device pin for IR LED IRLED2 Output of the Barcode Driver connected to the device pin for Barcode LED IRLEDEN Input to the IR Driver, Enable Control for IR LED, Active HIGH IRPWM Input to the IR Driver, pulse width modulated control signal for controlling IRLED output. Connects to FPGA logic, Active HIGH CURREN Input enabling mixed signal control block to supply reference current to RGB driver. Enabling the mixed signal control block takes 100 µs to reach a stable reference current value. 28 iCE40 LED Driver Usage Guide SB_IR500_DRV Attribute Description The SB_IR500_DRV primitive contains the following parameter and their default values: Parameter CURRENT_MODE = "0b0"; Parameter IR400_CURRENT = “0b00000000000000”; Parameter Values: “0b0” = Full Current Mode “0b1” = Half Current Mode “0b000000000000” = 0 mA. // Set this value to use the associated SB_IO_OD instance at IR LED location. “0b000000000111” = 50 mA for Full Mode; 25 mA for Half Mode “0b000000001111” = 100 mA for Full Mode; 50 mA for Half Mode “0b000000011111” = 150 mA for Full Mode; 75 mA for Half Mode “0b000000111111” = 200 mA for Full Mode; 100 mA for Half Mode “0b000001111111” = 250 mA for Full Mode; 125 mA for Half Mode “0b000011111111” = 300 mA for Full Mode; 150 mA for Half Mode “0b000111111111” = 350 mA for Full Mode; 175 mA for Half Mode “0b001111111111” = 400 mA for Full Mode; 200 mA for Half Mode “0b011111111111” = 450 mA for Full Mode; 225 mA for Half Mode “0b111111111111” = 500 mA for Full Mode; 250 mA for Half Mode LED Driver Current For iCE40 Ultra, the LED Driver Current block is used to activate the mixed signal control block which supplies reference current to the RGB and IR Drivers. This block connects a stable 40 µA reference current for the LED drivers. In iCE40 UltraLite, the user no longer needs to connect this block since it has been connected by default. Figure 25. LED Port Level SB_LED_DRV_CUR LEDPU EN Table 10. LED Port List Name EN LEDPU I/O Level Description Notes I Digital Enable mixed signal block Active HIGH O Analog Output LED Driver power up signal Analog LED Signal Description EN Input, enables mixed signal control block to supply reference current to the LED drivers. When it is not enabled (EN=0), no current is supplied, and the LED drivers are powered down. Enabling the mixed signal control block takes 100 µs to reach a stable reference current value. SW models the output to be LOW during the 100 µs. LEDPU Output, LED Power Up signal. Connects to *PU signals of SB_RGB_DRV and SB_IR_DRV primitives 29 iCE40 LED Driver Usage Guide High Current/High Drive Output iCE40LP and iCE40LM FPGAs feature three high current/high drive outputs that can source/sink up to 24 mA. These outputs provide significantly higher drive capability compared to normal IOs on the device and are ideal to drive three white LEDs or one RGB LED. These pins are labelled as HCIO in iCE40LP devices and HD on iCE40LM devices. These are not constant current drivers and require an external current limiting resistor when connecting to LEDs. The HCIO on the iCE40LP are available on the LP640 and LP1K devices in the 16-WLCSP package only. Refer to the pinout file for the High Current and High Drive IO location on the iCE40LP and iCE40LM respectively. To configure an IO with specific drive value, specify the DRIVE_STRENGTH synthesis attribute on the IO instance. The Synthesis Attribute Syntax is: /* synthesis DRIVE_STRENGTH = <Drive value> */ Table 11. Drive Value Drive Strength Value Description x1 Default drive strength. No replication of SB_IO. x2 Increase default drive strength by 2. SB_IO replicated once. x3 Increase default drive strength by 3. SB_IO replicated twice. 30 iCE40 LED Driver Usage Guide Technical Support Assistance e-mail: [email protected] Internet: www.latticesemi.com Revision History Date Version October 2014 1.1 General revision. Change Summary June 2014 1.0 Initial release. 31 iCE40 LED Driver Usage Guide Appendix A. Instantiation Templates for Primitives IR Driver in iCE40 Ultra SB_IR_DRV IR_DRIVER ( .IRLEDEN(ENABLE_IRLED), .IRPWM(IR_INPUT), .IRPU(led_power_up), .IRLED(IR_LED) ), Defparam IR_DRIVER.IR_CURRENT = “1111111111”, RGB Driver in iCE40 Ultra SB_RGB_DRV RGB_DRIVER ( .RGBLEDEN(ENABLE_LED), .RGB0PWM(RGB0), .RGB1PWM(RGB1), .RGB2PWM(RGB2), .RGBPU(led_power_up), .RGB0(LED0), .RGB1(LED1), .RGB2(LED2) ), Defparam RGB_DRIVER.RGB0_CURRENT = “111111”, Defparam RGB_DRIVER.RGB1_CURRENT = “111111” Defparam RGB_DRIVER.RGB2_CURRENT = “111111” LED Driver Current LED_DRV_CUR LED_CUR_inst ( .EN(enable_led_current), .LEDPU(led_power_up) ); High Current/High Drive Output module highdriveio (a, b, output_clk, c ); input a, b, output_clk; output c; assign x = a & b; SB_IO #(.PIN_TYPE("010101") ) x_inst (.PACKAGE_PIN(c), .OUTPUT_CLK(output_clk), .D_OUT_0(x) ) /* synthesis DRIVE_STRENGTH= x2 */; Endmodule IR400 Driver in iCE40 UltraLite SB_IR400_DRV IR_DRIVER ( .IRLEDEN(ENABLE_IRLED), .IRPWM(IR_INPUT), .CURREN(led_power_up), .IRLED(IR_LED) ), Defparam IR_DRIVER. CURRENT_MODE = “0”, Defparam IR_DRIVER.IR400_CURRENT = “11111111” 32 iCE40 LED Driver Usage Guide IR500 Driver in iCE40 UltraLite SB_IR500_DRV IR_DRIVER ( .IRLEDEN(ENABLE_IRLED), .IRPWM(IR_INPUT), .CURREN(led_power_up), .IRLED1(IR_LED1), .IRLED2(IR_LED2) ), Defparam IR_DRIVER. CURRENT_MODE = “0”, Defparam IR_DRIVER.IR500_CURRENT = “111111111111” BARCODE Driver SB_BARCODE_DRV BARCODE_DRIVER ( .BARCODEEN(ENABLE_BARCODE), .BARCODEPWM(BARCODE_INPUT), .CURREN(led_power_up), .BARCODE(BARCODE) ), Defparam BARCODE_DRIVER. CURRENT_MODE = “0”, Defparam BARCODE_DRIVER.BARCODE_CURRENT = “1111” RGB Driver in iCE40 UltraLite SB_RGBA_DRV RGB_DRIVER ( .RGBLEDEN(ENABLE_LED), .RGB0PWM(RGB0), .RGB1PWM(RGB1), .RGB2PWM(RGB2), .CURREN(led_power_up), .RGB0(LED0), .RGB1(LED1), .RGB2(LED2) ), Defparam RGB_DRIVER.CURRENT_MODE Defparam RGB_DRIVER.RGB0_CURRENT Defparam RGB_DRIVER.RGB1_CURRENT Defparam RGB_DRIVER.RGB2_CURRENT = = = = “0”, “111111” “111111” “111111” 33 iCE40 LED Driver Usage Guide Appendix B. Using RGB and IR Pins as User IO To use the RGB and IRLED pins as general io user must instantiate the SB_IO_OD primitive, see example below: module top(a,o1); input a; output o1; wire o1i; assign o1i = a; SB_IO_OD OpenDrainInst0 ( .PACKAGEPIN (o1), // User’s Pin signal name .LATCHINPUTVALUE (), // Latches/holds the Input value .CLOCKENABLE (), // Clock Enable common to input and // output clock .INPUTCLK (), // Clock for the input registers .OUTPUTCLK (), // Clock for the output registers .OUTPUTENABLE (), // Output Pin Tristate/Enable // control .DOUT0 (o1i), // Data 0 – out to Pin/Rising clk // edge .DOUT1 (), // Data 1 - out to Pin/Falling clk // edge .DIN0 (), // Data 0 - Pin input/Rising clk // edge .DIN1 () // Data 1 – Pin input/Falling clk // edge ); defparam OpenDrainInst0.PIN_TYPE = 6'b011001; defparam OpenDrainInst0.NEG_TRIGGER = 1'b0; endmodule 34 iCE40 LED Driver Usage Guide Appendix C. LED Connection Diagrams Figure 26. iCE40 UltraLite Circuit Diagram VDD VF RGB LED RGB0 RGB1 RGB2 VLEDOUTRGB VDD IR LED VF VLEDOUT = VDD-VF IRLED iCE40 UltraLite VLEDOUTIR 0.8 V for Full Current Mode ≥ V LEDOUTIR ≤ 3.6 V(abs. max) 0.55 V for Half Current Mode VDD BARCODE LED 0.5 V for Full Current Mode ≥ V LEDOUTRGB ≤ 3.6 V(abs. max) 0.35 V for Half Current Mode VF 0.8 V for Full Current Mode ≥ V LEDOUTBARCODE ≤ 3.6 V(abs. max) 0.55 V for Half Current Mode BARCODE VLEDOUTBARCODE Note: The LED driver for iCE40 devices are designed for the supply of 3.8 V to 4.3 V. The recommended voltage range for iCE40 device outputs is shown in the diagram. The LED leakage current, forward and reverse voltage drop is different depending upon the LED manufacturer. Designer can use external components such as diodes, resistors or isolation FETs along with the LED to meet the recommended voltage range on the outputs for the iCE40 device. 35 iCE40 LED Driver Usage Guide Figure 27. iCE40 Ultra Circuit Diagram VDD VF RGB LED RGB0 RGB1 RGB2 VLEDOUTRGB VDD IR LED VF VLEDOUT = VDD-VF IRLED iCE40 Ultra VLEDOUTIR 0.5 V ≤ V LEDOUTRGB ≤ 3.6 V(abs. max) 0.8 V ≤ V LEDOUTIR ≤ 3.6 V(abs. max) Note: The LED driver for iCE40 devices are designed for the supply of 3.8 V to 4.3 V. The recommended voltage range for iCE40 device outputs is shown in the diagram. The LED leakage current, forward and reverse voltage drop is different depending upon the LED manufacturer. Designer can use external components such as diodes, resistors or isolation FETs along with the LED to meet the recommended voltage range on the outputs for the iCE40 device. 36 iCE40 LED Driver Usage Guide Figure 28. iCE40LP and iCE40LM Circuit Diagram (HCIO/HD Output Sinking) VDD Red/Green/Blue: IF=(VDD-VF)/(R+Ron/N) Ron = 38Ω –50Ω N = Drive Value VF – RGB LED Rr IF Rg Rb IF IF HCIO/HD Group 0 HCIO/HD Group 1 HCIO/HD Group 2 VLEDOUT – VLEDOUT = VDD –VF iCE40LP/ iCE40LM 0.5 V ≤ V LEDOUT≤ 3.6 V(abs. max) Note: The LED driver for iCE40 devices are designed for the supply of 3.8 V to 4.3 V. The recommended voltage range for iCE40 device outputs is shown in the diagram. The LED leakage current, forward and reverse voltage drop is different depending upon the LED manufacturer. Designer can use external components such as diodes, resistors or isolation FETs along with the LED to meet the recommended voltage range on the outputs for the iCE40 device. 37 iCE40 LED Driver Usage Guide Appendix D. RGB PWM IP - LED Control Bus Addressable Registers LEDD_ADR[3:0] Name Usage Access 1000 LEDDCR0 LED Driver Control Register 0 W 1001 LEDDBR LED Driver Pre-scale Register W 1010 LEDDONR LED Driver ON Time Register W 1011 LEDDOFR LED Driver OFF Time Register W 0101 LEDDBCRR LED Driver Breathe On Control Register W 0110 LEDDBCFR LED Driver Breathe Off Control Register W 0001 LEDDPWRR LED Driver Pulse Width Register for RED W 0010 LEDDPWRG LED Driver Pulse Width Register for GREEN W 0011 LEDDPWRB LED Driver Pulse Width Register for BLUE W For LED Control registers access timing, please refer to (section reference here). LED Driver Control Register 0 (LEDDCR0) LEDDCR0 can be written through LED Control Bus. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 LEDDEN FR250 OUTPOL OUTSKEW QUICK STOP PWM MODE Bit1 Bit0 BRMSBEXT Table 12. LEDDCR0 Field Description Bit Field 7 LEDDEN 6 FR250 5 OUTPOL 4 OUTSKEW Description LED Driver Enable Bit — This bit enables the LED Driver. If LEDDEN is cleared, The LED Driver is disabled and the system clock into the LED Driver block will be gated off. 0 = LED Driver disabled 1 = LED Driver enabled Flick Rate Select Bit — This bit selects the flick rate for the PWM logic between 125 Hz and 250Hz 0 = 125Hz 1 = 250Hz PWM Outputs Polarity Select Bit — This bit selects the PWM outputs polarity. 0 = Active High 1 = Active Low PWM Output Skew Enable Bit — This bit enables the PWM slew to reduce simultaneous switching noise, based on BRMSBEXT [1:0] 0 = Disable Output Skew 1 = Enable Output Skew: BRMSBEXT[1:0] Delay PWMOUT0 Delay PWMOUT1 Delay PWMOUT2 3 QUICK STOP 00 0 1 LEDD 2 LEDD CLK Cycle CLK Cycle 01 0 2 LEDD 4 LEDD CLK Cycles CLK Cycles 10 0 4 LEDD 8 LEDD CLK Cycles CLK Cycles 11 0 8 LEDD CLK Cycles 16 LEDD CLK Cycles Blinking Sequence Quick Stop Enable Bit — This bit Enables the quick stop when LEDD_EXE going low, instead of waiting current ON period finished when breathe on is enabled. 0 = Stop the blinking sequence when current ON period finished when LEDD_EXE goes low. 1 = Immediately terminate the blinking sequence after LEDD_EXE goes low. (within 5 ledd_clk cycles) 38 iCE40 LED Driver Usage Guide Bit Field 2 PWM MODE 1 PWM Mode Selection Bit — This bit allow user to selection PWM mode between linear counter approach, which results ‘square’ PWM pulse per flick cycle, or LFSR approach which results PSUDO random PWM pulse per flick cycle (Spread Spectrum). 0 = Linear counter approach, which results ‘square’ PWM pulse per flick cycle 1 = LFSR approach which results PSUDO random PWM pulse per flick cycle (Spread Spectrum). Description 1:0 BRMSBEXT These two bits will serve as MSB of the Pre-scale Register to extend functional system clock frequency range. 1. The Polynomial for the LFSR: X^(8)+ X^(5)+ X^3+X+1 LED Driver Clock Pre-scale Register (LEDDBR) LEDDBR can be written through LED Control Bus. It will combine the LEDDCR0 [1:0] as MSB to form a 10 bits binary number to generate time period equivalent to 64 kHz. From here, 125 Hz or 250 Hz refresh rate will be generated depends on the LEDDCR0 [6] selection. LEDDCR0[1:0] Bit9 Bit8 LEDDBR[7:0] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit1 Bit0 Bit0 Register Value N = Fsys/64 kHz - 1 Note: The Fsys in the table above is the System Clock Frequency with range from 4 MHz to 64 MHz. LED Driver ON Time Register (LEDDONR) LEDDONR can be written through LED Control Bus. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 LED Blink ON Time Setup (NON) The blink ON time could be set from 0 to 8.16 seconds, with 0.032 seconds incremental step. he actual blink ON time could be calculated by using the formula below. Also all available blink ON time options are shown in the table following the formula. Blink ON Time = 0.032 * NON (Sec) LEDDONR [7:0] 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 00001010 00001011 00001100 00001101 00001110 00001111 00010000 00010001 00010010 00010011 00010100 00010101 00010110 00010111 00011000 00011001 00011010 00011011 00011100 00011101 00011110 00011111 Blink ON Time (Sec) 0 0.032 0.064 0.096 0.128 0.160 0.192 0.224 0.256 0.288 0.320 0.352 0.384 0.416 0.448 0.480 0.512 0.544 0.576 0.608 0.640 0.672 0.704 0.736 0.768 0.800 0.832 0.864 0.896 0.928 0.960 0.992 LEDDONR [7:0] Blink ON Time (Sec) LEDDONR [7:0] 00100000 00100001 00100010 00100011 00100100 00100101 00100110 00100111 00101000 00101001 00101010 00101011 00101100 00101101 00101110 00101111 00110000 00110001 00110010 00110011 00110100 00110101 00110110 00110111 00111000 00111001 00111010 00111011 00111100 00111101 00111110 00111111 1.024 1.056 1.088 1.120 1.152 1.184 1.216 1.248 1.280 1.312 1.344 1.376 1.408 1.440 1.472 1.504 1.536 1.568 1.600 1.632 1.664 1.696 1.728 1.760 1.792 1.824 1.856 1.888 1.920 1.952 1.984 2.016 01000000 01000001 01000010 01000011 01000100 01000101 01000110 01000111 01001000 01001001 01001010 01001011 01001100 01001101 01001110 01001111 01010000 01010001 01010010 01010011 01010100 01010101 01010110 01010111 01011000 01011001 01011010 01011011 01011100 01011101 01011110 01011111 Blink ON LEDDONR [7:0] Time (Sec) 2.048 2.080 2.112 2.144 2.176 2.208 2.240 2.272 2.304 2.336 2.368 2.400 2.432 2.464 2.496 2.528 2.560 2.592 2.624 2.656 2.688 2.720 2.752 2.784 2.816 2.848 2.880 2.912 2.944 2.976 3.008 3.040 01100000 01100001 01100010 01100011 01100100 01100101 01100110 01100111 01101000 01101001 01101010 01101011 01101100 01101101 01101110 01101111 01110000 01110001 01110010 01110011 01110100 01110101 01110110 01110111 01111000 01111001 01111010 01111011 01111100 01111101 01111110 01111111 Blink ON Time (Sec) LEDDONR [7:0] Blink ON Time (Sec) LEDDONR [7:0] Blink ON Time (Sec) LEDDONR [7:0] Blink ON Time (Sec) LEDDONR [7:0] Blink ON Time (Sec) 3.072 3.104 3.136 3.168 3.200 3.232 3.264 3.296 3.328 3.360 3.392 3.424 3.456 3.488 3.520 3.552 3.584 3.616 3.648 3.680 3.712 3.744 3.776 3.808 3.840 3.872 3.904 3.936 3.968 4.000 4.032 4.064 10000000 10000001 10000010 10000011 10000100 10000101 10000110 10000111 10001000 10001001 10001010 10001011 10001100 10001101 10001110 10001111 10010000 10010001 10010010 10010011 10010100 10010101 10010110 10010111 10011000 10011001 10011010 10011011 10011100 10011101 10011110 10011111 4.096 4.128 4.160 4.192 4.224 4.256 4.288 4.320 4.352 4.384 4.416 4.448 4.480 4.512 4.544 4.576 4.608 4.640 4.672 4.704 4.736 4.768 4.800 4.832 4.864 4.896 4.928 4.960 4.992 5.024 5.056 5.088 10100000 10100001 10100010 10100011 10100100 10100101 10100110 10100111 10101000 10101001 10101010 10101011 10101100 10101101 10101110 10101111 10110000 10110001 10110010 10110011 10110100 10110101 10110110 10110111 10111000 10111001 10111010 10111011 10111100 10111101 10111110 10111111 5.120 5.152 5.184 5.216 5.248 5.280 5.312 5.344 5.376 5.408 5.440 5.472 5.504 5.536 5.568 5.600 5.632 5.664 5.696 5.728 5.760 5.792 5.824 5.856 5.888 5.920 5.952 5.984 6.016 6.048 6.080 6.112 11000000 11000001 11000010 11000011 11000100 11000101 11000110 11000111 11001000 11001001 11001010 11001011 11001100 11001101 11001110 11001111 11010000 11010001 11010010 11010011 11010100 11010101 11010110 11010111 11011000 11011001 11011010 11011011 11011100 11011101 11011110 11011111 6.144 6.176 6.208 6.240 6.272 6.304 6.336 6.368 6.400 6.432 6.464 6.496 6.528 6.560 6.592 6.624 6.656 6.688 6.720 6.752 6.784 6.816 6.848 6.880 6.912 6.944 6.976 7.008 7.040 7.072 7.104 7.136 11100000 11100001 11100010 11100011 11100100 11100101 11100110 11100111 11101000 11101001 11101010 11101011 11101100 11101101 11101110 11101111 11110000 11110001 11110010 11110011 11110100 11110101 11110110 11110111 11111000 11111001 11111010 11111011 11111100 11111101 11111110 11111111 7.168 7.200 7.232 7.264 7.296 7.328 7.360 7.392 7.424 7.456 7.488 7.520 7.552 7.584 7.616 7.648 7.680 7.712 7.744 7.776 7.808 7.840 7.872 7.904 7.936 7.968 8.000 8.032 8.064 8.096 8.128 8.160 39 iCE40 LED Driver Usage Guide LED Driver OFF Time Register (LEDDOFR) LEDDOFR can be written through LED Control Bus. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LED Blink OFF Time Setup (NOFF) The blink OFF time could be set from 0 to 8.16 seconds, with 0.032 seconds incremental step. The actual blink OFF time could be calculated by using the formula below. Also all available blink OF time options are shown in the table following the formula. Blink OFF Time = 0.032 * NOFF (Sec) LEDDOFR [7:0] 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 00001010 00001011 00001100 00001101 00001110 00001111 00010000 00010001 00010010 00010011 00010100 00010101 00010110 00010111 00011000 00011001 00011010 00011011 00011100 00011101 00011110 00011111 Blink OFF Time (Sec) LEDDOFR [7:0] 0 0.032 0.064 0.096 0.128 0.160 0.192 0.224 0.256 0.288 0.320 0.352 0.384 0.416 0.448 0.480 0.512 0.544 0.576 0.608 0.640 0.672 0.704 0.736 0.768 0.800 0.832 0.864 0.896 0.928 0.960 0.992 00100000 00100001 00100010 00100011 00100100 00100101 00100110 00100111 00101000 00101001 00101010 00101011 00101100 00101101 00101110 00101111 00110000 00110001 00110010 00110011 00110100 00110101 00110110 00110111 00111000 00111001 00111010 00111011 00111100 00111101 00111110 00111111 Blink OFF Blink OFF LEDDOFR [7:0] LEDDOFR [7:0] Time (Sec) Time (Sec) 1.024 1.056 1.088 1.120 1.152 1.184 1.216 1.248 1.280 1.312 1.344 1.376 1.408 1.440 1.472 1.504 1.536 1.568 1.600 1.632 1.664 1.696 1.728 1.760 1.792 1.824 1.856 1.888 1.920 1.952 1.984 2.016 01000000 01000001 01000010 01000011 01000100 01000101 01000110 01000111 01001000 01001001 01001010 01001011 01001100 01001101 01001110 01001111 01010000 01010001 01010010 01010011 01010100 01010101 01010110 01010111 01011000 01011001 01011010 01011011 01011100 01011101 01011110 01011111 2.048 2.080 2.112 2.144 2.176 2.208 2.240 2.272 2.304 2.336 2.368 2.400 2.432 2.464 2.496 2.528 2.560 2.592 2.624 2.656 2.688 2.720 2.752 2.784 2.816 2.848 2.880 2.912 2.944 2.976 3.008 3.040 Blink OFF Time (Sec) LEDDOFR [7:0] Blink OFF Time (Sec) LEDDOFR [7:0] Blink OFF Time (Sec) LEDDOFR [7:0] Blink OFF Time (Sec) LEDDOFR [7:0] Blink OFF Time (Sec) 3.072 3.104 3.136 3.168 3.200 3.232 3.264 3.296 3.328 3.360 3.392 3.424 3.456 3.488 3.520 3.552 3.584 3.616 3.648 3.680 3.712 3.744 3.776 3.808 3.840 3.872 3.904 3.936 3.968 4.000 4.032 4.064 10000000 10000001 10000010 10000011 10000100 10000101 10000110 10000111 10001000 10001001 10001010 10001011 10001100 10001101 10001110 10001111 10010000 10010001 10010010 10010011 10010100 10010101 10010110 10010111 10011000 10011001 10011010 10011011 10011100 10011101 10011110 10011111 4.096 4.128 4.160 4.192 4.224 4.256 4.288 4.320 4.352 4.384 4.416 4.448 4.480 4.512 4.544 4.576 4.608 4.640 4.672 4.704 4.736 4.768 4.800 4.832 4.864 4.896 4.928 4.960 4.992 5.024 5.056 5.088 10100000 10100001 10100010 10100011 10100100 10100101 10100110 10100111 10101000 10101001 10101010 10101011 10101100 10101101 10101110 10101111 10110000 10110001 10110010 10110011 10110100 10110101 10110110 10110111 10111000 10111001 10111010 10111011 10111100 10111101 10111110 10111111 5.120 5.152 5.184 5.216 5.248 5.280 5.312 5.344 5.376 5.408 5.440 5.472 5.504 5.536 5.568 5.600 5.632 5.664 5.696 5.728 5.760 5.792 5.824 5.856 5.888 5.920 5.952 5.984 6.016 6.048 6.080 6.112 11000000 11000001 11000010 11000011 11000100 11000101 11000110 11000111 11001000 11001001 11001010 11001011 11001100 11001101 11001110 11001111 11010000 11010001 11010010 11010011 11010100 11010101 11010110 11010111 11011000 11011001 11011010 11011011 11011100 11011101 11011110 11011111 6.144 6.176 6.208 6.240 6.272 6.304 6.336 6.368 6.400 6.432 6.464 6.496 6.528 6.560 6.592 6.624 6.656 6.688 6.720 6.752 6.784 6.816 6.848 6.880 6.912 6.944 6.976 7.008 7.040 7.072 7.104 7.136 11100000 11100001 11100010 11100011 11100100 11100101 11100110 11100111 11101000 11101001 11101010 11101011 11101100 11101101 11101110 11101111 11110000 11110001 11110010 11110011 11110100 11110101 11110110 11110111 11111000 11111001 11111010 11111011 11111100 11111101 11111110 11111111 7.168 7.200 7.232 7.264 7.296 7.328 7.360 7.392 7.424 7.456 7.488 7.520 7.552 7.584 7.616 7.648 7.680 7.712 7.744 7.776 7.808 7.840 7.872 7.904 7.936 7.968 8.000 8.032 8.064 8.096 8.128 8.160 01100000 01100001 01100010 01100011 01100100 01100101 01100110 01100111 01101000 01101001 01101010 01101011 01101100 01101101 01101110 01101111 01110000 01110001 01110010 01110011 01110100 01110101 01110110 01110111 01111000 01111001 01111010 01111011 01111100 01111101 01111110 01111111 LED Driver Breathe ON Control Register (LEDDBCRR) LEDDBCRR can only be written through the LED Control Bus. Bit7 Bit6 Bit5 Bit4 Breathe ON Enable Breathe Edge Breathe Mode RSVD Bit3 Bit2 Bit1 Breathe ON Rate 40 Bit0 iCE40 LED Driver Usage Guide Table 13. LEDDBCRR Field Description Bit Field 7 Breathe ON Enable Breathe ON Enable Bit — This bit enables the breathe ON feature setup in bit[5] and bit [3:0]. 0 = The Breathe control if disabled; NO Breathe ON 1 = The breathe control is enabled 6 Breathe Edge Breathe Edge Selection Bit — This bit enables the breathe ON control present in this byte be applied for both breathe ON and OFF 0 = The breathe control in this byte only be applied for ON ramp. 1 = The Breathe control in this byte will be applied for both ON and OFF ramp. 5 Breathe Mode Breathe Mode Select Bit — This bit selects the breathe ON/OFF mode. If this bit is cleared, the LED Driver with breathe ON/[OFF] with fix rate set in bit [3:0] for all colors; If this bit is set, the LED Driver will breathe ON/[OFF] using modulated rate based on the its destination brightness level. 0 = Unique rate for breathe ON/[OFF] 1 = Modulate rate for breathe ON/[OFF], based on the destination brightness level. 4 RSVD 3:0 Breathe ON Rate Description User setup of the breathe ON/[OFF] rate. 4’b0000 = No Breathe ON/[OFF] The optional breathe ON/[OFF] range is show in Table 14. Table 14. Optional Breath ON/OFF Range UI1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Tramp (sec) 0.128 0.256 0.384 0.512 0.640 0.768 0.896 1.024 1.152 1.280 1.408 1.536 1.664 1.792 1.920 2.048 1. UI is the user input value in binary. The modulated ramp rate could be achieved by 16 bit counter which will increase on every flick rate cycle (125Hz) with the step size internally calculated based on the formula below: Brightness 256 Nstep = ---------------- ---------------------------UI + 1 16 During the ramp up, the PWM engine will take the MSB 8 bits of the 16 bit counter as input. This will result the ramp size of 256 - Brightness ------------------------------------------- UI + 1 16 ---------------------------------------------------------256 (of 255) increment per flick rate cycle (125 Hz). The effective breathe-on ramp rates are shown in the figure below. 41 iCE40 LED Driver Usage Guide LED Driver Breathe OFF Control Register (LEDDBCFR) LEDDBCFR can only be written through the LED Control Bus. Bit7 Breathe OFF Enable Bit6 Bit5 Bit4 PWM Range Extend Breathe Mode RSVD Bit3 Bit2 Bit1 Bit0 Breathe OFF Rate Table 15. LEDDBCFR Field Description Bit Field 7 Breathe OFF Enable Breathe OFF Enable Bit — This bit enables the breathe OFF feature setup in bit [5] and bit [3:0]. This bit will be overridden by LEDDBCRR [7] if the LEDDBCRR [6] is set. 0 = The Breathe OFF control if disabled; NO Breathe OFF 1 = The breathe OFF control is enabled Description 6 PWM Range Extend PWM Range Extend — This bit extend the original 255/256 PWM pulse width for the linear counter mode to 256/256 to provide constant on PWM output for testing. 0 = PWM extension OFF 1 = Extend the PWM pulse with from 255/256 to 256/256 for Linear Counter Mode. 5 Breathe Mode 4 RSVD 3:0 Breathe OFF Rate Breathe Mode Select Bit — This bit selects the breathe ON/OFF mode. If this bit is cleared, the LED Driver with breathe ON/[OFF] with fix rate set in bit [3:0] for all colors; If this bit is set, the LED Driver will breathe ON/[OFF] using modulated rate based on the its destination brightness level. This bit will be overridden by LEDDBCRR [5] if the LEDDBCRR [6] is set. 0 = Unique rate for breathe OFF 1 = Modulate rate for breathe OFF, based on the destination brightness level. User setup of the breathe OFF rate. 4’b0000 = No Breathe OFF The optional breathe OFF range is show in Table 16. Table 16. Optional Breath OFF Range UI1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Tramp (sec) 0.128 0.256 0.384 0.512 0.640 0.768 0.896 1.024 1.152 1.280 1.408 1.536 1.664 1.792 1.920 2.048 1. UI is the user input value in binary. Opposite to the ramp on period, the modulated ramp rate could be achieved by 16 bit counter which will decrease on every flick rate cycle (125 Hz) with the step size internally calculated based on the formula below: 256 Brightness Nstep = ---------------- X ---------------------------16 UI + 1 During the ramp up, the PWM engine will take the MSB 8 bits of the 16 bit counter as input. This will result the ramp size of 256 Brightness --------------- ----------------------------- UI + 1 16 ---------------------------------------------------------256 (of 255) increment per flick rate cycle (125 Hz). LED Driver RED Pulse Width Register (LEDDPWRR) LEDDPWRR can only be written through System Bus Bit7 Bit6 Bit5 Bit4 Bit3 RED Pulse Width (PWR) 42 Bit2 Bit1 Bit0 iCE40 LED Driver Usage Guide The LEDDPWRR allow user to setup the brightness of the RED LED through Pulse Width Modulation (PWM) with total 256 brightness level. Based on the PWR value, the modulated pulse with could be generated from 0 to 100% 1 - % per step. The Active Duty Cycle could be calculated as: of the flick rate cycle in --------256 PW R ADC (%)= ------------256 In Linear Counter Mode (Non-LSFSR Mode), if the LEDDBCFR[6] bit is set, with PWR = 8HFF setting, the Active Duty Cycle of the PWM output will be 100% instead of 255/256%. This way we could provide constant on PWM output for characterization and validation testing. LED Driver GREEN Pulse Width Register (LEDDPWRG) LEDDPWRG can only be written through System Bus Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 GREEN Pulse Width (PWG) The LEDDPWRG allow user to setup the brightness of the GREEN LED through Pulse Width Modulation (PWM) with total 256 brightness level. Based on the PWG value, the modulated pulse with could be generated from 0 to 1 - % per step. The Active Duty Cycle could be calculated as: 100% of the flick rate cycle in --------256 PW G ADC (%)= ------------256 In Linear Counter Mode (Non-LSFSR Mode), if the LEDDBCFR[6] bit is set, with PWR = 8HFF setting, the Active Duty Cycle of the PWM output will be 100% instead of 255/256%. This way we could provide constant on PWM output for characterization and validation testing. LED Driver BLUE Pulse Width Register (LEDDPWRB) LEDDPWRG can only be written through System Bus Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 BLUE Pulse Width (PWB) The LEDDPWRB allow user to setup the brightness of the BLUE LED through Pulse Width Modulation (PWM) with total 256 brightness level. Based on the PWB value, the modulated pulse with could be generated from 0 to 100% 1 - % per step. The Active Duty Cycle could be calculated as: of the flick rate cycle in --------256 PW B ADC (%)= -----------256 In Linear Counter Mode (Non-LSFSR Mode), if the LEDDBCFR[6] bit is set, with PWR = 8HFF setting, the Active Duty Cycle of the PWM output will be 100% instead of 255/256%. This way we could provide constant on PWM output for characterization and validation testing. 43 iCE40 LED Driver Usage Guide LEDD Control Register Waveform Shaping Waveform When BREATHE_MODE = 0 LEDDBCRR LEDDONR LEDDBCFR LEDDOFR Level 255 LEDDPWR0 LEDDPWR1 LEDDPWR2 PWMOUT0 PWMOUT1 PWMOUT2 LEDD _ON The LEDD Control Register waveform shaping, when BREATHE_MODE (LEDDBCRR/LEDDBCFR Bit [5]) is “0”, is demonstrated in the Figure below. Waveform When BREATHE_MODE = 1 LEDDBCRR LEDDONR LEDDBCFR LEDDOFR Level255 LEDDPWR0 LEDDPWR1 PWMOUT0 PWMOUT1 PWMOUT2 LEDDPWR2 LEDD _ON The LEDD Control Register waveform shaping, when BREATHE_MODE (LEDDBCRR/LEDDBCFR Bit [5]) is “1”, is demonstrated in the Figure below. 44 iCE40 LED Driver Usage Guide Appendix E. IR Transceiver IP IRTCV Control Bus Addressable Registers The IRTCV Control Bus addressable registers are shown in Table 17. Table 17. IRTCV Control Bus Addressable Register IRTCV_ADR[3:0] Name 0001 IRTCVCR IR Transceiver Control Register Usage Access W 0010 IRSYSFR3 IR Transceiver System Clock Frequency Register 3 W 0011 IRSYSFR2 IR Transceiver System Clock Frequency Register 2 W 0100 IRSYSFR1 IR Transceiver System Clock Frequency Register 1 W 0101 IRSYSFR0 IR Transceiver System Clock Frequency Register 0 W 0110 IRTCVFR2 IR Transceiver Clock Frequency Register 2 R/W 0111 IRTCVFR1 IR Transceiver Clock Frequency Register 1 R/W 1000 IRTCVFR0 IR Transceiver Clock Frequency Register 0 R/W 1001 IRTCVDR1 IR Transceiver Data 1 R/W 1010 IRTCVDR0 IR Transceiver Data 0 R/W 1011 IRTCVSR IR Transceiver Status Register R IR Transceiver Control Register (IRTCVCR) IRTCVCR can be written through IR Transceiver Control Bus. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 IRTCVEN DUTY33 OUTPOL DISOE USRMAX REMEASEN Bit1 Bit0 INFILTSEL Table 18. IRTCVCR Field Description Bit Field Description 7 IRTCVEN IR Transceiver Enable Bit — This bit enables the IR Transceiver IP. If IRTCVEN is cleared, The IR Transceiver is disabled. 0 = IR Transceiver disabled 1 = IR Transceiver enabled 6 DUTY33 ON Pulse Duty Cycle Select Bit — This bit selects the IR ON pulse duty cycle between 1/2 and 1/3 of the Transmit clock period. 0 = 1/2 TFTCV 1 = 1/3 TFTCV 5 OUTPOL PWM Outputs Polarity Select Bit — This bit selects the PWM outputs polarity. 0 = Active High 1 = Active Low 4 DISOE Disable Output On Error Bit — This bit disable the IR Transceiver transmit output upon Error. 0 = Continue On Error 1 = Disable IR_OUT On Error 3 USRMAX User defined the Maximum pulse count in learning mode — This bit enable capability to allow user specify the Maximum pulse count through IRTCVDR in learning. 0 = Maximum count is 15H7FFF 1 = User specify the Maximum count through IRTCVDR. 2 REMEASEN Learning TCV Clock Frequency Re-Measure Enable Bit — This bit enables the TCV clock frequency measurement on the beginning of every Active ON cycle group. 0 = Re-measuring Disabled, TCV frequency is evaluated only on the very first Active ON Cycle group. 1 = Re-measuring Enabled, 45 iCE40 LED Driver Usage Guide Bit Field 1:0 INFILTSEL Description Input Filter Select Bits — These bits select the Input Glitch Filter window for the input (IR_IN) in learning/receiving mode 00 = No Input Glitch Filtering 01 = Filter out Glitch less than 2 System Clock Cycles 10 = Filter out Glitch less than 4 System Clock Cycles 11 = Filter out Glitch less than 8 System Clock Cycles IR Transceiver Status Register (IRTCVSR) IRTCVSR can be read through the IR Transceiver Control Bus. It will report the IR Transceiver status with the bit definition shown below. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 BUSY TIP RSVD LFCNTOFL LDATOFL DATERR RFRDY DBUFRDY Table 19. IRTCVSR Field Description Bit Field 7 BUSY 6 TIP Description IR Transceiver BUSY — This bit indicates the IR Transceiver IP is busy, transmitting, receiving or calculating. 0 = Idle 1 = Busy Transceiver In Progress — This bit indicates the IR Transceiver is in the middle of transmitting or receiving. 0 = Not Transmitting or Receiving 1 = Transmitting or receiving 5 RSVD 4 LFCNTOFL Receiving Frequency Counter Overflow Flag — This bit indicates the IR Receiver Frequency evaluation Counter overflow when measuring TCV clock frequency. 0 = No Frequency Counter Overflow 1 = Frequency Counter Overflow - 3 LDATOFL Receiving Counter Overflow Flag — This bit indicates the IR Receiver Counter overflow when detecting the ON/OFF pulses/cycles in learning mode 0 = No Data Counter Overflow 1 = Data Counter Overflow 2 DATERR Data Error Flag — This bit indicates the IR Transceiver Data Error caused by data buffer under-run in transmit mode or data buffer over-run in learning mode. 0 = No Data Error 1 = Data Error Occurred 1 RFRDY Receiving Clock Frequency Ready — These bit indicates the receiving frequency have been detected and calculated in learning mode 0 = Receiving Frequency Value is not valid 1 = Receiving Frequency Value is valid 0 DBUFRDY Data Buffer Ready Flag — These bit indicates the Transmit buffer is empty in transmit mode or the receiving buffer is full in the learning mode. IRTCVDR0 write/read activity triggered... 0 = Data Buffer is NOT Ready 1 = Data Buffer is Ready The BUSY status flag active (High) causes the BUSY hand shaking signal to go high to inform the host in the FPGA fabric that the IR Transceiver IP is currently busy transmitting, receiving or performing internal parameter calculation. The IRTCV_BUSY pin is logically equivalent to the BUSY status flag. The DBUFRDY status flag is used in both transmitting mode and learning mode. In transmitting mode, it indicates that the IRTCVDR buffer is ready for writing by the host in FPGA fabric. The DBUFRDY flag is set when the IRTCVDR data is fetched into the transmitter by the IRTCV IP logic. Writing data into the IRTCVDR0 clears the DBU- 46 iCE40 LED Driver Usage Guide FRDY flag. Delay in writing data into the IRTCVDR (0) before current data transmitting is finished causes the DATERR flag to become high, to indicate that the IRTCVDR is under-run and that a transmitting sequence error occurred. Once the DATERR flag is set, it remains high until the IRTCVCR is re-written, or a new IRTCV event occurs (EXE rising). In learning mode, the DBUFRDY indicates that the IRTCVDR buffer is ready to read by the host in FPGA fabric. In learning mode, the DBUFRDY status flag indicates that the IRTCVDR buffer is ready for read by the host. Reading the data from IRTCVDR0 clears the FBUFRDY flag. Delay in reading data from the IRTCVDR (0) before next data detected and evaluated causes the DATERR flag to be set, and remains set until the IRTCVCR is re-written, or a new IRTCV event occurs. The DRDY pin is logically equivalent to the DBUFRDY status flag. The ERR pin, on the other hand, is logically equivalent to the DATERR status flag. The RFRDY status flag indicates that the receiving IR signal frequency is detected, calculated and ready for read from IRTCVFR ([2:0]) in learning mode. Reading the IRTCVFR (0) clears the DBUFRDY status flag. Writing to the IRTCVCR or a new IRTCV event also clears the DBUFRDY status flag. The LDATOFL status flag indicates that the counter, used to detect the ON pulses or OFF cycles, reached its maximum count in learning mode. It remains set until IRTCVCR is re-written or a new learning event is started. The LFCNTOFL status flag indicates that the counter, used to detect the IR_IN clock period, exceeds the (16 bits) range. Once it occurs, the previously detected IRIN rising edge is abandoned, and the clock period detection is started over. The LFCNTOFL status flag is cleared when the IRTCVCR is re-written or a new learning event is started. IR Transceiver System Clock Frequency Registers (IRSYSFR 0-3) IRSYSFRs can be written through LED Control Bus. IRSYSFR3 [3:0] IRSYSFR2 [7:0] IRSYSFR1 [7:0] IRSYSFR0 [7:0] System Clock Frequency FSYS (Hz) The IR System Clock Frequency Registers, total 28 bits, holding the binary number representing the system clock frequency in Hertz. For normal application, user should set the IRSYSFRs prior of setting the IRTCVFRs. When writing IRSYSFR3, the MSB four bits from the data bus are “don’t care”. IR Transceiver Clock Frequency Registers (IRTCVFR 0-2) IRTCVFRs can be written or read through the IR Transceiver Control Bus. IRTCVFR2 [7:0] IRTCVFR1 [7:0] IRTCVFR0 [7:0] IR Transceiver Clock Frequency FTCV (Hz) The IR Transceiver Clock Frequency Register, totals 24 bits, and holds the binary number representing the IR Transceiver clock frequency in Hertz. In transmit mode, you should write these four bytes sequentially from IRTCVFR2 to IRTCVFR0. In learning mode, the detected transceiver frequency is available from this 24-bit register once the DRDY signal is set. The transceiver frequency is evaluated at the beginning of every ON period. Internal clock count to generate the IR Transceiver Clock is computed using the formula below. F SYSN = ----------F TCV 47 iCE40 LED Driver Usage Guide IR Transceiver Data Registers (IRTCVDR 0-1) IRTCVDR0-1 can be written or read through the IR Transceiver Control Bus. BIT 15 IRTCVDR1 [7] IR_FLAG BIT [14:0] IRTCVDR1 [6:0] IRTCVDR0 [7:0] Number of ON/OFF Cycles Table 20. IRTCVDR 0-1 Field Description Bit Field Description 15 IR_FLAG IR FLAG Bit — This bit indicates the data represented in BIT[14:0] should be number of ON cycles or OFF cycles 0 = Bit [14:0] is number of OFF cycles to transmit 1 = Bit [14:0] is number of ON cycles to transmit 14:0 NCYCLES Number of ON/OFF Cycles During a typical transmit session, the host logic inside the FPGA fabric should monitor the DRDY flag. Once the DRDY flag is high, then the host should write next ON-OFF cycle count, with IR_FLAG at MSB, into the IRTCVDR0-1. The host logic has minimal 30 system clock (CLKI) cycles (worst case when FSYS_CLK = 4 MHz, FTCV = 120 kHz and IRTCVDR = 1) to complete written data into the IRTCVDR0-1 (2 bytes). Failure to do so causes the transmit error to occur and the ERR flag to become high. The transmit session should be then terminated by the host. The NCYCLE for ON-OFF should be non-zero number. If NCYCLE = 0 accidentally happens, the decimal 1 is assumed by the hardware. During a typical learning session, the host logic inside the FPGA fabric should monitor the DRDY flag. Once the DRDY flag is high, both the IRTCVFR (4 bytes) and the IRTCVDR (2 bytes) are ready for read. The host logic has minimal 30 system clock (CLKI) cycles (worst case when FSYS_CLK = 4 MHz, FTCV = 120 kHz and IRTCVDR = 1) to fetch the IRTCVDR (2 bytes). Failure to do so causes the learning error to occur and the ERR flag becomes high. The learning session should then be terminated by the host. The host should continuously examine the received OFF cycles count to determine the end of each frame (Large than 4096). The maximum count is 15’H7FFF (32,767). The Learning mode could not co-exist with the transmit mode. When accessing IRTCVDRs, IRTCVDR1 should be written/read first for two bytes data access, or the host could only write/read the IRTCVDR0 if the IRTCVDR1 is un-changed (or all Zero). 48 iCE40 LED Driver Usage Guide IR Transceiver Waveform Transmitting Waveform The typical IR Transmitting waveform (LEARN = 0) is demonstrated in Figure 29. Figure 29. Typical IR Transmitting Waveform EXE IR_FLAG=1; IR _FLAG=0; Ttcv Duty Cycle 1/2 or 1/3 of Ttcv Number of Cycles= IRTCVDR[14:0] Number of Cycles= IRTCVDR[14:0] IROUT BUSY DRDY DENI (Write) TtcvMinimal 30 CLKI (Fabric FSM Clock) cycles at worst case (ON-OFF Count = 1, FIRCV_CLK = 4 MHz, FTCV = 120 KHz). 49 iCE40 LED Driver Usage Guide Learning Waveform The typical IR Learning waveform (LEARN = 1) is demonstrated in Figure 30. Figure 30. Typical IR Learning Waveform EXE IR_FLAG=1; IR _FLAG=0; Ttcv Number of Cycles= IRTCVDR[14:0] Number of Cycles= IRTCVDR[14:0] IRIN BUSY DRDY DENI(Read) Max Count (32767) Minimal 30 CLKI (Fabric FSM Clock) cycles at worst case (ON-OFF Count > 1, FIRCV_CLK = 4MHz, FTCV = 120 KHz). Carrier Frequency Register (IRTCVFR) is ready for read after first valid DRDY flag. 50