ETC AM79Q2242JC

I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
Quad ISLAC™
Quad Intelligent Subscriber Line Audio-processing Circuit (Quad ISLAC™)
Am79Q2241/2242/2243 Device
ORDERING INFORMATION
APPLICATIONS
Voice over IP/DSL — Integrated Access Devices (IAD),
Smart Residential Gateways (SRG), Home Gateway/
Router
Am79Q2241 VC
Cable Telephony — NIU, Set-Top Box, Home Side
Am79Q2242 JC
68-pin PLCC
Am79Q2243 VC
80-pin TQFP
Box, Cable Modem, Cable PC
Fiber — Fiber in the Loop (FITL), Fiber to the
Home (FTTH)
Wireless Local Loop, Intelligent PBX
DESCRIPTION
CO
The Quad ISLAC™ device, in combination with an ISLIC™
device, implements a four channel universal telephone line
interface. This enables the design of a single, low cost, high
performance, fully software programmable line interface for
multiple country applications. All AC, DC, and signaling
parameters are fully programmable via microprocessor or GCI
interfaces. Additionally, the Quad ISLAC device has integrated
self-test and line-test capabilities to resolve faults to the line or
line circuit. The integrated test capability is crucial for remote
applications where dedicated test hardware is not cost
effective.
High performance digital signal processor
provides programmable control of all major
linecard functions
— A-law/µ-law and linear codec
— Transmit and receive gain
— Two-wire AC impedance
— Transhybrid balance
— Equalization
— DC loop feeding
RELATED LITERATURE
— Smooth or abrupt polarity reversal
— Loop supervision
— Off-hook debounce circuit
— Ground-key and ring-trip filters
— Ringing generation and control
— Adaptive hybrid balance
— Line and circuit testing
— Metering generation at 12 kHz and 16 kHz
080274 Am79D2251 Dual ISLAC Data Sheet
080248 Am79231 ISLIC Data Sheet
080693 Am79240 ISLIC Data Sheet
080249 Am79241 ISLIC Data Sheet
080253 Am79251 ISLIC Data Sheet
080344 Am79R2xx/Am79Q224x Technical Reference
080345 Am79R240/Am79D2251 Technical Reference
BLOCK DIAGRAM
— Tone generation
Package
64-pin TQFP
DLC-MUX
FEATURES
Device
— Envelope shaping and level control
Selectable PCM/MPI or GCI digital interfaces
— Supports most available master clock frequencies
from 512 kHz to 8.192 MHz
General purpose I/O pins
4
7
A1
ISLIC
B1
B2
A3
VCCD
VREF
DGND 1
7
A2
ISLIC
DGND 2
LD2
RC
Networks
and
Protection
ISLIC
DRA/DD
DRB
ISLIC
LD4
DXB
Quad ISLAC
RREF
Exceeds LSSGR and ITU requirements
TSCB
P 1-P 3
A4
I/O 1 - I/O 4
TSCA/G
LD3
B4
+3.3 V DC operation
4
ADGND 1
ADGND 2
B3
VCCA
LD1
5
Supports external ringing with on-chip ring-trip
circuit
— Automatic or manual ring-trip modes
External
Ringing
Sense
Resistors
DXA/DU
DCLK/S0
5
PCLK/FS
MCLK
RSHB
FS/DCL
BATH
RSLB
CS/RST
DIO/S1
BATL
RSPB
INT
BATP
Publication# 080250 Rev: G
Version:1.0
Date: Dec 20, 2001
Am79Q2241/42/43 Data Sheet
I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
TABLE OF CONTENTS
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
ORDERING INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
RELATED LITERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
QUAD ISLAC™ DEVICE INTERNAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
FEATURES OF THE INTELLIGENT ACCESS™ CHIPSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
CONNECTION DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
PIN DESCRIPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Environmental Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Electrical Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
INTELLIGENT ACCESS VOICE CHIPSETS SYSTEM TARGET SPECIFICATIONS . . . . . . . . .10
DC SPECIFICATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
TRANSMISSION AND SIGNALING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
TRANSMIT AND RECEIVE PATHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
ATTENUATION DISTORTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
GROUP DELAY DISTORTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
SINGLE FREQUENCY DISTORTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
INTERMODULATION DISTORTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
GAIN LINEARITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
TOTAL DISTORTION INCLUDING QUANTIZING DISTORTION . . . . . . . . . . . . . . . . . . . . . . . . .17
OVERLOAD COMPRESSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
DISCRIMINATION AGAINST OUT-OF-BAND INPUT SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . .18
SPURIOUS OUT-OF-BAND SIGNALS AT THE ANALOG OUTPUT . . . . . . . . . . . . . . . . . . . . . .18
SWITCHING CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
PCM SWITCHING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Microprocessor Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Master Clock: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
PCM Switching Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
GCI TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
GCI Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
APPLICATION CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
INTERNAL RINGING LINECARD SCHEMATIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
EXTERNAL RINGING LINECARD SCHEMATIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
LINECARD PARTS LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
PHYSICAL DIMENSIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
68-PIN PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
64-PIN THIN QUAD FLAT PACK (TQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
80-PIN THIN QUAD FLAT PACK (TQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
REVISION SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
REVISION A TO REVISION B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
REVISION B TO REVISIONC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
REVISION C TO REVISION D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
REVISION D TO REVISION E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
REVISION E TO REVISION F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
REVISION F TO G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2
Am79Q2241/42/43 Data Sheet
I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
PRODUCT DESCRIPTION
The Intelligent Access™ voice chipsets integrate all functions of the subscriber line for four subscriber lines. One or more of two
chip types are used to implement the linecard; an ISLIC device and a Quad ISLAC device. These provide the following basic
functions:
1.
The ISLIC device: A high voltage, bipolar IC that drives the subscriber line, maintains longitudinal balance and senses line
conditions.
2. The Quad ISLAC device: A low voltage CMOS IC that provides conversion and DSP functions for all 4 channels.
Complete schematics of linecards using the Intelligent Access voice chipsets for internal and external ringing are shown in
“Application Circuits” on page 26.
The ISLIC device uses reliable, bipolar technology to provide the power necessary to drive a wide variety of subscriber lines. It
can be programmed by the ISLAC device to operate in eight different modes that control power consumption and signaling
modes. This enables it to have full control over the subscriber loop. The ISLIC device is designed to be used exclusively with the
ISLAC device as part of a multiple-line chipset. The ISLIC device requires only +5 V power and the battery supplies for its
operation.
The ISLIC device implements a linear loop-current feeding method with the enhancement of intelligent thermal management in
a controlled manner. This limits the amount of power dissipated on the ISLIC chip by dissipating excess power in external
resistors.
Each ISLAC device contains high-performance codec circuits that provide A/D and D/A conversion for voice (codec), DC-feed
and supervision signals for four subscriber channels. The ISLAC device contains a DSP core that handles signaling, DC-feed,
supervision and line diagnostics for all four channels.
The DSP core selectively interfaces with three types of backplanes:
•
Standard PCM/MPI
•
Standard GCI
•
Modified GCI with a single analog line per GCI channel
The Intelligent Access voice chipset provides a complete software configurable solution to the BORSCHT functions as well as
complete programmable control over subscriber line DC-feed characteristics, such as current limit and feed resistance. In
addition, these chipsets provide system level solutions for the loop supervisory functions and metering. In total, they provide a
programmable solution that can satisfy worldwide linecard requirements by software configuration.
Software programmed filter coefficients, DC-feed data and supervision data are easily calculated with the WinSLACä software.
This PC software is provided free of charge. It allows the designer to enter a description of system requirements. WinSLAC then
computes the necessary coefficients and plots the predicted system results.
The ISLIC interface unit inside the ISLAC device processes information regarding the line voltages, loop currents and battery
voltage levels. These inputs allow the ISLAC device to place several key ISLIC performance parameters under software control.
The main functions that can be observed and/or controlled through the ISLAC backplane interface are:
•
DC-feed characteristics
•
Ground-key detection
•
Off-hook detection
•
Metering signal
•
Longitudinal operating point
•
Subscriber line voltage and currents
•
Ring-trip detection
•
Abrupt and smooth battery reversal
•
Subscriber line matching
•
Ringing generation
•
Sophisticated line and circuit tests
To accomplish these functions, the ISLIC device collects the following information and feeds it, in analog form, to the ISLAC
device:
•
•
•
•
•
•
•
The metallic (IMT) and longitudinal (ILG) loop currents
The AC (VTX) and DC (VSAB) loop voltages
The outputs supplied by the ISLAC device to the ISLIC device are then:
A voltage (VHLi) that provides control for the following high-level ISLIC device outputs:
DC loop current
Internal ringing signal
12 or 16 kHz metering signal
Am79Q2241/42/43 Data Sheet
3
I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
•
A low-level voltage proportional to the voice signal (VOUTi)
•
A voltage that controls longitudinal offset for test purposes (VLBi)
The ISLAC device performs the codec and filter functions associated with the four-wire section of the subscriber line circuitry in
a digital switch. These functions involve converting an analog voice signal into digital PCM samples and converting digital PCM
samples back into an analog signal. During conversion, digital filters are used to band-limit the voice signals.
The user-programmable filters set the receive and transmit gain, perform the transhybrid balancing function, permit adjustment
of the two-wire termination impedance and provide frequency attenuation adjustment (equalization) of the receive and transmit
paths. Adaptive transhybrid balancing is also included. All programmable digital filter coefficients can be calculated using
WinSLAC software. The PCM codes can be either 16-bit linear two’s-complement or 8-bit companded A-law or µ-law.
Besides the codec functions, the Intelligent Access voice chipset provides all the sensing, feedback, and clocking necessary to
completely control ISLIC device functions with programmable parameters. System-level parameters under programmable control
include active loop current limits, feed resistance, and feed mode voltages.
The ISLAC device supplies complete mode control to the ISLIC device using the control bus and (P1-P3) tri-level load signal
(LDi).
The Intelligent Access voice chipset provides extensive loop supervision capability including off-hook, ring-trip and ground-key
detection. Detection thresholds for these functions are programmable. A programmable debounce timer is available that
eliminates false detection due to contact bounce.
For subscriber line diagnostics, AC and DC line conditions can be monitored using built in test tools. Measured parameters can
be compared to programmed threshold levels to set a pass/fail bit. The user can choose to send the actual PCM measurement
data directly to a higher level processor by way of the voice channel. Both longitudinal and metallic resistance and capacitance
can be measured, which allows leakage resistance, line capacitance, and telephones to be identified.
Quad ISLAC™ Device Internal Block Diagram
IREF VREF
VHL 1
Clock and
Reference
Circuits
VLB 1
VOUT 1
VINI 1
VSAB 1
VIMT 1
VILG 1
XSB 1
Ch 1
Converter
Block
PCM
and
GCI
Interface
and
Time Slot
Assigner
MCLK
FS/DCL
PCLK/FS
DXA/DU
DRA/DD
TSCA/G
DXB
DRB
TSCB
DCLK/S0
Ch 2
(as Ch 1)
Digital
Signal
Processor
GCI Control
Logic and
Microprocessor
Interface
DIO/S1
CS/RST
INT
I/O 1
I/O 2
I/O 3
I/O 4
Ch 3
(as Ch 1)
LD 1
LD 2
ISLIC
Control
Logic
Ch 4
(as Ch 1)
Common
External
Sense
Inputs
4
Am79Q2241/42/43 Data Sheet
LD 3
LD 4
P1
P2
P3
XSC
SHB
SLB
SPB
I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
Features of the Intelligent Access™ Chipset
•
•
•
•
•
•
•
Performs all battery feed, ringing, signaling, hybrid and
test (BORSCHT) functions
Two chip solution supports high density, multi-channel
architecture
Single hardware design meets multiple country requirements through software programming of:
– Ringing waveform and frequency
– DC loop-feed characteristics and current-limit
– Loop-supervision detection thresholds
– Off-hook debounce circuit
– Ground-key and ring-trip filters
– Off-hook detect de-bounce interval
– Two-wire AC impedance
– Transhybrid balance
– Transmit and receive gains
– Equalization
– Digital I/O pins
– A-law/µ-law and linear selection
Supports internal and external battery-backed ringing
– Self-contained ringing generation and control
– Supports external ringing generator and ring relay
– Ring relay operation synchronized to zero crossings
of ringing voltage and current
– Integrated ring-trip filter and software enabled manual or automatic ring-trip mode
Supports metering generation with envelope shaping
Smooth or abrupt polarity reversal
Adaptive transhybrid balance
– Continuous or adapt and freeze
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Supports both loop-start and ground-start signaling
Exceeds LSSGR and CCITT central office requirements
Selectable PCM or GCI interface
– Supports most available master clock frequencies
from 512 kHz to 8.192 MHz
On-hook transmission
Power/service denial mode
Line-feed characteristics independent of battery voltage
Only 5 V, 3.3 V and battery supplies needed
Low idle-power per line
Linear power-feed with intelligent power-management
feature
Compatible with inexpensive protection networks;
Accommodates low-tolerance fuse resistors while maintaining longitudinal balance
Monitors two-wire interface voltages and currents for
subscriber line diagnostics
Built-in voice-path test modes
Power-cross, fault, and foreign voltage detection
Integrated line-test features
– Leakage
– Line and ringer capacitance
– Loop resistance
Integrated self-test features
– Echo gain, distortion, and noise
Small physical size
Up to three relay drivers per ISLIC™ device
– Configurable as test load switches
Am79Q2241/42/43 Data Sheet
5
I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
CONNECTION DIAGRAMS
VOUT3
1
68 67
66
65
64
63
62
61
10
60
VCCA3
SHB
11
59
IREF
SLB
12
58
VREF
13
57
XSB1
14
56
AGND2
15
55
VLB1
16
54
VIMT1
VILG2
17
53
VILG1
VSAB2
18
52
VSAB1
VCCA2
19
51
VCCA1
VHL2
20
50
VHL1
VIN2
21
49
VIN1
VOUT2
22
48
VOUT1
SPB
23
47
DGND2
DGND1
24
46
I/O3
I/O4
25
45
I/O1
I/O2
26
44
LD3
XSC
VCCA4
SHB
SLB
XSB2
AGND1
VLB2
33
34
35
36
37
38
39
40
41
42
43
VCCD
DIO/S1
DCLK/S0
CS/RST
LD1
VOUT3
57
VIN3
58
VHL3
59
VSAB3
VLB4
60
VILG3
VIMT4
61
VIMT3
VILG4
62
VLB3
VSAB4
63
56 55
54
53
52
51
50
49
XSB3
VHL4
64
XSB4
VIN4
64-Pin TQFP Connection Diagram
VOUT4
Figure 2.
32
TSCA/G
31
DXA/DU
30
DRA/DD
29
FS/DCL
28
PCLK/FS
LD2
27
MCLK
Am79Q2242
Quad ISLAC
68-Pin PLCC
INT
VIMT2
P1
VLB2
P2
AGND1
P3
XSB2
LD4
VCCA4
6
VIN3
2
VHL3
3
VSAB3
VLB4
4
VILG3
VIMT4
5
VIMT3
VILG4
6
VLB3
VSAB4
7
XSB3
VHL4
8
XSB4
VOUT4
9
68-Pin PLCC Connection Diagram
VIN4
XSC
Figure 1.
1
48
VCCA3
2
47
IREF
3
46
VREF
4
45
XSB1
5
44
AGND2
6
43
VLB1
7
42
VIMT1
41
VILG1
40
VSAB1
VCCA1
Am79Q2241
Quad ISLAC
64-Pin TQFP
VIMT2
8
VILG2
9
VSAB2
10
39
VCCA2
11
38
VHL1
VHL2
12
37
VIN1
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VCCD
DIO/S1
DCLK/S0
CS/RST
18
TSCA/G
17
DXA/DU
LD1
DRA/DD
33
FS/DCL
16
PCLK/FS
LD3
DGND1
MCLK
34
INT
15
P1
DGND2
SPB
P2
VOUT1
35
P3
36
14
LD4
13
LD2
VIN2
VOUT2
Am79Q2241/42/43 Data Sheet
I N T E L L I G E N T
A C C E S S
S O L U T I O N S
N/C
VOUT4
VIN4
VHL4
VSAB4
VILG4
VIMT4
VLB4
XSB4
XSB3
VLB3
VIMT3
VILG3
VSAB3
VHL3
VIN3
VOUT3
N/C
N/C
80-Pin TQFP Connection Diagram
XSC
Figure 3.
V O I C E ™
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
VCCA4
1
60
N/C
SHB
2
59
VCCA3
SLB
3
58
IREF
XSB2
4
57
VREF
AGND1
5
56
XSB1
VLB2
6
55
AGND2
VIMT2
7
54
VLB1
VILG2
8
53
VIMT1
VSAB2
9
52
VILG1
VCCA2
10
51
VSAB1
VHL2
11
50
VCCA1
VIN2
12
49
VHL1
VOUT2
13
48
VIN1
SPB
14
47
VOUT1
15
46
DGND2
I/O3
DGND1
Am79Q2243
Quad ISLAC
80-Pin TQFP
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
TSCA/G
VCCD
DIO/S1
DCLK/S0
CS/RST
N/C
N/C
N/C
LD1
DXA/DU
41
DRA/DD
LD3
20
TSCB
42
N/C
FS/DCL
19
PCLK/FS
N/C
MCLK
43
DRB
INT
18
P1
I/O1
DXB
P2
44
P3
45
LD4
16
17
LD2
I/O4
I/O2
Am79Q2241/42/43 Data Sheet
7
I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
PIN DESCRIPTIONS
Pin
I/O
Description
Analog Ground
DCLK/S0
Data Clock/GCI
Address Strap 0
DGND1,
DGND2
Digital Ground
Digital ground returns
DIO/S1
Data I/O/GCI
Address Strap 1
I/O
For PCM backplane operation, control data is serially written into and read out
of the ISLAC device via the DIO pin with the MSB first. The data clock (DCLK)
determines the data rate. DIO is high impedance except when data is being
transmitted from the ISLAC device under control of CS/RST. For GCI operation,
this pin is device address bit 1. 5 V tolerant.
DRA/DD,
DRB
RX Path A
Backplane Data/
GCI data
Downstream,
Receive Path B
backplane data
I
For the PCM highway, the receive PCM data is input serially through the DRA
or DRB ports. The data input is received every 125 µs and is shifted in, MSB
first, in 8-bit PCM or 16-bit linear bursts at the PCLK rate. The receive port can
receive information for direct control of the ISLIC device. This mode is selected
in Device Configuration Register 2 (RTSEN=1, RTSMD=1). When selected, this
data is received in an independently programmable timeslot from the PCM data.
For the GCI mode, downstream receive and control data is accepted on this pin.
The DRB pin is available only on the 80-pin TQFP package. 5 V tolerant.
O
For the PCM highway, the transmit PCM data is transmitted serially through the
DXA or DXB ports. The transmission data output is available every 125 µs and
is shifted out, MSB first, in 8-bit PCM or 16-bit linear bursts at the PCLK rate.
DXA and DXB are high impedance between bursts and while the device is in the
inactive mode. Can also select a mode (RTSEN= 1, RTSMD=1 or 0 in Device
Configuration Register 2) that transmits the Signaling Register MSB contents
first, in an independently programmable timeslot from the PCM data. This data
is transmitted in all modes except disconnect. For the GCI mode, upstream
transmit and signaling data is transferred on this pin. The DXB pin is available
only on the 80-pin TQFP package. 5 V tolerant.
I
For PCM operation, pin is Frame Sync. PCM operation is selected by the
presence of an 8 kHz Frame Sync signal on this pin in conjunction with the
PCLK on the PCLK/FS pin (see below). This 8 kHz pulse identifies the beginning
of a frame. The ISLAC device references individual timeslots with respect to this
input, which must be synchronized to PCLK. GCI operation is selected by the
presence of the downstream clock DCL, on this pin in conjunction with the
presence of a FS on the PCLK/FS pin. In GCI mode, the data rate is 2 MHz and
DCL must be either 2 or 4 MHz. 5 V tolerant.
O
For PCM operation, when a subscriber line requires service, this pin goes to a
logic 0 to interrupt a higher level processor. Several registers work together to
control operation of the interrupt: Signaling and Global Interrupt Registers with
their associated Mask Registers, and the Interrupt Register. See the description
at channel configuration register 6 (Mask) for operation. Logic drive is selectable
between open drain and TTL-compatible outputs.
I/O
General purpose, TTL-compatible, logic input/output connection for each of 4
channels. These control lines are TTL-compatible and each can be
programmed as an input or output in the Global I/O Direction Register. When
programmed as outputs, they can control an external logic device. When
programmed as inputs, they can monitor external, TTL-compatible logic circuits.
Data for these pins can be written or read individually (from the channel specific
I/O Register) or as a group (from the Global I/O Data Register). Not available on
the 64-pin package.
I
External resistor (RREF) connected between this pin and analog ground
generates an accurate, on-chip reference current for the A/D's and D/A's on the
ISLAC chip.
O
The LD pins output 3-level voltages. When LDn is a logic 0 (< 0.4 V), the
destination of the code on P1–P3 is the relay control latches in the ISLIC control
register. When LDn is a logic 1 (>VCC−0.4 V), the destination of P1–P3 is the
mode control latches. LDn is driven to VREF when the contents of the ISLIC
control register must not change.
DXA/DU,
DXB
FS/DCL
INT
TX Path A
Backplane Data/
GCI Data
Upstream, TX
Path B
Backplane Data
Frame sync/GCI
Downstream
Clock
Interrupt
I/O1–I/O4
Control Ports
IREF
Current
Reference
LD1–LD4
8
Pin Name
AGND1,
AGND2
Register Load
Analog circuitry ground returns
I
Provides data control for MPI interface control. For GCI operation, this pin is
device address bit 0.5 V tolerant.
Am79Q2241/42/43 Data Sheet
I N T E L L I G E N T
Pin
Pin Name
MCLK
Master Clock
A C C E S S
V O I C E ™
S O L U T I O N S
I/O
Description
I
For PCM backplane operation, the DSP master clock connects here. A signal is
required only for PCM backplane operation when PCLK is not used as the
master clock. MCLK can be a wide variety of frequencies. Upon initialization the
MCLK input is disabled, and relevant circuitry is driven by a connection to PCLK.
5 V tolerant.
PCLK/FS
PCM Clock/
Frame Sync
I
For PCM operation, this is PCM Clock. PCM operation is selected by the
presence of a PCLK signal on this pin in conjunction with the FS on the FS/DCL
pin (see below). For PCM backplane operation, connect a data clock, which
determines the rate at which PCM data is serially shifted into or out of the PCM
ports. PCLK can be any multiple of the FS frequency. The minimum clock
frequency for linear/ companded data plus signaling data is 256 kHz. For GCI
operation, this pin is Frame Sync. The FS signal is an 8 kHz pulse that identifies
the beginning of a frame. The ISLAC device references individual timeslots with
respect to this input, which must be synchronized to DCL. 5 V tolerant.
P1–P3
ISLIC Control
O
Control the operating modes of the four ISLIC devices connected to the Quad
ISLAC device.
I
For PCM backplane operation, a logic low on this pin for 16 or more DCLK
cycles resets the sequential logic in the ISLAC device into a known mode. A
logic low placed on this pin for less than 15 DCLK cycles is a chip select and
enables serial data transmission into or out of the DIO port. For GCI operation,
a logic low on this pin for 1 ms or longer resets the sequential logic into a known
mode. See Table 2-4 in the Technical Reference for details. 5 V tolerant.
I
Resistors that sense the high, low and positive battery voltages connect here. If
only one negative battery is used, connect both resistors at the supply. If the
positive battery is not used, leave the pin unconnected. These pins are current
inputs whose voltage is held at VREF.
Chip Select/
Reset
CS/RST
SHB, SLB,
SPB
Battery Sense
TSCA/G
Timeslot Control
A/GCI Mode
O (PCM)
I (GCI)
TSCB
Time Slot Control
B
O
VSAB1–
VSAB4
Loop voltage
sense
I
VCCA1–
VCCA4
Power Supply
+3.3 VDC supplies to the analog sections in each of the four channels.
VCCD
Power Supply
+3.3 VDC supply to all digital sections.
VREF
Analog
Reference
O
This pin provides a 1.4 V, single-ended reference to the four ISLIC devices to
which the ISLAC device is connected.
VHL1–
VHL4
High Level D/A
O
High-level loop control voltages on these pins are used to control DC-feed,
internal ringing, metering and polarity reversal for each ISLIC device.
I
Analog transmit signals (VTX) from each ISLIC device connect to these pins.
The ISLAC device converts these signals to digital words and processes them.
After processing, they are multiplexed into serial time slots and sent out of the
DXA/DU pin.
O
Normally connected to VCCA internally. They supply longitudinal reference
voltages to the ISLIC devices during certain test procedures. These outputs are
connected internally to VCCA during ISLIC Active, Standby, Ringing, and
Disconnect modes. During test modes, it can be connected to the receive D/A.
VIN1–
VIN4
TX Analog
VLB1–
VLB4
Longitudinal
Reference
For PCM backplane operation, TSCA or TSCB is active low when PCM data is
output on the DXA or DXB pins. The outputs are open-drain and are normally
inactive (high impedance). Pull-up loads should be connected to VCCD. TSCB
is only available on the 80 pin TQFP package. When GCI mode is selected, one
of two GCI modes may be selected by connecting TSCA/G to DGND or VCCD.
Connect to the VSAB pins of four ISLIC devices.
Package Type
Pin Options
DRB
80 pin
68 pin
64 pin
√
x
x
x
DXB
√
x
TSCB
√
x
x
I/O1–I/O4
√
√
x
Am79Q2241/42/43 Data Sheet
9
I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Stresses greater than those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to absolute maximum ratings for extended periods can affect device reliability
Storage Temperature
–60º C ≤ TA ≤ +125º C
Ambient Temperature, under Bias
–40º C ≤ TA ≤ +85º C
Ambient relative humidity (non condensing)
5 to 100%
VCCA with respect to DGND
–0.4 to + 3.6 V
VCCD with respect to DGND
–0.4 to + 3.6 V
VIN with respect to DGND
–0.4 to VCCA + 0.4 V
5 V tolerant pins
–0.4 to Vcc + 2.25 or 5.25 V,
whichever is less
AGND
DGND ± 0.4 V
Latch up immunity (any pin)
±100 mA
Any other pin with respect to DGND
–0.4 V to VCC
Operating Ranges
Operating ranges define those limits between which device functionality is guaranteed. Functionality of the device from 0 to 70º
C is guaranteed by production testing. Performance from –40 to 85ºC is guaranteed by characterization and periodic sampling
of production units.
Environmental Ranges
Ambient Temperature
–40 to +85º C
Ambient Relative Humidity
15 to 85%
Electrical Ranges
Analog Supply VCCA
+3.3 V ± 5%
Digital Supply VCCD
+3.3 V ± 5%
DGND
0V
AGND
DGND ±50 mV
SPECIFICATIONS
The performance targets defined in this section are for the entire linecard comprised of both chips in the Intelligent Access voice
chipsets unless otherwise noted. Specifications for the individual chips in the set will be published separately (see note 1). TA =
0 to 70º C unless otherwise noted.
Intelligent Access Voice Chipsets System Target Specifications
Item
Condition
Min
Typ
Max
Unit
Peak Ringing Voltage
Active Ringing mode,
RLOAD =1500 Ω,
VBH = 80 V
70
V
Output Impedance during
internal ringing
Active Ringing mode, Quad
ISLAC generating internal
ringing
200
Ω
Sinusoidal Ringing THD
Active Ringing mode,
RLOAD =1500Ω,
VBH = 80V, ISLAC generating
internal sinusoidal ringing
2
%
Note
Loop open, in anti-sat
PSRR (VBH, VBL)
10
f = 50 Hz
2
f = 200 to 3400 Hz
12
Am79Q2241/42/43 Data Sheet
dB
1, 2
I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
Note:
1.
Not tested or partially-tested in production.
2.
These numbers are only valid when an ISLIC device operates with an ISLAC device, because the ISLAC generates the anti-sat feed
characteristic. When the Intelligent Access voice chipsets operate in the normal feed region, the performance is dominated by the ISLIC
device. See appropriate ISLIC data sheet for specific PSRR.
DC Specifications
No.
1
2
4
5
Item
Condition
Min
Typ
Max
Input Low Voltage, I/O1–I/O4
–0.05
All other digital inputs
–0.50
0.80 V
Input High Voltage, I/O1–I/O4
2.36
Vcc+0.4
All other digital inputs
7
8
2.0
5.25
Input Leakage Current, I/O1–I/O4
0 to VCC
–10
+10
All other digital inputs
0 to 5.25 V
–120
+180
Input hysteresis (PCLK/FS, FS/DCL,
MCLK, DIO, DRA, DRB)
.15
.225
.3
I/O1–I/O4
.16
.25
.34
V
µA
2
V
High voltage
Iout = 1 mA
VCC–.4
—
Low voltage
Iout = 2 mA
—
0.4
Medium voltage
±10 µA
Output Low Voltage (DXA/DU, DIO,
I/O1–I/O4, INT, TSCA, TSCB, DXB,
P1-P3)
Iol = 1 mA
0.4
Iol = 10 mA
1.0
V
1
µA
Output Low Voltage
(I/O1 –I/O4, INT, TSCA, TSCB)
9
Output High Voltage (All digital outputs
except INT in open drain mode and
TSCA, TSCB)
10
Input Leakage Current (VIN1–VIN4,
VSAB1–VSAB4, VILG1–VILG4,
VIMT1–VIMT4)
Ioh = 400 µA
Note
1.36 V
Ternary output voltages, LD1–LD4
6
Unit
VREF
VCC–0.4
–1
0.2
Input voltage (VIN1–VIN4)
µ-law
3.205 dBm0
VREF
VREF
A-law
3.14 dBm0 to insertion
loss in ADC
–1.02
+1.02
13
Input Voltage (VSAB1–VSAB4 or
VIMT1–VIMT4 or VILG1–VILG4)
|Vov–VREF| where Vov
is input overload
voltage
0.99
14
Offset voltage allowed on VIN1–VIN4
12
15
VOUT1–VOUT4 offset Voltage
16
VHL output offset voltage
17
1.02
–50
V
1.05
+50
DISN off
–40
+40
DISN on
–80
+80
mV
4
TBD
Load current = 0 to 10
mA
Output voltage, VREF
1.4
V
Source or Sink
18
Capacitance load on VREF or
VOUT1–VOUT4
19
Output drive current, VOUT1–VOUT4
or VLB1–VLB4
20
Output Leakage Current
VOUT1–VOUT4 or VLB1–VLB4
Source or Sink
Am79Q2241/42/43 Data Sheet
–1
500
200
200
pF
2
+1
mA
2
500
nA
11
I N T E L L I G E N T
No.
A C C E S S
Item
V O I C E ™
Condition
21
Maximum output voltage on VOUT
22
VLB1–VLB4 operating voltage
|VOUT–VREF| with
peak digital input
S O L U T I O N S
Min
Typ
Max
0.99
1.02
1.05
Unit
8
Source current < 250µA
or
VREF
VREF
Sink current < 25 µA.
–1.02
+1.02
Maximum output voltage on VHL
(KRFB)
|VHL–VREF| with peak
digital input
0.97
24
Gain from VSAB to VHL
VFD = 1
4.9
5
5.1
V/V
25
Gain from VSAB to VHL
VFD = 0
–.0255
–.025
–.0245
V/V
26
% error of VLB voltage (For VLB
equation, see Am79R2xx/
Am79Q224x Technical Reference)
+5
%
23
27
Capacitance load on VLB1–VLB4
28
Capacitance load on XSB1–XSB4,
XSC
29
Quad ISLAC Power Dissipation
1.00
Note
V
1.03
–5
8
120
2
pF
400
One channel active
(ISLIC state register set
to active); three
channels inactive
(ISLIC state register set
to standby)
183
All channels active
(ISLIC state register set
to active)
264
340
All channels inactive
(ISLIC state register set
to standby)
143
188
2
235
mW
Transmission and Signaling Specifications
Table 1. 0 dBm0 Voltage Definitions with Unity Gain in X, R, GX, GR, AX, and AR
Transmit
Receive
A-law digital mW or equivalent (0 dBm0)
Signal at Digital Interface
0.5026
0.5026
µ-law digital mW or equivalent (0 dBm0)
0.4987
0.4987
±5,800 peak linear coded sine wave
0.5026
0.5025
No.
Item
Min
Typ
Max
Input: 1014Hz, –10dBm0
AR = AX = GR = GX = 0 dB,
DISN, R, X, B and Z disabled
–0.25
0
+0.25
A-D + D-A
Temperature = 70°C
–0.15
0
+0.15
A-D − D-A
Variation over temperature
–0.1
0
+0.1
2
Level set error (Error between
setting and actual value)
A-D AX + GX
D-A AR + GR
–0.1
0.1
3
DR to DX gain in full digital
loopback mode
DR Input: 1014 Hz, –10 dBm0
AR=AX=GR=GX=0 dB, DISN,
R, X, B and Z filters default
–0.3
+0.3
4
Idle Channel Noise,
Psophometric Weighted (A-law)
Insertion Loss
1
12
Condition
A-D
D-A
A-D (PCM output)
–69
D-A (VOUT)
–78
5
Idle Channel Noise,
C Message weighted (µ-law)
A-D (PCM output)
+19
D-A (VOUT
+12
6
Coder Offset decision value, Xn
A-D, Input signal = 0 V
Am79Q2241/42/43 Data Sheet
–7
+7
Unit
Vrms
Unit
Note
dB
3, 8
dBm0p
5
dBrnC0
Bits
2
I N T E L L I G E N T
No.
A C C E S S
Item
Min
PSRR (VCC)
A-D
Image frequency
D-A
Measure 8000 Hz-Input
frequency
DISN gain accuracy
9
End-to-end group delay
Typ
Max
37
Unit
Note
dB
1
Gdisn = –0.9375 to 0.9375
8
11
S O L U T I O N S
Condition
Input: 4.8 to 7.8 kHz, 200 mV
p-p
7
10
V O I C E ™
Vin = 0 dBm0
–0.25
+0.25
dB
525
µS
2, 6, 7
–75
dBm0
2
dBm0
2
1014Hz; –10dBm0
B = Z = 0; X = R = 1
Crosstalk
TX to RX
0 dBm0
300 Hz to 3400 Hz
same channel
RX to TX
0 dBm0
300 Hz to 3400 Hz
Crosstalk
TX or RX to TX
0 dBm0
1014 Hz
–76
Crosstalk
TX or RX to RX
0 dBm0
1014 Hz
–78
1.
Not tested or partially tested in production. This parameter is guaranteed by characterization or correlation to other tests.
2.
Guaranteed by design.
3.
Overall 1.014 kHz insertion loss error of the Intelligent Access voice chipset is guaranteed to be 0.34 dB
4.
These voltages are referred to VREF.
5.
When relative levels (dBm0) are used, the specification holds for any setting of (AX + GX) gain from 0 to 12 dB or (AR + GR) from 0 to –12
dB.
6.
Group delay spec valid only when Channels 1–4 occupy consecutive slots in the frame. Programming channels in non-consecutive timeslots
can add up to 1 frame delay in the Group delay measurements.
7.
The Group delay specification is defined as the sum of the minimum values of the group delays for transmit and the receive paths when the
B, X, R, and Z filters are disabled with null coefficients. See Figure 8 for Group Delay Distortion.
8.
Requires that the calibration command (7Ch) must be performed to achieve this performance.
Transmit and Receive Paths
In this section, the transmit path is defined as the analog input to the ISLAC device (VINn) to the PCM voice output of the ISLAC
A-law/µ-law speech compressor. The receive path is defined as the PCM voice input to the ISLAC speech expander to the analog
output of the ISLAC device (VOUTn). All limits defined in this section are tested with B = 0, Z = 0 and X = R = GR = 1.
When AR is enabled, a nominal gain of –6.02 dB is added to the analog section of the receive path.
When AX is enabled, a nominal gain of +6.02 dB is added to the analog section of the transmit path.
When relative levels (dBm0) are used in any of the following transmission characteristics, the specification holds for any setting
of (AX + GX) gain from 0 to 12 dB or (AR + GR) from 0 to –12 dB.
These transmission characteristics are valid for 0 to 70º C.
Am79Q2241/42/43 Data Sheet
13
I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
Attenuation Distortion
The attenuation of the signal in either path is nominally independent of the frequency. The deviations from nominal attenuation
will stay within the limits shown in Figure 4 and Figure 5. The reference frequency is 1014 Hz and the signal level is –10 dBm0.
The minimum transmit attenuation at 60 Hz is 24 dB.
Figure 4.
Transmit Path Attenuation vs. Frequency
Attenuation (dB)
2
1
0.80
0.65
0.6
0.2
0.125
0
-0.125
Figure 5.
3400
3200
Frequency (Hz)
3000
600
0
200
300
Acceptable Region
Receive Path Attenuation vs. Frequency
Attenuation (dB)
2
1
0.80
0.65
0.6
0.2
0.125
0
-0.125
14
Am79Q2241/42/43 Data Sheet
3400
3200
Frequency (Hz)
3000
600
0
200
300
Acceptable Region
I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
Group Delay Distortion
For either transmission path, the group delay distortion is within the limits shown in Figure 6. The minimum value of the group
delay is taken as the reference. The signal level is –10 dBm0.
Figure 6. Group Delay Distortion
420
Delay (µS)
150
Acceptable
Region
2800
Frequency (Hz)
2600
1000
500
0
600
90
Single Frequency Distortion
The output signal level, at any single frequency in the range of 300 to 3400 Hz, other than that due to an applied 0 dBm0 sine
wave signal with frequency f in the same frequency range, is less than –46 dBm0. With f swept between 0 to 300 Hz and 3.4 to
12 kHz, any generated output signals other than f are less than –28 dBm0. This specification is valid for either transmission path.
Intermodulation Distortion
TBD
Am79Q2241/42/43 Data Sheet
15
I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
Gain Linearity
The gain deviation relative to the gain at –10 dBm0 is within the limits shown in Figure 7 (A-law) and Figure 8 (µ-law) for either
transmission path when the input is a sine wave signal of 1014 Hz.
Figure 7.
A-law Gain Linearity with Tone Input (Both Paths)
1.5
0.55
0.25
Acceptable Region
0
Gain (dB)
-0.25
-55 -50
-40
-10
0
Input
Level
+3 (dBm0)
-0.55
-1.5
Figure 8. µ-law Gain Linearity with Tone Input (Both Paths)
1.4
0.45
0.25
Acceptable Region
Gain (dB)
0
-55 -50
-37
-10
-0.25
-0.45
-1.4
16
Am79Q2241/42/43 Data Sheet
0
Input
Level
+3 (dBm0)
I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
Total Distortion Including Quantizing Distortion
The signal to total distortion ratio will exceed the limits shown in Figure 9 for either path when the input signal is a sine wave
signal of frequency 1014 Hz.
Figure 9.
Total Distortion with Tone Input, Both Paths
Acceptable Region
B
A
A
B
C
D
C
D
A-Law
35.5dB
35.5dB
30dB
25dB
µ-Law
35.5dB
35.5dB
31dB
27dB
Signal-to-Total
Distortion (dB)
-45
-40
-30
0
Input Level (dBm0)
Overload Compression
Figure 10 shows the acceptable region of operation for input signal levels above the reference input power (0 dBm0). The
conditions for this figure are:
(1) 1 dB < GX ≤ +12 dB; (2) –12 dB ≤ GR < –1 dB; (3) Digital voice output connected to digital voice input; and (4) measurement
analog to analog.
Figure 10. A/A Overload Compression
9
8
7
Fundamental
Output Power
(dBm0)
6
Acceptable
Region
5
4
3
2.6
2
1
1
7
2
3
4
5
6
Fundamental Input Power (dBm0)
Am79Q2241/42/43 Data Sheet
8
9
17
I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
Discrimination Against Out-of-Band Input Signals
When an out-of-band sine wave signal with frequency and level A is applied to the analog input, there may be frequency
components below 4 kHz at the digital output which are caused by the out-of-band signal. These components are at least the
specified dB level below the level of a signal at the same output originating from a 1014 Hz sine wave signal with a level of A
dBm0 also applied to the analog input. The minimum specifications are shown in the following table
Table 2. Minimum Specifications for Out-of-Band Input Signals
Frequency of Out-of-Band Signal
Amplitude of Out-of-Band Signal
Level below A
16.6 Hz < f < 45 Hz
–25 dBm0 < A ≤ 0 dBm0
18 dB
45 Hz < f < 65 Hz
–25 dBm0 < A ≤ 0 dBm0
25 dB
65 Hz < f < 100 Hz
–25 dBm0 < A ≤ 0 dBm0
10 dB
3400 Hz < f < 4600 Hz
–25 dBm0 < A ≤ 0 dBm0
see Figure 11
4600 Hz < f < 100 kHz
–25 dBm0 < A ≤ 0 dBm0
32 dB
Figure 11.
Discrimination Against Out-of-Band Signals
0
-10
-20
Level (dB)
-28 dBm
-30
-32 dB, -25 dBm0 < input , 0 dBm0
-40
-50
3.4
4.0
4.6
Frequency (kHz)
Note:
The attenuation of the waveform below amplitude A between 3400 Hz and 4600 Hz is given by the formula:
π ( 4000 – f )
Attenuation (db) = 14 – 14 sin ----------------------------1200
Spurious Out-of-Band Signals at the Analog Output
With PCM code words representing a sine wave signal in the range of 300 Hz to 3400 Hz at a level of 0 dBm0 applied to the
digital input, the level of the spurious out-of-band signals at the analog output is less than the limits shown below.
Table 3. Limits for Spurious Out-of-Band Signals
Frequency
Level
4.6 kHz to 40 kHz
–32 dBm0
40 kHz to 240 kHz
–46 dBm0
240 kHz to 1 MHz
–36 dBm0
With code words representing any sine wave signal in the range 3.4 kHz to 4.0 kHz at a level of 0 dBm0 applied to the digital
input, the level of the signals at the analog output are below the limits in Figure 12. The amplitude of the spurious out-of-band
signals between 3400 Hz and 4600 Hz is given by the formula:
π ( f – 4000 )
A = – 14 – 14 sin ----------------------------- dBm0
1200
18
Am79Q2241/42/43 Data Sheet
I N T E L L I G E N T
A C C E S S
Figure 12.
V O I C E ™
S O L U T I O N S
Spurious Out-of-Band Signals
0
-10
-20
Level (dB)
-28 dBm
-30
-32 dB
-40
-50
3.4
4.0
4.6
Frequency (kHz)
SWITCHING CHARACTERISTICS
PCM Switching Characteristics
Figure 13.
PCM Switching Characteristics
2.4 V
2.0 V
2.0 V
TEST
POINTS
0.8 V
0.8 V
0.4 V
VCC = 3.3 V +5%, AGND = DGND = 0 V.
Am79Q2241/42/43 Data Sheet
19
I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
Microprocessor Interface
Min and max values are valid for all digital outputs with a 100 pF load, except DIO,DXA, INT, TSCA, TSCB and DXB which are
valid with 150 pF loads.
No.
Symbol
1
tDCY
Parameter
Min
Typ
Max
Data clock period
122
2
tDCH
Data clock HIGH pulse width
48
3
tDCL
Data clock LOW pulse width
48
4
tDCR
Rise time of clock
15
5
tDCF
Fall time of clock
15
6
tICSS
Chip select setup time, Input mode
30
tDCY–10
7
tICSH
Chip select hold time, Input mode
0
tDCH–20
8
tICSL
Chip select pulse width, Input mode
9
tICSO
Chip select off time, Input mode
10
tIDS
Input data setup time
25
Unit
Note
1
1
ns
7.5tDCY
7
1,6
11
tIDH
Input data hold time
30
13
tOCSS
Chip select setup time, Output mode
30
14
tOCSH
Chip select hold time, Output mode
15
tOCSL
Chip select pulse width, Output mode
16
tOCSO
Chip select off time, output Mode
17
tODD
Output data turn on delay
18
tODH
Output data hold time
19
tODOF
Output data turn off delay
20
tODC
Output data valid
5
tDCY–10
tDCH–20
8tDCY
2000
50
ns
1,6
3
50
0
50
PCM Interface
20
No.
Symbol
22
tPCY
Parameter
Min.
PCM clock period
23
tPCH
PCM clock HIGH pulse width
48
48
0.122
Typ
Max
Unit
Note
7.8125
µs
2
24
tPCL
PCM clock LOW pulse width
25
tPCF
Fall time of clock
26
tPCR
Rise time of clock
27
tFSS
FS setup time
30
28
tFSH
FS hold time
50
29
tTSD
Delay to TSCX valid
5
30
tTSO
Delay to TSCX off
5
31
tDXD
PCM data output delay
5
70
32
tDXH
PCM data output hold time
5
70
33
tDXZ
PCM data output delay to high-Z
10
70
34
tDRS
PCM data input setup time
25
35
tDRH
PCM data input hold time
36
tFST
PCM or frame sync jitter time
15
15
tPCY–30
80
5
–97
Am79Q2241/42/43 Data Sheet
97
ns
3
4
4
I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
Master Clock:
For a 2.048 mHz ± 100 PPM, 4.096 mHz ± 100 PPM, or 8.192 ± 100 PPM operation:
No.
Symbol
Parameter
Min
Typ
Max
Unit
No
7812
ns
2,8
37
tMCY
Period
38
tMCR
Rise time of clock
15
39
tMCF
Fall time of clock
15
40
tMCH
MCLK HIGH pulse width
48
41
tMCL
MCLK LOW pulse width
48
122
Note:
1.
DCLK may be stopped in the HIGH or LOW state indefinitely without loss of information. When CS makes a transition to the High state, the
last byte received will be interpreted by the Microprocessor Interface logic.
2.
The PCM clock (PCLK) frequency must be an integer multiple of the frame sync (FS) frequency and synchronous to the MCLK frequency.
The actual PCLK rate is dependent on the number of channels allocated within a frame. A PCLK of 1.544 mHz can be used for standard
US transmission systems. The minimum clock frequency is 128 kHz.
3.
TSCA is delayed from FS by a typical value of N • tPCY, where N is the value stored in the time/clock slot register.
4.
tTSO is defined as the delay time the output driver turns off after the PCLK transaction. The actual delay time is dependent on the load
circuitry. The maximum load capacitance on TSCX is 150 pF and the minimum pull-up resistance is 360 Ω.
5.
The first data bit is enabled on the falling edge of CS or on the falling edge of DCLK, whichever occurs last.
6.
If the MPI is being accessed while the MCLK (or PCLK if combined with MCLK) input is not active, a Chip Select Off time of 20 µs is required
when accessing coefficient RAM.
7.
If chip select is held low for 16 or more DCLK cycles, the part will reset.
8.
MCLK’s frequency can range from 128 kHz to 8.192 MHz and can be set with: Write/Read Device Configuration Register 1, and if necessary
Write/Read Master Clock Correction Register.
Am79Q2241/42/43 Data Sheet
21
I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
PCM Switching Waveforms
Figure 14.
Master Clock Timing
37
41
VIH
VIL
40
38
39
Figure 15.
Microprocessor Interface (Input Mode)
1
2
5
V IH
V IH
DCLK
V IL
V IL
3
7
9
4
CS
6
8
10
DIO
22
Data
Valid
11
Data
Valid
Data
Valid
Am79Q2241/42/43 Data Sheet
I N T E L L I G E N T
A C C E S S
Figure 16.
V O I C E ™
S O L U T I O N S
Microprocessor Interface (Output Mode)
V IH
DCLK
V IL
13
14
16
15
CS
20
18
17
DOUT
19
VOH Data
VOL Valid
Three-State
Data
Valid
Data
Valid
Three-State
Figure 17. PCM Highway Timing for XE = 0 (Transmit on Negative PCLK Edge)
Time Slot Zero, Clock Slot Zero
27
22
26
25
V IH
PCLK
V IL
23
24
28
FS
30
29
TSCA
See Note 4
31
32
33
V OH
DXA
First
Bit
V OL
35
34
VIH
DRA
First
Bit
Second
Bit
VIL
Am79Q2241/42/43 Data Sheet
23
I N T E L L I G E N T
Figure 18.
A C C E S S
V O I C E ™
S O L U T I O N S
PCM Highway Timing for XE = 1 (Transmit on Positive PCLK Edge)
Time Slot Zero, Clock Slot Zero
27
22
26
25
V IH
PCLK
V IL
23
24
FS
28
30
29
TSCA
See Note 4
31
32
33
V OH
DXA
First
Bit
V OL
35
34
V IH
First
Bit
DRA
Second
Bit
V IL
GCI Timing Specifications
Symbol
Signal
tR, tF
DCL
Parameter
Min
tDCL
DCL
tWH, tWL
DCL
tR, tF
FS
Rise/fall time
tSF
FS
Setup time
70
tHF
FS
Hold time
50
tWFH
FS
High pulse width
130
tDDC
DU
Delay from DCL edge
tDDF
DU
Delay from FS edge
tSD
DD
Data setup
twH+20
tHD
DD
Data hold
50
tRST
RST
Reset pulse width
1.1
Rise/fall time
Typ
Max
Unit
60
Period, FDCL = 2048 kHz
478
498
FDCL = 4096 kHz
239
249
Pulse width
90
60
tDCL–50
ns
100
150
ms
Note:
1.
The Data Clock (DCL) can be stopped in the high or low state without loss of information.
2.
A temporary stoppage of DCL must not put the ISLAC into a state in which it does not respond to a software reset command.
3.
All frequency-dependent specifications are guaranteed for clock frequencies within ±100 PPM from nominal.
24
Am79Q2241/42/43 Data Sheet
I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
GCI Waveforms
DCL
FS
BIT 7
DD,
DU
BIT 6
DETAIL A
tr
tf
DCL**
tWH
tDCL
tWL
FS
tSF
tHF
tWFH
tDDF
DU
tDDC
tSD
tHD
DD
** Timing diagram valid for
F DCL = 2048 or 4096 KHz
Am79Q2241/42/43 Data Sheet
25
I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
APPLICATION CIRCUITS
Internal Ringing Linecard Schematic
+5V
VCC
RSAi
3.3V
CREF
RRXi
RSN
SA
VOUT i
RHLai
A
RFAi
CHLb i
AD
DGND
RHLb i
VHL i
RHLci
U3
D1
RT i
RHLdi
VREF
AGND
CHLdi
CADi
VSAB
CHPi
BATH
D2
VTX
VCCD
VIN i
HPB
U4
B
VSABi
HPA
CS
DT1 i
VCC
+3.3VDC
VCCA
CSSi
RFBi
BD
RSBi
SB
VLB
VLB i
IMT
VIMT i
CBDi
TMS
RTEST
RMTi
U1
Am79R251
RMGPi
DT2 i***
U2
ISLAC
VREF
ILG
VILG i
BACK
PLANE
TMP
RLGi
TMN
VREF
RMGLi
DHi
BATH
VREF
VBH
VREF
DLi
BATL
VBL
LD
LD i
GND
CBATHi
CBATLi
RSVD
P1
P1
P2
P2
P3
P3
SPB
SLB
BATL
RSLB
SHB
BATH
RSHB
RYE
IREF
R2
RREF
R3
R1
*CSS required for > 2.2 Vms metering
**Connections shown for one channel
***DT2 i diode is optional; should be
connected if there is a chance that this
chip may be replaced by the Le79R251
device. Otherwise, it creates a short.
26
BGND
RSVD
Am79Q2241/42/43 Data Sheet
I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
External Ringing Linecard Schematic
RSAi
+5 V
3.3 V
VCC
SA
CREF
RRXi
RSN
VOUT i
RHLai
RFAi
A
1
8
CHLbi
AD
RHLbi
KR i (A)
VHL i
RHLci
CADi
6
7
RTi
U5
CHPi
BATH
DT1 i
HPA
AGND
RHLdi
CHLdi
VREF
VCCA
VSAB i
VSAB
2
DGND
VTX
VIN i
VLB
VLB i
IMT
VIMT i
CS
VCC
+3.3 VDC
VCCD
HPB
CSSi
RFBi
B
KR i (B)
CBDi
BD
RSBi
RMTi
SB
TMS
RTEST
U1
Am79R251
VREF
VILG i
ILG
U2
ISLAC
RMGPi
RLGi
BACK
PLANE
TMP
DT2 i***
VREF
TMN
VREF
VREF
RMGLi
DHi
BATH
VBH
LD
LD i
GND
DLi
BATL
VBL
CBATHi
CBATLi
P1
P1
P2
P2
P3
P3
SPB
SLB
BATL
RSLB
SHB
RSVD 2
BATH
RSHB
RYE
IREF
R2H
RREF
RTESTLi
R3H
RGFDLi
R1
KR i
+5V
Ring Bus
BGND
RSVD
XSB i
XSC
*CSS required for > 2.2 Vms metering
**Connections shown for one channel
***DT2i diode is optional; should be connected if there is a
chance that this chip may be replaced by the Le79R251
device.
R
SRBi
RSRC
Am79Q2241/42/43 Data Sheet
27
I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
LINECARD PARTS LIST
The following list defines the parts and part values required to meet target specification limits for channel i of the linecard (i = 1,
2, 3, 4)..
Item
Type
U1
Value
Tol.
Rating
Am79R241
U2
Am79X22xx
U3, U4
B1100CC
U5
TISP61089A
D1, D2
DHi, DLi, DT1i, DT2i
4
ISLAC device
100 V
1A
100 V
Diode
100 mA
100 V
Resistor
RSAi, RSBi
RTi
RRXi
RREF
TECCOR Battrax protector
Transient Voltage Suppressor, Power
Innovations
Diode
RFAi, RFBi
Comments
ISLIC device
50 ns
50 Ω
2%
Resistor
200 kΩ
2%
1/4 W
Resistor
80.6 kΩ
1%
1/10 W
Resistor
100 kΩ
1%
1/10 W
Resistor
69.8 kΩ
1%
1/10 W
RMGLi, RMGPi
Resistor
1 kΩ
5%
1W
RSHB, RSLB
Resistor
750 kΩ
1%
1/8 W
RHLai
Resistor
40.2 kΩ
1%
1/10 W
RHLbi
Resistor
4.32 kΩ
1%
1/10 W
RHLci
Resistor
2.87 kΩ
1%
1/10 W
RHLdi
Resistor
2.87 kΩ
1%
1/10 W
CHLbi
Capacitor
3.3 nF
10 %
10 V
Not Polarized
CHLdi
Capacitor
0.82 mF
10 %
10 V
Ceramic
2W
Fusible PTC protection resistors
Sense resistors
Current reference
Thermal management resistors
RMTi
Resistor
3.01 kΩ
1%
1/8 W
RLGi
Resistor
6.04 kΩ
1%
1/8 W
RTEST
Resistor
2 kΩ
1%
1W
Capacitor
22 nF
10%
100 V
Ceramic, not voltage sensitive
CBATHi, CBATLi
Capacitor
100 nF
20%
100 V
Ceramic
CHPi
Capacitor
22 nF
20%
100 V
Ceramic
1
Capacitor
100 nF
20%
100 V
Protector speed up capacitor
Capacitor
56 pF
5%
100 V
Ceramic
510 Ω
2%
2W
CADi, CBDi
CSi
CSSi
1
3
Test board
Components for External Ringing
RGFDi
Resistor
RSRBi, RSRc
Resistor
KRi
Relay
750 kΩ
2%
1/4 W
1.2 W typ
Matched to within 0.2% for initial
tolerance and 0 to 70° C ambient
temperature range.2 17 mW typ
5 V Coil
DPDT
Note:
1.
Value can be adjusted to suit application.
2.
Can be less stringent for relaxed ring-trip requirements.
3.
Required for metering > 2.2 Vrms, otherwise must be omitted.
4.
DT2i is optional - Should be put if there is a chance that this chip may be replaced by Am79R251.
28
Am79Q2241/42/43 Data Sheet
I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
PHYSICAL DIMENSIONS
68-Pin PLCC
PL 068
Dwg rev. AN; 8/00
Am79Q2241/42/43 Data Sheet
29
I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
64-Pin Thin Quad Flat Pack (TQFP)
PQT 064
Dwg rev. AS; 08/00
30
Am79Q2241/42/43 Data Sheet
I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
80-Pin Thin Quad Flat Pack (TQFP)
PQT 080
Dwg rev. AS; 08/00
Am79Q2241/42/43 Data Sheet
31
I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
REVISION SUMMARY
Revision A to Revision B
•
Revision A was a condensed version of the datasheet while Revision B contains the full version.
Revision B to RevisionC
•
Page 14, Linecard Parts List, Rows CHLbi and CHLdi: switched the numbers in the “Values” column.
Revision C to Revision D
•
•
Page 12, Figure 5, DT1i was added and the last note was modified.
Page 14, Linecard Parts List, Item U3, U4 Type information was changed.
Revision D to Revision E
•
•
•
Updated document to new format.
In Pin Descriptions Table, changed I/O status of TSCB to "O"
In DC Specifications Table, the following changes were made:
– changed information for "Quad ISLAC Power Dissipation".
– Updated "Min", "Max", and "Typ" values for Input Leakage Current (VIN1-4, VSAB1-4, VILG1-4, VIMT1-4, VSAB1-4)
– Updated "Min", "Max", and "Typ" values for Output Leakage Current (VOUT1-4 or VLB1-4)
•
Made the following changes to the Transmission and Signaling Specifications table:
– Reformatted table
– For Insertion Loss, changed one of the "A-D + D-A" items to "A-D − D-A"
– For PSRR, added "A-D" to item; added Min value of 37
– For Image frequency, added "D-A" to item; added Min value of 37
– For DISN gain accuracy, changed conditions to: Gdisn = −0.9375 to 0.9375; Vin = 0 dBm0
– For Crosstalk TX or RX to TX; TX or RX to RX, added 0dBm0 to conditions
•
•
•
•
Divided Transmit and Receive Path Attenuation vs. Frequency graphic into two separate graphics
In the "Intermodulation Distortion" section, changed text to "TBD"
Updated PCM Switching Characteristics graphic.
In "Master Clock" section, added information for tMCY; added Note 8
•
•
•
Updated External Ringing Linecard schematic.
Added a linecard parts list.
Updated all "Physical Dimensions" graphics.
Revision E to Revision F
•
In Pin Descriptions Table, pins LD1-LD4, changed description for logic 0 to < 0.4 V; changed description for logic 1 to
(VCC − 0.4 V)
•
•
In DC Specifications Table, item 6, removed "Output current" row; inserted "Medium Voltage" row.
Subscripted channel numbers throughout document.
Revision F to G
•
32
Corrected physical dimensions for 64-Pin TQFP.
Am79Q2241/42/43 Data Sheet
I N T E L L I G E N T
A C C E S S
V O I C E ™
S O L U T I O N S
The contents of this document are provided in connection with Legerity, Inc. products. Legerity makes no representations or warranties with respect to the accuracy
or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No
license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in Legerity's
Standard Terms and Conditions of Sale, Legerity assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including,
but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
Legerity's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other
applications intended to support or sustain life, or in any other application in which the failure of Legerity's product could create a situation where personal injury,
death, or severe property or environmental damage may occur. Legerity reserves the right to discontinue or make changes to its products at any time without notice.
© 2001 Legerity, Inc.
All rights reserved.
Trademarks
Legerity, the Legerity logo and combinations thereof, and QISLAC™, ISLAC™, and ISLIC™ are trademarks of Legerity, Inc.
Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am79Q2241/42/43 Data Sheet
33
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Fax: 773-867-2910
DALLAS
4965 Preston Park Blvd., Suite 280
Plano, TX USA 75093
MainLine: 972-985-5474
Fax: 972-985-5475
HUNTSVILLE
600 Boulevard South, Suite 104
Huntsville, AL USA 35802
MainLine: 256-705-3504
Fax: 256-705-3505
IRVINE
1114 Pacifica Court, Suite 250
Irvine, CA USA 92618
MainLine: 949-753-2712
Fax: 949-753-2713
NEW JERSEY
3000 Atrium Way, Suite 270
Mt. Laurel, NJ USA 08054
MainLine: 856-273-6912
Fax: 856-273-6914
OTTAWA
600 Terry Fox Drive
Ottawa, Ontario, Canada K26 4B6
MainLine: 613-599-2000
Fax: 613-599-2002
RALEIGH
2500 Regency Parkway, Suite 226
Cary, NC USA 27511
MainLine: 919-654-6843
Fax: 919-654-6781
SAN JOSE
1740 Technology Drive, Suite 290
San Jose, CA USA 95110
MainLine: 408-573-0650
Fax: 408-573-0402
Telephone: (512) 228-5400
Fax: (512) 228-5510
North America Toll Free: (800) 432-4009
Worldwide Sales Offices
Europe
Asia
BELGIUM
Baron Ruzettelaan 27
8310 Brugge
Belgium
MainLine: 32-50-28-88-10
Fax: 32-50-27-06-44
HONG KONG
Units 2401-2, 24th Floor
Jubilee Centre, 18 Fenwick Street
Wanchai, Hong Kong
MainLine: 852-2864-8300
Fax: 852-2866-1323
FRANCE
7, Avenue G. Pompidou
Suite 402
92300 Levallois-Perret, France
MainLine: 33-1-47-48-2206
Fax: 33-1-47-48-2568
KOREA
135-090 18th Fl., Kyoung Am Bldg
157-26, Samsung-dong, Kangnam-ku
Seoul, Korea
MainLine: 82-2-565-5951
Fax: 82-2-565-3788
GERMANY
Freisinger Str. 1
85737 Ismaning, Germany
MainLine: 49-89-1893-99-0
Fax: 49-89-1893-99-44
SHENZHEN
Room 703, Block D1
Fu Yuan Garden
Futian Free Trade Zone
Shenzhen, PR China 518031
MainLine: 86-755-3567-008
Fax: 86-755-3567-191
ITALY
Via F. Rosselli 3/2
20019 Settimo Mse, Milano Italy
MainLine: 39-02-3355521
Fax: 39-02-33555232
SWEDEN
Frösundaviks Allé 15, 4tr
SE-16970 Solna
Sweden
MainLine: 46-8-509-045-45
Fax: 46-8-509-046-36
TOKYO
Shinjuku NS Bldg. 5F
2-4-1 Nishi Shinjuku, Shinjuku-ku
Tokyo, Japan 163-0805
MainLine: 81-3-5339-2011
Fax: 81-3-5339-2012
UK
Regus House, Windmill Hill Business Park
Whitehill Way
SN5 6QR Swindon
Wiltshire UK
MainLine: 44-(0)1793-441408
Fax: 44-(0)1793-441608
To download or order product literature, visit our website at www.legerity.com.
To order literature in North America, call: (800) 572-4859 or 512-349-3193
or email: [email protected]
To order literature in Europe or Asia, call: 44-0-1179-341607
or email: Europe — [email protected]
Asia — [email protected]