New Product R2A20168NP/SA/SP 8-bit 8ch D/A Converter with Buffer Amplifiers R03DS0019EJ0100 Rev.1.00 2011.09.05 Description The R2A20168 is an integrated circuit semiconductor of CMOS structure with 8 channels of built in D/A unnecessary and enabling configuration of a system with few component parts. Serial data transfer type input can easily be used through a combination of three lines: DI, CLK, and LD. Outputs incorporate buffer op-amps that have a drive capacity of 1 mA or above for both sink source, and can operate over the entire voltage range from almost ground to Vcc ( 0 to 5V ), making peripheral elements unnecessary and enabling configuration of a system with few component parts. Very small QFN package is added to lineup. It is suitable for a small mounting and reduces the mounting area. Features Guarantee Nonlinearity error : +/-1.0LSB, Differential nonlinearity error : +/-0.7LSB Data transfer format: 12-bit serial data input type by 3 wire ( DI, SCK, LD ) Output buffer op-amps: Operable over entire voltage range from almost ground to Vcc ( 0 to 5V ) Very small size package line-up: QFN-16(pin pitch: 0.5mm), TSSOP-16(pin pitch 0.65mm) Application Conversion from digital data to analog control data for home-use and industrial equipment. Signal gain control or automatic adjustment of LCD-TV, PDP-TV or LCD display-monitor. Blurring correction control or various control of the interchangeable lens of digital still camera. Automatic adjustment by combination with microcomputer and EEPROM. (substitution of half fixed resistance) Block Diagram Number for SOP/TSSOP package Number for QFN package DI 14 12 12-bit shift register CLK 13 11 D0 D1 D2 D3 D4 D5 D6 D7 9 11 DO D8 D9 D10 D11 10 12 LD Channel decoder Vcc 9 7 1 2 3 4 5 6 7 8 8 Power on reset 8 1 GND 16 14 8 8–bit latch 8-bit latch 8-bit upper segment R-2R 8-bit upper segment R-2R 6 13 16 1 2 3 4 5 8 15 8 15 2 3 4 5 6 7 10 1 VrefU Ao1 Ao2 Ao3 Ao4 Ao5 Ao6 Ao7 Ao8 VrefL R03DS0019EJ0100 Rev.1.00 2011.09.05 Page 1 of 9 New Product R2A20168NP/SA/SP Pin Arrangement 13 Ao1 14 GND VrefL 1 16 GND Ao2 2 15 Ao1 Ao3 3 11 CLK Ao4 4 10 LD Ao5 5 9 DO Ao8 8 Ao7 5 Ao6 4 Vcc 7 Ao5 3 VrefU 6 Ao4 2 R2A20168SA/SP (Top view) Outline: PWQN0016KB-A [NP] Ao6 6 Ao7 7 VrefU 8 R2A20168SA/SP 12 DI R2A20168NP Ao3 1 15 VrefL 16 Ao2 R2A20168NP (Top view) 14 DI 13 CLK 12 LD 11 DO 10 Ao8 9 Vcc Outline: PTSP0016JB-A [SA] PRSP0016DH-B [SP] Pin Description Pin No. [TSSOP Symbol [QFN] /SOP] 12 14 DI 11 13 CLK 10 12 LD 9 11 Do 13 16 1 2 3 4 5 8 7 14 6 15 15 2 3 4 5 6 7 10 9 16 8 1 Ao1 Ao2 Ao3 Ao4 Ao5 Ao6 Ao7 Ao8 Vcc GND VrefU VrefL R03DS0019EJ0100 Rev.1.00 2011.09.05 Function Serial data input terminal. ( Input serial data with a 12-bit data length ) Serial clock input terminal (Input signal from DI terminal is input to 12-bit shift register at rise of serial clock.) Load terminal (When High level is input to LD terminal, value in 12-bit shift register is loaded into decoder and 8-bit latch.) Serial data output terminal (Data is sequentially output from the MSB bit.) 8-bit resolution D/A converter output terminals (After power on, all channels are reset and DAC data 00h is output.) Power supply terminal GND terminal D/A converter upper reference voltage input terminal D/A converter lower reference voltage input terminal Page 2 of 9 New Product R2A20168NP/SA/SP Absolute Maximum Ratings Item (Ta= +25deg unless otherwise noted) Symbol Conditions Ratings Unit Supply voltage Vcc -0.3 to +6.5 V D/A converter upper reference voltage VrefU -0.3 to +6.5 V D/A converter lower reference voltage VrefL -0.3 to +6.5 V Buffer amplifier output current IAO -2.0 to +2.0 mA Input voltage Vin -0.3 to Vcc+0.3 <+6.5 V Output voltage Vo -0.3 to Vcc+0.3 <+6.5 V Power dissipation Pd Ta= +85deg 290(NP) / 150(SA) / 300(SP) mW Ta> +25deg Continuous Thermal derating factor K theta 7.25(NP) / 3.75(SA) / 7.5(SP) mW/deg Operating temperature Topr -30 to +85 deg Storage temperature Tstg -40 to +125 deg Electrical Characteristics « Digital Part » ( Vcc, VrefU = +5V +/-10%, Vcc>VrefU, GND,VrefL =0V, Ta= -30 to +85deg, Unless otherwise noted ) Item Symbol Test conditions Limits Unit Min Typ Max 2.7 5.0 5.5 V Supply voltage Vcc Supply current Icc CLK =1MHz, Vcc =5V, IAO =0µA - 0.4 1.2 mA Input leak current IILK VIN = 0 to Vcc -10 - 10 µA Input low voltage VIL - - 0.2Vcc V Input high voltage VIH 0.8Vcc - - V Output low voltage VOL 4.0V < Vcc, IOL = 2.0mA - - 0.4 V Vcc < 4.0V, IOL = 1.5mA - - 0.4 V Output high voltage VOH IOH = -400µA Vcc – 0.4 - - V Supply voltage rise time *1 trVcc Vcc = 0 to 2.7V 100 - - µs VccPOR Vcc = 0 to 2.7V - 1.5 1.9 V tPOR Vcc < 0.1V 1 - - ms Internal reset operating voltage *1 Power supply restart interval (Power supply OFF ON) *1 *1 : When power supply is turned on, internal circuit is initialized by power on reset circuit. But, if re-powered on quickly, initialize is not operate. So, keep the time period of re-powered on (tPOR). trVcc Vcc tPOR (equivalent to trVcc) VccPOR GND Internal Reset signal < 0.1V GND Resetting period R03DS0019EJ0100 Rev.1.00 2011.09.05 Resetting period Page 3 of 9 R2A20168NP/SA/SP New Product « Analog Part » ( Vcc, VrefU = +5V +/-10%, Vcc>VrefU, GND,VrefL =0V, Ta= -30 to +85deg, Unless otherwise noted ) Limits Item Symbol Unit Test conditions VrefU=5V, VrefL=0V, IAO=0µA, Data condition: at maximum current Min Typ Max - 1.0 2.0 mA Current dissipation IrefU D/A converter upper reference voltage range *2 VrefU 0.7Vcc - Vcc V D/A converter lower reference voltage range *2 VrefL GND - 0.3Vcc V Buffer amplifier output voltage range VAO IAO = +/- 100 µA 0.1 - Vcc – 0.1 V IAO = +/- 500 µA 0.2 - Vcc – 0.2 V Buffer amplifier output drive range IAO Upper side saturation voltage = 0.3V, Lower side saturation voltage = 0.2V -1.0 - 1.0 mA Differential nonlinearity SDL -0.7 - 0.7 LSB Nonlinearity SL -1.0 - 1.0 LSB -2.0 - 2.0 LSB -2.0 - 2.0 LSB Zero code error SZERO Full scale error SFULL VrefU = 4.79V, VrefL = 0.95V, Vcc = 5.5V (15mV/LSB), Without load (IAO =0µA) Output capacitive load Co - - 0.1 µF Buffer amplifier output impedance Ro - 5.0 - ohm *2 : The output does not necessary be the value with the reference voltage setting range. The output value is determined by the buffer amplifier output voltage range (VAO). R03DS0019EJ0100 Rev.1.00 2011.09.05 Page 4 of 9 New Product R2A20168NP/SA/SP AC Characteristics ( Vcc,VrefU = +5V +/-10%, Vcc VrefU, GND=VrefL = 0V, Ta = -30 to +85deg, unless otherwise noted ) Limits Item Symbol Test conditions Unit Min Typ Max fCLK - 1.0 10 MHz Clock low pulse width tCKL 40 - - ns Clock high pulse width tCKH 40 - - ns Clock rise time tCR - - 200 ns Clock fall time tCF - - 200 ns Data setup time tDCH 4 - - ns Data hold time tCHD 30 - - ns LD setup time tCHL 40 - - ns LD hold time tLDC 40 - - ns LD high pulse width tLDH 40 - - ns Data output delay time tDO CL < 100 pF -10 - 50 ns tLDD Ta=25deg, CL<100pF, VAO: 0.54.5V, The time until the output becomes the final value of 1/2 LSB. - - 150 µs Clock frequency D/A output settling time Timing Chart tCR tCKH tCF CLK tCKL DI tDCH tCHD tCHL tLDH tLDC LD tLDD D/A output tDo Do output (Note) Timing chart above is a schematic representation of the timing of each signal type. CLK signal input is High or Low regardless, LD signal High input is enabled. R03DS0019EJ0100 Rev.1.00 2011.09.05 Page 5 of 9 New Product R2A20168NP/SA/SP Digital Data Format Last LSB First MSB D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 Channel select data DAC data Channel select data D8 0 0 0 0 0 0 0 0 1 1 D9 0 0 0 0 1 1 1 1 0 0 D10 0 0 1 1 0 0 1 1 0 0 D11 0 1 0 1 0 1 0 1 0 1 Chanel Selection Don’t care Ao1 select Ao2 select Ao3 select Ao4 select Ao5 select Ao6 select Ao7 select Ao8 select Don’t care : : : : : 1 1 1 1 1 1 0 1 Don’t care Don’t care D0 0 1 0 1 D1 0 0 1 1 D2 0 0 0 0 D3 0 0 0 0 D4 0 0 0 0 D5 0 0 0 0 D6 0 0 0 0 D7 0 0 0 0 D/A Output (VrefU – VrefL) / 256 x 1 + VrefL (VrefU – VrefL) / 256 x 2 + VrefL (VrefU – VrefL) / 256 x 3 + VrefL (VrefU – VrefL) / 256 x 4 + VrefL : : : : : : : : : 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (VrefU – VrefL) / 256 x 255 + VrefL DAC data R03DS0019EJ0100 Rev.1.00 2011.09.05 VrefU Page 6 of 9 New Product R2A20168NP/SA/SP Data Timing Chart ( Model ) MSB DI D11 LSB D10 D9 D8 D7 D2 D1 D0 CLK Whether CLK input is “H” or “L”, high level input of LD signal is recognized. LD D/A output Precaution For Use There are three terminals (Vcc, VrefU, VrefL) that should be impressed a constant voltage. When ripple or spike noise is input to this terminal, there is fear that the accuracy of D/A conversion becomes lower and this IC malfunction. So, when use this IC, please connect capacitor between these terminals (Vcc, VrefU, VrefL) and GND for stable D/A conversion. This IC’s output amplifier has an advantage to capacitive load, So, it’s no problem at device action when connect capacitor ( 0.1µF Max ) among output to GND for every noise elimination. Standard Application Circuit Vcc Ao1 + 10µF VrefU Ao2 + 10µF Analog voltage output LD MCU CLK DI Ao7 VrefL + 10µF Ao8 GND R03DS0019EJ0100 Rev.1.00 2011.09.05 Page 7 of 9 R2A20168NP/SA/SP New Product Package Dimensions PRSP0016DH-B [SP] PTSP0016JB-A [SA] R03DS0019EJ0100 Rev.1.00 2011.09.05 Page 8 of 9 New Product R2A20168NP/SA/SP PWQN0016KB-A [NP] Ordering Information Order part No. Package Name Package Code Package type No. Packing/Quantity R2A20168SP SOP-16 PRSP0016DH-B SP Embossed Taping/2,000 pcs. R2A20168SA TSSOP-16 RTSP0016JB-A SA Embossed Taping/2,000 pcs. R2A20168NP QFN-16 PWQN0016KB-A NP Embossed Taping/3,000 pcs. R03DS0019EJ0100 Rev.1.00 2011.09.05 Page 9 of 9 Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. 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