RENESAS M62367GP

M62367GP
3 V Type 8-bit 8ch D/A Converter with Buffer Amplifiers
REJ03D0877-0300
Rev.3.00
Mar 25, 2008
Description
The M62367GP is a CMOS semiconductor IC has 8 channels of 8-bit D/A converter. It is operable with a low supply
voltage between 2.7 to 3.6 V, and is easy to use due to serial data input, and 3-pin (DI, CLK, LD) connection with
microcomputer.
The IC also contains DO pin terminal, enabling cascade connection, and therefore is suitable for automatic control in
combination with a microcomputer.
Features
•
•
•
•
•
Operable with a low voltage between 2.7 to 3.6 V
12-bit serial data input (connected via 3 pins: DI, CLK, LD)
8 channels of R-2R and segment type high-performance 8-bit D/A converters
8 buffer operational amplifiers with full swing of output voltage between VCC and GND
High oscillation stability against the capacitive load of buffer operational amplifiers
Application
Digital/analog conversion in industrial or home-use electronic equipment.
Automatic control in combination with EEPROM and microcomputer (Substitute for conventional semi-fixed resistor).
Block Diagram
GND
AO1
DI
CLK
LD
Do
AO8
VCC
16
15
14
13
12
11
10
9
D/A
D/A
D/A
D/A
−
−
−
3
VO3
4
VO4
5
VO5
6
VO6
+
D/A
+
L
+
L
+
L
−
REJ03D0877-0300 Rev.3.00 Mar 25, 2008
Page 1 of 7
L
+
2
VO2
L
−
+
−
1
VSS
(VrefL)
L
........
(8)
8-bit R-2R
+segment
D/A converter
D/A
Address
decoder
(8)
+
D0 1 2 3 4 5 6 D7 D8 9 10 D11
8-bit
latch
8-bit
latch
−
+
−
12-bit shift register
8-bit R-2R
+segment
D/A converter
7
VO7
8
VDD
(VrefU)
M62367GP
Pin Arrangement
M62367GP
VSS
(VrefL)
AO2
1
16 GND
2
15 AO1
AO3
3
14 DI
AO4
4
13 CLK
AO5
5
12 LD
AO6
6
11 Do
AO7
VDD
(VrefU)
7
10 AO8
8
9
VCC
(Top view)
Outline: PLSP0016JA-A (16P2E-A)
Pin Description
Pin No.
Pin Name
14
11
13
DI
DO
CLK
12
LD
15
2
3
4
5
6
7
10
9
16
8
1
AO1
AO2
AO3
AO4
AO5
AO6
AO7
AO8
VCC
GND
VDD
VSS
Function
Serial data input terminal to input 12-bit length serial data
Terminal to output MSB data of 12-bit shift register
Shift clock input terminal. Input signal at DI pin is input to 12-bit shift register at rise of shift
clock pulse
When H-level signal is input to this terminal. The value stored in 12-bit shift register is
loaded in decoder and D/A converter output register.
8-bit D/A converter output terminal
Power supply terminal
GND terminal
D/A converter upper reference voltage input terminal
D/A converter lower reference voltage input terminal
REJ03D0877-0300 Rev.3.00 Mar 25, 2008
Page 2 of 7
M62367GP
Block Diagram for Explanation of Terminals
DI
CLK
VCC
GND
9
16
14
12-bit shift register
13
D0
D1
D2
D3
D4
D5
D6
D9
D10
D11
D0
11
DO
12
LD
1 2 3 4 5 6 7 8
(8)
..... D7
8-bit
latch
D0
............................... 8
...............................
8-bit
R-2R+segment
D/A converter
.........................................
15
..... D7
8-bit
latch
8-bit
R-2R+segment
D/A converter
+
−
+
−
8
D8
Address decoder
(8)
1
D7
10
AO8
AO1
VDD
(VrefU)
1
VSS
(VrefL)
Absolute Maximum Ratings
Item
Supply voltage
Upper reference voltage of D/A converter
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
REJ03D0877-0300 Rev.3.00 Mar 25, 2008
Page 3 of 7
Symbol
VCC
VDD
VIN
VO
Pd
Topr
Tstg
Ratings
–0.3 to +7.0
–0.3 to +7.0
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
150
–20 to +85
–40 to +125
Unit
V
V
V
V
mW
°C
°C
M62367GP
Electrical Characteristics
<Digital Part>
(VCC, VrefU = +3 V ± 10%, VCC ≥ VrefU, GND, VrefL = 0 V, Ta = –20 to +85°C, unless otherwise noted.)
Min
Limits
Typ
Max
Unit
Supply voltage
Circuit current
VCC
ICC
2.7
—
3.0
0.6
3.6
2.0
V
mA
Input leak current
Input low voltage
Input high voltage
Output low voltage
Output high voltage
IILK
VIL
VIH
VOL
VOH
–10
—
0.8 VCC
—
VCC – 0.4
—
—
—
—
—
10
0.2 VCC
—
0.4
—
µA
V
V
V
V
Item
Symbol
Conditions
CLK = 1 MHz operation,
VCC = 3 V, IAO = 0 µA
VIN = 0 to VCC
IOL = 2.5 mA
IOH = –400 µA
<Analog Part>
(VCC, VrefU = +3 V ± 10%, VCC ≥ VrefU, GND, VrefL = 0 V, Ta = –20 to +85°C, unless otherwise noted.)
Item
Min
Limits
Typ
Max
Unit
Conditions
Current dissipation
IrefU
—
0.6
1.5
mA
VrefU = 3 V, VrefL = 0 V
Data condition: at maximum current
D/A converter upper
reference voltage range
VrefU
0.7 VCC
—
VCC
V
D/A converter lower
reference voltage range
VrefL
GND
—
0.3 VCC
V
Reference voltage cannot always
be set to any value in this range,
because it is restricted to the buffer
amplifier output voltage range.
Buffer amplifier output
driver voltage range
VAO
0.1
0.2
—
—
VCC – 0.1
VCC – 0.2
V
V
Buffer amplifier output
voltage range
IAO
–0.3
—
1
mA
Differential nonlinearity
error
Nonlinearity error
Zero code error
Full scale error
Output capacitive load
SDL
–1.0
—
1.0
LSB
SL
SZERO
SFULL
CO
–1.5
–2
–2
—
—
—
—
—
—
5
1.5
2
2
0.1
—
LSB
LSB
LSB
µF
Ω
Buffer amplifier output
impedance
Symbol
RO
REJ03D0877-0300 Rev.3.00 Mar 25, 2008
Page 4 of 7
IAO = ±100 µA
IAO = +500 µA
–200 µA
Upper saturation voltage = 0.4 V
Lower saturation voltage = 0.4 V
VCC = 2.760 V
VrefU = 2.610 V
VrefL = 0.050 V (10 mV/LSB)
Without load (IAO = ±0)
M62367GP
AC Characteristics
(VCC, VrefU = +3 V ± 10%, VCC ≥ VrefU, GND, VrefL = 0 V, Ta = –20 to +85°C, unless otherwise noted.)
Item
Clock "L" pulse width
Clock "H" pulse width
Clock rise time
Clock fall time
Data setup time
Data hold time
LD setup time
LD hold time
LD "H" pulse duration time
Data output delay time
D/A output setting time
Symbol
tCKL
tCKH
tCR
tCF
tDCH
tCHD
tCHL
tLDC
tLDH
tDO
tLDD
Min
Limits
Typ
Max
Unit
200
200
—
—
30
60
200
100
100
70
—
—
—
—
—
—
—
—
—
—
—
—
—
—
200
200
—
—
—
—
—
350
300
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Conditions
CL = 100 pF
CL ≥ 100 pF, VAO: 0.1 ↔ 2.6 V
This time until the output becomes
the final value of 1/2 LSB
Timing Chart
tCR
tCKH
tCF
CLK
tCKL
tLDC
DI
tDCH
tLDH
tCHD
tCHL
LD
tLDD
D/A output
tDO
DO output
REJ03D0877-0300 Rev.3.00 Mar 25, 2008
Page 5 of 7
M62367GP
Digital Data Format
First
MSB
Last
LSB
D0
D1
D2
D3
D4
D5
D6
D7
DAC data
D8
D9
D10
D11
DAC select data
DAC Data
D0
0
1
0
1
:
0
1
D1
0
0
1
1
:
1
1
Note:
D2
0
0
0
0
:
1
1
D3
0
0
0
0
:
1
1
D4
0
0
0
0
:
1
1
D5
0
0
0
0
:
1
1
D6
0
0
0
0
:
1
1
D7
0
0
0
0
:
1
1
D/A Output
(VrefU – VrefL) / 256 × 1 + VrefL
(VrefU – VrefL) / 256 × 2 + VrefL
(VrefU – VrefL) / 256 × 3 + VrefL
(VrefU – VrefL) / 256 × 4 + VrefL
:
(VrefU – VrefL) / 256 × 255 + VrefL
VrefU
VrefU = VDD, VrefL = VSS
DAC Select Data
D8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D9
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D10
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D11
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC Selection
Don't care
AO1 selection
AO2 selection
AO3 selection
AO4 selection
AO5 selection
AO6 selection
AO7 selection
AO8 selection
Don't care
Don't care
Don't care
Don't care
Don't care
Don't care
Don't care
Timing Chart (Model)
MSB
DI
D11
LSB
D10
CLK
LD
D/A
output
REJ03D0877-0300 Rev.3.00 Mar 25, 2008
Page 6 of 7
D9
D8
.............
..................
D2
D1
D0
M62367GP
Package Dimensions
JEITA Package Code
P-LSSOP16-4.4x5-0.65
RENESAS Code
PLSP0016JA-A
MASS[Typ.]
0.06g
9
E
16
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
*1
HE
Previous Code
16P2E-A
F
1
8
Index mark
c
A2
A1
Reference Dimension in Millimeters
Symbol
*2
A
L
D
*3
e
bp
y
Detail F
D
E
A2
A
A1
bp
c
HE
e
y
L
REJ03D0877-0300 Rev.3.00 Mar 25, 2008
Page 7 of 7
Min
4.9
4.3
Nom Max
5.0 5.1
4.4 4.5
1.15
1.45
0
0.1 0.2
0.17 0.22 0.32
0.13 0.15 0.2
0°
10°
6.2 6.4 6.6
0.53 0.65 0.77
0.10
0.3 0.5 0.7
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