New Product R2A20164NP/SA 8-bit 4ch D/A Converter with Buffer Amplifiers R03DS0017EJ0100 Rev.1.00 2011.09.05 Description The R2A20164 is an integrated circuit semiconductor of CMOS structure with 4 channels of built in D/A unnecessary and enabling configuration of a system with few component parts. Serial data transfer type input can easily be used through a combination of three lines: DI, CLK, and LD. Outputs incorporate buffer op-amps that have a drive capacity of 1 mA or above for both sink source, and can operate over the entire voltage range from almost ground to Vcc ( 0 to 5V ), making peripheral elements unnecessary and enabling configuration of a system with few component parts. Very small QFN package is added to lineup. It is suitable for a small mounting and reduces the mounting area. Features Guarantee Differential nonlinearity error : +/-0.7LSB, Nonlinearity error : +/-1.0LSB Data transfer format: 12-bit serial data input type by 3 wire ( DI, SCK, LD ) Output buffer op-amps: Operable over entire voltage range from almost ground to Vcc ( 0 to 5V ) 4 reference voltage terminals ( 2ch 2 composition and completely independent of the power supply terminal) Very small size package line-up: QFN-16 (pin pitch: 0.5mm), TSSOP-16 (pin pitch 0.65mm) Application Conversion from digital data to analog control data for home-use and industrial equipment. Signal gain control or automatic adjustment of LCD-TV, PDP-TV or LCD display-monitor. Blurring correction control or various control of the interchangeable lens of digital still camera. Automatic adjustment by combination with microcomputer and EEPROM. (substitution of half fixed resistance) Block Diagram Number for TSSOP package Number for QFN package DI 12 10 CLK 13 11 Vcc 15 13 12-bit shift register 12 14 Do 9 11 LD D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 Channel decoder 8 Power on reset GND 9 7 VrefU1 4 VrefL1 1 15 8bit Latch 8bit Latch 8bit Latch 8bit Latch 8-bit upper segment R-2R 8-bit upper segment R-2R 8-bit upper segment R-2R 8-bit upper segment R-2R R03DS0017EJ0100 Rev.1.00 2011.09.05 5 VrefU2 6 8 VrefL2 3 2 16 1 4 5 2 3 6 7 Ao1 Ao2 Ao3 Ao4 Page 1 of 8 New Product R2A20164NP/SA Pin Arrangement Ao3 4 14 N.C. 13 Vcc N.C. 8 3 Ao4 5 VrefU2 GND 7 2 VrefL2 6 VrefU1 R2A20164SA (Top view) VrefL1 1 Ao1 2 12 Do 11 CLK VrefU1 4 10 DI VrefU2 5 9 LD Ao2 3 Ao3 6 16 N.C. R2A20164SA 1 R2A20164NP Ao2 15 VrefL1 16 Ao1 R2A20164NP (Top view) Ao4 7 Outline: PWQN0016KB-A [NP] 14 Do 13 CLK 12 DI 11 LD 10 N.C. VrefL2 8 N.C. : Not connected 15 Vcc 9 GND N.C. : Not connected Outline: PTSP0016JB-A [SA] Pin Description Pin No. Symbol Function [QFN] [TSSOP] 10 12 DI 11 13 CLK Serial clock input terminal (Input signal from DI terminal is input to 12-bit shift register at rise of serial clock.) 9 11 LD Load terminal (When High level is input to LD terminal, value in 12-bit shift register is loaded into decoder and 8-bit latch.) 12 14 Do Serial data output terminal (Data is sequentially output from the MSB bit.) 16 2 Ao1 1 3 Ao2 4 6 Ao3 5 7 Ao4 13 15 Vcc 7 9 GND GND terminal 2 4 VrefU1 D/A converter upper reference voltage input terminal for ch1 and ch2 3 5 VrefU2 D/A converter upper reference voltage input terminal for ch3 and ch4 15 1 VrefL1 D/A converter lower reference voltage input terminal for ch1 and ch2 6 8 VrefL2 D/A converter lower reference voltage input terminal for ch3 and ch4 8 10 N.C. Not connected 14 16 N.C. Not connected R03DS0017EJ0100 Rev.1.00 2011.09.05 Serial data input terminal. ( Input serial data with a 12-bit data length ) 8-bit resolution D/A converter output terminals (After power on, all channels are reset and DAC data 00h is output.) Power supply terminal Page 2 of 8 New Product R2A20164NP/SA Absolute Maximum Ratings Item (Ta= +25deg unless otherwise noted) Symbol Ratings Unit Vcc -0.3 to +6.5 V D/A converter upper reference voltage VrefU1,VrefU2 -0.3 to +6.5 V D/A converter lower reference voltage VrefL1,VrefL2 -0.3 to +6.5 V Supply voltage Condition Buffer amplifier output current IAO -2.0 to +2.0 mA Input voltage Vin -0.3 to Vcc+0.3 <+6.5 V Output voltage Vo -0.3 to Vcc+0.3 <+6.5 V Continuous Pd Ta= +85deg 290(NP) / 150(SA) mW Thermal derating factor K theta Ta> +25deg 7.25(NP) / 3.75(SA) mW/deg Operating temperature Topr -30 to +85 deg Storage temperature Tstg -40 to +125 deg Power dissipation Electrical Characteristics « Digital Part » (Vcc,VrefU1,VrefU2 = +5V +/-10%, Vcc > VrefU1,VrefU2, GND=VrefL1=VrefL2= 0V, Ta= -30 to +85deg unless otherwise noted) Limits Item Symbol Test conditions Unit Min Typ Max 2.7 5.0 5.5 V Supply voltage Vcc Supply current Icc CLK = 1MHz, Vcc = 5V, IAO = 0µA - 0.3 0.9 mA Input leak current IILK VIN = 0 to Vcc -10 - 10 µA Input low voltage VIL - - 0.2Vcc V 4.0V < Vcc 0.5Vcc - - V Input high voltage VIH Vcc < 4.0V 0.8Vcc - - V 4.0V < Vcc, IOL = 2.0 mA - - 0.4 V Vcc < 4.0V, IOL = 1.5 mA - - 0.4 V VOL Output low voltage Output high voltage VOH IOH = -400 µA Vcc – 0.4 - - V Supply voltage rise time *1 trVcc Vcc = 0 to 2.7V 100 - - µs VccPOR Vcc = 0 to 2.7V - 1.5 1.9 V tPOR Vcc < 0.1V 1 - - ms Internal reset operating voltage *1 Power supply restart interval (Power supply OFF ON) *1 *1 : When power supply is turned on, internal circuit is initialized by power on reset circuit. But, if re-powered on quickly, initialize is not operate. So, keep the time period of re-powered on (tPOR). trVcc Vcc tPOR (equivalent to trVcc) VccPOR GND Internal Reset signal < 0.1V GND Resetting period R03DS0017EJ0100 Rev.1.00 2011.09.05 Resetting period Page 3 of 8 New Product R2A20164NP/SA « Analog Part » (Vcc,VrefU1,VrefU2 = +5V +/-10%, Vcc>VrefU1,VrefU2, GND=VrefL1=VrefL2= 0V, Ta= -30 to +85deg unless otherwise noted) Limits Item Symbol Current dissipation IrefU1, 2 Unit Test conditions VrefU1=VrefU2=5V, VrefL1=VrefL2=0V, IAO=0µA, Data condition: at maximum current for each terminal Min Typ Max - 0.3 0.6 mA D/A converter upper reference voltage range *2 VrefU 0.7Vcc - Vcc V D/A converter lower reference voltage range *2 VrefL GND - 0.3Vcc V Buffer amplifier output voltage range VAO IAO = +/- 100 µA 0.1 - Vcc – 0.1 V IAO = +/- 500 µA 0.2 - Vcc – 0.2 V Buffer amplifier output drive range IAO Upper side saturation voltage = 0.3V, Lower side saturation voltage = 0.2V -1.0 - 1.0 mA Differential nonlinearity SDL -0.7 - 0.7 LSB Nonlinearity SL -1.0 - 1.0 LSB -2.0 - 2.0 LSB -2.0 - 2.0 LSB Zero code error SZERO Full scale error SFULL VrefU = 4.79V, VrefL = 0.95V, Vcc = 5.5V (15mV/LSB), Without load (IAO =0µA) Output capacitive load Co - - 0.1 µF Buffer amplifier output impedance Ro - 5.0 - ohm *2 : The output does not necessary be the value with the reference voltage setting range. The output value is determined by the buffer amplifier output voltage range (VAO). R03DS0017EJ0100 Rev.1.00 2011.09.05 Page 4 of 8 New Product R2A20164NP/SA AC Characteristics (Vcc,VrefU1,VrefU2 = +5V +/-10%, Vcc >VrefU1,VrefU2, GND=VrefL1=VrefL2= 0V, Ta= -30 to +85deg unless otherwise noted) Limits Item Test conditions Symbol Min Typ Max Unit Clock frequency fCLK - 1.0 10 MHz Clock low pulse width tCKL 40 - - ns Clock high pulse width tCKH 40 - - ns Clock rise time tCR - - 200 ns Clock fall time tCF - - 200 ns Data setup time tDCH 4 - - ns Data hold time tCHD 30 - - ns LD setup time tCHL 40 - - ns LD hold time tLDC 40 - - ns LD high pulse width tLDH 40 - - ns Data output delay time tDO CL< 100 pF -10 - 50 ns tLDD Ta=25deg, CL<100pF, VAO: 0.54.5V, The time until the output becomes the final value of 1/2 LSB. - - 150 µs D/A output settling time Timing Chart tCR tCKH tCF CLK tCKL DI tDCH tCHD tCHL tLDH tLDC LD tLDD D/A output tDo Do output (Note) Timing chart above is a schematic representation of the timing of each signal type. CLK signal input is High or Low regardless, LD signal High input is enabled. R03DS0017EJ0100 Rev.1.00 2011.09.05 Page 5 of 8 New Product R2A20164NP/SA Digital Data Format Last LSB First MSB D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 Channel select data DAC data Channel select data D8 0 0 0 0 0 0 D9 0 0 0 0 1 1 D10 0 0 1 1 0 0 D11 0 1 0 1 0 1 : : : : : 1 1 1 1 1 1 0 1 Don’t care D0 0 1 0 1 D1 0 0 1 1 D2 0 0 0 0 D3 0 0 0 0 D4 0 0 0 0 D5 0 0 0 0 D6 0 0 0 0 D7 0 0 0 0 : : : : : : : : : 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (VrefU – VrefL) / 256 x 255 + VrefL Chanel Selection Don’t care Ao1 select Ao2 select Ao3 select Ao4 select Don’t care Don’t care DAC data D/A Output (VrefU – VrefL) / 256 x 1 + VrefL (VrefU – VrefL) / 256 x 2 + VrefL (VrefU – VrefL) / 256 x 3 + VrefL (VrefU – VrefL) / 256 x 4 + VrefL VrefU Data Timing Chart ( Model ) MSB DI D11 LSB D10 D9 D8 D7 D2 D1 D0 CLK Whether CLK input is “H” or “L”, high level input of LD signal is recognized. LD D/A output R03DS0017EJ0100 Rev.1.00 2011.09.05 Page 6 of 8 New Product R2A20164NP/SA Precaution For use There are five terminals (Vcc, VrefU1,2, VrefL1,2) that should be impressed a constant voltage. When ripple or spike noise is input to this terminal, there is fear that the accuracy of D/A conversion becomes lower and this IC malfunction. So, when use this IC, please connect capacitor between these terminals (Vcc, VrefU1,2, VrefL1,2) and GND for stable D/A conversion. This IC’s output amplifier has an advantage to capacitive load, So, it’s no problem at device action when connect capacitor ( 0.1µF Max ) among output to GND for every noise elimination. Standard Application Circuit Vcc Ao1 + 10µF VrefU1 Ao2 + 10µF Analog voltage output VrefU2 + 10µF Ao3 LD Ao4 MCU CLK DI VrefL1 + 10µF VrefL2 + 10µF GND Ordering Information Order part No. Package Name Package Code Package type No. Packing/Quantity R2A20164SA TSSOP-16 RTSP0016JB-A SA Embossed Taping/2,000 pcs. R2A20164NP QFN-16 PWQN0016KB-A NP Embossed Taping/3,000 pcs. R03DS0017EJ0100 Rev.1.00 2011.09.05 Page 7 of 8 R2A20164NP/SA New Product Package Dimensions PTSP0016JB-A [SA] PWQN0016KB-A [NP] R03DS0017EJ0100 Rev.1.00 2011.09.05 Page 8 of 8 Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. 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