Considerations in Converting from SMT to Die Assemblies National Semiconductor Technical Seminar Series Die Product Business Unit 1 Approaches, Options & Solutions • Die conversion trends and drivers • Die interconnect approaches • Device and information resources • Implementation 2 National Semiconductor Corporation Confidential 2003 National Semiconductor Corporation © 2002 Die Conversion Trends & Drivers • Form factor • Integration • Performance • Reliability 3 National Semiconductor Corporation Confidential 2003 National Semiconductor Corporation © 2002 Form Factor / Integration Reduced Size g g g g Improved Integration gggg ggg ggg g g g g g g g g g g g g g g g g g g g g g g gg gg g gg gg ggg 10mm SMD 5mm COB 3mm FC “Daughter board” 4 National Semiconductor Corporation Confidential 2003 National Semiconductor Corporation © 2002 Form Factor / Integration • Impact on current model – ≈ 25% of size – ≈ 50% weight – Same height – Improved testability – Increased reliability 5 National Semiconductor Corporation Confidential 2003 National Semiconductor Corporation © 2002 Form Factor / Integration Height variations of packaging approachs 160 140 100 80 60 40 20 Minimum Effective Height p Fl ip Ch i O B C P LL P TS SO SP C TQ FP P SS O Q FP SO IC IP D C 0 PL C Total package height (mils) 120 6 National Semiconductor Corporation Confidential 2003 National Semiconductor Corporation © 2002 Form Factor / Integration Silicon to Substrate Layout Ratio Due to Package/Interconnect 100 Large die Small die Stacked Die 60 40 20 Fli pC hip CO B CS P LL P TS SO P SS OP QF P TQ FP PL CC SO IC 0 DI P Silicon Ratio in % 80 Effects are die size dependent Potential Package/Interconnect Option 7 National Semiconductor Corporation Confidential 2003 National Semiconductor Corporation © 2002 Performance • Improved Electrical Performance – Shorter Interconnections • Inductance / capacitance • Power / ground distribution Buffer ROUT Receiver Chip Lead RLINE + - LLINE CLINE Lead Type SMD PGA Wire Bond Solder Bump pF 1 1 0.5 0.1 nH 1 - 12 2-5 1-3 0.01 8 National Semiconductor Corporation Confidential 2003 National Semiconductor Corporation © 2002 Reliability • Improved die Reliability due to Reduced Connections IC Bond Pad Substrate Trace 9 National Semiconductor Corporation Confidential © 2002 2003 National Semiconductor Corporation Die Interconnect Approaches • Wire Bond – Aluminum wedge – Gold ball • Flip Chip – Solder – Anisotropic adhesive – Gold • Trade offs 10 National Semiconductor Corporation Confidential 2003 National Semiconductor Corporation © 2002 Wire Bond • Bare die utilizing wire bond technology COB: Chip-on-board (wire bond) Wire bond Encapsulant (low stress) Die (active surface up) Substrate 11 National Semiconductor Corporation Confidential 2003 National Semiconductor Corporation © 2002 Wire Bond • Common COB wire bond types – Al wedge bond Al wire 12 National Semiconductor Corporation Confidential 2003 National Semiconductor Corporation © 2002 Wire Bond • Common COB wire bond types – Au ball bond Au wire Die pad ball bond Die bond pad 13 National Semiconductor Corporation Confidential 2003 National Semiconductor Corporation © 2002 Flip Chip • Bump layout – Peripheral – Area array Interconnect Material Die (active surface down) Substrate 14 National Semiconductor Corporation Confidential 2003 National Semiconductor Corporation © 2002 Flip Chip • Solder Bump Flip Chip – High lead solder – Eutectic solder (63% Sn, 37% Pb) – Lead-free solders 15 National Semiconductor Corporation Confidential 2003 National Semiconductor Corporation © 2002 Flip Chip - Solder Bump Build-up Starting Bond Pad Electroplate Solder Spin on BCB Strip Dam Template Define Pad Opening Reflow Solder Sputter/Evaporate UBM Image Solder Dam Etch UBM 16 National Semiconductor Corporation Confidential 2003 National Semiconductor Corporation © 2002 Flip Chip • Anisotropic Conductive Adhesive (ACA) Specialized applications: LCD, display drivers Pressure m Te u re rat pe Bumped Pad Die ACF Trace Pad Substrate Time 17 National Semiconductor Corporation Confidential 2003 National Semiconductor Corporation © 2002 Flip Chip • Gold Flip Chip Attach Specialized applications: LCD, medical, disk drives Ball Attach Wire preparation Bond tool Bond Pad Initial Ball Stud Formation 18 National Semiconductor Corporation Confidential 2003 National Semiconductor Corporation © 2002 Tradeoffs I/O capability COB v flip chip 150um bumped array 100um wire bond 600 mils Courtesy IBM Microelectronics 19 National Semiconductor Corporation Confidential 2003 National Semiconductor Corporation © 2002 Tradeoffs • Peripheral Bond Pads - COB 20 National Semiconductor Corporation Confidential 2003 National Semiconductor Corporation © 2002 Tradeoffs - COB • Advantages – – – – Reliable connection Manufacturing experience Low volume – cost effective Die availability • Challenges – – – – – – Overmold / glob-top req’d High pin counts Bond pad pitch & pad size High volume manufacturing Arrays and staggered bond pads Mixed with SMT 21 National Semiconductor Corporation Confidential 2003 National Semiconductor Corporation © 2002 Tradeoffs • Peripheral Array Solder Bumps – Pitch – Routing 22 National Semiconductor Corporation Confidential 2003 National Semiconductor Corporation © 2002 Tradeoffs • Area Array Solder Bumps – Size – Design flexibility – Routing – Pitch 23 National Semiconductor Corporation Confidential 2003 National Semiconductor Corporation © 2002 Tradeoffs - Flip Chip • Advantages – – – – – Smallest footprint per active circuitry Increased functionality per substrate area Improved thermal capability Lower cost in volume processing Improved performance R, L, C • Challenges – – – – – – Handling and die placement Lack of standard bump technology Cost effective high density substrates CTE matched or underfill - reliability Product availability & need for redistribution Industry infrastructure 24 National Semiconductor Corporation Confidential 2003 National Semiconductor Corporation © 2002 Tradeoffs Technology Comparison Size Component integration Process complexity I/O count Performance Manufacturability Cost SMT Good Good Best Good Good Best Better COB Better Better Better Better Better Best Best Flip Chip Best Best Good Best Best Good Best? 25 National Semiconductor Corporation Confidential 2003 National Semiconductor Corporation © 2002 Supplier & General Information Resources • Multiple functions available – Die suppliers • Information – Interconnect – Performance – Consortiums & Standards Organizations – Outsourcing 26 National Semiconductor Corporation Confidential 2003 National Semiconductor Corporation © 2002 Supplier & General Information Resources • Interconnect – National Semiconductor: www.national.com – Kulicke & Soffa: www.kns.com – Unitive: www.unitive.com – G. Riley: www.flipchips.com – Georgia Tech: www.marc.gatech.edu – Trade shows and symposiums • HDI / PCB: www.hdiexpo.com, www.pcbwest.com • IMAPS: www.imaps.org • ECTC: www.ectc.net • SMT: www.smta.org • China International IC 27 National Semiconductor Corporation Confidential © 2002 2003 National Semiconductor Corporation Supplier & General Information Resources • Consortiums & Standards Organizations – Die Products Consortium: www.dieproduct.com – High density packaging user group: www.hdpug.org – Good Die: www.gooddie.net – Cenelec: www.cenelec.org 28 National Semiconductor Corporation Confidential © 2002 2003 National Semiconductor Corporation Supplier & General Information Resources • Outsourcing – Flextronics: www.flextronics.com – Solectron: www.solectron.com – Celestica: www.celestica.com – SCI / Sanmina: www.sanmina.com – Others world wide 29 National Semiconductor Corporation Confidential © 2002 2003 National Semiconductor Corporation Supplier & General Information Resources • Performance options – “Known Good Die” • Performance guarantee • Testing strategies – “Pretty Good Die” • Quality • Other… buyer beware! 30 National Semiconductor Corporation Confidential © 2002 2003 National Semiconductor Corporation Implementation • Converting from SMT to COB or flip chip 31 National Semiconductor Corporation Confidential © 2002 2003 National Semiconductor Corporation Implementation • COB process flow Adhesive Application Die Placement & Wire Bond Encapsulation Adhesive Cure Paste Dispense and Die Attach Cure Oven Wire Bond Plasma Clean Glob Top Dispense Cure Oven 32 National Semiconductor Corporation Confidential © 2002 2003 National Semiconductor Corporation Implementation • Equipment conversion strategies – COB • Adhesive dispense • Die attach • Plasma clean • Wire bond • Encapsulation 33 National Semiconductor Corporation Confidential © 2002 2003 National Semiconductor Corporation Implementation • Flip chip process flow Solder bump Flux dipping Flux dip and flip chip mount Alignment Placement Reflow Oven Reflow soldering Flux Clean Flux cleaning Under-fill Dispense Under-fill dispense and cure Cure Oven 34 National Semiconductor Corporation Confidential © 2002 2003 National Semiconductor Corporation Implementation • Equipment conversion strategies – Flip Chip • Flux application • Chip placement • Reflow • Underfill 35 National Semiconductor Corporation Confidential © 2002 2003 National Semiconductor Corporation 36